2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_8 2
50 #define TIMER1_PRESCALER_DIV_64 3
51 #define TIMER1_PRESCALER_DIV_256 4
52 #define TIMER1_PRESCALER_DIV_1024 5
53 #define TIMER1_PRESCALER_DIV_FALL 6
54 #define TIMER1_PRESCALER_DIV_RISE 7
56 #define TIMER1_PRESCALER_REG_0 0
57 #define TIMER1_PRESCALER_REG_1 1
58 #define TIMER1_PRESCALER_REG_2 8
59 #define TIMER1_PRESCALER_REG_3 64
60 #define TIMER1_PRESCALER_REG_4 256
61 #define TIMER1_PRESCALER_REG_5 1024
62 #define TIMER1_PRESCALER_REG_6 -1
63 #define TIMER1_PRESCALER_REG_7 -2
66 /* available timers */
68 /* overflow interrupt number */
69 #define SIG_OVERFLOW_TOTAL_NUM 0
71 /* output compare interrupt number */
72 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
75 #define PWM_TOTAL_NUM 0
77 /* input capture interrupt number */
78 #define SIG_INPUT_CAPTURE_TOTAL_NUM 0
82 #define CLKPS0_REG CLKPR
83 #define CLKPS1_REG CLKPR
84 #define CLKPS2_REG CLKPR
85 #define CLKPS3_REG CLKPR
86 #define CLKPCE_REG CLKPR
89 #define ACIS0_REG ACSR
90 #define ACIS1_REG ACSR
98 #define PCIE0_REG GIMSK
99 #define PCIE1_REG GIMSK
100 #define INT0_REG GIMSK
103 #define ADC0D_REG DIDR0
104 #define ADC1D_REG DIDR0
105 #define ADC2D_REG DIDR0
106 #define ADC3D_REG DIDR0
107 #define AIN0D_REG DIDR0
108 #define AIN1D_REG DIDR0
111 #define MUX0_REG ADMUX
112 #define MUX1_REG ADMUX
113 #define MUX2_REG ADMUX
114 #define REFS_REG ADMUX
127 #define DDB0_REG DDRB
128 #define DDB1_REG DDRB
129 #define DDB2_REG DDRB
130 #define DDB3_REG DDRB
131 #define DDB4_REG DDRB
132 #define DDB5_REG DDRB
133 #define DDB6_REG DDRB
134 #define DDB7_REG DDRB
137 #define WDP0_REG WDTCSR
138 #define WDP1_REG WDTCSR
139 #define WDP2_REG WDTCSR
140 #define WDE_REG WDTCSR
141 #define WDCE_REG WDTCSR
142 #define WDP3_REG WDTCSR
143 #define WDIE_REG WDTCSR
144 #define WDIF_REG WDTCSR
147 #define EEDR0_REG EEDR
148 #define EEDR1_REG EEDR
149 #define EEDR2_REG EEDR
150 #define EEDR3_REG EEDR
151 #define EEDR4_REG EEDR
152 #define EEDR5_REG EEDR
153 #define EEDR6_REG EEDR
154 #define EEDR7_REG EEDR
157 /* #define OCR1_0_REG OCR1A */ /* dup in OCR1B */
158 /* #define OCR1_1_REG OCR1A */ /* dup in OCR1B */
159 /* #define OCR1_2_REG OCR1A */ /* dup in OCR1B */
160 /* #define OCR1_3_REG OCR1A */ /* dup in OCR1B */
161 /* #define OCR1_4_REG OCR1A */ /* dup in OCR1B */
162 /* #define OCR1_5_REG OCR1A */ /* dup in OCR1B */
163 /* #define OCR1_6_REG OCR1A */ /* dup in OCR1B */
164 /* #define OCR1_7_REG OCR1A */ /* dup in OCR1B */
167 #define WGM10_REG TCCR1A
168 #define WGM11_REG TCCR1A
169 #define COM1B0_REG TCCR1A
170 #define COM1B1_REG TCCR1A
171 #define COM1A0_REG TCCR1A
172 #define COM1A1_REG TCCR1A
175 #define PSR10_REG GTCCR
176 #define TSM_REG GTCCR
179 #define CS10_REG TCCR1B
180 #define CS11_REG TCCR1B
181 #define CS12_REG TCCR1B
182 #define WGM12_REG TCCR1B
183 #define FOC1B_REG TCCR1B
184 #define FOC1A_REG TCCR1B
187 #define PCIF0_REG GIFR
188 #define PCIF1_REG GIFR
189 #define INTF0_REG GIFR
192 #define CAL0_REG OSCCAL
193 #define CAL1_REG OSCCAL
194 #define CAL2_REG OSCCAL
195 #define CAL3_REG OSCCAL
196 #define CAL4_REG OSCCAL
197 #define CAL5_REG OSCCAL
198 #define CAL6_REG OSCCAL
199 #define CAL7_REG OSCCAL
202 #define DDA0_REG DDRA
203 #define DDA1_REG DDRA
204 #define DDA2_REG DDRA
205 #define DDA3_REG DDRA
206 #define DDA4_REG DDRA
207 #define DDA5_REG DDRA
208 #define DDA6_REG DDRA
209 #define DDA7_REG DDRA
212 #define ADPS0_REG ADCSRA
213 #define ADPS1_REG ADCSRA
214 #define ADPS2_REG ADCSRA
215 #define ADIE_REG ADCSRA
216 #define ADIF_REG ADCSRA
217 #define ADATE_REG ADCSRA
218 #define ADSC_REG ADCSRA
219 #define ADEN_REG ADCSRA
222 #define ACME_REG ADCSRB
223 #define ADTS0_REG ADCSRB
224 #define ADTS1_REG ADCSRB
225 #define ADTS2_REG ADCSRB
226 #define ADLAR_REG ADCSRB
227 #define BVRON_REG ADCSRB
230 /* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
231 /* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
232 /* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
233 /* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
234 /* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
235 /* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
236 /* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
237 /* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
240 /* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
241 /* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
242 /* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
243 /* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
244 /* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
245 /* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
246 /* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
247 /* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
263 #define PRADC_REG PRR
264 #define PRUSI_REG PRR
265 #define PRTIM0_REG PRR
266 #define PRTIM1_REG PRR
269 #define GPIOR10_REG GPIOR1
270 #define GPIOR11_REG GPIOR1
271 #define GPIOR12_REG GPIOR1
272 #define GPIOR13_REG GPIOR1
273 #define GPIOR14_REG GPIOR1
274 #define GPIOR15_REG GPIOR1
275 #define GPIOR16_REG GPIOR1
276 #define GPIOR17_REG GPIOR1
279 #define GPIOR00_REG GPIOR0
280 #define GPIOR01_REG GPIOR0
281 #define GPIOR02_REG GPIOR0
282 #define GPIOR03_REG GPIOR0
283 #define GPIOR04_REG GPIOR0
284 #define GPIOR05_REG GPIOR0
285 #define GPIOR06_REG GPIOR0
286 #define GPIOR07_REG GPIOR0
289 #define GPIOR20_REG GPIOR2
290 #define GPIOR21_REG GPIOR2
291 #define GPIOR22_REG GPIOR2
292 #define GPIOR23_REG GPIOR2
293 #define GPIOR24_REG GPIOR2
294 #define GPIOR25_REG GPIOR2
295 #define GPIOR26_REG GPIOR2
296 #define GPIOR27_REG GPIOR2
299 #define PORF_REG MCUSR
300 #define EXTRF_REG MCUSR
301 #define BORF_REG MCUSR
302 #define WDRF_REG MCUSR
305 #define EERE_REG EECR
306 #define EEPE_REG EECR
307 #define EEMPE_REG EECR
308 #define EERIE_REG EECR
309 #define EEPM0_REG EECR
310 #define EEPM1_REG EECR
313 #define USICNT0_REG USISR
314 #define USICNT1_REG USISR
315 #define USICNT2_REG USISR
316 #define USICNT3_REG USISR
317 #define USIDC_REG USISR
318 #define USIPF_REG USISR
319 #define USIOIF_REG USISR
320 #define USISIF_REG USISR
323 #define SPMEN_REG SPMCSR
324 #define PGERS_REG SPMCSR
325 #define PGWRT_REG SPMCSR
326 #define RFLB_REG SPMCSR
327 #define CTPB_REG SPMCSR
330 #define ADCL0_REG ADCL
331 #define ADCL1_REG ADCL
332 #define ADCL2_REG ADCL
333 #define ADCL3_REG ADCL
334 #define ADCL4_REG ADCL
335 #define ADCL5_REG ADCL
336 #define ADCL6_REG ADCL
337 #define ADCL7_REG ADCL
340 #define EEAR0_REG EEAR
341 #define EEAR1_REG EEAR
342 #define EEAR2_REG EEAR
343 #define EEAR3_REG EEAR
344 #define EEAR4_REG EEAR
345 #define EEAR5_REG EEAR
348 #define PORTB0_REG PORTB
349 #define PORTB1_REG PORTB
350 #define PORTB2_REG PORTB
351 #define PORTB3_REG PORTB
352 #define PORTB4_REG PORTB
353 #define PORTB5_REG PORTB
354 #define PORTB6_REG PORTB
355 #define PORTB7_REG PORTB
358 #define ADCH0_REG ADCH
359 #define ADCH1_REG ADCH
360 #define ADCH2_REG ADCH
361 #define ADCH3_REG ADCH
362 #define ADCH4_REG ADCH
363 #define ADCH5_REG ADCH
364 #define ADCH6_REG ADCH
365 #define ADCH7_REG ADCH
368 #define PORTA0_REG PORTA
369 #define PORTA1_REG PORTA
370 #define PORTA2_REG PORTA
371 #define PORTA3_REG PORTA
372 #define PORTA4_REG PORTA
373 #define PORTA5_REG PORTA
374 #define PORTA6_REG PORTA
375 #define PORTA7_REG PORTA
378 #define TCNT0_0_REG TCNT0
379 #define TCNT0_1_REG TCNT0
380 #define TCNT0_2_REG TCNT0
381 #define TCNT0_3_REG TCNT0
382 #define TCNT0_4_REG TCNT0
383 #define TCNT0_5_REG TCNT0
384 #define TCNT0_6_REG TCNT0
385 #define TCNT0_7_REG TCNT0
388 #define TCNT1_0_REG TCNT1
389 #define TCNT1_1_REG TCNT1
390 #define TCNT1_2_REG TCNT1
391 #define TCNT1_3_REG TCNT1
392 #define TCNT1_4_REG TCNT1
393 #define TCNT1_5_REG TCNT1
394 #define TCNT1_6_REG TCNT1
395 #define TCNT1_7_REG TCNT1
398 #define TOIE0_REG TIMSK0
399 #define OCIE0A_REG TIMSK0
400 #define OCIE0B_REG TIMSK0
403 #define TOIE1_REG TIMSK1
404 #define OCIE1A_REG TIMSK1
405 #define OCIE1B_REG TIMSK1
408 #define CS00_REG TCCR0B
409 #define CS01_REG TCCR0B
410 #define CS02_REG TCCR0B
411 #define WGM02_REG TCCR0B
412 #define FOC0B_REG TCCR0B
413 #define FOC0A_REG TCCR0B
416 #define WGM00_REG TCCR0A
417 #define WGM01_REG TCCR0A
418 #define COM0B0_REG TCCR0A
419 #define COM0B1_REG TCCR0A
420 #define COM0A0_REG TCCR0A
421 #define COM0A1_REG TCCR0A
424 #define USITC_REG USICR
425 #define USICLK_REG USICR
426 #define USICS0_REG USICR
427 #define USICS1_REG USICR
428 #define USIWM0_REG USICR
429 #define USIWM1_REG USICR
430 #define USIOIE_REG USICR
431 #define USISIE_REG USICR
434 #define PCINT0_REG PCMSK0
435 #define PCINT1_REG PCMSK0
436 #define PCINT2_REG PCMSK0
437 #define PCINT3_REG PCMSK0
438 #define PCINT4_REG PCMSK0
439 #define PCINT5_REG PCMSK0
440 #define PCINT6_REG PCMSK0
441 #define PCINT7_REG PCMSK0
444 #define PCINT8_REG PCMSK1
445 #define PCINT9_REG PCMSK1
446 #define PCINT10_REG PCMSK1
447 #define PCINT11_REG PCMSK1
448 #define PCINT12_REG PCMSK1
449 #define PCINT13_REG PCMSK1
450 #define PCINT14_REG PCMSK1
451 #define PCINT15_REG PCMSK1
454 #define PINB0_REG PINB
455 #define PINB1_REG PINB
456 #define PINB2_REG PINB
457 #define PINB3_REG PINB
458 #define PINB4_REG PINB
459 #define PINB5_REG PINB
460 #define PINB6_REG PINB
461 #define PINB7_REG PINB
464 #define PINA0_REG PINA
465 #define PINA1_REG PINA
466 #define PINA2_REG PINA
467 #define PINA3_REG PINA
468 #define PINA4_REG PINA
469 #define PINA5_REG PINA
470 #define PINA6_REG PINA
471 #define PINA7_REG PINA
474 /* #define OCR1_0_REG OCR1B */ /* dup in OCR1A */
475 /* #define OCR1_1_REG OCR1B */ /* dup in OCR1A */
476 /* #define OCR1_2_REG OCR1B */ /* dup in OCR1A */
477 /* #define OCR1_3_REG OCR1B */ /* dup in OCR1A */
478 /* #define OCR1_4_REG OCR1B */ /* dup in OCR1A */
479 /* #define OCR1_5_REG OCR1B */ /* dup in OCR1A */
480 /* #define OCR1_6_REG OCR1B */ /* dup in OCR1A */
481 /* #define OCR1_7_REG OCR1B */ /* dup in OCR1A */
484 #define ISC00_REG MCUCR
485 #define ISC01_REG MCUCR
486 #define BODSE_REG MCUCR
487 #define SM0_REG MCUCR
488 #define SM1_REG MCUCR
490 #define PUD_REG MCUCR
491 #define BODS_REG MCUCR
494 #define USIDR0_REG USIDR
495 #define USIDR1_REG USIDR
496 #define USIDR2_REG USIDR
497 #define USIDR3_REG USIDR
498 #define USIDR4_REG USIDR
499 #define USIDR5_REG USIDR
500 #define USIDR6_REG USIDR
501 #define USIDR7_REG USIDR
504 #define USIBR0_REG USIBR
505 #define USIBR1_REG USIBR
506 #define USIBR2_REG USIBR
507 #define USIBR3_REG USIBR
508 #define USIBR4_REG USIBR
509 #define USIBR5_REG USIBR
510 #define USIBR6_REG USIBR
511 #define USIBR7_REG USIBR
514 #define TOV0_REG TIFR0
515 #define OCF0A_REG TIFR0
516 #define OCF0B_REG TIFR0
519 #define TOV1_REG TIFR1
520 #define OCF1A_REG TIFR1
521 #define OCF1B_REG TIFR1