drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34 #include "rte_pmd_bnxt.h"
  35
  36 #define DRV_MODULE_NAME         "bnxt"
  37 static const char bnxt_version[] =
  38         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  39
  40 /*
  41  * The set of PCI devices this driver supports
  42  */
  43 static const struct rte_pci_id bnxt_pci_id_map[] = {
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  47                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
  87         { .vendor_id = 0, /* sentinel */ },
  88 };
  89
  90 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  91 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  92 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  93 #define BNXT_DEVARG_REPRESENTOR "representor"
  94 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
  95 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
  96 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
  97 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
  98 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
  99 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 100
 101 static const char *const bnxt_dev_args[] = {
 102         BNXT_DEVARG_REPRESENTOR,
 103         BNXT_DEVARG_TRUFLOW,
 104         BNXT_DEVARG_FLOW_XSTAT,
 105         BNXT_DEVARG_MAX_NUM_KFLOWS,
 106         BNXT_DEVARG_REP_BASED_PF,
 107         BNXT_DEVARG_REP_IS_PF,
 108         BNXT_DEVARG_REP_Q_R2F,
 109         BNXT_DEVARG_REP_Q_F2R,
 110         BNXT_DEVARG_REP_FC_R2F,
 111         BNXT_DEVARG_REP_FC_F2R,
 112         NULL
 113 };
 114
 115 /*
 116  * truflow == false to disable the feature
 117  * truflow == true to enable the feature
 118  */
 119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 120
 121 /*
 122  * flow_xstat == false to disable the feature
 123  * flow_xstat == true to enable the feature
 124  */
 125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 126
 127 /*
 128  * rep_is_pf == false to indicate VF representor
 129  * rep_is_pf == true to indicate PF representor
 130  */
 131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 132
 133 /*
 134  * rep_based_pf == Physical index of the PF
 135  */
 136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 137 /*
 138  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 139  */
 140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 141
 142 /*
 143  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 144  */
 145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 146
 147 /*
 148  * rep_fc_r2f == Flow control for the representor to endpoint direction
 149  */
 150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 151
 152 /*
 153  * rep_fc_f2r == Flow control for the endpoint to representor direction
 154  */
 155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 156
 157 int bnxt_cfa_code_dynfield_offset = -1;
 158
 159 /*
 160  * max_num_kflows must be >= 32
 161  * and must be a power-of-2 supported value
 162  * return: 1 -> invalid
 163  *         0 -> valid
 164  */
 165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 166 {
 167         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 168                 return 1;
 169         return 0;
 170 }
 171
 172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 176 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 177 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 178 static void bnxt_dev_recover(void *arg);
 179 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 180 static void bnxt_free_rep_info(struct bnxt *bp);
 181
 182 int is_bnxt_in_error(struct bnxt *bp)
 183 {
 184         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 185                 return -EIO;
 186         if (bp->flags & BNXT_FLAG_FW_RESET)
 187                 return -EBUSY;
 188
 189         return 0;
 190 }
 191
 192 /***********************/
 193
 194 /*
 195  * High level utility functions
 196  */
 197
 198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 199 {
 200         unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
 201                                              BNXT_RSS_TBL_SIZE_P5);
 202
 203         if (!BNXT_CHIP_P5(bp))
 204                 return 1;
 205
 206         return RTE_ALIGN_MUL_CEIL(num_rss_rings,
 207                                   BNXT_RSS_ENTRIES_PER_CTX_P5) /
 208                                   BNXT_RSS_ENTRIES_PER_CTX_P5;
 209 }
 210
 211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 212 {
 213         if (!BNXT_CHIP_P5(bp))
 214                 return HW_HASH_INDEX_SIZE;
 215
 216         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
 217 }
 218
 219 static void bnxt_free_parent_info(struct bnxt *bp)
 220 {
 221         rte_free(bp->parent);
 222 }
 223
 224 static void bnxt_free_pf_info(struct bnxt *bp)
 225 {
 226         rte_free(bp->pf);
 227 }
 228
 229 static void bnxt_free_link_info(struct bnxt *bp)
 230 {
 231         rte_free(bp->link_info);
 232 }
 233
 234 static void bnxt_free_leds_info(struct bnxt *bp)
 235 {
 236         if (BNXT_VF(bp))
 237                 return;
 238
 239         rte_free(bp->leds);
 240         bp->leds = NULL;
 241 }
 242
 243 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 244 {
 245         rte_free(bp->flow_stat);
 246         bp->flow_stat = NULL;
 247 }
 248
 249 static void bnxt_free_cos_queues(struct bnxt *bp)
 250 {
 251         rte_free(bp->rx_cos_queue);
 252         rte_free(bp->tx_cos_queue);
 253 }
 254
 255 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 256 {
 257         bnxt_free_filter_mem(bp);
 258         bnxt_free_vnic_attributes(bp);
 259         bnxt_free_vnic_mem(bp);
 260
 261         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 262          * If the number of rings change across fw update,
 263          * we don't have much choice except to warn the user.
 264          */
 265         if (!reconfig) {
 266                 bnxt_free_stats(bp);
 267                 bnxt_free_tx_rings(bp);
 268                 bnxt_free_rx_rings(bp);
 269         }
 270         bnxt_free_async_cp_ring(bp);
 271         bnxt_free_rxtx_nq_ring(bp);
 272
 273         rte_free(bp->grp_info);
 274         bp->grp_info = NULL;
 275 }
 276
 277 static int bnxt_alloc_parent_info(struct bnxt *bp)
 278 {
 279         bp->parent = rte_zmalloc("bnxt_parent_info",
 280                                  sizeof(struct bnxt_parent_info), 0);
 281         if (bp->parent == NULL)
 282                 return -ENOMEM;
 283
 284         return 0;
 285 }
 286
 287 static int bnxt_alloc_pf_info(struct bnxt *bp)
 288 {
 289         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 290         if (bp->pf == NULL)
 291                 return -ENOMEM;
 292
 293         return 0;
 294 }
 295
 296 static int bnxt_alloc_link_info(struct bnxt *bp)
 297 {
 298         bp->link_info =
 299                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 300         if (bp->link_info == NULL)
 301                 return -ENOMEM;
 302
 303         return 0;
 304 }
 305
 306 static int bnxt_alloc_leds_info(struct bnxt *bp)
 307 {
 308         if (BNXT_VF(bp))
 309                 return 0;
 310
 311         bp->leds = rte_zmalloc("bnxt_leds",
 312                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 313                                0);
 314         if (bp->leds == NULL)
 315                 return -ENOMEM;
 316
 317         return 0;
 318 }
 319
 320 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 321 {
 322         bp->rx_cos_queue =
 323                 rte_zmalloc("bnxt_rx_cosq",
 324                             BNXT_COS_QUEUE_COUNT *
 325                             sizeof(struct bnxt_cos_queue_info),
 326                             0);
 327         if (bp->rx_cos_queue == NULL)
 328                 return -ENOMEM;
 329
 330         bp->tx_cos_queue =
 331                 rte_zmalloc("bnxt_tx_cosq",
 332                             BNXT_COS_QUEUE_COUNT *
 333                             sizeof(struct bnxt_cos_queue_info),
 334                             0);
 335         if (bp->tx_cos_queue == NULL)
 336                 return -ENOMEM;
 337
 338         return 0;
 339 }
 340
 341 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 342 {
 343         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 344                                     sizeof(struct bnxt_flow_stat_info), 0);
 345         if (bp->flow_stat == NULL)
 346                 return -ENOMEM;
 347
 348         return 0;
 349 }
 350
 351 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 352 {
 353         int rc;
 354
 355         rc = bnxt_alloc_ring_grps(bp);
 356         if (rc)
 357                 goto alloc_mem_err;
 358
 359         rc = bnxt_alloc_async_ring_struct(bp);
 360         if (rc)
 361                 goto alloc_mem_err;
 362
 363         rc = bnxt_alloc_vnic_mem(bp);
 364         if (rc)
 365                 goto alloc_mem_err;
 366
 367         rc = bnxt_alloc_vnic_attributes(bp);
 368         if (rc)
 369                 goto alloc_mem_err;
 370
 371         rc = bnxt_alloc_filter_mem(bp);
 372         if (rc)
 373                 goto alloc_mem_err;
 374
 375         rc = bnxt_alloc_async_cp_ring(bp);
 376         if (rc)
 377                 goto alloc_mem_err;
 378
 379         rc = bnxt_alloc_rxtx_nq_ring(bp);
 380         if (rc)
 381                 goto alloc_mem_err;
 382
 383         if (BNXT_FLOW_XSTATS_EN(bp)) {
 384                 rc = bnxt_alloc_flow_stats_info(bp);
 385                 if (rc)
 386                         goto alloc_mem_err;
 387         }
 388
 389         return 0;
 390
 391 alloc_mem_err:
 392         bnxt_free_mem(bp, reconfig);
 393         return rc;
 394 }
 395
 396 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 397 {
 398         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 399         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 400         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 401         struct bnxt_rx_queue *rxq;
 402         unsigned int j;
 403         int rc;
 404
 405         rc = bnxt_vnic_grp_alloc(bp, vnic);
 406         if (rc)
 407                 goto err_out;
 408
 409         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 410                     vnic_id, vnic, vnic->fw_grp_ids);
 411
 412         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 413         if (rc)
 414                 goto err_out;
 415
 416         /* Alloc RSS context only if RSS mode is enabled */
 417         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 418                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 419
 420                 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
 421                         PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
 422                                     bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
 423                         PMD_DRV_LOG(ERR,
 424                                     "Only queues 0-%d will be in RSS table\n",
 425                                     BNXT_RSS_TBL_SIZE_P5 - 1);
 426                 }
 427
 428                 rc = 0;
 429                 for (j = 0; j < nr_ctxs; j++) {
 430                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 431                         if (rc)
 432                                 break;
 433                 }
 434                 if (rc) {
 435                         PMD_DRV_LOG(ERR,
 436                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 437                                     vnic_id, j, rc);
 438                         goto err_out;
 439                 }
 440                 vnic->num_lb_ctxts = nr_ctxs;
 441         }
 442
 443         /*
 444          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 445          * setting is not available at this time, it will not be
 446          * configured correctly in the CFA.
 447          */
 448         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 449                 vnic->vlan_strip = true;
 450         else
 451                 vnic->vlan_strip = false;
 452
 453         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 454         if (rc)
 455                 goto err_out;
 456
 457         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 458         if (rc)
 459                 goto err_out;
 460
 461         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 462                 rxq = bp->eth_dev->data->rx_queues[j];
 463
 464                 PMD_DRV_LOG(DEBUG,
 465                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 466                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 467
 468                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 469                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 470                 else
 471                         vnic->rx_queue_cnt++;
 472         }
 473
 474         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 475
 476         rc = bnxt_vnic_rss_configure(bp, vnic);
 477         if (rc)
 478                 goto err_out;
 479
 480         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 481
 482         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 483                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 484         else
 485                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 486
 487         return 0;
 488 err_out:
 489         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 490                     vnic_id, rc);
 491         return rc;
 492 }
 493
 494 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 495 {
 496         int rc = 0;
 497
 498         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 499                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 500         if (rc)
 501                 return rc;
 502
 503         PMD_DRV_LOG(DEBUG,
 504                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 505                     " rx_fc_in_tbl.ctx_id = %d\n",
 506                     bp->flow_stat->rx_fc_in_tbl.va,
 507                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 508                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 509
 510         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 511                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 512         if (rc)
 513                 return rc;
 514
 515         PMD_DRV_LOG(DEBUG,
 516                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 517                     " rx_fc_out_tbl.ctx_id = %d\n",
 518                     bp->flow_stat->rx_fc_out_tbl.va,
 519                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 520                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 521
 522         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 523                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 524         if (rc)
 525                 return rc;
 526
 527         PMD_DRV_LOG(DEBUG,
 528                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 529                     " tx_fc_in_tbl.ctx_id = %d\n",
 530                     bp->flow_stat->tx_fc_in_tbl.va,
 531                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 532                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 533
 534         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 535                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 536         if (rc)
 537                 return rc;
 538
 539         PMD_DRV_LOG(DEBUG,
 540                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 541                     " tx_fc_out_tbl.ctx_id = %d\n",
 542                     bp->flow_stat->tx_fc_out_tbl.va,
 543                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 544                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 545
 546         memset(bp->flow_stat->rx_fc_out_tbl.va,
 547                0,
 548                bp->flow_stat->rx_fc_out_tbl.size);
 549         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 550                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 551                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 552                                        bp->flow_stat->max_fc,
 553                                        true);
 554         if (rc)
 555                 return rc;
 556
 557         memset(bp->flow_stat->tx_fc_out_tbl.va,
 558                0,
 559                bp->flow_stat->tx_fc_out_tbl.size);
 560         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 561                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 562                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 563                                        bp->flow_stat->max_fc,
 564                                        true);
 565
 566         return rc;
 567 }
 568
 569 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 570                                   struct bnxt_ctx_mem_buf_info *ctx)
 571 {
 572         if (!ctx)
 573                 return -EINVAL;
 574
 575         ctx->va = rte_zmalloc(type, size, 0);
 576         if (ctx->va == NULL)
 577                 return -ENOMEM;
 578         rte_mem_lock_page(ctx->va);
 579         ctx->size = size;
 580         ctx->dma = rte_mem_virt2iova(ctx->va);
 581         if (ctx->dma == RTE_BAD_IOVA)
 582                 return -ENOMEM;
 583
 584         return 0;
 585 }
 586
 587 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 588 {
 589         struct rte_pci_device *pdev = bp->pdev;
 590         char type[RTE_MEMZONE_NAMESIZE];
 591         uint16_t max_fc;
 592         int rc = 0;
 593
 594         max_fc = bp->flow_stat->max_fc;
 595
 596         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 597                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 598         /* 4 bytes for each counter-id */
 599         rc = bnxt_alloc_ctx_mem_buf(type,
 600                                     max_fc * 4,
 601                                     &bp->flow_stat->rx_fc_in_tbl);
 602         if (rc)
 603                 return rc;
 604
 605         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 606                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 607         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 608         rc = bnxt_alloc_ctx_mem_buf(type,
 609                                     max_fc * 16,
 610                                     &bp->flow_stat->rx_fc_out_tbl);
 611         if (rc)
 612                 return rc;
 613
 614         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 615                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 616         /* 4 bytes for each counter-id */
 617         rc = bnxt_alloc_ctx_mem_buf(type,
 618                                     max_fc * 4,
 619                                     &bp->flow_stat->tx_fc_in_tbl);
 620         if (rc)
 621                 return rc;
 622
 623         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 624                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 625         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 626         rc = bnxt_alloc_ctx_mem_buf(type,
 627                                     max_fc * 16,
 628                                     &bp->flow_stat->tx_fc_out_tbl);
 629         if (rc)
 630                 return rc;
 631
 632         rc = bnxt_register_fc_ctx_mem(bp);
 633
 634         return rc;
 635 }
 636
 637 static int bnxt_init_ctx_mem(struct bnxt *bp)
 638 {
 639         int rc = 0;
 640
 641         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 642             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 643             !BNXT_FLOW_XSTATS_EN(bp))
 644                 return 0;
 645
 646         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 647         if (rc)
 648                 return rc;
 649
 650         rc = bnxt_init_fc_ctx_mem(bp);
 651
 652         return rc;
 653 }
 654
 655 static int bnxt_update_phy_setting(struct bnxt *bp)
 656 {
 657         struct rte_eth_link new;
 658         int rc;
 659
 660         rc = bnxt_get_hwrm_link_config(bp, &new);
 661         if (rc) {
 662                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 663                 return rc;
 664         }
 665
 666         /*
 667          * On BCM957508-N2100 adapters, FW will not allow any user other
 668          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 669          * always returns link up. Force phy update always in that case.
 670          */
 671         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 672                 rc = bnxt_set_hwrm_link_config(bp, true);
 673                 if (rc) {
 674                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 675                         return rc;
 676                 }
 677         }
 678
 679         return rc;
 680 }
 681
 682 static int bnxt_init_chip(struct bnxt *bp)
 683 {
 684         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 685         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 686         uint32_t intr_vector = 0;
 687         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 688         uint32_t vec = BNXT_MISC_VEC_ID;
 689         unsigned int i, j;
 690         int rc;
 691
 692         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 693                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 694                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 695                 bp->flags |= BNXT_FLAG_JUMBO;
 696         } else {
 697                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 698                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 699                 bp->flags &= ~BNXT_FLAG_JUMBO;
 700         }
 701
 702         /* THOR does not support ring groups.
 703          * But we will use the array to save RSS context IDs.
 704          */
 705         if (BNXT_CHIP_P5(bp))
 706                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
 707
 708         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 709         if (rc) {
 710                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 711                 goto err_out;
 712         }
 713
 714         rc = bnxt_alloc_hwrm_rings(bp);
 715         if (rc) {
 716                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 717                 goto err_out;
 718         }
 719
 720         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 721         if (rc) {
 722                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 723                 goto err_out;
 724         }
 725
 726         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 727                 goto skip_cosq_cfg;
 728
 729         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 730                 if (bp->rx_cos_queue[i].id != 0xff) {
 731                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 732
 733                         if (!vnic) {
 734                                 PMD_DRV_LOG(ERR,
 735                                             "Num pools more than FW profile\n");
 736                                 rc = -EINVAL;
 737                                 goto err_out;
 738                         }
 739                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 740                         bp->rx_cosq_cnt++;
 741                 }
 742         }
 743
 744 skip_cosq_cfg:
 745         rc = bnxt_mq_rx_configure(bp);
 746         if (rc) {
 747                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 748                 goto err_out;
 749         }
 750
 751         /* VNIC configuration */
 752         for (i = 0; i < bp->nr_vnics; i++) {
 753                 rc = bnxt_setup_one_vnic(bp, i);
 754                 if (rc)
 755                         goto err_out;
 756         }
 757
 758         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 759         if (rc) {
 760                 PMD_DRV_LOG(ERR,
 761                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 762                 goto err_out;
 763         }
 764
 765         /* check and configure queue intr-vector mapping */
 766         if ((rte_intr_cap_multiple(intr_handle) ||
 767              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 768             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 769                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 770                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 771                 if (intr_vector > bp->rx_cp_nr_rings) {
 772                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 773                                         bp->rx_cp_nr_rings);
 774                         return -ENOTSUP;
 775                 }
 776                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 777                 if (rc)
 778                         return rc;
 779         }
 780
 781         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 782                 intr_handle->intr_vec =
 783                         rte_zmalloc("intr_vec",
 784                                     bp->eth_dev->data->nb_rx_queues *
 785                                     sizeof(int), 0);
 786                 if (intr_handle->intr_vec == NULL) {
 787                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 788                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 789                         rc = -ENOMEM;
 790                         goto err_disable;
 791                 }
 792                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 793                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 794                          intr_handle->intr_vec, intr_handle->nb_efd,
 795                         intr_handle->max_intr);
 796                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 797                      queue_id++) {
 798                         intr_handle->intr_vec[queue_id] =
 799                                                         vec + BNXT_RX_VEC_START;
 800                         if (vec < base + intr_handle->nb_efd - 1)
 801                                 vec++;
 802                 }
 803         }
 804
 805         /* enable uio/vfio intr/eventfd mapping */
 806         rc = rte_intr_enable(intr_handle);
 807 #ifndef RTE_EXEC_ENV_FREEBSD
 808         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 809         if (rc)
 810                 goto err_free;
 811 #endif
 812
 813         rc = bnxt_update_phy_setting(bp);
 814         if (rc)
 815                 goto err_free;
 816
 817         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 818         if (!bp->mark_table)
 819                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 820
 821         return 0;
 822
 823 err_free:
 824         rte_free(intr_handle->intr_vec);
 825 err_disable:
 826         rte_intr_efd_disable(intr_handle);
 827 err_out:
 828         /* Some of the error status returned by FW may not be from errno.h */
 829         if (rc > 0)
 830                 rc = -EIO;
 831
 832         return rc;
 833 }
 834
 835 static int bnxt_shutdown_nic(struct bnxt *bp)
 836 {
 837         bnxt_free_all_hwrm_resources(bp);
 838         bnxt_free_all_filters(bp);
 839         bnxt_free_all_vnics(bp);
 840         return 0;
 841 }
 842
 843 /*
 844  * Device configuration and status function
 845  */
 846
 847 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 848 {
 849         uint32_t link_speed = bp->link_info->support_speeds;
 850         uint32_t speed_capa = 0;
 851
 852         /* If PAM4 is configured, use PAM4 supported speed */
 853         if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
 854                 link_speed = bp->link_info->support_pam4_speeds;
 855
 856         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 857                 speed_capa |= ETH_LINK_SPEED_100M;
 858         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 859                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 860         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 861                 speed_capa |= ETH_LINK_SPEED_1G;
 862         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 863                 speed_capa |= ETH_LINK_SPEED_2_5G;
 864         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 865                 speed_capa |= ETH_LINK_SPEED_10G;
 866         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 867                 speed_capa |= ETH_LINK_SPEED_20G;
 868         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 869                 speed_capa |= ETH_LINK_SPEED_25G;
 870         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 871                 speed_capa |= ETH_LINK_SPEED_40G;
 872         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 873                 speed_capa |= ETH_LINK_SPEED_50G;
 874         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 875                 speed_capa |= ETH_LINK_SPEED_100G;
 876         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 877                 speed_capa |= ETH_LINK_SPEED_50G;
 878         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 879                 speed_capa |= ETH_LINK_SPEED_100G;
 880         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 881                 speed_capa |= ETH_LINK_SPEED_200G;
 882
 883         if (bp->link_info->auto_mode ==
 884             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 885                 speed_capa |= ETH_LINK_SPEED_FIXED;
 886         else
 887                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 888
 889         return speed_capa;
 890 }
 891
 892 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 893                                 struct rte_eth_dev_info *dev_info)
 894 {
 895         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 896         struct bnxt *bp = eth_dev->data->dev_private;
 897         uint16_t max_vnics, i, j, vpool, vrxq;
 898         unsigned int max_rx_rings;
 899         int rc;
 900
 901         rc = is_bnxt_in_error(bp);
 902         if (rc)
 903                 return rc;
 904
 905         /* MAC Specifics */
 906         dev_info->max_mac_addrs = bp->max_l2_ctx;
 907         dev_info->max_hash_mac_addrs = 0;
 908
 909         /* PF/VF specifics */
 910         if (BNXT_PF(bp))
 911                 dev_info->max_vfs = pdev->max_vfs;
 912
 913         max_rx_rings = bnxt_max_rings(bp);
 914         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 915         dev_info->max_rx_queues = max_rx_rings;
 916         dev_info->max_tx_queues = max_rx_rings;
 917         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 918         dev_info->hash_key_size = 40;
 919         max_vnics = bp->max_vnics;
 920
 921         /* MTU specifics */
 922         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 923         dev_info->max_mtu = BNXT_MAX_MTU;
 924
 925         /* Fast path specifics */
 926         dev_info->min_rx_bufsize = 1;
 927         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 928
 929         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 930         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 931                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 932         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 933         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
 934                                     dev_info->tx_queue_offload_capa;
 935         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 936
 937         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 938
 939         /* *INDENT-OFF* */
 940         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 941                 .rx_thresh = {
 942                         .pthresh = 8,
 943                         .hthresh = 8,
 944                         .wthresh = 0,
 945                 },
 946                 .rx_free_thresh = 32,
 947                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 948         };
 949
 950         dev_info->default_txconf = (struct rte_eth_txconf) {
 951                 .tx_thresh = {
 952                         .pthresh = 32,
 953                         .hthresh = 0,
 954                         .wthresh = 0,
 955                 },
 956                 .tx_free_thresh = 32,
 957                 .tx_rs_thresh = 32,
 958         };
 959         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 960
 961         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 962         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 963         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 964         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 965         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 966
 967         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 968                 dev_info->switch_info.name = eth_dev->device->name;
 969                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 970                 dev_info->switch_info.port_id =
 971                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 972                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 973         }
 974
 975         /* *INDENT-ON* */
 976
 977         /*
 978          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 979          *       need further investigation.
 980          */
 981
 982         /* VMDq resources */
 983         vpool = 64; /* ETH_64_POOLS */
 984         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 985         for (i = 0; i < 4; vpool >>= 1, i++) {
 986                 if (max_vnics > vpool) {
 987                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 988                                 if (dev_info->max_rx_queues > vrxq) {
 989                                         if (vpool > vrxq)
 990                                                 vpool = vrxq;
 991                                         goto found;
 992                                 }
 993                         }
 994                         /* Not enough resources to support VMDq */
 995                         break;
 996                 }
 997         }
 998         /* Not enough resources to support VMDq */
 999         vpool = 0;
1000         vrxq = 0;
1001 found:
1002         dev_info->max_vmdq_pools = vpool;
1003         dev_info->vmdq_queue_num = vrxq;
1004
1005         dev_info->vmdq_pool_base = 0;
1006         dev_info->vmdq_queue_base = 0;
1007
1008         return 0;
1009 }
1010
1011 /* Configure the device based on the configuration provided */
1012 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1013 {
1014         struct bnxt *bp = eth_dev->data->dev_private;
1015         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1016         int rc;
1017
1018         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1019         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1020         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1021         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1022
1023         rc = is_bnxt_in_error(bp);
1024         if (rc)
1025                 return rc;
1026
1027         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1028                 rc = bnxt_hwrm_check_vf_rings(bp);
1029                 if (rc) {
1030                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1031                         return -ENOSPC;
1032                 }
1033
1034                 /* If a resource has already been allocated - in this case
1035                  * it is the async completion ring, free it. Reallocate it after
1036                  * resource reservation. This will ensure the resource counts
1037                  * are calculated correctly.
1038                  */
1039
1040                 pthread_mutex_lock(&bp->def_cp_lock);
1041
1042                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1043                         bnxt_disable_int(bp);
1044                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1045                 }
1046
1047                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1048                 if (rc) {
1049                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1050                         pthread_mutex_unlock(&bp->def_cp_lock);
1051                         return -ENOSPC;
1052                 }
1053
1054                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1055                         rc = bnxt_alloc_async_cp_ring(bp);
1056                         if (rc) {
1057                                 pthread_mutex_unlock(&bp->def_cp_lock);
1058                                 return rc;
1059                         }
1060                         bnxt_enable_int(bp);
1061                 }
1062
1063                 pthread_mutex_unlock(&bp->def_cp_lock);
1064         }
1065
1066         /* Inherit new configurations */
1067         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1068             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1069             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1070                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1071             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1072             bp->max_stat_ctx)
1073                 goto resource_error;
1074
1075         if (BNXT_HAS_RING_GRPS(bp) &&
1076             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1077                 goto resource_error;
1078
1079         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1080             bp->max_vnics < eth_dev->data->nb_rx_queues)
1081                 goto resource_error;
1082
1083         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1084         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1085
1086         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1087                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1088         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1089
1090         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1091                 eth_dev->data->mtu =
1092                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1093                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1094                         BNXT_NUM_VLANS;
1095                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1096         }
1097         return 0;
1098
1099 resource_error:
1100         PMD_DRV_LOG(ERR,
1101                     "Insufficient resources to support requested config\n");
1102         PMD_DRV_LOG(ERR,
1103                     "Num Queues Requested: Tx %d, Rx %d\n",
1104                     eth_dev->data->nb_tx_queues,
1105                     eth_dev->data->nb_rx_queues);
1106         PMD_DRV_LOG(ERR,
1107                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1108                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1109                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1110         return -ENOSPC;
1111 }
1112
1113 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1114 {
1115         struct rte_eth_link *link = &eth_dev->data->dev_link;
1116
1117         if (link->link_status)
1118                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1119                         eth_dev->data->port_id,
1120                         (uint32_t)link->link_speed,
1121                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1122                         ("full-duplex") : ("half-duplex\n"));
1123         else
1124                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1125                         eth_dev->data->port_id);
1126 }
1127
1128 /*
1129  * Determine whether the current configuration requires support for scattered
1130  * receive; return 1 if scattered receive is required and 0 if not.
1131  */
1132 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1133 {
1134         uint16_t buf_size;
1135         int i;
1136
1137         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1138                 return 1;
1139
1140         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1141                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1142
1143                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1144                                       RTE_PKTMBUF_HEADROOM);
1145                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1146                         return 1;
1147         }
1148         return 0;
1149 }
1150
1151 static eth_rx_burst_t
1152 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1153 {
1154         struct bnxt *bp = eth_dev->data->dev_private;
1155
1156 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1157 #ifndef RTE_LIBRTE_IEEE1588
1158         /*
1159          * Vector mode receive can be enabled only if scatter rx is not
1160          * in use and rx offloads are limited to VLAN stripping and
1161          * CRC stripping.
1162          */
1163         if (!eth_dev->data->scattered_rx &&
1164             !(eth_dev->data->dev_conf.rxmode.offloads &
1165               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1166                 DEV_RX_OFFLOAD_KEEP_CRC |
1167                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1168                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1169                 DEV_RX_OFFLOAD_UDP_CKSUM |
1170                 DEV_RX_OFFLOAD_TCP_CKSUM |
1171                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1172                 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1173                 DEV_RX_OFFLOAD_RSS_HASH |
1174                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1175             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1176             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1177                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1178                             eth_dev->data->port_id);
1179                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1180                 return bnxt_recv_pkts_vec;
1181         }
1182         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1183                     eth_dev->data->port_id);
1184         PMD_DRV_LOG(INFO,
1185                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1186                     eth_dev->data->port_id,
1187                     eth_dev->data->scattered_rx,
1188                     eth_dev->data->dev_conf.rxmode.offloads);
1189 #endif
1190 #endif
1191         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1192         return bnxt_recv_pkts;
1193 }
1194
1195 static eth_tx_burst_t
1196 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1197 {
1198 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1199 #ifndef RTE_LIBRTE_IEEE1588
1200         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1201         struct bnxt *bp = eth_dev->data->dev_private;
1202
1203         /*
1204          * Vector mode transmit can be enabled only if not using scatter rx
1205          * or tx offloads.
1206          */
1207         if (!eth_dev->data->scattered_rx &&
1208             !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1209             !BNXT_TRUFLOW_EN(bp) &&
1210             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1211                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1212                             eth_dev->data->port_id);
1213                 return bnxt_xmit_pkts_vec;
1214         }
1215         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1216                     eth_dev->data->port_id);
1217         PMD_DRV_LOG(INFO,
1218                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1219                     eth_dev->data->port_id,
1220                     eth_dev->data->scattered_rx,
1221                     offloads);
1222 #endif
1223 #endif
1224         return bnxt_xmit_pkts;
1225 }
1226
1227 static int bnxt_handle_if_change_status(struct bnxt *bp)
1228 {
1229         int rc;
1230
1231         /* Since fw has undergone a reset and lost all contexts,
1232          * set fatal flag to not issue hwrm during cleanup
1233          */
1234         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1235         bnxt_uninit_resources(bp, true);
1236
1237         /* clear fatal flag so that re-init happens */
1238         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1239         rc = bnxt_init_resources(bp, true);
1240
1241         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1242
1243         return rc;
1244 }
1245
1246 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1247 {
1248         struct bnxt *bp = eth_dev->data->dev_private;
1249         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1250         int vlan_mask = 0;
1251         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1252
1253         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1254                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1255                 return -EINVAL;
1256         }
1257
1258         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1259                 PMD_DRV_LOG(ERR,
1260                             "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1261                             bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1262
1263         do {
1264                 rc = bnxt_hwrm_if_change(bp, true);
1265                 if (rc == 0 || rc != -EAGAIN)
1266                         break;
1267
1268                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1269         } while (retry_cnt--);
1270
1271         if (rc)
1272                 return rc;
1273
1274         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1275                 rc = bnxt_handle_if_change_status(bp);
1276                 if (rc)
1277                         return rc;
1278         }
1279
1280         bnxt_enable_int(bp);
1281
1282         rc = bnxt_init_chip(bp);
1283         if (rc)
1284                 goto error;
1285
1286         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1287         eth_dev->data->dev_started = 1;
1288
1289         bnxt_link_update_op(eth_dev, 1);
1290
1291         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1292                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1293         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1294                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1295         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1296         if (rc)
1297                 goto error;
1298
1299         /* Initialize bnxt ULP port details */
1300         rc = bnxt_ulp_port_init(bp);
1301         if (rc)
1302                 goto error;
1303
1304         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1305         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1306
1307         bnxt_schedule_fw_health_check(bp);
1308
1309         return 0;
1310
1311 error:
1312         bnxt_shutdown_nic(bp);
1313         bnxt_free_tx_mbufs(bp);
1314         bnxt_free_rx_mbufs(bp);
1315         bnxt_hwrm_if_change(bp, false);
1316         eth_dev->data->dev_started = 0;
1317         return rc;
1318 }
1319
1320 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1321 {
1322         struct bnxt *bp = eth_dev->data->dev_private;
1323         int rc = 0;
1324
1325         if (!bp->link_info->link_up)
1326                 rc = bnxt_set_hwrm_link_config(bp, true);
1327         if (!rc)
1328                 eth_dev->data->dev_link.link_status = 1;
1329
1330         bnxt_print_link_info(eth_dev);
1331         return rc;
1332 }
1333
1334 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1335 {
1336         struct bnxt *bp = eth_dev->data->dev_private;
1337
1338         eth_dev->data->dev_link.link_status = 0;
1339         bnxt_set_hwrm_link_config(bp, false);
1340         bp->link_info->link_up = 0;
1341
1342         return 0;
1343 }
1344
1345 static void bnxt_free_switch_domain(struct bnxt *bp)
1346 {
1347         int rc = 0;
1348
1349         if (bp->switch_domain_id) {
1350                 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1351                 if (rc)
1352                         PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1353                                     bp->switch_domain_id, rc);
1354         }
1355 }
1356
1357 /* Unload the driver, release resources */
1358 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1359 {
1360         struct bnxt *bp = eth_dev->data->dev_private;
1361         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1362         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1363         struct rte_eth_link link;
1364         int ret;
1365
1366         eth_dev->data->dev_started = 0;
1367         eth_dev->data->scattered_rx = 0;
1368
1369         /* Prevent crashes when queues are still in use */
1370         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1371         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1372
1373         bnxt_disable_int(bp);
1374
1375         /* disable uio/vfio intr/eventfd mapping */
1376         rte_intr_disable(intr_handle);
1377
1378         /* Stop the child representors for this device */
1379         ret = bnxt_rep_stop_all(bp);
1380         if (ret != 0)
1381                 return ret;
1382
1383         /* delete the bnxt ULP port details */
1384         bnxt_ulp_port_deinit(bp);
1385
1386         bnxt_cancel_fw_health_check(bp);
1387
1388         /* Do not bring link down during reset recovery */
1389         if (!is_bnxt_in_error(bp)) {
1390                 bnxt_dev_set_link_down_op(eth_dev);
1391                 /* Wait for link to be reset */
1392                 if (BNXT_SINGLE_PF(bp))
1393                         rte_delay_ms(500);
1394                 /* clear the recorded link status */
1395                 memset(&link, 0, sizeof(link));
1396                 rte_eth_linkstatus_set(eth_dev, &link);
1397         }
1398
1399         /* Clean queue intr-vector mapping */
1400         rte_intr_efd_disable(intr_handle);
1401         if (intr_handle->intr_vec != NULL) {
1402                 rte_free(intr_handle->intr_vec);
1403                 intr_handle->intr_vec = NULL;
1404         }
1405
1406         bnxt_hwrm_port_clr_stats(bp);
1407         bnxt_free_tx_mbufs(bp);
1408         bnxt_free_rx_mbufs(bp);
1409         /* Process any remaining notifications in default completion queue */
1410         bnxt_int_handler(eth_dev);
1411         bnxt_shutdown_nic(bp);
1412         bnxt_hwrm_if_change(bp, false);
1413
1414         rte_free(bp->mark_table);
1415         bp->mark_table = NULL;
1416
1417         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1418         bp->rx_cosq_cnt = 0;
1419         /* All filters are deleted on a port stop. */
1420         if (BNXT_FLOW_XSTATS_EN(bp))
1421                 bp->flow_stat->flow_count = 0;
1422
1423         return 0;
1424 }
1425
1426 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1427 {
1428         struct bnxt *bp = eth_dev->data->dev_private;
1429         int ret = 0;
1430
1431         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1432                 return 0;
1433
1434         /* cancel the recovery handler before remove dev */
1435         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1436         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1437         bnxt_cancel_fc_thread(bp);
1438
1439         if (eth_dev->data->dev_started)
1440                 ret = bnxt_dev_stop_op(eth_dev);
1441
1442         bnxt_free_switch_domain(bp);
1443
1444         bnxt_uninit_resources(bp, false);
1445
1446         bnxt_free_leds_info(bp);
1447         bnxt_free_cos_queues(bp);
1448         bnxt_free_link_info(bp);
1449         bnxt_free_pf_info(bp);
1450         bnxt_free_parent_info(bp);
1451
1452         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1453         bp->tx_mem_zone = NULL;
1454         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1455         bp->rx_mem_zone = NULL;
1456
1457         bnxt_hwrm_free_vf_info(bp);
1458
1459         rte_free(bp->grp_info);
1460         bp->grp_info = NULL;
1461
1462         return ret;
1463 }
1464
1465 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1466                                     uint32_t index)
1467 {
1468         struct bnxt *bp = eth_dev->data->dev_private;
1469         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1470         struct bnxt_vnic_info *vnic;
1471         struct bnxt_filter_info *filter, *temp_filter;
1472         uint32_t i;
1473
1474         if (is_bnxt_in_error(bp))
1475                 return;
1476
1477         /*
1478          * Loop through all VNICs from the specified filter flow pools to
1479          * remove the corresponding MAC addr filter
1480          */
1481         for (i = 0; i < bp->nr_vnics; i++) {
1482                 if (!(pool_mask & (1ULL << i)))
1483                         continue;
1484
1485                 vnic = &bp->vnic_info[i];
1486                 filter = STAILQ_FIRST(&vnic->filter);
1487                 while (filter) {
1488                         temp_filter = STAILQ_NEXT(filter, next);
1489                         if (filter->mac_index == index) {
1490                                 STAILQ_REMOVE(&vnic->filter, filter,
1491                                                 bnxt_filter_info, next);
1492                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1493                                 bnxt_free_filter(bp, filter);
1494                         }
1495                         filter = temp_filter;
1496                 }
1497         }
1498 }
1499
1500 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1501                                struct rte_ether_addr *mac_addr, uint32_t index,
1502                                uint32_t pool)
1503 {
1504         struct bnxt_filter_info *filter;
1505         int rc = 0;
1506
1507         /* Attach requested MAC address to the new l2_filter */
1508         STAILQ_FOREACH(filter, &vnic->filter, next) {
1509                 if (filter->mac_index == index) {
1510                         PMD_DRV_LOG(DEBUG,
1511                                     "MAC addr already existed for pool %d\n",
1512                                     pool);
1513                         return 0;
1514                 }
1515         }
1516
1517         filter = bnxt_alloc_filter(bp);
1518         if (!filter) {
1519                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1520                 return -ENODEV;
1521         }
1522
1523         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1524          * if the MAC that's been programmed now is a different one, then,
1525          * copy that addr to filter->l2_addr
1526          */
1527         if (mac_addr)
1528                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1529         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1530
1531         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1532         if (!rc) {
1533                 filter->mac_index = index;
1534                 if (filter->mac_index == 0)
1535                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1536                 else
1537                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1538         } else {
1539                 bnxt_free_filter(bp, filter);
1540         }
1541
1542         return rc;
1543 }
1544
1545 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1546                                 struct rte_ether_addr *mac_addr,
1547                                 uint32_t index, uint32_t pool)
1548 {
1549         struct bnxt *bp = eth_dev->data->dev_private;
1550         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1551         int rc = 0;
1552
1553         rc = is_bnxt_in_error(bp);
1554         if (rc)
1555                 return rc;
1556
1557         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1558                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1559                 return -ENOTSUP;
1560         }
1561
1562         if (!vnic) {
1563                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1564                 return -EINVAL;
1565         }
1566
1567         /* Filter settings will get applied when port is started */
1568         if (!eth_dev->data->dev_started)
1569                 return 0;
1570
1571         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1572
1573         return rc;
1574 }
1575
1576 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1577 {
1578         int rc = 0;
1579         struct bnxt *bp = eth_dev->data->dev_private;
1580         struct rte_eth_link new;
1581         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1582                         BNXT_MIN_LINK_WAIT_CNT;
1583
1584         rc = is_bnxt_in_error(bp);
1585         if (rc)
1586                 return rc;
1587
1588         memset(&new, 0, sizeof(new));
1589         do {
1590                 /* Retrieve link info from hardware */
1591                 rc = bnxt_get_hwrm_link_config(bp, &new);
1592                 if (rc) {
1593                         new.link_speed = ETH_LINK_SPEED_100M;
1594                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1595                         PMD_DRV_LOG(ERR,
1596                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1597                         goto out;
1598                 }
1599
1600                 if (!wait_to_complete || new.link_status)
1601                         break;
1602
1603                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1604         } while (cnt--);
1605
1606         /* Only single function PF can bring phy down.
1607          * When port is stopped, report link down for VF/MH/NPAR functions.
1608          */
1609         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1610                 memset(&new, 0, sizeof(new));
1611
1612 out:
1613         /* Timed out or success */
1614         if (new.link_status != eth_dev->data->dev_link.link_status ||
1615             new.link_speed != eth_dev->data->dev_link.link_speed) {
1616                 rte_eth_linkstatus_set(eth_dev, &new);
1617
1618                 rte_eth_dev_callback_process(eth_dev,
1619                                              RTE_ETH_EVENT_INTR_LSC,
1620                                              NULL);
1621
1622                 bnxt_print_link_info(eth_dev);
1623         }
1624
1625         return rc;
1626 }
1627
1628 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1629 {
1630         struct bnxt *bp = eth_dev->data->dev_private;
1631         struct bnxt_vnic_info *vnic;
1632         uint32_t old_flags;
1633         int rc;
1634
1635         rc = is_bnxt_in_error(bp);
1636         if (rc)
1637                 return rc;
1638
1639         /* Filter settings will get applied when port is started */
1640         if (!eth_dev->data->dev_started)
1641                 return 0;
1642
1643         if (bp->vnic_info == NULL)
1644                 return 0;
1645
1646         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1647
1648         old_flags = vnic->flags;
1649         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1650         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1651         if (rc != 0)
1652                 vnic->flags = old_flags;
1653
1654         return rc;
1655 }
1656
1657 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1658 {
1659         struct bnxt *bp = eth_dev->data->dev_private;
1660         struct bnxt_vnic_info *vnic;
1661         uint32_t old_flags;
1662         int rc;
1663
1664         rc = is_bnxt_in_error(bp);
1665         if (rc)
1666                 return rc;
1667
1668         /* Filter settings will get applied when port is started */
1669         if (!eth_dev->data->dev_started)
1670                 return 0;
1671
1672         if (bp->vnic_info == NULL)
1673                 return 0;
1674
1675         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1676
1677         old_flags = vnic->flags;
1678         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1679         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1680         if (rc != 0)
1681                 vnic->flags = old_flags;
1682
1683         return rc;
1684 }
1685
1686 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1687 {
1688         struct bnxt *bp = eth_dev->data->dev_private;
1689         struct bnxt_vnic_info *vnic;
1690         uint32_t old_flags;
1691         int rc;
1692
1693         rc = is_bnxt_in_error(bp);
1694         if (rc)
1695                 return rc;
1696
1697         /* Filter settings will get applied when port is started */
1698         if (!eth_dev->data->dev_started)
1699                 return 0;
1700
1701         if (bp->vnic_info == NULL)
1702                 return 0;
1703
1704         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1705
1706         old_flags = vnic->flags;
1707         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1708         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1709         if (rc != 0)
1710                 vnic->flags = old_flags;
1711
1712         return rc;
1713 }
1714
1715 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1716 {
1717         struct bnxt *bp = eth_dev->data->dev_private;
1718         struct bnxt_vnic_info *vnic;
1719         uint32_t old_flags;
1720         int rc;
1721
1722         rc = is_bnxt_in_error(bp);
1723         if (rc)
1724                 return rc;
1725
1726         /* Filter settings will get applied when port is started */
1727         if (!eth_dev->data->dev_started)
1728                 return 0;
1729
1730         if (bp->vnic_info == NULL)
1731                 return 0;
1732
1733         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1734
1735         old_flags = vnic->flags;
1736         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1737         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1738         if (rc != 0)
1739                 vnic->flags = old_flags;
1740
1741         return rc;
1742 }
1743
1744 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1745 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1746 {
1747         if (qid >= bp->rx_nr_rings)
1748                 return NULL;
1749
1750         return bp->eth_dev->data->rx_queues[qid];
1751 }
1752
1753 /* Return rxq corresponding to a given rss table ring/group ID. */
1754 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1755 {
1756         struct bnxt_rx_queue *rxq;
1757         unsigned int i;
1758
1759         if (!BNXT_HAS_RING_GRPS(bp)) {
1760                 for (i = 0; i < bp->rx_nr_rings; i++) {
1761                         rxq = bp->eth_dev->data->rx_queues[i];
1762                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1763                                 return rxq->index;
1764                 }
1765         } else {
1766                 for (i = 0; i < bp->rx_nr_rings; i++) {
1767                         if (bp->grp_info[i].fw_grp_id == fwr)
1768                                 return i;
1769                 }
1770         }
1771
1772         return INVALID_HW_RING_ID;
1773 }
1774
1775 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1776                             struct rte_eth_rss_reta_entry64 *reta_conf,
1777                             uint16_t reta_size)
1778 {
1779         struct bnxt *bp = eth_dev->data->dev_private;
1780         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1781         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1782         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1783         uint16_t idx, sft;
1784         int i, rc;
1785
1786         rc = is_bnxt_in_error(bp);
1787         if (rc)
1788                 return rc;
1789
1790         if (!vnic->rss_table)
1791                 return -EINVAL;
1792
1793         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1794                 return -EINVAL;
1795
1796         if (reta_size != tbl_size) {
1797                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1798                         "(%d) must equal the size supported by the hardware "
1799                         "(%d)\n", reta_size, tbl_size);
1800                 return -EINVAL;
1801         }
1802
1803         for (i = 0; i < reta_size; i++) {
1804                 struct bnxt_rx_queue *rxq;
1805
1806                 idx = i / RTE_RETA_GROUP_SIZE;
1807                 sft = i % RTE_RETA_GROUP_SIZE;
1808
1809                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1810                         continue;
1811
1812                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1813                 if (!rxq) {
1814                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1815                         return -EINVAL;
1816                 }
1817
1818                 if (BNXT_CHIP_P5(bp)) {
1819                         vnic->rss_table[i * 2] =
1820                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1821                         vnic->rss_table[i * 2 + 1] =
1822                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1823                 } else {
1824                         vnic->rss_table[i] =
1825                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1826                 }
1827         }
1828
1829         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1830         return rc;
1831 }
1832
1833 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1834                               struct rte_eth_rss_reta_entry64 *reta_conf,
1835                               uint16_t reta_size)
1836 {
1837         struct bnxt *bp = eth_dev->data->dev_private;
1838         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1839         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1840         uint16_t idx, sft, i;
1841         int rc;
1842
1843         rc = is_bnxt_in_error(bp);
1844         if (rc)
1845                 return rc;
1846
1847         /* Retrieve from the default VNIC */
1848         if (!vnic)
1849                 return -EINVAL;
1850         if (!vnic->rss_table)
1851                 return -EINVAL;
1852
1853         if (reta_size != tbl_size) {
1854                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1855                         "(%d) must equal the size supported by the hardware "
1856                         "(%d)\n", reta_size, tbl_size);
1857                 return -EINVAL;
1858         }
1859
1860         for (idx = 0, i = 0; i < reta_size; i++) {
1861                 idx = i / RTE_RETA_GROUP_SIZE;
1862                 sft = i % RTE_RETA_GROUP_SIZE;
1863
1864                 if (reta_conf[idx].mask & (1ULL << sft)) {
1865                         uint16_t qid;
1866
1867                         if (BNXT_CHIP_P5(bp))
1868                                 qid = bnxt_rss_to_qid(bp,
1869                                                       vnic->rss_table[i * 2]);
1870                         else
1871                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1872
1873                         if (qid == INVALID_HW_RING_ID) {
1874                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1875                                 return -EINVAL;
1876                         }
1877                         reta_conf[idx].reta[sft] = qid;
1878                 }
1879         }
1880
1881         return 0;
1882 }
1883
1884 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1885                                    struct rte_eth_rss_conf *rss_conf)
1886 {
1887         struct bnxt *bp = eth_dev->data->dev_private;
1888         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1889         struct bnxt_vnic_info *vnic;
1890         int rc;
1891
1892         rc = is_bnxt_in_error(bp);
1893         if (rc)
1894                 return rc;
1895
1896         /*
1897          * If RSS enablement were different than dev_configure,
1898          * then return -EINVAL
1899          */
1900         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1901                 if (!rss_conf->rss_hf)
1902                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1903         } else {
1904                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1905                         return -EINVAL;
1906         }
1907
1908         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1909         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1910                rss_conf,
1911                sizeof(*rss_conf));
1912
1913         /* Update the default RSS VNIC(s) */
1914         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1915         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1916         vnic->hash_mode =
1917                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
1918                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
1919
1920         /*
1921          * If hashkey is not specified, use the previously configured
1922          * hashkey
1923          */
1924         if (!rss_conf->rss_key)
1925                 goto rss_config;
1926
1927         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1928                 PMD_DRV_LOG(ERR,
1929                             "Invalid hashkey length, should be 16 bytes\n");
1930                 return -EINVAL;
1931         }
1932         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1933
1934 rss_config:
1935         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1936         return rc;
1937 }
1938
1939 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1940                                      struct rte_eth_rss_conf *rss_conf)
1941 {
1942         struct bnxt *bp = eth_dev->data->dev_private;
1943         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1944         int len, rc;
1945         uint32_t hash_types;
1946
1947         rc = is_bnxt_in_error(bp);
1948         if (rc)
1949                 return rc;
1950
1951         /* RSS configuration is the same for all VNICs */
1952         if (vnic && vnic->rss_hash_key) {
1953                 if (rss_conf->rss_key) {
1954                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1955                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1956                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1957                 }
1958
1959                 hash_types = vnic->hash_type;
1960                 rss_conf->rss_hf = 0;
1961                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1962                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1963                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1964                 }
1965                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1966                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1967                         hash_types &=
1968                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1969                 }
1970                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1971                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1972                         hash_types &=
1973                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1974                 }
1975                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1976                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1977                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1978                 }
1979                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1980                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1981                         hash_types &=
1982                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1983                 }
1984                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1985                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1986                         hash_types &=
1987                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1988                 }
1989
1990                 rss_conf->rss_hf |=
1991                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
1992
1993                 if (hash_types) {
1994                         PMD_DRV_LOG(ERR,
1995                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1996                                 vnic->hash_type);
1997                         return -ENOTSUP;
1998                 }
1999         } else {
2000                 rss_conf->rss_hf = 0;
2001         }
2002         return 0;
2003 }
2004
2005 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2006                                struct rte_eth_fc_conf *fc_conf)
2007 {
2008         struct bnxt *bp = dev->data->dev_private;
2009         struct rte_eth_link link_info;
2010         int rc;
2011
2012         rc = is_bnxt_in_error(bp);
2013         if (rc)
2014                 return rc;
2015
2016         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2017         if (rc)
2018                 return rc;
2019
2020         memset(fc_conf, 0, sizeof(*fc_conf));
2021         if (bp->link_info->auto_pause)
2022                 fc_conf->autoneg = 1;
2023         switch (bp->link_info->pause) {
2024         case 0:
2025                 fc_conf->mode = RTE_FC_NONE;
2026                 break;
2027         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2028                 fc_conf->mode = RTE_FC_TX_PAUSE;
2029                 break;
2030         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2031                 fc_conf->mode = RTE_FC_RX_PAUSE;
2032                 break;
2033         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2034                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2035                 fc_conf->mode = RTE_FC_FULL;
2036                 break;
2037         }
2038         return 0;
2039 }
2040
2041 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2042                                struct rte_eth_fc_conf *fc_conf)
2043 {
2044         struct bnxt *bp = dev->data->dev_private;
2045         int rc;
2046
2047         rc = is_bnxt_in_error(bp);
2048         if (rc)
2049                 return rc;
2050
2051         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2052                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2053                 return -ENOTSUP;
2054         }
2055
2056         switch (fc_conf->mode) {
2057         case RTE_FC_NONE:
2058                 bp->link_info->auto_pause = 0;
2059                 bp->link_info->force_pause = 0;
2060                 break;
2061         case RTE_FC_RX_PAUSE:
2062                 if (fc_conf->autoneg) {
2063                         bp->link_info->auto_pause =
2064                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2065                         bp->link_info->force_pause = 0;
2066                 } else {
2067                         bp->link_info->auto_pause = 0;
2068                         bp->link_info->force_pause =
2069                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2070                 }
2071                 break;
2072         case RTE_FC_TX_PAUSE:
2073                 if (fc_conf->autoneg) {
2074                         bp->link_info->auto_pause =
2075                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2076                         bp->link_info->force_pause = 0;
2077                 } else {
2078                         bp->link_info->auto_pause = 0;
2079                         bp->link_info->force_pause =
2080                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2081                 }
2082                 break;
2083         case RTE_FC_FULL:
2084                 if (fc_conf->autoneg) {
2085                         bp->link_info->auto_pause =
2086                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2087                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2088                         bp->link_info->force_pause = 0;
2089                 } else {
2090                         bp->link_info->auto_pause = 0;
2091                         bp->link_info->force_pause =
2092                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2093                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2094                 }
2095                 break;
2096         }
2097         return bnxt_set_hwrm_link_config(bp, true);
2098 }
2099
2100 /* Add UDP tunneling port */
2101 static int
2102 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2103                          struct rte_eth_udp_tunnel *udp_tunnel)
2104 {
2105         struct bnxt *bp = eth_dev->data->dev_private;
2106         uint16_t tunnel_type = 0;
2107         int rc = 0;
2108
2109         rc = is_bnxt_in_error(bp);
2110         if (rc)
2111                 return rc;
2112
2113         switch (udp_tunnel->prot_type) {
2114         case RTE_TUNNEL_TYPE_VXLAN:
2115                 if (bp->vxlan_port_cnt) {
2116                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2117                                 udp_tunnel->udp_port);
2118                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2119                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2120                                 return -ENOSPC;
2121                         }
2122                         bp->vxlan_port_cnt++;
2123                         return 0;
2124                 }
2125                 tunnel_type =
2126                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2127                 bp->vxlan_port_cnt++;
2128                 break;
2129         case RTE_TUNNEL_TYPE_GENEVE:
2130                 if (bp->geneve_port_cnt) {
2131                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2132                                 udp_tunnel->udp_port);
2133                         if (bp->geneve_port != udp_tunnel->udp_port) {
2134                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2135                                 return -ENOSPC;
2136                         }
2137                         bp->geneve_port_cnt++;
2138                         return 0;
2139                 }
2140                 tunnel_type =
2141                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2142                 bp->geneve_port_cnt++;
2143                 break;
2144         default:
2145                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2146                 return -ENOTSUP;
2147         }
2148         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2149                                              tunnel_type);
2150         return rc;
2151 }
2152
2153 static int
2154 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2155                          struct rte_eth_udp_tunnel *udp_tunnel)
2156 {
2157         struct bnxt *bp = eth_dev->data->dev_private;
2158         uint16_t tunnel_type = 0;
2159         uint16_t port = 0;
2160         int rc = 0;
2161
2162         rc = is_bnxt_in_error(bp);
2163         if (rc)
2164                 return rc;
2165
2166         switch (udp_tunnel->prot_type) {
2167         case RTE_TUNNEL_TYPE_VXLAN:
2168                 if (!bp->vxlan_port_cnt) {
2169                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2170                         return -EINVAL;
2171                 }
2172                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2173                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2174                                 udp_tunnel->udp_port, bp->vxlan_port);
2175                         return -EINVAL;
2176                 }
2177                 if (--bp->vxlan_port_cnt)
2178                         return 0;
2179
2180                 tunnel_type =
2181                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2182                 port = bp->vxlan_fw_dst_port_id;
2183                 break;
2184         case RTE_TUNNEL_TYPE_GENEVE:
2185                 if (!bp->geneve_port_cnt) {
2186                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2187                         return -EINVAL;
2188                 }
2189                 if (bp->geneve_port != udp_tunnel->udp_port) {
2190                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2191                                 udp_tunnel->udp_port, bp->geneve_port);
2192                         return -EINVAL;
2193                 }
2194                 if (--bp->geneve_port_cnt)
2195                         return 0;
2196
2197                 tunnel_type =
2198                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2199                 port = bp->geneve_fw_dst_port_id;
2200                 break;
2201         default:
2202                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2203                 return -ENOTSUP;
2204         }
2205
2206         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2207         return rc;
2208 }
2209
2210 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2211 {
2212         struct bnxt_filter_info *filter;
2213         struct bnxt_vnic_info *vnic;
2214         int rc = 0;
2215         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2216
2217         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2218         filter = STAILQ_FIRST(&vnic->filter);
2219         while (filter) {
2220                 /* Search for this matching MAC+VLAN filter */
2221                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2222                         /* Delete the filter */
2223                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2224                         if (rc)
2225                                 return rc;
2226                         STAILQ_REMOVE(&vnic->filter, filter,
2227                                       bnxt_filter_info, next);
2228                         bnxt_free_filter(bp, filter);
2229                         PMD_DRV_LOG(INFO,
2230                                     "Deleted vlan filter for %d\n",
2231                                     vlan_id);
2232                         return 0;
2233                 }
2234                 filter = STAILQ_NEXT(filter, next);
2235         }
2236         return -ENOENT;
2237 }
2238
2239 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2240 {
2241         struct bnxt_filter_info *filter;
2242         struct bnxt_vnic_info *vnic;
2243         int rc = 0;
2244         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2245                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2246         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2247
2248         /* Implementation notes on the use of VNIC in this command:
2249          *
2250          * By default, these filters belong to default vnic for the function.
2251          * Once these filters are set up, only destination VNIC can be modified.
2252          * If the destination VNIC is not specified in this command,
2253          * then the HWRM shall only create an l2 context id.
2254          */
2255
2256         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2257         filter = STAILQ_FIRST(&vnic->filter);
2258         /* Check if the VLAN has already been added */
2259         while (filter) {
2260                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2261                         return -EEXIST;
2262
2263                 filter = STAILQ_NEXT(filter, next);
2264         }
2265
2266         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2267          * command to create MAC+VLAN filter with the right flags, enables set.
2268          */
2269         filter = bnxt_alloc_filter(bp);
2270         if (!filter) {
2271                 PMD_DRV_LOG(ERR,
2272                             "MAC/VLAN filter alloc failed\n");
2273                 return -ENOMEM;
2274         }
2275         /* MAC + VLAN ID filter */
2276         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2277          * untagged packets are received
2278          *
2279          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2280          * packets and only the programmed vlan's packets are received
2281          */
2282         filter->l2_ivlan = vlan_id;
2283         filter->l2_ivlan_mask = 0x0FFF;
2284         filter->enables |= en;
2285         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2286
2287         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2288         if (rc) {
2289                 /* Free the newly allocated filter as we were
2290                  * not able to create the filter in hardware.
2291                  */
2292                 bnxt_free_filter(bp, filter);
2293                 return rc;
2294         }
2295
2296         filter->mac_index = 0;
2297         /* Add this new filter to the list */
2298         if (vlan_id == 0)
2299                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2300         else
2301                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2302
2303         PMD_DRV_LOG(INFO,
2304                     "Added Vlan filter for %d\n", vlan_id);
2305         return rc;
2306 }
2307
2308 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2309                 uint16_t vlan_id, int on)
2310 {
2311         struct bnxt *bp = eth_dev->data->dev_private;
2312         int rc;
2313
2314         rc = is_bnxt_in_error(bp);
2315         if (rc)
2316                 return rc;
2317
2318         if (!eth_dev->data->dev_started) {
2319                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2320                 return -EINVAL;
2321         }
2322
2323         /* These operations apply to ALL existing MAC/VLAN filters */
2324         if (on)
2325                 return bnxt_add_vlan_filter(bp, vlan_id);
2326         else
2327                 return bnxt_del_vlan_filter(bp, vlan_id);
2328 }
2329
2330 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2331                                     struct bnxt_vnic_info *vnic)
2332 {
2333         struct bnxt_filter_info *filter;
2334         int rc;
2335
2336         filter = STAILQ_FIRST(&vnic->filter);
2337         while (filter) {
2338                 if (filter->mac_index == 0 &&
2339                     !memcmp(filter->l2_addr, bp->mac_addr,
2340                             RTE_ETHER_ADDR_LEN)) {
2341                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2342                         if (!rc) {
2343                                 STAILQ_REMOVE(&vnic->filter, filter,
2344                                               bnxt_filter_info, next);
2345                                 bnxt_free_filter(bp, filter);
2346                         }
2347                         return rc;
2348                 }
2349                 filter = STAILQ_NEXT(filter, next);
2350         }
2351         return 0;
2352 }
2353
2354 static int
2355 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2356 {
2357         struct bnxt_vnic_info *vnic;
2358         unsigned int i;
2359         int rc;
2360
2361         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2362         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2363                 /* Remove any VLAN filters programmed */
2364                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2365                         bnxt_del_vlan_filter(bp, i);
2366
2367                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2368                 if (rc)
2369                         return rc;
2370         } else {
2371                 /* Default filter will allow packets that match the
2372                  * dest mac. So, it has to be deleted, otherwise, we
2373                  * will endup receiving vlan packets for which the
2374                  * filter is not programmed, when hw-vlan-filter
2375                  * configuration is ON
2376                  */
2377                 bnxt_del_dflt_mac_filter(bp, vnic);
2378                 /* This filter will allow only untagged packets */
2379                 bnxt_add_vlan_filter(bp, 0);
2380         }
2381         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2382                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2383
2384         return 0;
2385 }
2386
2387 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2388 {
2389         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2390         unsigned int i;
2391         int rc;
2392
2393         /* Destroy vnic filters and vnic */
2394         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2395             DEV_RX_OFFLOAD_VLAN_FILTER) {
2396                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2397                         bnxt_del_vlan_filter(bp, i);
2398         }
2399         bnxt_del_dflt_mac_filter(bp, vnic);
2400
2401         rc = bnxt_hwrm_vnic_free(bp, vnic);
2402         if (rc)
2403                 return rc;
2404
2405         rte_free(vnic->fw_grp_ids);
2406         vnic->fw_grp_ids = NULL;
2407
2408         vnic->rx_queue_cnt = 0;
2409
2410         return 0;
2411 }
2412
2413 static int
2414 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2415 {
2416         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2417         int rc;
2418
2419         /* Destroy, recreate and reconfigure the default vnic */
2420         rc = bnxt_free_one_vnic(bp, 0);
2421         if (rc)
2422                 return rc;
2423
2424         /* default vnic 0 */
2425         rc = bnxt_setup_one_vnic(bp, 0);
2426         if (rc)
2427                 return rc;
2428
2429         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2430             DEV_RX_OFFLOAD_VLAN_FILTER) {
2431                 rc = bnxt_add_vlan_filter(bp, 0);
2432                 if (rc)
2433                         return rc;
2434                 rc = bnxt_restore_vlan_filters(bp);
2435                 if (rc)
2436                         return rc;
2437         } else {
2438                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2439                 if (rc)
2440                         return rc;
2441         }
2442
2443         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2444         if (rc)
2445                 return rc;
2446
2447         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2448                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2449
2450         return rc;
2451 }
2452
2453 static int
2454 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2455 {
2456         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2457         struct bnxt *bp = dev->data->dev_private;
2458         int rc;
2459
2460         rc = is_bnxt_in_error(bp);
2461         if (rc)
2462                 return rc;
2463
2464         /* Filter settings will get applied when port is started */
2465         if (!dev->data->dev_started)
2466                 return 0;
2467
2468         if (mask & ETH_VLAN_FILTER_MASK) {
2469                 /* Enable or disable VLAN filtering */
2470                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2471                 if (rc)
2472                         return rc;
2473         }
2474
2475         if (mask & ETH_VLAN_STRIP_MASK) {
2476                 /* Enable or disable VLAN stripping */
2477                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2478                 if (rc)
2479                         return rc;
2480         }
2481
2482         if (mask & ETH_VLAN_EXTEND_MASK) {
2483                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2484                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2485                 else
2486                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2487         }
2488
2489         return 0;
2490 }
2491
2492 static int
2493 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2494                       uint16_t tpid)
2495 {
2496         struct bnxt *bp = dev->data->dev_private;
2497         int qinq = dev->data->dev_conf.rxmode.offloads &
2498                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2499
2500         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2501             vlan_type != ETH_VLAN_TYPE_OUTER) {
2502                 PMD_DRV_LOG(ERR,
2503                             "Unsupported vlan type.");
2504                 return -EINVAL;
2505         }
2506         if (!qinq) {
2507                 PMD_DRV_LOG(ERR,
2508                             "QinQ not enabled. Needs to be ON as we can "
2509                             "accelerate only outer vlan\n");
2510                 return -EINVAL;
2511         }
2512
2513         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2514                 switch (tpid) {
2515                 case RTE_ETHER_TYPE_QINQ:
2516                         bp->outer_tpid_bd =
2517                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2518                                 break;
2519                 case RTE_ETHER_TYPE_VLAN:
2520                         bp->outer_tpid_bd =
2521                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2522                                 break;
2523                 case RTE_ETHER_TYPE_QINQ1:
2524                         bp->outer_tpid_bd =
2525                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2526                                 break;
2527                 case RTE_ETHER_TYPE_QINQ2:
2528                         bp->outer_tpid_bd =
2529                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2530                                 break;
2531                 case RTE_ETHER_TYPE_QINQ3:
2532                         bp->outer_tpid_bd =
2533                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2534                                 break;
2535                 default:
2536                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2537                         return -EINVAL;
2538                 }
2539                 bp->outer_tpid_bd |= tpid;
2540                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2541         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2542                 PMD_DRV_LOG(ERR,
2543                             "Can accelerate only outer vlan in QinQ\n");
2544                 return -EINVAL;
2545         }
2546
2547         return 0;
2548 }
2549
2550 static int
2551 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2552                              struct rte_ether_addr *addr)
2553 {
2554         struct bnxt *bp = dev->data->dev_private;
2555         /* Default Filter is tied to VNIC 0 */
2556         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2557         int rc;
2558
2559         rc = is_bnxt_in_error(bp);
2560         if (rc)
2561                 return rc;
2562
2563         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2564                 return -EPERM;
2565
2566         if (rte_is_zero_ether_addr(addr))
2567                 return -EINVAL;
2568
2569         /* Filter settings will get applied when port is started */
2570         if (!dev->data->dev_started)
2571                 return 0;
2572
2573         /* Check if the requested MAC is already added */
2574         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2575                 return 0;
2576
2577         /* Destroy filter and re-create it */
2578         bnxt_del_dflt_mac_filter(bp, vnic);
2579
2580         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2581         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2582                 /* This filter will allow only untagged packets */
2583                 rc = bnxt_add_vlan_filter(bp, 0);
2584         } else {
2585                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2586         }
2587
2588         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2589         return rc;
2590 }
2591
2592 static int
2593 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2594                           struct rte_ether_addr *mc_addr_set,
2595                           uint32_t nb_mc_addr)
2596 {
2597         struct bnxt *bp = eth_dev->data->dev_private;
2598         char *mc_addr_list = (char *)mc_addr_set;
2599         struct bnxt_vnic_info *vnic;
2600         uint32_t off = 0, i = 0;
2601         int rc;
2602
2603         rc = is_bnxt_in_error(bp);
2604         if (rc)
2605                 return rc;
2606
2607         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2608
2609         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2610                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2611                 goto allmulti;
2612         }
2613
2614         /* TODO Check for Duplicate mcast addresses */
2615         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2616         for (i = 0; i < nb_mc_addr; i++) {
2617                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2618                         RTE_ETHER_ADDR_LEN);
2619                 off += RTE_ETHER_ADDR_LEN;
2620         }
2621
2622         vnic->mc_addr_cnt = i;
2623         if (vnic->mc_addr_cnt)
2624                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2625         else
2626                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2627
2628 allmulti:
2629         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2630 }
2631
2632 static int
2633 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2634 {
2635         struct bnxt *bp = dev->data->dev_private;
2636         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2637         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2638         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2639         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2640         int ret;
2641
2642         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2643                         fw_major, fw_minor, fw_updt, fw_rsvd);
2644
2645         ret += 1; /* add the size of '\0' */
2646         if (fw_size < (uint32_t)ret)
2647                 return ret;
2648         else
2649                 return 0;
2650 }
2651
2652 static void
2653 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2654         struct rte_eth_rxq_info *qinfo)
2655 {
2656         struct bnxt *bp = dev->data->dev_private;
2657         struct bnxt_rx_queue *rxq;
2658
2659         if (is_bnxt_in_error(bp))
2660                 return;
2661
2662         rxq = dev->data->rx_queues[queue_id];
2663
2664         qinfo->mp = rxq->mb_pool;
2665         qinfo->scattered_rx = dev->data->scattered_rx;
2666         qinfo->nb_desc = rxq->nb_rx_desc;
2667
2668         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2669         qinfo->conf.rx_drop_en = rxq->drop_en;
2670         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2671         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2672 }
2673
2674 static void
2675 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2676         struct rte_eth_txq_info *qinfo)
2677 {
2678         struct bnxt *bp = dev->data->dev_private;
2679         struct bnxt_tx_queue *txq;
2680
2681         if (is_bnxt_in_error(bp))
2682                 return;
2683
2684         txq = dev->data->tx_queues[queue_id];
2685
2686         qinfo->nb_desc = txq->nb_tx_desc;
2687
2688         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2689         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2690         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2691
2692         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2693         qinfo->conf.tx_rs_thresh = 0;
2694         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2695         qinfo->conf.offloads = txq->offloads;
2696 }
2697
2698 static const struct {
2699         eth_rx_burst_t pkt_burst;
2700         const char *info;
2701 } bnxt_rx_burst_info[] = {
2702         {bnxt_recv_pkts,        "Scalar"},
2703 #if defined(RTE_ARCH_X86)
2704         {bnxt_recv_pkts_vec,    "Vector SSE"},
2705 #elif defined(RTE_ARCH_ARM64)
2706         {bnxt_recv_pkts_vec,    "Vector Neon"},
2707 #endif
2708 };
2709
2710 static int
2711 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2712                        struct rte_eth_burst_mode *mode)
2713 {
2714         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2715         size_t i;
2716
2717         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2718                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2719                         snprintf(mode->info, sizeof(mode->info), "%s",
2720                                  bnxt_rx_burst_info[i].info);
2721                         return 0;
2722                 }
2723         }
2724
2725         return -EINVAL;
2726 }
2727
2728 static const struct {
2729         eth_tx_burst_t pkt_burst;
2730         const char *info;
2731 } bnxt_tx_burst_info[] = {
2732         {bnxt_xmit_pkts,        "Scalar"},
2733 #if defined(RTE_ARCH_X86)
2734         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2735 #elif defined(RTE_ARCH_ARM64)
2736         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2737 #endif
2738 };
2739
2740 static int
2741 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2742                        struct rte_eth_burst_mode *mode)
2743 {
2744         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2745         size_t i;
2746
2747         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2748                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2749                         snprintf(mode->info, sizeof(mode->info), "%s",
2750                                  bnxt_tx_burst_info[i].info);
2751                         return 0;
2752                 }
2753         }
2754
2755         return -EINVAL;
2756 }
2757
2758 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2759 {
2760         struct bnxt *bp = eth_dev->data->dev_private;
2761         uint32_t new_pkt_size;
2762         uint32_t rc = 0;
2763         uint32_t i;
2764
2765         rc = is_bnxt_in_error(bp);
2766         if (rc)
2767                 return rc;
2768
2769         /* Exit if receive queues are not configured yet */
2770         if (!eth_dev->data->nb_rx_queues)
2771                 return rc;
2772
2773         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2774                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2775
2776         /*
2777          * Disallow any MTU change that would require scattered receive support
2778          * if it is not already enabled.
2779          */
2780         if (eth_dev->data->dev_started &&
2781             !eth_dev->data->scattered_rx &&
2782             (new_pkt_size >
2783              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2784                 PMD_DRV_LOG(ERR,
2785                             "MTU change would require scattered rx support. ");
2786                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2787                 return -EINVAL;
2788         }
2789
2790         if (new_mtu > RTE_ETHER_MTU) {
2791                 bp->flags |= BNXT_FLAG_JUMBO;
2792                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2793                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2794         } else {
2795                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2796                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2797                 bp->flags &= ~BNXT_FLAG_JUMBO;
2798         }
2799
2800         /* Is there a change in mtu setting? */
2801         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2802                 return rc;
2803
2804         for (i = 0; i < bp->nr_vnics; i++) {
2805                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2806                 uint16_t size = 0;
2807
2808                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2809                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2810                 if (rc)
2811                         break;
2812
2813                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2814                 size -= RTE_PKTMBUF_HEADROOM;
2815
2816                 if (size < new_mtu) {
2817                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2818                         if (rc)
2819                                 return rc;
2820                 }
2821         }
2822
2823         if (!rc)
2824                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2825
2826         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2827
2828         return rc;
2829 }
2830
2831 static int
2832 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2833 {
2834         struct bnxt *bp = dev->data->dev_private;
2835         uint16_t vlan = bp->vlan;
2836         int rc;
2837
2838         rc = is_bnxt_in_error(bp);
2839         if (rc)
2840                 return rc;
2841
2842         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2843                 PMD_DRV_LOG(ERR,
2844                         "PVID cannot be modified for this function\n");
2845                 return -ENOTSUP;
2846         }
2847         bp->vlan = on ? pvid : 0;
2848
2849         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2850         if (rc)
2851                 bp->vlan = vlan;
2852         return rc;
2853 }
2854
2855 static int
2856 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2857 {
2858         struct bnxt *bp = dev->data->dev_private;
2859         int rc;
2860
2861         rc = is_bnxt_in_error(bp);
2862         if (rc)
2863                 return rc;
2864
2865         return bnxt_hwrm_port_led_cfg(bp, true);
2866 }
2867
2868 static int
2869 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2870 {
2871         struct bnxt *bp = dev->data->dev_private;
2872         int rc;
2873
2874         rc = is_bnxt_in_error(bp);
2875         if (rc)
2876                 return rc;
2877
2878         return bnxt_hwrm_port_led_cfg(bp, false);
2879 }
2880
2881 static uint32_t
2882 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2883 {
2884         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2885         uint32_t desc = 0, raw_cons = 0, cons;
2886         struct bnxt_cp_ring_info *cpr;
2887         struct bnxt_rx_queue *rxq;
2888         struct rx_pkt_cmpl *rxcmp;
2889         int rc;
2890
2891         rc = is_bnxt_in_error(bp);
2892         if (rc)
2893                 return rc;
2894
2895         rxq = dev->data->rx_queues[rx_queue_id];
2896         cpr = rxq->cp_ring;
2897         raw_cons = cpr->cp_raw_cons;
2898
2899         while (1) {
2900                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2901                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2902                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2903
2904                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2905                         break;
2906                 } else {
2907                         raw_cons++;
2908                         desc++;
2909                 }
2910         }
2911
2912         return desc;
2913 }
2914
2915 static int
2916 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2917 {
2918         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2919         struct bnxt_rx_ring_info *rxr;
2920         struct bnxt_cp_ring_info *cpr;
2921         struct rte_mbuf *rx_buf;
2922         struct rx_pkt_cmpl *rxcmp;
2923         uint32_t cons, cp_cons;
2924         int rc;
2925
2926         if (!rxq)
2927                 return -EINVAL;
2928
2929         rc = is_bnxt_in_error(rxq->bp);
2930         if (rc)
2931                 return rc;
2932
2933         cpr = rxq->cp_ring;
2934         rxr = rxq->rx_ring;
2935
2936         if (offset >= rxq->nb_rx_desc)
2937                 return -EINVAL;
2938
2939         cons = RING_CMP(cpr->cp_ring_struct, offset);
2940         cp_cons = cpr->cp_raw_cons;
2941         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2942
2943         if (cons > cp_cons) {
2944                 if (CMPL_VALID(rxcmp, cpr->valid))
2945                         return RTE_ETH_RX_DESC_DONE;
2946         } else {
2947                 if (CMPL_VALID(rxcmp, !cpr->valid))
2948                         return RTE_ETH_RX_DESC_DONE;
2949         }
2950         rx_buf = rxr->rx_buf_ring[cons];
2951         if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2952                 return RTE_ETH_RX_DESC_UNAVAIL;
2953
2954
2955         return RTE_ETH_RX_DESC_AVAIL;
2956 }
2957
2958 static int
2959 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2960 {
2961         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2962         struct bnxt_tx_ring_info *txr;
2963         struct bnxt_cp_ring_info *cpr;
2964         struct bnxt_sw_tx_bd *tx_buf;
2965         struct tx_pkt_cmpl *txcmp;
2966         uint32_t cons, cp_cons;
2967         int rc;
2968
2969         if (!txq)
2970                 return -EINVAL;
2971
2972         rc = is_bnxt_in_error(txq->bp);
2973         if (rc)
2974                 return rc;
2975
2976         cpr = txq->cp_ring;
2977         txr = txq->tx_ring;
2978
2979         if (offset >= txq->nb_tx_desc)
2980                 return -EINVAL;
2981
2982         cons = RING_CMP(cpr->cp_ring_struct, offset);
2983         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2984         cp_cons = cpr->cp_raw_cons;
2985
2986         if (cons > cp_cons) {
2987                 if (CMPL_VALID(txcmp, cpr->valid))
2988                         return RTE_ETH_TX_DESC_UNAVAIL;
2989         } else {
2990                 if (CMPL_VALID(txcmp, !cpr->valid))
2991                         return RTE_ETH_TX_DESC_UNAVAIL;
2992         }
2993         tx_buf = &txr->tx_buf_ring[cons];
2994         if (tx_buf->mbuf == NULL)
2995                 return RTE_ETH_TX_DESC_DONE;
2996
2997         return RTE_ETH_TX_DESC_FULL;
2998 }
2999
3000 int
3001 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3002                     enum rte_filter_type filter_type,
3003                     enum rte_filter_op filter_op, void *arg)
3004 {
3005         struct bnxt *bp = dev->data->dev_private;
3006         int ret = 0;
3007
3008         if (!bp)
3009                 return -EIO;
3010
3011         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3012                 struct bnxt_representor *vfr = dev->data->dev_private;
3013                 bp = vfr->parent_dev->data->dev_private;
3014                 /* parent is deleted while children are still valid */
3015                 if (!bp) {
3016                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3017                                     dev->data->port_id,
3018                                     filter_type,
3019                                     filter_op);
3020                         return -EIO;
3021                 }
3022         }
3023
3024         ret = is_bnxt_in_error(bp);
3025         if (ret)
3026                 return ret;
3027
3028         switch (filter_type) {
3029         case RTE_ETH_FILTER_GENERIC:
3030                 if (filter_op != RTE_ETH_FILTER_GET)
3031                         return -EINVAL;
3032
3033                 /* PMD supports thread-safe flow operations.  rte_flow API
3034                  * functions can avoid mutex for multi-thread safety.
3035                  */
3036                 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3037
3038                 if (BNXT_TRUFLOW_EN(bp))
3039                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3040                 else
3041                         *(const void **)arg = &bnxt_flow_ops;
3042                 break;
3043         default:
3044                 PMD_DRV_LOG(ERR,
3045                         "Filter type (%d) not supported", filter_type);
3046                 ret = -EINVAL;
3047                 break;
3048         }
3049         return ret;
3050 }
3051
3052 static const uint32_t *
3053 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3054 {
3055         static const uint32_t ptypes[] = {
3056                 RTE_PTYPE_L2_ETHER_VLAN,
3057                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3058                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3059                 RTE_PTYPE_L4_ICMP,
3060                 RTE_PTYPE_L4_TCP,
3061                 RTE_PTYPE_L4_UDP,
3062                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3063                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3064                 RTE_PTYPE_INNER_L4_ICMP,
3065                 RTE_PTYPE_INNER_L4_TCP,
3066                 RTE_PTYPE_INNER_L4_UDP,
3067                 RTE_PTYPE_UNKNOWN
3068         };
3069
3070         if (!dev->rx_pkt_burst)
3071                 return NULL;
3072
3073         return ptypes;
3074 }
3075
3076 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3077                          int reg_win)
3078 {
3079         uint32_t reg_base = *reg_arr & 0xfffff000;
3080         uint32_t win_off;
3081         int i;
3082
3083         for (i = 0; i < count; i++) {
3084                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3085                         return -ERANGE;
3086         }
3087         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3088         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3089         return 0;
3090 }
3091
3092 static int bnxt_map_ptp_regs(struct bnxt *bp)
3093 {
3094         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3095         uint32_t *reg_arr;
3096         int rc, i;
3097
3098         reg_arr = ptp->rx_regs;
3099         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3100         if (rc)
3101                 return rc;
3102
3103         reg_arr = ptp->tx_regs;
3104         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3105         if (rc)
3106                 return rc;
3107
3108         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3109                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3110
3111         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3112                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3113
3114         return 0;
3115 }
3116
3117 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3118 {
3119         rte_write32(0, (uint8_t *)bp->bar0 +
3120                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3121         rte_write32(0, (uint8_t *)bp->bar0 +
3122                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3123 }
3124
3125 static uint64_t bnxt_cc_read(struct bnxt *bp)
3126 {
3127         uint64_t ns;
3128
3129         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3130                               BNXT_GRCPF_REG_SYNC_TIME));
3131         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3132                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3133         return ns;
3134 }
3135
3136 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3137 {
3138         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3139         uint32_t fifo;
3140
3141         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3142                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3143         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3144                 return -EAGAIN;
3145
3146         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3147                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3148         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3149                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3150         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3151                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3152
3153         return 0;
3154 }
3155
3156 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3157 {
3158         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3159         struct bnxt_pf_info *pf = bp->pf;
3160         uint16_t port_id;
3161         uint32_t fifo;
3162
3163         if (!ptp)
3164                 return -ENODEV;
3165
3166         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3167                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3168         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3169                 return -EAGAIN;
3170
3171         port_id = pf->port_id;
3172         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3173                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3174
3175         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3176                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3177         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3178 /*              bnxt_clr_rx_ts(bp);       TBD  */
3179                 return -EBUSY;
3180         }
3181
3182         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3183                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3184         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3185                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3186
3187         return 0;
3188 }
3189
3190 static int
3191 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3192 {
3193         uint64_t ns;
3194         struct bnxt *bp = dev->data->dev_private;
3195         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3196
3197         if (!ptp)
3198                 return 0;
3199
3200         ns = rte_timespec_to_ns(ts);
3201         /* Set the timecounters to a new value. */
3202         ptp->tc.nsec = ns;
3203
3204         return 0;
3205 }
3206
3207 static int
3208 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3209 {
3210         struct bnxt *bp = dev->data->dev_private;
3211         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3212         uint64_t ns, systime_cycles = 0;
3213         int rc = 0;
3214
3215         if (!ptp)
3216                 return 0;
3217
3218         if (BNXT_CHIP_P5(bp))
3219                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3220                                              &systime_cycles);
3221         else
3222                 systime_cycles = bnxt_cc_read(bp);
3223
3224         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3225         *ts = rte_ns_to_timespec(ns);
3226
3227         return rc;
3228 }
3229 static int
3230 bnxt_timesync_enable(struct rte_eth_dev *dev)
3231 {
3232         struct bnxt *bp = dev->data->dev_private;
3233         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3234         uint32_t shift = 0;
3235         int rc;
3236
3237         if (!ptp)
3238                 return 0;
3239
3240         ptp->rx_filter = 1;
3241         ptp->tx_tstamp_en = 1;
3242         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3243
3244         rc = bnxt_hwrm_ptp_cfg(bp);
3245         if (rc)
3246                 return rc;
3247
3248         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3249         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3250         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3251
3252         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3253         ptp->tc.cc_shift = shift;
3254         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3255
3256         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3257         ptp->rx_tstamp_tc.cc_shift = shift;
3258         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3259
3260         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3261         ptp->tx_tstamp_tc.cc_shift = shift;
3262         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3263
3264         if (!BNXT_CHIP_P5(bp))
3265                 bnxt_map_ptp_regs(bp);
3266
3267         return 0;
3268 }
3269
3270 static int
3271 bnxt_timesync_disable(struct rte_eth_dev *dev)
3272 {
3273         struct bnxt *bp = dev->data->dev_private;
3274         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3275
3276         if (!ptp)
3277                 return 0;
3278
3279         ptp->rx_filter = 0;
3280         ptp->tx_tstamp_en = 0;
3281         ptp->rxctl = 0;
3282
3283         bnxt_hwrm_ptp_cfg(bp);
3284
3285         if (!BNXT_CHIP_P5(bp))
3286                 bnxt_unmap_ptp_regs(bp);
3287
3288         return 0;
3289 }
3290
3291 static int
3292 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3293                                  struct timespec *timestamp,
3294                                  uint32_t flags __rte_unused)
3295 {
3296         struct bnxt *bp = dev->data->dev_private;
3297         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3298         uint64_t rx_tstamp_cycles = 0;
3299         uint64_t ns;
3300
3301         if (!ptp)
3302                 return 0;
3303
3304         if (BNXT_CHIP_P5(bp))
3305                 rx_tstamp_cycles = ptp->rx_timestamp;
3306         else
3307                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3308
3309         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3310         *timestamp = rte_ns_to_timespec(ns);
3311         return  0;
3312 }
3313
3314 static int
3315 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3316                                  struct timespec *timestamp)
3317 {
3318         struct bnxt *bp = dev->data->dev_private;
3319         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3320         uint64_t tx_tstamp_cycles = 0;
3321         uint64_t ns;
3322         int rc = 0;
3323
3324         if (!ptp)
3325                 return 0;
3326
3327         if (BNXT_CHIP_P5(bp))
3328                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3329                                              &tx_tstamp_cycles);
3330         else
3331                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3332
3333         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3334         *timestamp = rte_ns_to_timespec(ns);
3335
3336         return rc;
3337 }
3338
3339 static int
3340 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3341 {
3342         struct bnxt *bp = dev->data->dev_private;
3343         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3344
3345         if (!ptp)
3346                 return 0;
3347
3348         ptp->tc.nsec += delta;
3349
3350         return 0;
3351 }
3352
3353 static int
3354 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3355 {
3356         struct bnxt *bp = dev->data->dev_private;
3357         int rc;
3358         uint32_t dir_entries;
3359         uint32_t entry_length;
3360
3361         rc = is_bnxt_in_error(bp);
3362         if (rc)
3363                 return rc;
3364
3365         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3366                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3367                     bp->pdev->addr.devid, bp->pdev->addr.function);
3368
3369         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3370         if (rc != 0)
3371                 return rc;
3372
3373         return dir_entries * entry_length;
3374 }
3375
3376 static int
3377 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3378                 struct rte_dev_eeprom_info *in_eeprom)
3379 {
3380         struct bnxt *bp = dev->data->dev_private;
3381         uint32_t index;
3382         uint32_t offset;
3383         int rc;
3384
3385         rc = is_bnxt_in_error(bp);
3386         if (rc)
3387                 return rc;
3388
3389         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3390                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3391                     bp->pdev->addr.devid, bp->pdev->addr.function,
3392                     in_eeprom->offset, in_eeprom->length);
3393
3394         if (in_eeprom->offset == 0) /* special offset value to get directory */
3395                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3396                                                 in_eeprom->data);
3397
3398         index = in_eeprom->offset >> 24;
3399         offset = in_eeprom->offset & 0xffffff;
3400
3401         if (index != 0)
3402                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3403                                            in_eeprom->length, in_eeprom->data);
3404
3405         return 0;
3406 }
3407
3408 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3409 {
3410         switch (dir_type) {
3411         case BNX_DIR_TYPE_CHIMP_PATCH:
3412         case BNX_DIR_TYPE_BOOTCODE:
3413         case BNX_DIR_TYPE_BOOTCODE_2:
3414         case BNX_DIR_TYPE_APE_FW:
3415         case BNX_DIR_TYPE_APE_PATCH:
3416         case BNX_DIR_TYPE_KONG_FW:
3417         case BNX_DIR_TYPE_KONG_PATCH:
3418         case BNX_DIR_TYPE_BONO_FW:
3419         case BNX_DIR_TYPE_BONO_PATCH:
3420                 /* FALLTHROUGH */
3421                 return true;
3422         }
3423
3424         return false;
3425 }
3426
3427 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3428 {
3429         switch (dir_type) {
3430         case BNX_DIR_TYPE_AVS:
3431         case BNX_DIR_TYPE_EXP_ROM_MBA:
3432         case BNX_DIR_TYPE_PCIE:
3433         case BNX_DIR_TYPE_TSCF_UCODE:
3434         case BNX_DIR_TYPE_EXT_PHY:
3435         case BNX_DIR_TYPE_CCM:
3436         case BNX_DIR_TYPE_ISCSI_BOOT:
3437         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3438         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3439                 /* FALLTHROUGH */
3440                 return true;
3441         }
3442
3443         return false;
3444 }
3445
3446 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3447 {
3448         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3449                 bnxt_dir_type_is_other_exec_format(dir_type);
3450 }
3451
3452 static int
3453 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3454                 struct rte_dev_eeprom_info *in_eeprom)
3455 {
3456         struct bnxt *bp = dev->data->dev_private;
3457         uint8_t index, dir_op;
3458         uint16_t type, ext, ordinal, attr;
3459         int rc;
3460
3461         rc = is_bnxt_in_error(bp);
3462         if (rc)
3463                 return rc;
3464
3465         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3466                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3467                     bp->pdev->addr.devid, bp->pdev->addr.function,
3468                     in_eeprom->offset, in_eeprom->length);
3469
3470         if (!BNXT_PF(bp)) {
3471                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3472                 return -EINVAL;
3473         }
3474
3475         type = in_eeprom->magic >> 16;
3476
3477         if (type == 0xffff) { /* special value for directory operations */
3478                 index = in_eeprom->magic & 0xff;
3479                 dir_op = in_eeprom->magic >> 8;
3480                 if (index == 0)
3481                         return -EINVAL;
3482                 switch (dir_op) {
3483                 case 0x0e: /* erase */
3484                         if (in_eeprom->offset != ~in_eeprom->magic)
3485                                 return -EINVAL;
3486                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3487                 default:
3488                         return -EINVAL;
3489                 }
3490         }
3491
3492         /* Create or re-write an NVM item: */
3493         if (bnxt_dir_type_is_executable(type) == true)
3494                 return -EOPNOTSUPP;
3495         ext = in_eeprom->magic & 0xffff;
3496         ordinal = in_eeprom->offset >> 16;
3497         attr = in_eeprom->offset & 0xffff;
3498
3499         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3500                                      in_eeprom->data, in_eeprom->length);
3501 }
3502
3503 /*
3504  * Initialization
3505  */
3506
3507 static const struct eth_dev_ops bnxt_dev_ops = {
3508         .dev_infos_get = bnxt_dev_info_get_op,
3509         .dev_close = bnxt_dev_close_op,
3510         .dev_configure = bnxt_dev_configure_op,
3511         .dev_start = bnxt_dev_start_op,
3512         .dev_stop = bnxt_dev_stop_op,
3513         .dev_set_link_up = bnxt_dev_set_link_up_op,
3514         .dev_set_link_down = bnxt_dev_set_link_down_op,
3515         .stats_get = bnxt_stats_get_op,
3516         .stats_reset = bnxt_stats_reset_op,
3517         .rx_queue_setup = bnxt_rx_queue_setup_op,
3518         .rx_queue_release = bnxt_rx_queue_release_op,
3519         .tx_queue_setup = bnxt_tx_queue_setup_op,
3520         .tx_queue_release = bnxt_tx_queue_release_op,
3521         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3522         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3523         .reta_update = bnxt_reta_update_op,
3524         .reta_query = bnxt_reta_query_op,
3525         .rss_hash_update = bnxt_rss_hash_update_op,
3526         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3527         .link_update = bnxt_link_update_op,
3528         .promiscuous_enable = bnxt_promiscuous_enable_op,
3529         .promiscuous_disable = bnxt_promiscuous_disable_op,
3530         .allmulticast_enable = bnxt_allmulticast_enable_op,
3531         .allmulticast_disable = bnxt_allmulticast_disable_op,
3532         .mac_addr_add = bnxt_mac_addr_add_op,
3533         .mac_addr_remove = bnxt_mac_addr_remove_op,
3534         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3535         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3536         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3537         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3538         .vlan_filter_set = bnxt_vlan_filter_set_op,
3539         .vlan_offload_set = bnxt_vlan_offload_set_op,
3540         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3541         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3542         .mtu_set = bnxt_mtu_set_op,
3543         .mac_addr_set = bnxt_set_default_mac_addr_op,
3544         .xstats_get = bnxt_dev_xstats_get_op,
3545         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3546         .xstats_reset = bnxt_dev_xstats_reset_op,
3547         .fw_version_get = bnxt_fw_version_get,
3548         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3549         .rxq_info_get = bnxt_rxq_info_get_op,
3550         .txq_info_get = bnxt_txq_info_get_op,
3551         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3552         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3553         .dev_led_on = bnxt_dev_led_on_op,
3554         .dev_led_off = bnxt_dev_led_off_op,
3555         .rx_queue_start = bnxt_rx_queue_start,
3556         .rx_queue_stop = bnxt_rx_queue_stop,
3557         .tx_queue_start = bnxt_tx_queue_start,
3558         .tx_queue_stop = bnxt_tx_queue_stop,
3559         .filter_ctrl = bnxt_filter_ctrl_op,
3560         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3561         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3562         .get_eeprom           = bnxt_get_eeprom_op,
3563         .set_eeprom           = bnxt_set_eeprom_op,
3564         .timesync_enable      = bnxt_timesync_enable,
3565         .timesync_disable     = bnxt_timesync_disable,
3566         .timesync_read_time   = bnxt_timesync_read_time,
3567         .timesync_write_time   = bnxt_timesync_write_time,
3568         .timesync_adjust_time = bnxt_timesync_adjust_time,
3569         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3570         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3571 };
3572
3573 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3574 {
3575         uint32_t offset;
3576
3577         /* Only pre-map the reset GRC registers using window 3 */
3578         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3579                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3580
3581         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3582
3583         return offset;
3584 }
3585
3586 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3587 {
3588         struct bnxt_error_recovery_info *info = bp->recovery_info;
3589         uint32_t reg_base = 0xffffffff;
3590         int i;
3591
3592         /* Only pre-map the monitoring GRC registers using window 2 */
3593         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3594                 uint32_t reg = info->status_regs[i];
3595
3596                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3597                         continue;
3598
3599                 if (reg_base == 0xffffffff)
3600                         reg_base = reg & 0xfffff000;
3601                 if ((reg & 0xfffff000) != reg_base)
3602                         return -ERANGE;
3603
3604                 /* Use mask 0xffc as the Lower 2 bits indicates
3605                  * address space location
3606                  */
3607                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3608                                                 (reg & 0xffc);
3609         }
3610
3611         if (reg_base == 0xffffffff)
3612                 return 0;
3613
3614         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3615                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3616
3617         return 0;
3618 }
3619
3620 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3621 {
3622         struct bnxt_error_recovery_info *info = bp->recovery_info;
3623         uint32_t delay = info->delay_after_reset[index];
3624         uint32_t val = info->reset_reg_val[index];
3625         uint32_t reg = info->reset_reg[index];
3626         uint32_t type, offset;
3627
3628         type = BNXT_FW_STATUS_REG_TYPE(reg);
3629         offset = BNXT_FW_STATUS_REG_OFF(reg);
3630
3631         switch (type) {
3632         case BNXT_FW_STATUS_REG_TYPE_CFG:
3633                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3634                 break;
3635         case BNXT_FW_STATUS_REG_TYPE_GRC:
3636                 offset = bnxt_map_reset_regs(bp, offset);
3637                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3638                 break;
3639         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3640                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3641                 break;
3642         }
3643         /* wait on a specific interval of time until core reset is complete */
3644         if (delay)
3645                 rte_delay_ms(delay);
3646 }
3647
3648 static void bnxt_dev_cleanup(struct bnxt *bp)
3649 {
3650         bp->eth_dev->data->dev_link.link_status = 0;
3651         bp->link_info->link_up = 0;
3652         if (bp->eth_dev->data->dev_started)
3653                 bnxt_dev_stop_op(bp->eth_dev);
3654
3655         bnxt_uninit_resources(bp, true);
3656 }
3657
3658 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3659 {
3660         struct rte_eth_dev *dev = bp->eth_dev;
3661         struct rte_vlan_filter_conf *vfc;
3662         int vidx, vbit, rc;
3663         uint16_t vlan_id;
3664
3665         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3666                 vfc = &dev->data->vlan_filter_conf;
3667                 vidx = vlan_id / 64;
3668                 vbit = vlan_id % 64;
3669
3670                 /* Each bit corresponds to a VLAN id */
3671                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3672                         rc = bnxt_add_vlan_filter(bp, vlan_id);
3673                         if (rc)
3674                                 return rc;
3675                 }
3676         }
3677
3678         return 0;
3679 }
3680
3681 static int bnxt_restore_mac_filters(struct bnxt *bp)
3682 {
3683         struct rte_eth_dev *dev = bp->eth_dev;
3684         struct rte_eth_dev_info dev_info;
3685         struct rte_ether_addr *addr;
3686         uint64_t pool_mask;
3687         uint32_t pool = 0;
3688         uint16_t i;
3689         int rc;
3690
3691         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3692                 return 0;
3693
3694         rc = bnxt_dev_info_get_op(dev, &dev_info);
3695         if (rc)
3696                 return rc;
3697
3698         /* replay MAC address configuration */
3699         for (i = 1; i < dev_info.max_mac_addrs; i++) {
3700                 addr = &dev->data->mac_addrs[i];
3701
3702                 /* skip zero address */
3703                 if (rte_is_zero_ether_addr(addr))
3704                         continue;
3705
3706                 pool = 0;
3707                 pool_mask = dev->data->mac_pool_sel[i];
3708
3709                 do {
3710                         if (pool_mask & 1ULL) {
3711                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3712                                 if (rc)
3713                                         return rc;
3714                         }
3715                         pool_mask >>= 1;
3716                         pool++;
3717                 } while (pool_mask);
3718         }
3719
3720         return 0;
3721 }
3722
3723 static int bnxt_restore_filters(struct bnxt *bp)
3724 {
3725         struct rte_eth_dev *dev = bp->eth_dev;
3726         int ret = 0;
3727
3728         if (dev->data->all_multicast) {
3729                 ret = bnxt_allmulticast_enable_op(dev);
3730                 if (ret)
3731                         return ret;
3732         }
3733         if (dev->data->promiscuous) {
3734                 ret = bnxt_promiscuous_enable_op(dev);
3735                 if (ret)
3736                         return ret;
3737         }
3738
3739         ret = bnxt_restore_mac_filters(bp);
3740         if (ret)
3741                 return ret;
3742
3743         ret = bnxt_restore_vlan_filters(bp);
3744         /* TODO restore other filters as well */
3745         return ret;
3746 }
3747
3748 static void bnxt_dev_recover(void *arg)
3749 {
3750         struct bnxt *bp = arg;
3751         int timeout = bp->fw_reset_max_msecs;
3752         int rc = 0;
3753
3754         /* Clear Error flag so that device re-init should happen */
3755         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3756
3757         do {
3758                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
3759                 if (rc == 0)
3760                         break;
3761                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3762                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3763         } while (rc && timeout);
3764
3765         if (rc) {
3766                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3767                 goto err;
3768         }
3769
3770         rc = bnxt_init_resources(bp, true);
3771         if (rc) {
3772                 PMD_DRV_LOG(ERR,
3773                             "Failed to initialize resources after reset\n");
3774                 goto err;
3775         }
3776         /* clear reset flag as the device is initialized now */
3777         bp->flags &= ~BNXT_FLAG_FW_RESET;
3778
3779         rc = bnxt_dev_start_op(bp->eth_dev);
3780         if (rc) {
3781                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3782                 goto err_start;
3783         }
3784
3785         rc = bnxt_restore_filters(bp);
3786         if (rc)
3787                 goto err_start;
3788
3789         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3790         return;
3791 err_start:
3792         bnxt_dev_stop_op(bp->eth_dev);
3793 err:
3794         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3795         bnxt_uninit_resources(bp, false);
3796         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3797 }
3798
3799 void bnxt_dev_reset_and_resume(void *arg)
3800 {
3801         struct bnxt *bp = arg;
3802         int rc;
3803
3804         bnxt_dev_cleanup(bp);
3805
3806         bnxt_wait_for_device_shutdown(bp);
3807
3808         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3809                                bnxt_dev_recover, (void *)bp);
3810         if (rc)
3811                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3812 }
3813
3814 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3815 {
3816         struct bnxt_error_recovery_info *info = bp->recovery_info;
3817         uint32_t reg = info->status_regs[index];
3818         uint32_t type, offset, val = 0;
3819
3820         type = BNXT_FW_STATUS_REG_TYPE(reg);
3821         offset = BNXT_FW_STATUS_REG_OFF(reg);
3822
3823         switch (type) {
3824         case BNXT_FW_STATUS_REG_TYPE_CFG:
3825                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3826                 break;
3827         case BNXT_FW_STATUS_REG_TYPE_GRC:
3828                 offset = info->mapped_status_regs[index];
3829                 /* FALLTHROUGH */
3830         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3831                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3832                                        offset));
3833                 break;
3834         }
3835
3836         return val;
3837 }
3838
3839 static int bnxt_fw_reset_all(struct bnxt *bp)
3840 {
3841         struct bnxt_error_recovery_info *info = bp->recovery_info;
3842         uint32_t i;
3843         int rc = 0;
3844
3845         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3846                 /* Reset through master function driver */
3847                 for (i = 0; i < info->reg_array_cnt; i++)
3848                         bnxt_write_fw_reset_reg(bp, i);
3849                 /* Wait for time specified by FW after triggering reset */
3850                 rte_delay_ms(info->master_func_wait_period_after_reset);
3851         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3852                 /* Reset with the help of Kong processor */
3853                 rc = bnxt_hwrm_fw_reset(bp);
3854                 if (rc)
3855                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3856         }
3857
3858         return rc;
3859 }
3860
3861 static void bnxt_fw_reset_cb(void *arg)
3862 {
3863         struct bnxt *bp = arg;
3864         struct bnxt_error_recovery_info *info = bp->recovery_info;
3865         int rc = 0;
3866
3867         /* Only Master function can do FW reset */
3868         if (bnxt_is_master_func(bp) &&
3869             bnxt_is_recovery_enabled(bp)) {
3870                 rc = bnxt_fw_reset_all(bp);
3871                 if (rc) {
3872                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3873                         return;
3874                 }
3875         }
3876
3877         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3878          * EXCEPTION_FATAL_ASYNC event to all the functions
3879          * (including MASTER FUNC). After receiving this Async, all the active
3880          * drivers should treat this case as FW initiated recovery
3881          */
3882         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3883                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3884                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3885
3886                 /* To recover from error */
3887                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3888                                   (void *)bp);
3889         }
3890 }
3891
3892 /* Driver should poll FW heartbeat, reset_counter with the frequency
3893  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3894  * When the driver detects heartbeat stop or change in reset_counter,
3895  * it has to trigger a reset to recover from the error condition.
3896  * A “master PF” is the function who will have the privilege to
3897  * initiate the chimp reset. The master PF will be elected by the
3898  * firmware and will be notified through async message.
3899  */
3900 static void bnxt_check_fw_health(void *arg)
3901 {
3902         struct bnxt *bp = arg;
3903         struct bnxt_error_recovery_info *info = bp->recovery_info;
3904         uint32_t val = 0, wait_msec;
3905
3906         if (!info || !bnxt_is_recovery_enabled(bp) ||
3907             is_bnxt_in_error(bp))
3908                 return;
3909
3910         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3911         if (val == info->last_heart_beat)
3912                 goto reset;
3913
3914         info->last_heart_beat = val;
3915
3916         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3917         if (val != info->last_reset_counter)
3918                 goto reset;
3919
3920         info->last_reset_counter = val;
3921
3922         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3923                           bnxt_check_fw_health, (void *)bp);
3924
3925         return;
3926 reset:
3927         /* Stop DMA to/from device */
3928         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3929         bp->flags |= BNXT_FLAG_FW_RESET;
3930
3931         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3932
3933         if (bnxt_is_master_func(bp))
3934                 wait_msec = info->master_func_wait_period;
3935         else
3936                 wait_msec = info->normal_func_wait_period;
3937
3938         rte_eal_alarm_set(US_PER_MS * wait_msec,
3939                           bnxt_fw_reset_cb, (void *)bp);
3940 }
3941
3942 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3943 {
3944         uint32_t polling_freq;
3945
3946         pthread_mutex_lock(&bp->health_check_lock);
3947
3948         if (!bnxt_is_recovery_enabled(bp))
3949                 goto done;
3950
3951         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3952                 goto done;
3953
3954         polling_freq = bp->recovery_info->driver_polling_freq;
3955
3956         rte_eal_alarm_set(US_PER_MS * polling_freq,
3957                           bnxt_check_fw_health, (void *)bp);
3958         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3959
3960 done:
3961         pthread_mutex_unlock(&bp->health_check_lock);
3962 }
3963
3964 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3965 {
3966         if (!bnxt_is_recovery_enabled(bp))
3967                 return;
3968
3969         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
3970         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3971 }
3972
3973 static bool bnxt_vf_pciid(uint16_t device_id)
3974 {
3975         switch (device_id) {
3976         case BROADCOM_DEV_ID_57304_VF:
3977         case BROADCOM_DEV_ID_57406_VF:
3978         case BROADCOM_DEV_ID_5731X_VF:
3979         case BROADCOM_DEV_ID_5741X_VF:
3980         case BROADCOM_DEV_ID_57414_VF:
3981         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
3982         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
3983         case BROADCOM_DEV_ID_58802_VF:
3984         case BROADCOM_DEV_ID_57500_VF1:
3985         case BROADCOM_DEV_ID_57500_VF2:
3986         case BROADCOM_DEV_ID_58818_VF:
3987                 /* FALLTHROUGH */
3988                 return true;
3989         default:
3990                 return false;
3991         }
3992 }
3993
3994 /* Phase 5 device */
3995 static bool bnxt_p5_device(uint16_t device_id)
3996 {
3997         switch (device_id) {
3998         case BROADCOM_DEV_ID_57508:
3999         case BROADCOM_DEV_ID_57504:
4000         case BROADCOM_DEV_ID_57502:
4001         case BROADCOM_DEV_ID_57508_MF1:
4002         case BROADCOM_DEV_ID_57504_MF1:
4003         case BROADCOM_DEV_ID_57502_MF1:
4004         case BROADCOM_DEV_ID_57508_MF2:
4005         case BROADCOM_DEV_ID_57504_MF2:
4006         case BROADCOM_DEV_ID_57502_MF2:
4007         case BROADCOM_DEV_ID_57500_VF1:
4008         case BROADCOM_DEV_ID_57500_VF2:
4009         case BROADCOM_DEV_ID_58812:
4010         case BROADCOM_DEV_ID_58814:
4011         case BROADCOM_DEV_ID_58818:
4012         case BROADCOM_DEV_ID_58818_VF:
4013                 /* FALLTHROUGH */
4014                 return true;
4015         default:
4016                 return false;
4017         }
4018 }
4019
4020 bool bnxt_stratus_device(struct bnxt *bp)
4021 {
4022         uint16_t device_id = bp->pdev->id.device_id;
4023
4024         switch (device_id) {
4025         case BROADCOM_DEV_ID_STRATUS_NIC:
4026         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4027         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4028                 /* FALLTHROUGH */
4029                 return true;
4030         default:
4031                 return false;
4032         }
4033 }
4034
4035 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4036 {
4037         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4038         struct bnxt *bp = eth_dev->data->dev_private;
4039
4040         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4041         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4042         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4043         if (!bp->bar0 || !bp->doorbell_base) {
4044                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4045                 return -ENODEV;
4046         }
4047
4048         bp->eth_dev = eth_dev;
4049         bp->pdev = pci_dev;
4050
4051         return 0;
4052 }
4053
4054 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4055                                   struct bnxt_ctx_pg_info *ctx_pg,
4056                                   uint32_t mem_size,
4057                                   const char *suffix,
4058                                   uint16_t idx)
4059 {
4060         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4061         const struct rte_memzone *mz = NULL;
4062         char mz_name[RTE_MEMZONE_NAMESIZE];
4063         rte_iova_t mz_phys_addr;
4064         uint64_t valid_bits = 0;
4065         uint32_t sz;
4066         int i;
4067
4068         if (!mem_size)
4069                 return 0;
4070
4071         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4072                          BNXT_PAGE_SIZE;
4073         rmem->page_size = BNXT_PAGE_SIZE;
4074         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4075         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4076         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4077
4078         valid_bits = PTU_PTE_VALID;
4079
4080         if (rmem->nr_pages > 1) {
4081                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4082                          "bnxt_ctx_pg_tbl%s_%x_%d",
4083                          suffix, idx, bp->eth_dev->data->port_id);
4084                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4085                 mz = rte_memzone_lookup(mz_name);
4086                 if (!mz) {
4087                         mz = rte_memzone_reserve_aligned(mz_name,
4088                                                 rmem->nr_pages * 8,
4089                                                 SOCKET_ID_ANY,
4090                                                 RTE_MEMZONE_2MB |
4091                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4092                                                 RTE_MEMZONE_IOVA_CONTIG,
4093                                                 BNXT_PAGE_SIZE);
4094                         if (mz == NULL)
4095                                 return -ENOMEM;
4096                 }
4097
4098                 memset(mz->addr, 0, mz->len);
4099                 mz_phys_addr = mz->iova;
4100
4101                 rmem->pg_tbl = mz->addr;
4102                 rmem->pg_tbl_map = mz_phys_addr;
4103                 rmem->pg_tbl_mz = mz;
4104         }
4105
4106         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4107                  suffix, idx, bp->eth_dev->data->port_id);
4108         mz = rte_memzone_lookup(mz_name);
4109         if (!mz) {
4110                 mz = rte_memzone_reserve_aligned(mz_name,
4111                                                  mem_size,
4112                                                  SOCKET_ID_ANY,
4113                                                  RTE_MEMZONE_1GB |
4114                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4115                                                  RTE_MEMZONE_IOVA_CONTIG,
4116                                                  BNXT_PAGE_SIZE);
4117                 if (mz == NULL)
4118                         return -ENOMEM;
4119         }
4120
4121         memset(mz->addr, 0, mz->len);
4122         mz_phys_addr = mz->iova;
4123
4124         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4125                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4126                 rmem->dma_arr[i] = mz_phys_addr + sz;
4127
4128                 if (rmem->nr_pages > 1) {
4129                         if (i == rmem->nr_pages - 2 &&
4130                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4131                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4132                         else if (i == rmem->nr_pages - 1 &&
4133                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4134                                 valid_bits |= PTU_PTE_LAST;
4135
4136                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4137                                                            valid_bits);
4138                 }
4139         }
4140
4141         rmem->mz = mz;
4142         if (rmem->vmem_size)
4143                 rmem->vmem = (void **)mz->addr;
4144         rmem->dma_arr[0] = mz_phys_addr;
4145         return 0;
4146 }
4147
4148 static void bnxt_free_ctx_mem(struct bnxt *bp)
4149 {
4150         int i;
4151
4152         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4153                 return;
4154
4155         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4156         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4157         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4158         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4159         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4160         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4161         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4162         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4163         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4164         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4165         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4166
4167         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4168                 if (bp->ctx->tqm_mem[i])
4169                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4170         }
4171
4172         rte_free(bp->ctx);
4173         bp->ctx = NULL;
4174 }
4175
4176 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4177
4178 #define min_t(type, x, y) ({                    \
4179         type __min1 = (x);                      \
4180         type __min2 = (y);                      \
4181         __min1 < __min2 ? __min1 : __min2; })
4182
4183 #define max_t(type, x, y) ({                    \
4184         type __max1 = (x);                      \
4185         type __max2 = (y);                      \
4186         __max1 > __max2 ? __max1 : __max2; })
4187
4188 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4189
4190 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4191 {
4192         struct bnxt_ctx_pg_info *ctx_pg;
4193         struct bnxt_ctx_mem_info *ctx;
4194         uint32_t mem_size, ena, entries;
4195         uint32_t entries_sp, min;
4196         int i, rc;
4197
4198         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4199         if (rc) {
4200                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4201                 return rc;
4202         }
4203         ctx = bp->ctx;
4204         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4205                 return 0;
4206
4207         ctx_pg = &ctx->qp_mem;
4208         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4209         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4210         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4211         if (rc)
4212                 return rc;
4213
4214         ctx_pg = &ctx->srq_mem;
4215         ctx_pg->entries = ctx->srq_max_l2_entries;
4216         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4217         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4218         if (rc)
4219                 return rc;
4220
4221         ctx_pg = &ctx->cq_mem;
4222         ctx_pg->entries = ctx->cq_max_l2_entries;
4223         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4224         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4225         if (rc)
4226                 return rc;
4227
4228         ctx_pg = &ctx->vnic_mem;
4229         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4230                 ctx->vnic_max_ring_table_entries;
4231         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4232         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4233         if (rc)
4234                 return rc;
4235
4236         ctx_pg = &ctx->stat_mem;
4237         ctx_pg->entries = ctx->stat_max_entries;
4238         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4239         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4240         if (rc)
4241                 return rc;
4242
4243         min = ctx->tqm_min_entries_per_ring;
4244
4245         entries_sp = ctx->qp_max_l2_entries +
4246                      ctx->vnic_max_vnic_entries +
4247                      2 * ctx->qp_min_qp1_entries + min;
4248         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4249
4250         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4251         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4252         entries = clamp_t(uint32_t, entries, min,
4253                           ctx->tqm_max_entries_per_ring);
4254         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4255                 ctx_pg = ctx->tqm_mem[i];
4256                 ctx_pg->entries = i ? entries : entries_sp;
4257                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4258                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4259                 if (rc)
4260                         return rc;
4261                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4262         }
4263
4264         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4265         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4266         if (rc)
4267                 PMD_DRV_LOG(ERR,
4268                             "Failed to configure context mem: rc = %d\n", rc);
4269         else
4270                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4271
4272         return rc;
4273 }
4274
4275 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4276 {
4277         struct rte_pci_device *pci_dev = bp->pdev;
4278         char mz_name[RTE_MEMZONE_NAMESIZE];
4279         const struct rte_memzone *mz = NULL;
4280         uint32_t total_alloc_len;
4281         rte_iova_t mz_phys_addr;
4282
4283         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4284                 return 0;
4285
4286         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4287                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4288                  pci_dev->addr.bus, pci_dev->addr.devid,
4289                  pci_dev->addr.function, "rx_port_stats");
4290         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4291         mz = rte_memzone_lookup(mz_name);
4292         total_alloc_len =
4293                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4294                                        sizeof(struct rx_port_stats_ext) + 512);
4295         if (!mz) {
4296                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4297                                          SOCKET_ID_ANY,
4298                                          RTE_MEMZONE_2MB |
4299                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4300                                          RTE_MEMZONE_IOVA_CONTIG);
4301                 if (mz == NULL)
4302                         return -ENOMEM;
4303         }
4304         memset(mz->addr, 0, mz->len);
4305         mz_phys_addr = mz->iova;
4306
4307         bp->rx_mem_zone = (const void *)mz;
4308         bp->hw_rx_port_stats = mz->addr;
4309         bp->hw_rx_port_stats_map = mz_phys_addr;
4310
4311         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4312                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4313                  pci_dev->addr.bus, pci_dev->addr.devid,
4314                  pci_dev->addr.function, "tx_port_stats");
4315         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4316         mz = rte_memzone_lookup(mz_name);
4317         total_alloc_len =
4318                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4319                                        sizeof(struct tx_port_stats_ext) + 512);
4320         if (!mz) {
4321                 mz = rte_memzone_reserve(mz_name,
4322                                          total_alloc_len,
4323                                          SOCKET_ID_ANY,
4324                                          RTE_MEMZONE_2MB |
4325                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4326                                          RTE_MEMZONE_IOVA_CONTIG);
4327                 if (mz == NULL)
4328                         return -ENOMEM;
4329         }
4330         memset(mz->addr, 0, mz->len);
4331         mz_phys_addr = mz->iova;
4332
4333         bp->tx_mem_zone = (const void *)mz;
4334         bp->hw_tx_port_stats = mz->addr;
4335         bp->hw_tx_port_stats_map = mz_phys_addr;
4336         bp->flags |= BNXT_FLAG_PORT_STATS;
4337
4338         /* Display extended statistics if FW supports it */
4339         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4340             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4341             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4342                 return 0;
4343
4344         bp->hw_rx_port_stats_ext = (void *)
4345                 ((uint8_t *)bp->hw_rx_port_stats +
4346                  sizeof(struct rx_port_stats));
4347         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4348                 sizeof(struct rx_port_stats);
4349         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4350
4351         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4352             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4353                 bp->hw_tx_port_stats_ext = (void *)
4354                         ((uint8_t *)bp->hw_tx_port_stats +
4355                          sizeof(struct tx_port_stats));
4356                 bp->hw_tx_port_stats_ext_map =
4357                         bp->hw_tx_port_stats_map +
4358                         sizeof(struct tx_port_stats);
4359                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4360         }
4361
4362         return 0;
4363 }
4364
4365 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4366 {
4367         struct bnxt *bp = eth_dev->data->dev_private;
4368         int rc = 0;
4369
4370         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4371                                                RTE_ETHER_ADDR_LEN *
4372                                                bp->max_l2_ctx,
4373                                                0);
4374         if (eth_dev->data->mac_addrs == NULL) {
4375                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4376                 return -ENOMEM;
4377         }
4378
4379         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4380                 if (BNXT_PF(bp))
4381                         return -EINVAL;
4382
4383                 /* Generate a random MAC address, if none was assigned by PF */
4384                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4385                 bnxt_eth_hw_addr_random(bp->mac_addr);
4386                 PMD_DRV_LOG(INFO,
4387                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4388                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4389                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4390
4391                 rc = bnxt_hwrm_set_mac(bp);
4392                 if (rc)
4393                         return rc;
4394         }
4395
4396         /* Copy the permanent MAC from the FUNC_QCAPS response */
4397         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4398
4399         return rc;
4400 }
4401
4402 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4403 {
4404         int rc = 0;
4405
4406         /* MAC is already configured in FW */
4407         if (BNXT_HAS_DFLT_MAC_SET(bp))
4408                 return 0;
4409
4410         /* Restore the old MAC configured */
4411         rc = bnxt_hwrm_set_mac(bp);
4412         if (rc)
4413                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4414
4415         return rc;
4416 }
4417
4418 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4419 {
4420         if (!BNXT_PF(bp))
4421                 return;
4422
4423         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4424
4425         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4426                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4427         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4428         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4429         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4430         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4431 }
4432
4433 uint16_t
4434 bnxt_get_svif(uint16_t port_id, bool func_svif,
4435               enum bnxt_ulp_intf_type type)
4436 {
4437         struct rte_eth_dev *eth_dev;
4438         struct bnxt *bp;
4439
4440         eth_dev = &rte_eth_devices[port_id];
4441         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4442                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4443                 if (!vfr)
4444                         return 0;
4445
4446                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4447                         return vfr->svif;
4448
4449                 eth_dev = vfr->parent_dev;
4450         }
4451
4452         bp = eth_dev->data->dev_private;
4453
4454         return func_svif ? bp->func_svif : bp->port_svif;
4455 }
4456
4457 uint16_t
4458 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4459 {
4460         struct rte_eth_dev *eth_dev;
4461         struct bnxt_vnic_info *vnic;
4462         struct bnxt *bp;
4463
4464         eth_dev = &rte_eth_devices[port];
4465         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4466                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4467                 if (!vfr)
4468                         return 0;
4469
4470                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4471                         return vfr->dflt_vnic_id;
4472
4473                 eth_dev = vfr->parent_dev;
4474         }
4475
4476         bp = eth_dev->data->dev_private;
4477
4478         vnic = BNXT_GET_DEFAULT_VNIC(bp);
4479
4480         return vnic->fw_vnic_id;
4481 }
4482
4483 uint16_t
4484 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4485 {
4486         struct rte_eth_dev *eth_dev;
4487         struct bnxt *bp;
4488
4489         eth_dev = &rte_eth_devices[port];
4490         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4491                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4492                 if (!vfr)
4493                         return 0;
4494
4495                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4496                         return vfr->fw_fid;
4497
4498                 eth_dev = vfr->parent_dev;
4499         }
4500
4501         bp = eth_dev->data->dev_private;
4502
4503         return bp->fw_fid;
4504 }
4505
4506 enum bnxt_ulp_intf_type
4507 bnxt_get_interface_type(uint16_t port)
4508 {
4509         struct rte_eth_dev *eth_dev;
4510         struct bnxt *bp;
4511
4512         eth_dev = &rte_eth_devices[port];
4513         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4514                 return BNXT_ULP_INTF_TYPE_VF_REP;
4515
4516         bp = eth_dev->data->dev_private;
4517         if (BNXT_PF(bp))
4518                 return BNXT_ULP_INTF_TYPE_PF;
4519         else if (BNXT_VF_IS_TRUSTED(bp))
4520                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4521         else if (BNXT_VF(bp))
4522                 return BNXT_ULP_INTF_TYPE_VF;
4523
4524         return BNXT_ULP_INTF_TYPE_INVALID;
4525 }
4526
4527 uint16_t
4528 bnxt_get_phy_port_id(uint16_t port_id)
4529 {
4530         struct bnxt_representor *vfr;
4531         struct rte_eth_dev *eth_dev;
4532         struct bnxt *bp;
4533
4534         eth_dev = &rte_eth_devices[port_id];
4535         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4536                 vfr = eth_dev->data->dev_private;
4537                 if (!vfr)
4538                         return 0;
4539
4540                 eth_dev = vfr->parent_dev;
4541         }
4542
4543         bp = eth_dev->data->dev_private;
4544
4545         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4546 }
4547
4548 uint16_t
4549 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4550 {
4551         struct rte_eth_dev *eth_dev;
4552         struct bnxt *bp;
4553
4554         eth_dev = &rte_eth_devices[port_id];
4555         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4556                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4557                 if (!vfr)
4558                         return 0;
4559
4560                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4561                         return vfr->fw_fid - 1;
4562
4563                 eth_dev = vfr->parent_dev;
4564         }
4565
4566         bp = eth_dev->data->dev_private;
4567
4568         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4569 }
4570
4571 uint16_t
4572 bnxt_get_vport(uint16_t port_id)
4573 {
4574         return (1 << bnxt_get_phy_port_id(port_id));
4575 }
4576
4577 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4578 {
4579         struct bnxt_error_recovery_info *info = bp->recovery_info;
4580
4581         if (info) {
4582                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4583                         memset(info, 0, sizeof(*info));
4584                 return;
4585         }
4586
4587         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4588                 return;
4589
4590         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4591                            sizeof(*info), 0);
4592         if (!info)
4593                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4594
4595         bp->recovery_info = info;
4596 }
4597
4598 static void bnxt_check_fw_status(struct bnxt *bp)
4599 {
4600         uint32_t fw_status;
4601
4602         if (!(bp->recovery_info &&
4603               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4604                 return;
4605
4606         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
4607         if (fw_status != BNXT_FW_STATUS_HEALTHY)
4608                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
4609                             fw_status);
4610 }
4611
4612 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
4613 {
4614         struct bnxt_error_recovery_info *info = bp->recovery_info;
4615         uint32_t status_loc;
4616         uint32_t sig_ver;
4617
4618         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
4619                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4620         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4621                                    BNXT_GRCP_WINDOW_2_BASE +
4622                                    offsetof(struct hcomm_status,
4623                                             sig_ver)));
4624         /* If the signature is absent, then FW does not support this feature */
4625         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
4626             HCOMM_STATUS_SIGNATURE_VAL)
4627                 return 0;
4628
4629         if (!info) {
4630                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4631                                    sizeof(*info), 0);
4632                 if (!info)
4633                         return -ENOMEM;
4634                 bp->recovery_info = info;
4635         } else {
4636                 memset(info, 0, sizeof(*info));
4637         }
4638
4639         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4640                                       BNXT_GRCP_WINDOW_2_BASE +
4641                                       offsetof(struct hcomm_status,
4642                                                fw_status_loc)));
4643
4644         /* Only pre-map the FW health status GRC register */
4645         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
4646                 return 0;
4647
4648         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
4649         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
4650                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
4651
4652         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
4653                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4654
4655         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
4656
4657         return 0;
4658 }
4659
4660 static int bnxt_init_fw(struct bnxt *bp)
4661 {
4662         uint16_t mtu;
4663         int rc = 0;
4664
4665         bp->fw_cap = 0;
4666
4667         rc = bnxt_map_hcomm_fw_status_reg(bp);
4668         if (rc)
4669                 return rc;
4670
4671         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4672         if (rc) {
4673                 bnxt_check_fw_status(bp);
4674                 return rc;
4675         }
4676
4677         rc = bnxt_hwrm_func_reset(bp);
4678         if (rc)
4679                 return -EIO;
4680
4681         rc = bnxt_hwrm_vnic_qcaps(bp);
4682         if (rc)
4683                 return rc;
4684
4685         rc = bnxt_hwrm_queue_qportcfg(bp);
4686         if (rc)
4687                 return rc;
4688
4689         /* Get the MAX capabilities for this function.
4690          * This function also allocates context memory for TQM rings and
4691          * informs the firmware about this allocated backing store memory.
4692          */
4693         rc = bnxt_hwrm_func_qcaps(bp);
4694         if (rc)
4695                 return rc;
4696
4697         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4698         if (rc)
4699                 return rc;
4700
4701         bnxt_hwrm_port_mac_qcfg(bp);
4702
4703         bnxt_hwrm_parent_pf_qcfg(bp);
4704
4705         bnxt_hwrm_port_phy_qcaps(bp);
4706
4707         bnxt_alloc_error_recovery_info(bp);
4708         /* Get the adapter error recovery support info */
4709         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4710         if (rc)
4711                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4712
4713         bnxt_hwrm_port_led_qcaps(bp);
4714
4715         return 0;
4716 }
4717
4718 static int
4719 bnxt_init_locks(struct bnxt *bp)
4720 {
4721         int err;
4722
4723         err = pthread_mutex_init(&bp->flow_lock, NULL);
4724         if (err) {
4725                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4726                 return err;
4727         }
4728
4729         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4730         if (err) {
4731                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4732                 return err;
4733         }
4734
4735         err = pthread_mutex_init(&bp->health_check_lock, NULL);
4736         if (err)
4737                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
4738         return err;
4739 }
4740
4741 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4742 {
4743         int rc = 0;
4744
4745         rc = bnxt_init_fw(bp);
4746         if (rc)
4747                 return rc;
4748
4749         if (!reconfig_dev) {
4750                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4751                 if (rc)
4752                         return rc;
4753         } else {
4754                 rc = bnxt_restore_dflt_mac(bp);
4755                 if (rc)
4756                         return rc;
4757         }
4758
4759         bnxt_config_vf_req_fwd(bp);
4760
4761         rc = bnxt_hwrm_func_driver_register(bp);
4762         if (rc) {
4763                 PMD_DRV_LOG(ERR, "Failed to register driver");
4764                 return -EBUSY;
4765         }
4766
4767         if (BNXT_PF(bp)) {
4768                 if (bp->pdev->max_vfs) {
4769                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4770                         if (rc) {
4771                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4772                                 return rc;
4773                         }
4774                 } else {
4775                         rc = bnxt_hwrm_allocate_pf_only(bp);
4776                         if (rc) {
4777                                 PMD_DRV_LOG(ERR,
4778                                             "Failed to allocate PF resources");
4779                                 return rc;
4780                         }
4781                 }
4782         }
4783
4784         rc = bnxt_alloc_mem(bp, reconfig_dev);
4785         if (rc)
4786                 return rc;
4787
4788         rc = bnxt_setup_int(bp);
4789         if (rc)
4790                 return rc;
4791
4792         rc = bnxt_request_int(bp);
4793         if (rc)
4794                 return rc;
4795
4796         rc = bnxt_init_ctx_mem(bp);
4797         if (rc) {
4798                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
4799                 return rc;
4800         }
4801
4802         rc = bnxt_init_locks(bp);
4803         if (rc)
4804                 return rc;
4805
4806         return 0;
4807 }
4808
4809 static int
4810 bnxt_parse_devarg_truflow(__rte_unused const char *key,
4811                           const char *value, void *opaque_arg)
4812 {
4813         struct bnxt *bp = opaque_arg;
4814         unsigned long truflow;
4815         char *end = NULL;
4816
4817         if (!value || !opaque_arg) {
4818                 PMD_DRV_LOG(ERR,
4819                             "Invalid parameter passed to truflow devargs.\n");
4820                 return -EINVAL;
4821         }
4822
4823         truflow = strtoul(value, &end, 10);
4824         if (end == NULL || *end != '\0' ||
4825             (truflow == ULONG_MAX && errno == ERANGE)) {
4826                 PMD_DRV_LOG(ERR,
4827                             "Invalid parameter passed to truflow devargs.\n");
4828                 return -EINVAL;
4829         }
4830
4831         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
4832                 PMD_DRV_LOG(ERR,
4833                             "Invalid value passed to truflow devargs.\n");
4834                 return -EINVAL;
4835         }
4836
4837         if (truflow) {
4838                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
4839                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
4840         } else {
4841                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
4842                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
4843         }
4844
4845         return 0;
4846 }
4847
4848 static int
4849 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
4850                              const char *value, void *opaque_arg)
4851 {
4852         struct bnxt *bp = opaque_arg;
4853         unsigned long flow_xstat;
4854         char *end = NULL;
4855
4856         if (!value || !opaque_arg) {
4857                 PMD_DRV_LOG(ERR,
4858                             "Invalid parameter passed to flow_xstat devarg.\n");
4859                 return -EINVAL;
4860         }
4861
4862         flow_xstat = strtoul(value, &end, 10);
4863         if (end == NULL || *end != '\0' ||
4864             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
4865                 PMD_DRV_LOG(ERR,
4866                             "Invalid parameter passed to flow_xstat devarg.\n");
4867                 return -EINVAL;
4868         }
4869
4870         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
4871                 PMD_DRV_LOG(ERR,
4872                             "Invalid value passed to flow_xstat devarg.\n");
4873                 return -EINVAL;
4874         }
4875
4876         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
4877         if (BNXT_FLOW_XSTATS_EN(bp))
4878                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
4879
4880         return 0;
4881 }
4882
4883 static int
4884 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
4885                                         const char *value, void *opaque_arg)
4886 {
4887         struct bnxt *bp = opaque_arg;
4888         unsigned long max_num_kflows;
4889         char *end = NULL;
4890
4891         if (!value || !opaque_arg) {
4892                 PMD_DRV_LOG(ERR,
4893                         "Invalid parameter passed to max_num_kflows devarg.\n");
4894                 return -EINVAL;
4895         }
4896
4897         max_num_kflows = strtoul(value, &end, 10);
4898         if (end == NULL || *end != '\0' ||
4899                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
4900                 PMD_DRV_LOG(ERR,
4901                         "Invalid parameter passed to max_num_kflows devarg.\n");
4902                 return -EINVAL;
4903         }
4904
4905         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
4906                 PMD_DRV_LOG(ERR,
4907                         "Invalid value passed to max_num_kflows devarg.\n");
4908                 return -EINVAL;
4909         }
4910
4911         bp->max_num_kflows = max_num_kflows;
4912         if (bp->max_num_kflows)
4913                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
4914                                 max_num_kflows);
4915
4916         return 0;
4917 }
4918
4919 static int
4920 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
4921                             const char *value, void *opaque_arg)
4922 {
4923         struct bnxt_representor *vfr_bp = opaque_arg;
4924         unsigned long rep_is_pf;
4925         char *end = NULL;
4926
4927         if (!value || !opaque_arg) {
4928                 PMD_DRV_LOG(ERR,
4929                             "Invalid parameter passed to rep_is_pf devargs.\n");
4930                 return -EINVAL;
4931         }
4932
4933         rep_is_pf = strtoul(value, &end, 10);
4934         if (end == NULL || *end != '\0' ||
4935             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
4936                 PMD_DRV_LOG(ERR,
4937                             "Invalid parameter passed to rep_is_pf devargs.\n");
4938                 return -EINVAL;
4939         }
4940
4941         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
4942                 PMD_DRV_LOG(ERR,
4943                             "Invalid value passed to rep_is_pf devargs.\n");
4944                 return -EINVAL;
4945         }
4946
4947         vfr_bp->flags |= rep_is_pf;
4948         if (BNXT_REP_PF(vfr_bp))
4949                 PMD_DRV_LOG(INFO, "PF representor\n");
4950         else
4951                 PMD_DRV_LOG(INFO, "VF representor\n");
4952
4953         return 0;
4954 }
4955
4956 static int
4957 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
4958                                const char *value, void *opaque_arg)
4959 {
4960         struct bnxt_representor *vfr_bp = opaque_arg;
4961         unsigned long rep_based_pf;
4962         char *end = NULL;
4963
4964         if (!value || !opaque_arg) {
4965                 PMD_DRV_LOG(ERR,
4966                             "Invalid parameter passed to rep_based_pf "
4967                             "devargs.\n");
4968                 return -EINVAL;
4969         }
4970
4971         rep_based_pf = strtoul(value, &end, 10);
4972         if (end == NULL || *end != '\0' ||
4973             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
4974                 PMD_DRV_LOG(ERR,
4975                             "Invalid parameter passed to rep_based_pf "
4976                             "devargs.\n");
4977                 return -EINVAL;
4978         }
4979
4980         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
4981                 PMD_DRV_LOG(ERR,
4982                             "Invalid value passed to rep_based_pf devargs.\n");
4983                 return -EINVAL;
4984         }
4985
4986         vfr_bp->rep_based_pf = rep_based_pf;
4987         vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
4988
4989         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
4990
4991         return 0;
4992 }
4993
4994 static int
4995 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
4996                             const char *value, void *opaque_arg)
4997 {
4998         struct bnxt_representor *vfr_bp = opaque_arg;
4999         unsigned long rep_q_r2f;
5000         char *end = NULL;
5001
5002         if (!value || !opaque_arg) {
5003                 PMD_DRV_LOG(ERR,
5004                             "Invalid parameter passed to rep_q_r2f "
5005                             "devargs.\n");
5006                 return -EINVAL;
5007         }
5008
5009         rep_q_r2f = strtoul(value, &end, 10);
5010         if (end == NULL || *end != '\0' ||
5011             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5012                 PMD_DRV_LOG(ERR,
5013                             "Invalid parameter passed to rep_q_r2f "
5014                             "devargs.\n");
5015                 return -EINVAL;
5016         }
5017
5018         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5019                 PMD_DRV_LOG(ERR,
5020                             "Invalid value passed to rep_q_r2f devargs.\n");
5021                 return -EINVAL;
5022         }
5023
5024         vfr_bp->rep_q_r2f = rep_q_r2f;
5025         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5026         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5027
5028         return 0;
5029 }
5030
5031 static int
5032 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5033                             const char *value, void *opaque_arg)
5034 {
5035         struct bnxt_representor *vfr_bp = opaque_arg;
5036         unsigned long rep_q_f2r;
5037         char *end = NULL;
5038
5039         if (!value || !opaque_arg) {
5040                 PMD_DRV_LOG(ERR,
5041                             "Invalid parameter passed to rep_q_f2r "
5042                             "devargs.\n");
5043                 return -EINVAL;
5044         }
5045
5046         rep_q_f2r = strtoul(value, &end, 10);
5047         if (end == NULL || *end != '\0' ||
5048             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5049                 PMD_DRV_LOG(ERR,
5050                             "Invalid parameter passed to rep_q_f2r "
5051                             "devargs.\n");
5052                 return -EINVAL;
5053         }
5054
5055         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5056                 PMD_DRV_LOG(ERR,
5057                             "Invalid value passed to rep_q_f2r devargs.\n");
5058                 return -EINVAL;
5059         }
5060
5061         vfr_bp->rep_q_f2r = rep_q_f2r;
5062         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5063         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5064
5065         return 0;
5066 }
5067
5068 static int
5069 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5070                              const char *value, void *opaque_arg)
5071 {
5072         struct bnxt_representor *vfr_bp = opaque_arg;
5073         unsigned long rep_fc_r2f;
5074         char *end = NULL;
5075
5076         if (!value || !opaque_arg) {
5077                 PMD_DRV_LOG(ERR,
5078                             "Invalid parameter passed to rep_fc_r2f "
5079                             "devargs.\n");
5080                 return -EINVAL;
5081         }
5082
5083         rep_fc_r2f = strtoul(value, &end, 10);
5084         if (end == NULL || *end != '\0' ||
5085             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5086                 PMD_DRV_LOG(ERR,
5087                             "Invalid parameter passed to rep_fc_r2f "
5088                             "devargs.\n");
5089                 return -EINVAL;
5090         }
5091
5092         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5093                 PMD_DRV_LOG(ERR,
5094                             "Invalid value passed to rep_fc_r2f devargs.\n");
5095                 return -EINVAL;
5096         }
5097
5098         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5099         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5100         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5101
5102         return 0;
5103 }
5104
5105 static int
5106 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5107                              const char *value, void *opaque_arg)
5108 {
5109         struct bnxt_representor *vfr_bp = opaque_arg;
5110         unsigned long rep_fc_f2r;
5111         char *end = NULL;
5112
5113         if (!value || !opaque_arg) {
5114                 PMD_DRV_LOG(ERR,
5115                             "Invalid parameter passed to rep_fc_f2r "
5116                             "devargs.\n");
5117                 return -EINVAL;
5118         }
5119
5120         rep_fc_f2r = strtoul(value, &end, 10);
5121         if (end == NULL || *end != '\0' ||
5122             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5123                 PMD_DRV_LOG(ERR,
5124                             "Invalid parameter passed to rep_fc_f2r "
5125                             "devargs.\n");
5126                 return -EINVAL;
5127         }
5128
5129         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5130                 PMD_DRV_LOG(ERR,
5131                             "Invalid value passed to rep_fc_f2r devargs.\n");
5132                 return -EINVAL;
5133         }
5134
5135         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5136         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5137         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5138
5139         return 0;
5140 }
5141
5142 static void
5143 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5144 {
5145         struct rte_kvargs *kvlist;
5146
5147         if (devargs == NULL)
5148                 return;
5149
5150         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5151         if (kvlist == NULL)
5152                 return;
5153
5154         /*
5155          * Handler for "truflow" devarg.
5156          * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1"
5157          */
5158         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5159                            bnxt_parse_devarg_truflow, bp);
5160
5161         /*
5162          * Handler for "flow_xstat" devarg.
5163          * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5164          */
5165         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5166                            bnxt_parse_devarg_flow_xstat, bp);
5167
5168         /*
5169          * Handler for "max_num_kflows" devarg.
5170          * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5171          */
5172         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5173                            bnxt_parse_devarg_max_num_kflows, bp);
5174
5175         rte_kvargs_free(kvlist);
5176 }
5177
5178 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5179 {
5180         int rc = 0;
5181
5182         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5183                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5184                 if (rc)
5185                         PMD_DRV_LOG(ERR,
5186                                     "Failed to alloc switch domain: %d\n", rc);
5187                 else
5188                         PMD_DRV_LOG(INFO,
5189                                     "Switch domain allocated %d\n",
5190                                     bp->switch_domain_id);
5191         }
5192
5193         return rc;
5194 }
5195
5196 static int
5197 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5198 {
5199         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5200         static int version_printed;
5201         struct bnxt *bp;
5202         int rc;
5203
5204         if (version_printed++ == 0)
5205                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5206
5207         eth_dev->dev_ops = &bnxt_dev_ops;
5208         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5209         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5210         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5211         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5212         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5213
5214         /*
5215          * For secondary processes, we don't initialise any further
5216          * as primary has already done this work.
5217          */
5218         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5219                 return 0;
5220
5221         rte_eth_copy_pci_info(eth_dev, pci_dev);
5222         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5223
5224         bp = eth_dev->data->dev_private;
5225
5226         /* Parse dev arguments passed on when starting the DPDK application. */
5227         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5228
5229         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5230
5231         if (bnxt_vf_pciid(pci_dev->id.device_id))
5232                 bp->flags |= BNXT_FLAG_VF;
5233
5234         if (bnxt_p5_device(pci_dev->id.device_id))
5235                 bp->flags |= BNXT_FLAG_CHIP_P5;
5236
5237         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5238             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5239             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5240             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5241                 bp->flags |= BNXT_FLAG_STINGRAY;
5242
5243         if (BNXT_TRUFLOW_EN(bp)) {
5244                 /* extra mbuf field is required to store CFA code from mark */
5245                 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5246                         .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5247                         .size = sizeof(bnxt_cfa_code_dynfield_t),
5248                         .align = __alignof__(bnxt_cfa_code_dynfield_t),
5249                 };
5250                 bnxt_cfa_code_dynfield_offset =
5251                         rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5252                 if (bnxt_cfa_code_dynfield_offset < 0) {
5253                         PMD_DRV_LOG(ERR,
5254                             "Failed to register mbuf field for TruFlow mark\n");
5255                         return -rte_errno;
5256                 }
5257         }
5258
5259         rc = bnxt_init_board(eth_dev);
5260         if (rc) {
5261                 PMD_DRV_LOG(ERR,
5262                             "Failed to initialize board rc: %x\n", rc);
5263                 return rc;
5264         }
5265
5266         rc = bnxt_alloc_pf_info(bp);
5267         if (rc)
5268                 goto error_free;
5269
5270         rc = bnxt_alloc_link_info(bp);
5271         if (rc)
5272                 goto error_free;
5273
5274         rc = bnxt_alloc_parent_info(bp);
5275         if (rc)
5276                 goto error_free;
5277
5278         rc = bnxt_alloc_hwrm_resources(bp);
5279         if (rc) {
5280                 PMD_DRV_LOG(ERR,
5281                             "Failed to allocate hwrm resource rc: %x\n", rc);
5282                 goto error_free;
5283         }
5284         rc = bnxt_alloc_leds_info(bp);
5285         if (rc)
5286                 goto error_free;
5287
5288         rc = bnxt_alloc_cos_queues(bp);
5289         if (rc)
5290                 goto error_free;
5291
5292         rc = bnxt_init_resources(bp, false);
5293         if (rc)
5294                 goto error_free;
5295
5296         rc = bnxt_alloc_stats_mem(bp);
5297         if (rc)
5298                 goto error_free;
5299
5300         bnxt_alloc_switch_domain(bp);
5301
5302         PMD_DRV_LOG(INFO,
5303                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5304                     pci_dev->mem_resource[0].phys_addr,
5305                     pci_dev->mem_resource[0].addr);
5306
5307         return 0;
5308
5309 error_free:
5310         bnxt_dev_uninit(eth_dev);
5311         return rc;
5312 }
5313
5314
5315 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5316 {
5317         if (!ctx)
5318                 return;
5319
5320         if (ctx->va)
5321                 rte_free(ctx->va);
5322
5323         ctx->va = NULL;
5324         ctx->dma = RTE_BAD_IOVA;
5325         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5326 }
5327
5328 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5329 {
5330         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5331                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5332                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5333                                   bp->flow_stat->max_fc,
5334                                   false);
5335
5336         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5337                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5338                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5339                                   bp->flow_stat->max_fc,
5340                                   false);
5341
5342         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5343                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5344         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5345
5346         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5347                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5348         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5349
5350         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5351                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5352         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5353
5354         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5355                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5356         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5357 }
5358
5359 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5360 {
5361         bnxt_unregister_fc_ctx_mem(bp);
5362
5363         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5364         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5365         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5366         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5367 }
5368
5369 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5370 {
5371         if (BNXT_FLOW_XSTATS_EN(bp))
5372                 bnxt_uninit_fc_ctx_mem(bp);
5373 }
5374
5375 static void
5376 bnxt_free_error_recovery_info(struct bnxt *bp)
5377 {
5378         rte_free(bp->recovery_info);
5379         bp->recovery_info = NULL;
5380         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5381 }
5382
5383 static void
5384 bnxt_uninit_locks(struct bnxt *bp)
5385 {
5386         pthread_mutex_destroy(&bp->flow_lock);
5387         pthread_mutex_destroy(&bp->def_cp_lock);
5388         pthread_mutex_destroy(&bp->health_check_lock);
5389         if (bp->rep_info) {
5390                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5391                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
5392         }
5393 }
5394
5395 static int
5396 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5397 {
5398         int rc;
5399
5400         bnxt_free_int(bp);
5401         bnxt_free_mem(bp, reconfig_dev);
5402
5403         bnxt_hwrm_func_buf_unrgtr(bp);
5404         rte_free(bp->pf->vf_req_buf);
5405
5406         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5407         bp->flags &= ~BNXT_FLAG_REGISTERED;
5408         bnxt_free_ctx_mem(bp);
5409         if (!reconfig_dev) {
5410                 bnxt_free_hwrm_resources(bp);
5411                 bnxt_free_error_recovery_info(bp);
5412         }
5413
5414         bnxt_uninit_ctx_mem(bp);
5415
5416         bnxt_uninit_locks(bp);
5417         bnxt_free_flow_stats_info(bp);
5418         bnxt_free_rep_info(bp);
5419         rte_free(bp->ptp_cfg);
5420         bp->ptp_cfg = NULL;
5421         return rc;
5422 }
5423
5424 static int
5425 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5426 {
5427         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5428                 return -EPERM;
5429
5430         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5431
5432         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5433                 bnxt_dev_close_op(eth_dev);
5434
5435         return 0;
5436 }
5437
5438 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5439 {
5440         struct bnxt *bp = eth_dev->data->dev_private;
5441         struct rte_eth_dev *vf_rep_eth_dev;
5442         int ret = 0, i;
5443
5444         if (!bp)
5445                 return -EINVAL;
5446
5447         for (i = 0; i < bp->num_reps; i++) {
5448                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5449                 if (!vf_rep_eth_dev)
5450                         continue;
5451                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5452                             vf_rep_eth_dev->data->port_id);
5453                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5454         }
5455         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5456                     eth_dev->data->port_id);
5457         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5458
5459         return ret;
5460 }
5461
5462 static void bnxt_free_rep_info(struct bnxt *bp)
5463 {
5464         rte_free(bp->rep_info);
5465         bp->rep_info = NULL;
5466         rte_free(bp->cfa_code_map);
5467         bp->cfa_code_map = NULL;
5468 }
5469
5470 static int bnxt_init_rep_info(struct bnxt *bp)
5471 {
5472         int i = 0, rc;
5473
5474         if (bp->rep_info)
5475                 return 0;
5476
5477         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5478                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5479                                    0);
5480         if (!bp->rep_info) {
5481                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5482                 return -ENOMEM;
5483         }
5484         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5485                                        sizeof(*bp->cfa_code_map) *
5486                                        BNXT_MAX_CFA_CODE, 0);
5487         if (!bp->cfa_code_map) {
5488                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5489                 bnxt_free_rep_info(bp);
5490                 return -ENOMEM;
5491         }
5492
5493         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5494                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5495
5496         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5497         if (rc) {
5498                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5499                 bnxt_free_rep_info(bp);
5500                 return rc;
5501         }
5502
5503         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5504         if (rc) {
5505                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5506                 bnxt_free_rep_info(bp);
5507                 return rc;
5508         }
5509
5510         return rc;
5511 }
5512
5513 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5514                                struct rte_eth_devargs *eth_da,
5515                                struct rte_eth_dev *backing_eth_dev,
5516                                const char *dev_args)
5517 {
5518         struct rte_eth_dev *vf_rep_eth_dev;
5519         char name[RTE_ETH_NAME_MAX_LEN];
5520         struct bnxt *backing_bp;
5521         uint16_t num_rep;
5522         int i, ret = 0;
5523         struct rte_kvargs *kvlist = NULL;
5524
5525         num_rep = eth_da->nb_representor_ports;
5526         if (num_rep > BNXT_MAX_VF_REPS) {
5527                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5528                             num_rep, BNXT_MAX_VF_REPS);
5529                 return -EINVAL;
5530         }
5531
5532         if (num_rep >= RTE_MAX_ETHPORTS) {
5533                 PMD_DRV_LOG(ERR,
5534                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5535                             num_rep, RTE_MAX_ETHPORTS);
5536                 return -EINVAL;
5537         }
5538
5539         backing_bp = backing_eth_dev->data->dev_private;
5540
5541         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5542                 PMD_DRV_LOG(ERR,
5543                             "Not a PF or trusted VF. No Representor support\n");
5544                 /* Returning an error is not an option.
5545                  * Applications are not handling this correctly
5546                  */
5547                 return 0;
5548         }
5549
5550         if (bnxt_init_rep_info(backing_bp))
5551                 return 0;
5552
5553         for (i = 0; i < num_rep; i++) {
5554                 struct bnxt_representor representor = {
5555                         .vf_id = eth_da->representor_ports[i],
5556                         .switch_domain_id = backing_bp->switch_domain_id,
5557                         .parent_dev = backing_eth_dev
5558                 };
5559
5560                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5561                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5562                                     representor.vf_id, BNXT_MAX_VF_REPS);
5563                         continue;
5564                 }
5565
5566                 /* representor port net_bdf_port */
5567                 snprintf(name, sizeof(name), "net_%s_representor_%d",
5568                          pci_dev->device.name, eth_da->representor_ports[i]);
5569
5570                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
5571                 if (kvlist) {
5572                         /*
5573                          * Handler for "rep_is_pf" devarg.
5574                          * Invoked as for ex: "-a 000:00:0d.0,
5575                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5576                          */
5577                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
5578                                                  bnxt_parse_devarg_rep_is_pf,
5579                                                  (void *)&representor);
5580                         if (ret) {
5581                                 ret = -EINVAL;
5582                                 goto err;
5583                         }
5584                         /*
5585                          * Handler for "rep_based_pf" devarg.
5586                          * Invoked as for ex: "-a 000:00:0d.0,
5587                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5588                          */
5589                         ret = rte_kvargs_process(kvlist,
5590                                                  BNXT_DEVARG_REP_BASED_PF,
5591                                                  bnxt_parse_devarg_rep_based_pf,
5592                                                  (void *)&representor);
5593                         if (ret) {
5594                                 ret = -EINVAL;
5595                                 goto err;
5596                         }
5597                         /*
5598                          * Handler for "rep_based_pf" devarg.
5599                          * Invoked as for ex: "-a 000:00:0d.0,
5600                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5601                          */
5602                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
5603                                                  bnxt_parse_devarg_rep_q_r2f,
5604                                                  (void *)&representor);
5605                         if (ret) {
5606                                 ret = -EINVAL;
5607                                 goto err;
5608                         }
5609                         /*
5610                          * Handler for "rep_based_pf" devarg.
5611                          * Invoked as for ex: "-a 000:00:0d.0,
5612                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5613                          */
5614                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
5615                                                  bnxt_parse_devarg_rep_q_f2r,
5616                                                  (void *)&representor);
5617                         if (ret) {
5618                                 ret = -EINVAL;
5619                                 goto err;
5620                         }
5621                         /*
5622                          * Handler for "rep_based_pf" devarg.
5623                          * Invoked as for ex: "-a 000:00:0d.0,
5624                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5625                          */
5626                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
5627                                                  bnxt_parse_devarg_rep_fc_r2f,
5628                                                  (void *)&representor);
5629                         if (ret) {
5630                                 ret = -EINVAL;
5631                                 goto err;
5632                         }
5633                         /*
5634                          * Handler for "rep_based_pf" devarg.
5635                          * Invoked as for ex: "-a 000:00:0d.0,
5636                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5637                          */
5638                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
5639                                                  bnxt_parse_devarg_rep_fc_f2r,
5640                                                  (void *)&representor);
5641                         if (ret) {
5642                                 ret = -EINVAL;
5643                                 goto err;
5644                         }
5645                 }
5646
5647                 ret = rte_eth_dev_create(&pci_dev->device, name,
5648                                          sizeof(struct bnxt_representor),
5649                                          NULL, NULL,
5650                                          bnxt_representor_init,
5651                                          &representor);
5652                 if (ret) {
5653                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
5654                                     "representor %s.", name);
5655                         goto err;
5656                 }
5657
5658                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
5659                 if (!vf_rep_eth_dev) {
5660                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
5661                                     " for VF-Rep: %s.", name);
5662                         ret = -ENODEV;
5663                         goto err;
5664                 }
5665
5666                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
5667                             backing_eth_dev->data->port_id);
5668                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
5669                                                          vf_rep_eth_dev;
5670                 backing_bp->num_reps++;
5671
5672         }
5673
5674         rte_kvargs_free(kvlist);
5675         return 0;
5676
5677 err:
5678         /* If num_rep > 1, then rollback already created
5679          * ports, since we'll be failing the probe anyway
5680          */
5681         if (num_rep > 1)
5682                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
5683         rte_errno = -ret;
5684         rte_kvargs_free(kvlist);
5685
5686         return ret;
5687 }
5688
5689 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5690                           struct rte_pci_device *pci_dev)
5691 {
5692         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
5693         struct rte_eth_dev *backing_eth_dev;
5694         uint16_t num_rep;
5695         int ret = 0;
5696
5697         if (pci_dev->device.devargs) {
5698                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
5699                                             &eth_da);
5700                 if (ret)
5701                         return ret;
5702         }
5703
5704         num_rep = eth_da.nb_representor_ports;
5705         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
5706                     num_rep);
5707
5708         /* We could come here after first level of probe is already invoked
5709          * as part of an application bringup(OVS-DPDK vswitchd), so first check
5710          * for already allocated eth_dev for the backing device (PF/Trusted VF)
5711          */
5712         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5713         if (backing_eth_dev == NULL) {
5714                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
5715                                          sizeof(struct bnxt),
5716                                          eth_dev_pci_specific_init, pci_dev,
5717                                          bnxt_dev_init, NULL);
5718
5719                 if (ret || !num_rep)
5720                         return ret;
5721
5722                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5723         }
5724         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
5725                     backing_eth_dev->data->port_id);
5726
5727         if (!num_rep)
5728                 return ret;
5729
5730         /* probe representor ports now */
5731         ret = bnxt_rep_port_probe(pci_dev, &eth_da, backing_eth_dev,
5732                                   pci_dev->device.devargs->args);
5733
5734         return ret;
5735 }
5736
5737 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5738 {
5739         struct rte_eth_dev *eth_dev;
5740
5741         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5742         if (!eth_dev)
5743                 return 0; /* Invoked typically only by OVS-DPDK, by the
5744                            * time it comes here the eth_dev is already
5745                            * deleted by rte_eth_dev_close(), so returning
5746                            * +ve value will at least help in proper cleanup
5747                            */
5748
5749         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
5750         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
5751                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
5752                         return rte_eth_dev_destroy(eth_dev,
5753                                                    bnxt_representor_uninit);
5754                 else
5755                         return rte_eth_dev_destroy(eth_dev,
5756                                                    bnxt_dev_uninit);
5757         } else {
5758                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5759         }
5760 }
5761
5762 static struct rte_pci_driver bnxt_rte_pmd = {
5763         .id_table = bnxt_pci_id_map,
5764         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
5765                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
5766                                                   * and OVS-DPDK
5767                                                   */
5768         .probe = bnxt_pci_probe,
5769         .remove = bnxt_pci_remove,
5770 };
5771
5772 static bool
5773 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5774 {
5775         if (strcmp(dev->device->driver->name, drv->driver.name))
5776                 return false;
5777
5778         return true;
5779 }
5780
5781 bool is_bnxt_supported(struct rte_eth_dev *dev)
5782 {
5783         return is_device_supported(dev, &bnxt_rte_pmd);
5784 }
5785
5786 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
5787 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5788 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5789 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");