drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30 #define HWRM_VERSION_1_10_2_13          0x10a020d
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(int) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages == 0)
  68                 return;
  69
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 static struct bnxt_cp_ring_info*
  79 bnxt_get_ring_info_by_id(struct bnxt *bp, uint16_t rid, uint16_t type)
  80 {
  81         struct bnxt_cp_ring_info *cp_ring = NULL;
  82         uint16_t i;
  83
  84         switch (type) {
  85         case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
  86         case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
  87                 /* FALLTHROUGH */
  88                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
  89                         struct bnxt_rx_queue *rxq = bp->rx_queues[i];
  90
  91                         if (rxq->cp_ring->cp_ring_struct->fw_ring_id ==
  92                             rte_cpu_to_le_16(rid)) {
  93                                 return rxq->cp_ring;
  94                         }
  95                 }
  96                 break;
  97         case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
  98                 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
  99                         struct bnxt_tx_queue *txq = bp->tx_queues[i];
 100
 101                         if (txq->cp_ring->cp_ring_struct->fw_ring_id ==
 102                             rte_cpu_to_le_16(rid)) {
 103                                 return txq->cp_ring;
 104                         }
 105                 }
 106                 break;
 107         default:
 108                 return cp_ring;
 109         }
 110         return cp_ring;
 111 }
 112
 113 /* Complete a sweep of the CQ ring for the corresponding Tx/Rx/AGG ring.
 114  * If the CMPL_BASE_TYPE_HWRM_DONE is not encountered by the last pass,
 115  * before timeout, we force the done bit for the cleanup to proceed.
 116  * Also if cpr is null, do nothing.. The HWRM command is  not for a
 117  * Tx/Rx/AGG ring cleanup.
 118  */
 119 static int
 120 bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info *cpr,
 121                         bool tx, bool rx, bool timeout)
 122 {
 123         int done = 0;
 124
 125         if (cpr != NULL) {
 126                 if (tx)
 127                         done = bnxt_flush_tx_cmp(cpr);
 128
 129                 if (rx)
 130                         done = bnxt_flush_rx_cmp(cpr);
 131
 132                 if (done)
 133                         PMD_DRV_LOG(DEBUG, "HWRM DONE for %s ring\n",
 134                                     rx ? "Rx" : "Tx");
 135
 136                 /* We are about to timeout and still haven't seen the
 137                  * HWRM done for the Ring free. Force the cleanup.
 138                  */
 139                 if (!done && timeout) {
 140                         done = 1;
 141                         PMD_DRV_LOG(DEBUG, "Timing out for %s ring\n",
 142                                     rx ? "Rx" : "Tx");
 143                 }
 144         } else {
 145                 /* This HWRM command is not for a Tx/Rx/AGG ring cleanup.
 146                  * Otherwise the cpr would have been valid. So do nothing.
 147                  */
 148                 done = 1;
 149         }
 150
 151         return done;
 152 }
 153
 154 /*
 155  * HWRM Functions (sent to HWRM)
 156  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
 157  * HWRM command times out, or a negative error code if the HWRM
 158  * command was failed by the FW.
 159  */
 160
 161 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
 162                                   uint32_t msg_len, bool use_kong_mb)
 163 {
 164         unsigned int i;
 165         struct input *req = msg;
 166         struct output *resp = bp->hwrm_cmd_resp_addr;
 167         uint32_t *data = msg;
 168         uint8_t *bar;
 169         uint8_t *valid;
 170         uint16_t max_req_len = bp->max_req_len;
 171         struct hwrm_short_input short_input = { 0 };
 172         uint16_t bar_offset = use_kong_mb ?
 173                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
 174         uint16_t mb_trigger_offset = use_kong_mb ?
 175                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 176         struct bnxt_cp_ring_info *cpr = NULL;
 177         bool is_rx = false;
 178         bool is_tx = false;
 179         uint32_t timeout;
 180
 181         /* Do not send HWRM commands to firmware in error state */
 182         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 183                 return 0;
 184
 185         timeout = bp->hwrm_cmd_timeout;
 186
 187         /* Update the message length for backing store config for new FW. */
 188         if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
 189             rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
 190                 msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
 191
 192         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 193             msg_len > bp->max_req_len) {
 194                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 195
 196                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 197                 memcpy(short_cmd_req, req, msg_len);
 198
 199                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 200                 short_input.signature = rte_cpu_to_le_16(
 201                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 202                 short_input.size = rte_cpu_to_le_16(msg_len);
 203                 short_input.req_addr =
 204                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 205
 206                 data = (uint32_t *)&short_input;
 207                 msg_len = sizeof(short_input);
 208
 209                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 210         }
 211
 212         /* Write request msg to hwrm channel */
 213         for (i = 0; i < msg_len; i += 4) {
 214                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 215                 rte_write32(*data, bar);
 216                 data++;
 217         }
 218
 219         /* Zero the rest of the request space */
 220         for (; i < max_req_len; i += 4) {
 221                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 222                 rte_write32(0, bar);
 223         }
 224
 225         /* Ring channel doorbell */
 226         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 227         rte_write32(1, bar);
 228         /*
 229          * Make sure the channel doorbell ring command complete before
 230          * reading the response to avoid getting stale or invalid
 231          * responses.
 232          */
 233         rte_io_mb();
 234
 235         /* Check ring flush is done.
 236          * This is valid only for Tx and Rx rings (including AGG rings).
 237          * The Tx and Rx rings should be freed once the HW confirms all
 238          * the internal buffers and BDs associated with the rings are
 239          * consumed and the corresponding DMA is handled.
 240          */
 241         if (rte_cpu_to_le_16(req->cmpl_ring) != INVALID_HW_RING_ID) {
 242                 /* Check if the TxCQ matches. If that fails check if RxCQ
 243                  * matches. And if neither match, is_rx = false, is_tx = false.
 244                  */
 245                 cpr = bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 246                                                HWRM_RING_FREE_INPUT_RING_TYPE_TX);
 247                 if (cpr == NULL) {
 248                         /* Not a TxCQ. Check if the RxCQ matches. */
 249                         cpr =
 250                         bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 251                                                  HWRM_RING_FREE_INPUT_RING_TYPE_RX);
 252                         if (cpr != NULL)
 253                                 is_rx = true;
 254                 } else {
 255                         is_tx = true;
 256                 }
 257         }
 258
 259         /* Poll for the valid bit */
 260         for (i = 0; i < timeout; i++) {
 261                 int done;
 262
 263                 done = bnxt_check_cq_hwrm_done(cpr, is_tx, is_rx,
 264                                                i == timeout - 1);
 265                 /* Sanity check on the resp->resp_len */
 266                 rte_io_rmb();
 267                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 268                         /* Last byte of resp contains the valid key */
 269                         valid = (uint8_t *)resp + resp->resp_len - 1;
 270                         if (*valid == HWRM_RESP_VALID_KEY && done)
 271                                 break;
 272                 }
 273                 rte_delay_us(1);
 274         }
 275
 276         if (i >= timeout) {
 277                 /* Suppress VER_GET timeout messages during reset recovery */
 278                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 279                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 280                         return -ETIMEDOUT;
 281
 282                 PMD_DRV_LOG(ERR,
 283                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 284                             req->req_type, req->seq_id);
 285                 return -ETIMEDOUT;
 286         }
 287         return 0;
 288 }
 289
 290 /*
 291  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 292  * spinlock, and does initial processing.
 293  *
 294  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 295  * releases the spinlock only if it returns. If the regular int return codes
 296  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 297  * directly, rather it should be copied and modified to suit the function.
 298  *
 299  * HWRM_UNLOCK() must be called after all response processing is completed.
 300  */
 301 #define HWRM_PREP(req, type, kong) do { \
 302         rte_spinlock_lock(&bp->hwrm_lock); \
 303         if (bp->hwrm_cmd_resp_addr == NULL) { \
 304                 rte_spinlock_unlock(&bp->hwrm_lock); \
 305                 return -EACCES; \
 306         } \
 307         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 308         (req)->req_type = rte_cpu_to_le_16(type); \
 309         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 310         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 311                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 312         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 313         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 314 } while (0)
 315
 316 #define HWRM_CHECK_RESULT_SILENT() do {\
 317         if (rc) { \
 318                 rte_spinlock_unlock(&bp->hwrm_lock); \
 319                 return rc; \
 320         } \
 321         if (resp->error_code) { \
 322                 rc = rte_le_to_cpu_16(resp->error_code); \
 323                 rte_spinlock_unlock(&bp->hwrm_lock); \
 324                 return rc; \
 325         } \
 326 } while (0)
 327
 328 #define HWRM_CHECK_RESULT() do {\
 329         if (rc) { \
 330                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 331                 rte_spinlock_unlock(&bp->hwrm_lock); \
 332                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 333                         rc = -EACCES; \
 334                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 335                         rc = -ENOSPC; \
 336                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 337                         rc = -EINVAL; \
 338                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 339                         rc = -ENOTSUP; \
 340                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 341                         rc = -EAGAIN; \
 342                 else if (rc > 0) \
 343                         rc = -EIO; \
 344                 return rc; \
 345         } \
 346         if (resp->error_code) { \
 347                 rc = rte_le_to_cpu_16(resp->error_code); \
 348                 if (resp->resp_len >= 16) { \
 349                         struct hwrm_err_output *tmp_hwrm_err_op = \
 350                                                 (void *)resp; \
 351                         PMD_DRV_LOG(ERR, \
 352                                 "error %d:%d:%08x:%04x\n", \
 353                                 rc, tmp_hwrm_err_op->cmd_err, \
 354                                 rte_le_to_cpu_32(\
 355                                         tmp_hwrm_err_op->opaque_0), \
 356                                 rte_le_to_cpu_16(\
 357                                         tmp_hwrm_err_op->opaque_1)); \
 358                 } else { \
 359                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 360                 } \
 361                 rte_spinlock_unlock(&bp->hwrm_lock); \
 362                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 363                         rc = -EACCES; \
 364                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 365                         rc = -ENOSPC; \
 366                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 367                         rc = -EINVAL; \
 368                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 369                         rc = -ENOTSUP; \
 370                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 371                         rc = -EAGAIN; \
 372                 else if (rc > 0) \
 373                         rc = -EIO; \
 374                 return rc; \
 375         } \
 376 } while (0)
 377
 378 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 379
 380 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 381                                 bool use_kong_mb,
 382                                 uint16_t msg_type,
 383                                 void *msg,
 384                                 uint32_t msg_len,
 385                                 void *resp_msg,
 386                                 uint32_t resp_len)
 387 {
 388         int rc = 0;
 389         bool mailbox = BNXT_USE_CHIMP_MB;
 390         struct input *req = msg;
 391         struct output *resp = bp->hwrm_cmd_resp_addr;
 392
 393         if (use_kong_mb)
 394                 mailbox = BNXT_USE_KONG(bp);
 395
 396         HWRM_PREP(req, msg_type, mailbox);
 397
 398         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 399
 400         HWRM_CHECK_RESULT();
 401
 402         if (resp_msg)
 403                 memcpy(resp_msg, resp, resp_len);
 404
 405         HWRM_UNLOCK();
 406
 407         return rc;
 408 }
 409
 410 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 411                                   bool use_kong_mb,
 412                                   uint16_t tf_type,
 413                                   uint16_t tf_subtype,
 414                                   uint32_t *tf_response_code,
 415                                   void *msg,
 416                                   uint32_t msg_len,
 417                                   void *response,
 418                                   uint32_t response_len)
 419 {
 420         int rc = 0;
 421         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 422         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 423         bool mailbox = BNXT_USE_CHIMP_MB;
 424
 425         if (msg_len > sizeof(req.tf_req))
 426                 return -ENOMEM;
 427
 428         if (use_kong_mb)
 429                 mailbox = BNXT_USE_KONG(bp);
 430
 431         HWRM_PREP(&req, HWRM_TF, mailbox);
 432         /* Build request using the user supplied request payload.
 433          * TLV request size is checked at build time against HWRM
 434          * request max size, thus no checking required.
 435          */
 436         req.tf_type = tf_type;
 437         req.tf_subtype = tf_subtype;
 438         memcpy(req.tf_req, msg, msg_len);
 439
 440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 441         HWRM_CHECK_RESULT();
 442
 443         /* Copy the resp to user provided response buffer */
 444         if (response != NULL)
 445                 /* Post process response data. We need to copy only
 446                  * the 'payload' as the HWRM data structure really is
 447                  * HWRM header + msg header + payload and the TFLIB
 448                  * only provided a payload place holder.
 449                  */
 450                 if (response_len != 0) {
 451                         memcpy(response,
 452                                resp->tf_resp,
 453                                response_len);
 454                 }
 455
 456         /* Extract the internal tflib response code */
 457         *tf_response_code = resp->tf_resp_code;
 458         HWRM_UNLOCK();
 459
 460         return rc;
 461 }
 462
 463 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 464 {
 465         int rc = 0;
 466         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 467         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 468
 469         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 470         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 471         req.mask = 0;
 472
 473         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 474
 475         HWRM_CHECK_RESULT();
 476         HWRM_UNLOCK();
 477
 478         return rc;
 479 }
 480
 481 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 482                                  struct bnxt_vnic_info *vnic,
 483                                  uint16_t vlan_count,
 484                                  struct bnxt_vlan_table_entry *vlan_table)
 485 {
 486         int rc = 0;
 487         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 488         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 489         uint32_t mask = 0;
 490
 491         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 492                 return rc;
 493
 494         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 495         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 496
 497         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 498                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 499         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 500                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 501
 502         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 503                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 504
 505         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 506                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 507         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 508                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 509                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 510                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 511         }
 512         if (vlan_table) {
 513                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 514                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 515                 req.vlan_tag_tbl_addr =
 516                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 517                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 518         }
 519         req.mask = rte_cpu_to_le_32(mask);
 520
 521         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 522
 523         HWRM_CHECK_RESULT();
 524         HWRM_UNLOCK();
 525
 526         return rc;
 527 }
 528
 529 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 530                         uint16_t vlan_count,
 531                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 532 {
 533         int rc = 0;
 534         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 535         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 536                                                 bp->hwrm_cmd_resp_addr;
 537
 538         /*
 539          * Older HWRM versions did not support this command, and the set_rx_mask
 540          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 541          * removed from set_rx_mask call, and this command was added.
 542          *
 543          * This command is also present from 1.7.8.11 and higher,
 544          * as well as 1.7.8.0
 545          */
 546         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 547                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 548                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 549                                         (11)))
 550                                 return 0;
 551                 }
 552         }
 553         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 554         req.fid = rte_cpu_to_le_16(fid);
 555
 556         req.vlan_tag_mask_tbl_addr =
 557                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 558         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 559
 560         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 561
 562         HWRM_CHECK_RESULT();
 563         HWRM_UNLOCK();
 564
 565         return rc;
 566 }
 567
 568 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 569                              struct bnxt_filter_info *filter)
 570 {
 571         int rc = 0;
 572         struct bnxt_filter_info *l2_filter = filter;
 573         struct bnxt_vnic_info *vnic = NULL;
 574         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 575         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 576
 577         if (filter->fw_l2_filter_id == UINT64_MAX)
 578                 return 0;
 579
 580         if (filter->matching_l2_fltr_ptr)
 581                 l2_filter = filter->matching_l2_fltr_ptr;
 582
 583         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 584                     filter, l2_filter, l2_filter->l2_ref_cnt);
 585
 586         if (l2_filter->l2_ref_cnt == 0)
 587                 return 0;
 588
 589         if (l2_filter->l2_ref_cnt > 0)
 590                 l2_filter->l2_ref_cnt--;
 591
 592         if (l2_filter->l2_ref_cnt > 0)
 593                 return 0;
 594
 595         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 596
 597         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 598
 599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 600
 601         HWRM_CHECK_RESULT();
 602         HWRM_UNLOCK();
 603
 604         filter->fw_l2_filter_id = UINT64_MAX;
 605         if (l2_filter->l2_ref_cnt == 0) {
 606                 vnic = l2_filter->vnic;
 607                 if (vnic) {
 608                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 609                                       bnxt_filter_info, next);
 610                         bnxt_free_filter(bp, l2_filter);
 611                 }
 612         }
 613
 614         return 0;
 615 }
 616
 617 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 618                          uint16_t dst_id,
 619                          struct bnxt_filter_info *filter)
 620 {
 621         int rc = 0;
 622         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 623         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 624         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 625         const struct rte_eth_vmdq_rx_conf *conf =
 626                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 627         uint32_t enables = 0;
 628         uint16_t j = dst_id - 1;
 629
 630         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 631         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 632             conf->pool_map[j].pools & (1UL << j)) {
 633                 PMD_DRV_LOG(DEBUG,
 634                         "Add vlan %u to vmdq pool %u\n",
 635                         conf->pool_map[j].vlan_id, j);
 636
 637                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 638                 filter->enables |=
 639                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 640                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 641         }
 642
 643         if (filter->fw_l2_filter_id != UINT64_MAX)
 644                 bnxt_hwrm_clear_l2_filter(bp, filter);
 645
 646         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 647
 648         /* PMD does not support XDP and RoCE */
 649         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
 650                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
 651         req.flags = rte_cpu_to_le_32(filter->flags);
 652
 653         enables = filter->enables |
 654               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 655         req.dst_id = rte_cpu_to_le_16(dst_id);
 656
 657         if (enables &
 658             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 659                 memcpy(req.l2_addr, filter->l2_addr,
 660                        RTE_ETHER_ADDR_LEN);
 661         if (enables &
 662             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 663                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 664                        RTE_ETHER_ADDR_LEN);
 665         if (enables &
 666             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 667                 req.l2_ovlan = filter->l2_ovlan;
 668         if (enables &
 669             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 670                 req.l2_ivlan = filter->l2_ivlan;
 671         if (enables &
 672             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 673                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 674         if (enables &
 675             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 676                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 677         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 678                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 679         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 680                 req.src_type = filter->src_type;
 681         if (filter->pri_hint) {
 682                 req.pri_hint = filter->pri_hint;
 683                 req.l2_filter_id_hint =
 684                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 685         }
 686
 687         req.enables = rte_cpu_to_le_32(enables);
 688
 689         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 690
 691         HWRM_CHECK_RESULT();
 692
 693         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 694         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 695         HWRM_UNLOCK();
 696
 697         filter->l2_ref_cnt++;
 698
 699         return rc;
 700 }
 701
 702 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 703 {
 704         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 705         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 706         uint32_t flags = 0;
 707         int rc;
 708
 709         if (!ptp)
 710                 return 0;
 711
 712         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 713
 714         if (ptp->rx_filter)
 715                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 716         else
 717                 flags |=
 718                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 719         if (ptp->tx_tstamp_en)
 720                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 721         else
 722                 flags |=
 723                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 724         req.flags = rte_cpu_to_le_32(flags);
 725         req.enables = rte_cpu_to_le_32
 726                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 727         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 728
 729         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 730         HWRM_UNLOCK();
 731
 732         return rc;
 733 }
 734
 735 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 736 {
 737         int rc = 0;
 738         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 739         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 740         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 741
 742         if (ptp)
 743                 return 0;
 744
 745         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 746
 747         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 748
 749         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 750
 751         HWRM_CHECK_RESULT();
 752
 753         if (BNXT_CHIP_P5(bp)) {
 754                 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS))
 755                         return 0;
 756         } else {
 757                 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 758                         return 0;
 759         }
 760
 761         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 762                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 763
 764         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 765         if (!ptp)
 766                 return -ENOMEM;
 767
 768         if (!BNXT_CHIP_P5(bp)) {
 769                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 770                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 771                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 772                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 773                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 774                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 775                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 776                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 777                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 778                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 779                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 780                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 781                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 782                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 783                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 784                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 785                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 786                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 787         }
 788
 789         ptp->bp = bp;
 790         bp->ptp_cfg = ptp;
 791
 792         return 0;
 793 }
 794
 795 void bnxt_free_vf_info(struct bnxt *bp)
 796 {
 797         int i;
 798
 799         if (bp->pf == NULL)
 800                 return;
 801
 802         if (bp->pf->vf_info == NULL)
 803                 return;
 804
 805         for (i = 0; i < bp->pf->max_vfs; i++) {
 806                 rte_free(bp->pf->vf_info[i].vlan_table);
 807                 bp->pf->vf_info[i].vlan_table = NULL;
 808                 rte_free(bp->pf->vf_info[i].vlan_as_table);
 809                 bp->pf->vf_info[i].vlan_as_table = NULL;
 810         }
 811         rte_free(bp->pf->vf_info);
 812         bp->pf->vf_info = NULL;
 813 }
 814
 815 static int bnxt_alloc_vf_info(struct bnxt *bp, uint16_t max_vfs)
 816 {
 817         struct bnxt_child_vf_info *vf_info = bp->pf->vf_info;
 818         int i;
 819
 820         if (vf_info)
 821                 bnxt_free_vf_info(bp);
 822
 823         vf_info = rte_zmalloc("bnxt_vf_info", sizeof(*vf_info) * max_vfs, 0);
 824         if (vf_info == NULL) {
 825                 PMD_DRV_LOG(ERR, "Failed to alloc vf info\n");
 826                 return -ENOMEM;
 827         }
 828
 829         bp->pf->max_vfs = max_vfs;
 830         for (i = 0; i < max_vfs; i++) {
 831                 vf_info[i].fid = bp->pf->first_vf_id + i;
 832                 vf_info[i].vlan_table = rte_zmalloc("VF VLAN table",
 833                                                     getpagesize(), getpagesize());
 834                 if (vf_info[i].vlan_table == NULL) {
 835                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN table for VF %d\n", i);
 836                         goto err;
 837                 }
 838                 rte_mem_lock_page(vf_info[i].vlan_table);
 839
 840                 vf_info[i].vlan_as_table = rte_zmalloc("VF VLAN AS table",
 841                                                        getpagesize(), getpagesize());
 842                 if (vf_info[i].vlan_as_table == NULL) {
 843                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN AS table for VF %d\n", i);
 844                         goto err;
 845                 }
 846                 rte_mem_lock_page(vf_info[i].vlan_as_table);
 847
 848                 STAILQ_INIT(&vf_info[i].filter);
 849         }
 850
 851         bp->pf->vf_info = vf_info;
 852
 853         return 0;
 854 err:
 855         bnxt_free_vf_info(bp);
 856         return -ENOMEM;
 857 }
 858
 859 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 860 {
 861         int rc = 0;
 862         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 863         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 864         uint16_t new_max_vfs;
 865         uint32_t flags;
 866
 867         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 868
 869         req.fid = rte_cpu_to_le_16(0xffff);
 870
 871         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 872
 873         HWRM_CHECK_RESULT();
 874
 875         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 876         flags = rte_le_to_cpu_32(resp->flags);
 877         if (BNXT_PF(bp)) {
 878                 bp->pf->port_id = resp->port_id;
 879                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 880                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 881                 new_max_vfs = bp->pdev->max_vfs;
 882                 if (new_max_vfs != bp->pf->max_vfs) {
 883                         rc = bnxt_alloc_vf_info(bp, new_max_vfs);
 884                         if (rc)
 885                                 goto unlock;
 886                 }
 887         }
 888
 889         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 890         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 891                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 892                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 893         } else {
 894                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 895         }
 896         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 897         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 898         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 899         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 900         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 901         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 902         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 903         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
 904                 bp->max_l2_ctx += bp->max_rx_em_flows;
 905         /* TODO: For now, do not support VMDq/RFS on VFs. */
 906         if (BNXT_PF(bp)) {
 907                 if (bp->pf->max_vfs)
 908                         bp->max_vnics = 1;
 909                 else
 910                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 911         } else {
 912                 bp->max_vnics = 1;
 913         }
 914         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 915                     bp->max_l2_ctx, bp->max_vnics);
 916         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 917         if (BNXT_PF(bp)) {
 918                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 919                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 920                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 921                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 922                         HWRM_UNLOCK();
 923                         bnxt_hwrm_ptp_qcfg(bp);
 924                 }
 925         }
 926
 927         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 928                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 929
 930         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 931                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 932                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 933         }
 934
 935         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 936                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 937
 938         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 939                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 940
 941         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
 942                 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
 943
 944         if (!(flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED)) {
 945                 bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT;
 946                 PMD_DRV_LOG(DEBUG, "VLAN acceleration for TX is enabled\n");
 947         }
 948 unlock:
 949         HWRM_UNLOCK();
 950
 951         return rc;
 952 }
 953
 954 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 955 {
 956         int rc;
 957
 958         rc = __bnxt_hwrm_func_qcaps(bp);
 959         if (rc == -ENOMEM)
 960                 return rc;
 961
 962         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 963                 rc = bnxt_alloc_ctx_mem(bp);
 964                 if (rc)
 965                         return rc;
 966
 967                 /* On older FW,
 968                  * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 969                  * But the error can be ignored. Return success.
 970                  */
 971                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 972                 if (!rc)
 973                         bp->flags |= BNXT_FLAG_NEW_RM;
 974         }
 975
 976         return 0;
 977 }
 978
 979 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 980 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 981 {
 982         int rc = 0;
 983         uint32_t flags;
 984         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 985         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 986
 987         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 988
 989         req.target_id = rte_cpu_to_le_16(0xffff);
 990
 991         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 992
 993         HWRM_CHECK_RESULT();
 994
 995         flags = rte_le_to_cpu_32(resp->flags);
 996
 997         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 998                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 999                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
1000         }
1001
1002         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
1003                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
1004
1005         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
1006                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
1007
1008         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP) {
1009                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_VLAN_RX_STRIP;
1010                 PMD_DRV_LOG(DEBUG, "Rx VLAN strip capability enabled\n");
1011         }
1012
1013         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
1014
1015         HWRM_UNLOCK();
1016
1017         return rc;
1018 }
1019
1020 int bnxt_hwrm_func_reset(struct bnxt *bp)
1021 {
1022         int rc = 0;
1023         struct hwrm_func_reset_input req = {.req_type = 0 };
1024         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
1025
1026         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
1027
1028         req.enables = rte_cpu_to_le_32(0);
1029
1030         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1031
1032         HWRM_CHECK_RESULT();
1033         HWRM_UNLOCK();
1034
1035         return rc;
1036 }
1037
1038 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
1039 {
1040         int rc;
1041         uint32_t flags = 0;
1042         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
1043         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
1044
1045         if (bp->flags & BNXT_FLAG_REGISTERED)
1046                 return 0;
1047
1048         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
1049                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
1050         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1051                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
1052
1053         /* PFs and trusted VFs should indicate the support of the
1054          * Master capability on non Stingray platform
1055          */
1056         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
1057                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
1058
1059         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
1060         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
1061                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
1062         req.ver_maj = RTE_VER_YEAR;
1063         req.ver_min = RTE_VER_MONTH;
1064         req.ver_upd = RTE_VER_MINOR;
1065
1066         if (BNXT_PF(bp)) {
1067                 req.enables |= rte_cpu_to_le_32(
1068                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
1069                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
1070                        RTE_MIN(sizeof(req.vf_req_fwd),
1071                                sizeof(bp->pf->vf_req_fwd)));
1072         }
1073
1074         req.flags = rte_cpu_to_le_32(flags);
1075
1076         req.async_event_fwd[0] |=
1077                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
1078                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
1079                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
1080                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
1081                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
1082         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1083                 req.async_event_fwd[0] |=
1084                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
1085         req.async_event_fwd[1] |=
1086                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
1087                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
1088         if (BNXT_PF(bp))
1089                 req.async_event_fwd[1] |=
1090                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
1091
1092         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
1093                 req.async_event_fwd[1] |=
1094                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
1095
1096         req.async_event_fwd[2] |=
1097                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST |
1098                                  ASYNC_CMPL_EVENT_ID_ERROR_REPORT);
1099
1100         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1101
1102         HWRM_CHECK_RESULT();
1103
1104         flags = rte_le_to_cpu_32(resp->flags);
1105         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
1106                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
1107
1108         HWRM_UNLOCK();
1109
1110         bp->flags |= BNXT_FLAG_REGISTERED;
1111
1112         return rc;
1113 }
1114
1115 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
1116 {
1117         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
1118                 return 0;
1119
1120         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
1121 }
1122
1123 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
1124 {
1125         int rc;
1126         uint32_t flags = 0;
1127         uint32_t enables;
1128         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1129         struct hwrm_func_vf_cfg_input req = {0};
1130
1131         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
1132
1133         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
1134                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
1135                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
1136                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1137                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
1138
1139         if (BNXT_HAS_RING_GRPS(bp)) {
1140                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
1141                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
1142         }
1143
1144         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
1145         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
1146                                             AGG_RING_MULTIPLIER);
1147         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1148         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1149                                               bp->tx_nr_rings +
1150                                               BNXT_NUM_ASYNC_CPR(bp));
1151         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1152         if (bp->vf_resv_strategy ==
1153             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1154                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1155                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1156                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1157                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1158                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1159                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1160         } else if (bp->vf_resv_strategy ==
1161                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1162                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1163                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1164         }
1165
1166         if (test)
1167                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1168                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1169                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1170                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1171                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1172                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1173
1174         if (test && BNXT_HAS_RING_GRPS(bp))
1175                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1176
1177         req.flags = rte_cpu_to_le_32(flags);
1178         req.enables |= rte_cpu_to_le_32(enables);
1179
1180         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1181
1182         if (test)
1183                 HWRM_CHECK_RESULT_SILENT();
1184         else
1185                 HWRM_CHECK_RESULT();
1186
1187         HWRM_UNLOCK();
1188         return rc;
1189 }
1190
1191 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1192 {
1193         int rc;
1194         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1195         struct hwrm_func_resource_qcaps_input req = {0};
1196
1197         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1198         req.fid = rte_cpu_to_le_16(0xffff);
1199
1200         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1201
1202         HWRM_CHECK_RESULT_SILENT();
1203
1204         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1205         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1206         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1207         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1208         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1209         /* func_resource_qcaps does not return max_rx_em_flows.
1210          * So use the value provided by func_qcaps.
1211          */
1212         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1213         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1214                 bp->max_l2_ctx += bp->max_rx_em_flows;
1215         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1216         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1217         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1218         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1219         if (bp->vf_resv_strategy >
1220             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1221                 bp->vf_resv_strategy =
1222                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1223
1224         HWRM_UNLOCK();
1225         return rc;
1226 }
1227
1228 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1229 {
1230         int rc = 0;
1231         struct hwrm_ver_get_input req = {.req_type = 0 };
1232         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1233         uint32_t fw_version;
1234         uint16_t max_resp_len;
1235         char type[RTE_MEMZONE_NAMESIZE];
1236         uint32_t dev_caps_cfg;
1237
1238         bp->max_req_len = HWRM_MAX_REQ_LEN;
1239         bp->hwrm_cmd_timeout = timeout;
1240         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1241
1242         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1243         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1244         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1245
1246         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1247
1248         if (bp->flags & BNXT_FLAG_FW_RESET)
1249                 HWRM_CHECK_RESULT_SILENT();
1250         else
1251                 HWRM_CHECK_RESULT();
1252
1253         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY) {
1254                 rc = -EAGAIN;
1255                 goto error;
1256         }
1257
1258         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
1259                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1260                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1261                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
1262                 resp->hwrm_fw_rsvd_8b);
1263         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1264                      (resp->hwrm_fw_min_8b << 16) |
1265                      (resp->hwrm_fw_bld_8b << 8) |
1266                      resp->hwrm_fw_rsvd_8b;
1267         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1268                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1269
1270         fw_version = resp->hwrm_intf_maj_8b << 16;
1271         fw_version |= resp->hwrm_intf_min_8b << 8;
1272         fw_version |= resp->hwrm_intf_upd_8b;
1273         bp->hwrm_spec_code = fw_version;
1274
1275         /* def_req_timeout value is in milliseconds */
1276         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1277         /* convert timeout to usec */
1278         bp->hwrm_cmd_timeout *= 1000;
1279         if (!bp->hwrm_cmd_timeout)
1280                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1281
1282         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1283                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1284                 rc = -EINVAL;
1285                 goto error;
1286         }
1287
1288         if (bp->max_req_len > resp->max_req_win_len) {
1289                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1290                 rc = -EINVAL;
1291                 goto error;
1292         }
1293
1294         bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1295
1296         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1297         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1298         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1299                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1300
1301         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1302         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1303
1304         RTE_VERIFY(max_resp_len <= bp->max_resp_len);
1305         bp->max_resp_len = max_resp_len;
1306
1307         if ((dev_caps_cfg &
1308                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1309             (dev_caps_cfg &
1310              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1311                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1312                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1313         }
1314
1315         if (((dev_caps_cfg &
1316               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1317              (dev_caps_cfg &
1318               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1319             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1320                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1321                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1322                         bp->pdev->addr.devid, bp->pdev->addr.function);
1323
1324                 rte_free(bp->hwrm_short_cmd_req_addr);
1325
1326                 bp->hwrm_short_cmd_req_addr =
1327                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1328                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1329                         rc = -ENOMEM;
1330                         goto error;
1331                 }
1332                 bp->hwrm_short_cmd_req_dma_addr =
1333                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1334                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1335                         rte_free(bp->hwrm_short_cmd_req_addr);
1336                         PMD_DRV_LOG(ERR,
1337                                 "Unable to map buffer to physical memory.\n");
1338                         rc = -ENOMEM;
1339                         goto error;
1340                 }
1341         }
1342         if (dev_caps_cfg &
1343             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1344                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1345                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1346         }
1347         if (dev_caps_cfg &
1348             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1349                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1350         if (dev_caps_cfg &
1351             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1352                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1353                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1354         }
1355
1356         if (dev_caps_cfg &
1357             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1358                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1359                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1360         }
1361
1362         if (dev_caps_cfg &
1363             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED) {
1364                 PMD_DRV_LOG(DEBUG, "Host-based truflow feature enabled.\n");
1365                 bp->fw_cap |= BNXT_FW_CAP_TRUFLOW_EN;
1366         }
1367
1368 error:
1369         HWRM_UNLOCK();
1370         return rc;
1371 }
1372
1373 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1374 {
1375         int rc;
1376         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1377         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1378
1379         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1380                 return 0;
1381
1382         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1383         req.flags = flags;
1384
1385         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1386
1387         HWRM_CHECK_RESULT();
1388         HWRM_UNLOCK();
1389
1390         PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
1391                     bp->eth_dev->data->port_id);
1392
1393         return rc;
1394 }
1395
1396 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1397 {
1398         int rc = 0;
1399         struct hwrm_port_phy_cfg_input req = {0};
1400         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1401         uint32_t enables = 0;
1402
1403         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1404
1405         if (conf->link_up) {
1406                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1407                 if (bp->link_info->auto_mode && conf->link_speed) {
1408                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1409                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1410                 }
1411
1412                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1413                 /*
1414                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1415                  * any auto mode, even "none".
1416                  */
1417                 if (!conf->link_speed) {
1418                         /* No speeds specified. Enable AutoNeg - all speeds */
1419                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1420                         req.auto_mode =
1421                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1422                 } else {
1423                         if (bp->link_info->link_signal_mode) {
1424                                 enables |=
1425                                 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1426                                 req.force_pam4_link_speed =
1427                                         rte_cpu_to_le_16(conf->link_speed);
1428                         } else {
1429                                 req.force_link_speed =
1430                                         rte_cpu_to_le_16(conf->link_speed);
1431                         }
1432                 }
1433                 /* AutoNeg - Advertise speeds specified. */
1434                 if (conf->auto_link_speed_mask &&
1435                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1436                         req.auto_mode =
1437                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1438                         req.auto_link_speed_mask =
1439                                 conf->auto_link_speed_mask;
1440                         if (conf->auto_pam4_link_speeds) {
1441                                 enables |=
1442                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1443                                 req.auto_link_pam4_speed_mask =
1444                                         conf->auto_pam4_link_speeds;
1445                         } else {
1446                                 enables |=
1447                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1448                         }
1449                 }
1450                 if (conf->auto_link_speed &&
1451                 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1452                         enables |=
1453                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1454
1455                 req.auto_duplex = conf->duplex;
1456                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1457                 req.auto_pause = conf->auto_pause;
1458                 req.force_pause = conf->force_pause;
1459                 /* Set force_pause if there is no auto or if there is a force */
1460                 if (req.auto_pause && !req.force_pause)
1461                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1462                 else
1463                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1464
1465                 req.enables = rte_cpu_to_le_32(enables);
1466         } else {
1467                 req.flags =
1468                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1469                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1470         }
1471
1472         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1473
1474         HWRM_CHECK_RESULT();
1475         HWRM_UNLOCK();
1476
1477         return rc;
1478 }
1479
1480 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1481                                    struct bnxt_link_info *link_info)
1482 {
1483         int rc = 0;
1484         struct hwrm_port_phy_qcfg_input req = {0};
1485         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1486
1487         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1488
1489         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1490
1491         HWRM_CHECK_RESULT();
1492
1493         link_info->phy_link_status = resp->link;
1494         link_info->link_up =
1495                 (link_info->phy_link_status ==
1496                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1497         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1498         link_info->duplex = resp->duplex_cfg;
1499         link_info->pause = resp->pause;
1500         link_info->auto_pause = resp->auto_pause;
1501         link_info->force_pause = resp->force_pause;
1502         link_info->auto_mode = resp->auto_mode;
1503         link_info->phy_type = resp->phy_type;
1504         link_info->media_type = resp->media_type;
1505
1506         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1507         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1508         link_info->auto_link_speed_mask = rte_le_to_cpu_16(resp->auto_link_speed_mask);
1509         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1510         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1511         link_info->phy_ver[0] = resp->phy_maj;
1512         link_info->phy_ver[1] = resp->phy_min;
1513         link_info->phy_ver[2] = resp->phy_bld;
1514         link_info->link_signal_mode =
1515                 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1516         link_info->force_pam4_link_speed =
1517                         rte_le_to_cpu_16(resp->force_pam4_link_speed);
1518         link_info->support_pam4_speeds =
1519                         rte_le_to_cpu_16(resp->support_pam4_speeds);
1520         link_info->auto_pam4_link_speeds =
1521                         rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1522         link_info->module_status = resp->module_status;
1523         HWRM_UNLOCK();
1524
1525         PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1526                     link_info->link_speed, link_info->auto_mode,
1527                     link_info->auto_link_speed, link_info->auto_link_speed_mask,
1528                     link_info->support_speeds, link_info->force_link_speed);
1529         PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1530                     link_info->link_signal_mode,
1531                     link_info->auto_pam4_link_speeds,
1532                     link_info->support_pam4_speeds,
1533                     link_info->force_pam4_link_speed);
1534         return rc;
1535 }
1536
1537 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1538 {
1539         int rc = 0;
1540         struct hwrm_port_phy_qcaps_input req = {0};
1541         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1542         struct bnxt_link_info *link_info = bp->link_info;
1543
1544         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1545                 return 0;
1546
1547         HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1548
1549         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1550
1551         HWRM_CHECK_RESULT_SILENT();
1552
1553         bp->port_cnt = resp->port_cnt;
1554         if (resp->supported_speeds_auto_mode)
1555                 link_info->support_auto_speeds =
1556                         rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1557         if (resp->supported_pam4_speeds_auto_mode)
1558                 link_info->support_pam4_auto_speeds =
1559                         rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1560
1561         HWRM_UNLOCK();
1562
1563         /* Older firmware does not have supported_auto_speeds, so assume
1564          * that all supported speeds can be autonegotiated.
1565          */
1566         if (link_info->auto_link_speed_mask && !link_info->support_auto_speeds)
1567                 link_info->support_auto_speeds = link_info->support_speeds;
1568
1569         return 0;
1570 }
1571
1572 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1573 {
1574         int i = 0;
1575
1576         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1577                 if (bp->tx_cos_queue[i].profile ==
1578                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1579                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1580                         return true;
1581                 }
1582         }
1583         return false;
1584 }
1585
1586 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1587 {
1588         int i = 0;
1589
1590         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1591                 if (bp->tx_cos_queue[i].profile !=
1592                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1593                     bp->tx_cos_queue[i].id !=
1594                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1595                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1596                         break;
1597                 }
1598         }
1599 }
1600
1601 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1602 {
1603         int rc = 0;
1604         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1605         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1606         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1607         int i;
1608
1609 get_rx_info:
1610         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1611
1612         req.flags = rte_cpu_to_le_32(dir);
1613         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1614         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1615             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1616                 req.drv_qmap_cap =
1617                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1618         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1619
1620         HWRM_CHECK_RESULT();
1621
1622         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1623                 GET_TX_QUEUE_INFO(0);
1624                 GET_TX_QUEUE_INFO(1);
1625                 GET_TX_QUEUE_INFO(2);
1626                 GET_TX_QUEUE_INFO(3);
1627                 GET_TX_QUEUE_INFO(4);
1628                 GET_TX_QUEUE_INFO(5);
1629                 GET_TX_QUEUE_INFO(6);
1630                 GET_TX_QUEUE_INFO(7);
1631         } else  {
1632                 GET_RX_QUEUE_INFO(0);
1633                 GET_RX_QUEUE_INFO(1);
1634                 GET_RX_QUEUE_INFO(2);
1635                 GET_RX_QUEUE_INFO(3);
1636                 GET_RX_QUEUE_INFO(4);
1637                 GET_RX_QUEUE_INFO(5);
1638                 GET_RX_QUEUE_INFO(6);
1639                 GET_RX_QUEUE_INFO(7);
1640         }
1641
1642         HWRM_UNLOCK();
1643
1644         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1645                 goto done;
1646
1647         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1648                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1649         } else {
1650                 int j;
1651
1652                 /* iterate and find the COSq profile to use for Tx */
1653                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1654                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1655                                 if (bp->tx_cos_queue[i].id != 0xff)
1656                                         bp->tx_cosq_id[j++] =
1657                                                 bp->tx_cos_queue[i].id;
1658                         }
1659                 } else {
1660                         /* When CoS classification is disabled, for normal NIC
1661                          * operations, ideally we should look to use LOSSY.
1662                          * If not found, fallback to the first valid profile
1663                          */
1664                         if (!bnxt_find_lossy_profile(bp))
1665                                 bnxt_find_first_valid_profile(bp);
1666
1667                 }
1668         }
1669
1670         bp->max_tc = resp->max_configurable_queues;
1671         bp->max_lltc = resp->max_configurable_lossless_queues;
1672         if (bp->max_tc > BNXT_MAX_QUEUE)
1673                 bp->max_tc = BNXT_MAX_QUEUE;
1674         bp->max_q = bp->max_tc;
1675
1676         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1677                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1678                 goto get_rx_info;
1679         }
1680
1681 done:
1682         return rc;
1683 }
1684
1685 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1686                          struct bnxt_ring *ring,
1687                          uint32_t ring_type, uint32_t map_index,
1688                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1689                          uint16_t tx_cosq_id)
1690 {
1691         int rc = 0;
1692         uint32_t enables = 0;
1693         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1694         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1695         struct rte_mempool *mb_pool;
1696         uint16_t rx_buf_size;
1697
1698         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1699
1700         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1701         req.fbo = rte_cpu_to_le_32(0);
1702         /* Association of ring index with doorbell index */
1703         req.logical_id = rte_cpu_to_le_16(map_index);
1704         req.length = rte_cpu_to_le_32(ring->ring_size);
1705
1706         switch (ring_type) {
1707         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1708                 req.ring_type = ring_type;
1709                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1710                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1711                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1712                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1713                         enables |=
1714                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1715                 break;
1716         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1717                 req.ring_type = ring_type;
1718                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1719                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1720                 if (BNXT_CHIP_P5(bp)) {
1721                         mb_pool = bp->rx_queues[0]->mb_pool;
1722                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1723                                       RTE_PKTMBUF_HEADROOM;
1724                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1725                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1726                         enables |=
1727                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1728                 }
1729                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1730                         enables |=
1731                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1732                 break;
1733         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1734                 req.ring_type = ring_type;
1735                 if (BNXT_HAS_NQ(bp)) {
1736                         /* Association of cp ring with nq */
1737                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1738                         enables |=
1739                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1740                 }
1741                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1742                 break;
1743         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1744                 req.ring_type = ring_type;
1745                 req.page_size = BNXT_PAGE_SHFT;
1746                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1747                 break;
1748         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1749                 req.ring_type = ring_type;
1750                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1751
1752                 mb_pool = bp->rx_queues[0]->mb_pool;
1753                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1754                               RTE_PKTMBUF_HEADROOM;
1755                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1756                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1757
1758                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1759                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1760                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1761                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1762                 break;
1763         default:
1764                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1765                         ring_type);
1766                 HWRM_UNLOCK();
1767                 return -EINVAL;
1768         }
1769         req.enables = rte_cpu_to_le_32(enables);
1770
1771         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1772
1773         if (rc || resp->error_code) {
1774                 if (rc == 0 && resp->error_code)
1775                         rc = rte_le_to_cpu_16(resp->error_code);
1776                 switch (ring_type) {
1777                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1778                         PMD_DRV_LOG(ERR,
1779                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1780                         HWRM_UNLOCK();
1781                         return rc;
1782                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1783                         PMD_DRV_LOG(ERR,
1784                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1785                         HWRM_UNLOCK();
1786                         return rc;
1787                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1788                         PMD_DRV_LOG(ERR,
1789                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1790                                     rc);
1791                         HWRM_UNLOCK();
1792                         return rc;
1793                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1794                         PMD_DRV_LOG(ERR,
1795                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1796                         HWRM_UNLOCK();
1797                         return rc;
1798                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1799                         PMD_DRV_LOG(ERR,
1800                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1801                         HWRM_UNLOCK();
1802                         return rc;
1803                 default:
1804                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1805                         HWRM_UNLOCK();
1806                         return rc;
1807                 }
1808         }
1809
1810         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1811         HWRM_UNLOCK();
1812         return rc;
1813 }
1814
1815 int bnxt_hwrm_ring_free(struct bnxt *bp,
1816                         struct bnxt_ring *ring, uint32_t ring_type,
1817                         uint16_t cp_ring_id)
1818 {
1819         int rc;
1820         struct hwrm_ring_free_input req = {.req_type = 0 };
1821         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1822
1823         if (ring->fw_ring_id == INVALID_HW_RING_ID)
1824                 return -EINVAL;
1825
1826         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1827
1828         req.ring_type = ring_type;
1829         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1830         req.cmpl_ring = rte_cpu_to_le_16(cp_ring_id);
1831
1832         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1833         ring->fw_ring_id = INVALID_HW_RING_ID;
1834
1835         if (rc || resp->error_code) {
1836                 if (rc == 0 && resp->error_code)
1837                         rc = rte_le_to_cpu_16(resp->error_code);
1838                 HWRM_UNLOCK();
1839
1840                 switch (ring_type) {
1841                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1842                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1843                                 rc);
1844                         return rc;
1845                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1846                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1847                                 rc);
1848                         return rc;
1849                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1850                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1851                                 rc);
1852                         return rc;
1853                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1854                         PMD_DRV_LOG(ERR,
1855                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1856                         return rc;
1857                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1858                         PMD_DRV_LOG(ERR,
1859                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1860                         return rc;
1861                 default:
1862                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1863                         return rc;
1864                 }
1865         }
1866         HWRM_UNLOCK();
1867         return 0;
1868 }
1869
1870 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1871 {
1872         int rc = 0;
1873         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1874         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1875
1876         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1877
1878         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1879         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1880         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1881         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1882
1883         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1884
1885         HWRM_CHECK_RESULT();
1886
1887         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1888
1889         HWRM_UNLOCK();
1890
1891         return rc;
1892 }
1893
1894 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1895 {
1896         int rc;
1897         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1898         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1899
1900         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1901
1902         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1903
1904         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1905
1906         HWRM_CHECK_RESULT();
1907         HWRM_UNLOCK();
1908
1909         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1910         return rc;
1911 }
1912
1913 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1914 {
1915         int rc = 0;
1916         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1917         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1918
1919         if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE)
1920                 return rc;
1921
1922         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1923
1924         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1925
1926         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1927
1928         HWRM_CHECK_RESULT();
1929         HWRM_UNLOCK();
1930
1931         return rc;
1932 }
1933
1934 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1935 {
1936         int rc;
1937         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1938         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1939
1940         if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE)
1941                 return 0;
1942
1943         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1944
1945         req.update_period_ms = rte_cpu_to_le_32(0);
1946
1947         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1948
1949         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1950
1951         HWRM_CHECK_RESULT();
1952
1953         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1954
1955         HWRM_UNLOCK();
1956
1957         return rc;
1958 }
1959
1960 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1961 {
1962         int rc;
1963         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1964         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1965
1966         if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE)
1967                 return 0;
1968
1969         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1970
1971         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1972
1973         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1974
1975         HWRM_CHECK_RESULT();
1976         HWRM_UNLOCK();
1977
1978         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1979
1980         return rc;
1981 }
1982
1983 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1984 {
1985         int rc = 0, i, j;
1986         struct hwrm_vnic_alloc_input req = { 0 };
1987         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1988
1989         if (!BNXT_HAS_RING_GRPS(bp))
1990                 goto skip_ring_grps;
1991
1992         /* map ring groups to this vnic */
1993         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1994                 vnic->start_grp_id, vnic->end_grp_id);
1995         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1996                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1997
1998         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1999         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
2000         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
2001         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
2002
2003 skip_ring_grps:
2004         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
2005         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
2006
2007         if (vnic->func_default)
2008                 req.flags =
2009                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
2010         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2011
2012         HWRM_CHECK_RESULT();
2013
2014         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
2015         HWRM_UNLOCK();
2016         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2017         return rc;
2018 }
2019
2020 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
2021                                         struct bnxt_vnic_info *vnic,
2022                                         struct bnxt_plcmodes_cfg *pmode)
2023 {
2024         int rc = 0;
2025         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
2026         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2027
2028         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
2029
2030         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2031
2032         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2033
2034         HWRM_CHECK_RESULT();
2035
2036         pmode->flags = rte_le_to_cpu_32(resp->flags);
2037         /* dflt_vnic bit doesn't exist in the _cfg command */
2038         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
2039         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
2040         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
2041         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
2042
2043         HWRM_UNLOCK();
2044
2045         return rc;
2046 }
2047
2048 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
2049                                        struct bnxt_vnic_info *vnic,
2050                                        struct bnxt_plcmodes_cfg *pmode)
2051 {
2052         int rc = 0;
2053         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2054         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2055
2056         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2057                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2058                 return rc;
2059         }
2060
2061         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2062
2063         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2064         req.flags = rte_cpu_to_le_32(pmode->flags);
2065         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
2066         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
2067         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
2068         req.enables = rte_cpu_to_le_32(
2069             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
2070             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
2071             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
2072         );
2073
2074         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2075
2076         HWRM_CHECK_RESULT();
2077         HWRM_UNLOCK();
2078
2079         return rc;
2080 }
2081
2082 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2083 {
2084         int rc = 0;
2085         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
2086         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2087         struct bnxt_plcmodes_cfg pmodes = { 0 };
2088         uint32_t ctx_enable_flag = 0;
2089         uint32_t enables = 0;
2090
2091         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2092                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2093                 return rc;
2094         }
2095
2096         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
2097         if (rc)
2098                 return rc;
2099
2100         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
2101
2102         if (BNXT_CHIP_P5(bp)) {
2103                 int dflt_rxq = vnic->start_grp_id;
2104                 struct bnxt_rx_ring_info *rxr;
2105                 struct bnxt_cp_ring_info *cpr;
2106                 struct bnxt_rx_queue *rxq;
2107                 int i;
2108
2109                 /*
2110                  * The first active receive ring is used as the VNIC
2111                  * default receive ring. If there are no active receive
2112                  * rings (all corresponding receive queues are stopped),
2113                  * the first receive ring is used.
2114                  */
2115                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
2116                         rxq = bp->eth_dev->data->rx_queues[i];
2117                         if (rxq->rx_started) {
2118                                 dflt_rxq = i;
2119                                 break;
2120                         }
2121                 }
2122
2123                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
2124                 rxr = rxq->rx_ring;
2125                 cpr = rxq->cp_ring;
2126
2127                 req.default_rx_ring_id =
2128                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
2129                 req.default_cmpl_ring_id =
2130                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
2131                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
2132                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
2133                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
2134                         enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
2135                         req.rx_csum_v2_mode =
2136                                 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
2137                 }
2138                 goto config_mru;
2139         }
2140
2141         /* Only RSS support for now TBD: COS & LB */
2142         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
2143         if (vnic->lb_rule != 0xffff)
2144                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
2145         if (vnic->cos_rule != 0xffff)
2146                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
2147         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
2148                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
2149                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
2150         }
2151         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
2152                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
2153                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
2154         }
2155
2156         enables |= ctx_enable_flag;
2157         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
2158         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
2159         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
2160         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2161
2162 config_mru:
2163         req.enables = rte_cpu_to_le_32(enables);
2164         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2165         req.mru = rte_cpu_to_le_16(vnic->mru);
2166         /* Configure default VNIC only once. */
2167         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2168                 req.flags |=
2169                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2170                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2171         }
2172         if (vnic->vlan_strip)
2173                 req.flags |=
2174                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2175         if (vnic->bd_stall)
2176                 req.flags |=
2177                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2178         if (vnic->rss_dflt_cr)
2179                 req.flags |= rte_cpu_to_le_32(
2180                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2181
2182         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2183
2184         HWRM_CHECK_RESULT();
2185         HWRM_UNLOCK();
2186
2187         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2188
2189         return rc;
2190 }
2191
2192 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2193                 int16_t fw_vf_id)
2194 {
2195         int rc = 0;
2196         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2197         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2198
2199         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2200                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2201                 return rc;
2202         }
2203         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2204
2205         req.enables =
2206                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2207         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2208         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2209
2210         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2211
2212         HWRM_CHECK_RESULT();
2213
2214         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2215         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2216         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2217         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2218         vnic->mru = rte_le_to_cpu_16(resp->mru);
2219         vnic->func_default = rte_le_to_cpu_32(
2220                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2221         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2222                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2223         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2224                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2225         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2226                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2227
2228         HWRM_UNLOCK();
2229
2230         return rc;
2231 }
2232
2233 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2234                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2235 {
2236         int rc = 0;
2237         uint16_t ctx_id;
2238         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2239         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2240                                                 bp->hwrm_cmd_resp_addr;
2241
2242         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2243
2244         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2245         HWRM_CHECK_RESULT();
2246
2247         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2248         if (!BNXT_HAS_RING_GRPS(bp))
2249                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2250         else if (ctx_idx == 0)
2251                 vnic->rss_rule = ctx_id;
2252
2253         HWRM_UNLOCK();
2254
2255         return rc;
2256 }
2257
2258 static
2259 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2260                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2261 {
2262         int rc = 0;
2263         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2264         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2265                                                 bp->hwrm_cmd_resp_addr;
2266
2267         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2268                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2269                 return rc;
2270         }
2271         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2272
2273         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2274
2275         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2276
2277         HWRM_CHECK_RESULT();
2278         HWRM_UNLOCK();
2279
2280         return rc;
2281 }
2282
2283 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2284 {
2285         int rc = 0;
2286
2287         if (BNXT_CHIP_P5(bp)) {
2288                 int j;
2289
2290                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2291                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2292                                                       vnic,
2293                                                       vnic->fw_grp_ids[j]);
2294                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2295                 }
2296                 vnic->num_lb_ctxts = 0;
2297         } else {
2298                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2299                 vnic->rss_rule = INVALID_HW_RING_ID;
2300         }
2301
2302         return rc;
2303 }
2304
2305 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2306 {
2307         int rc = 0;
2308         struct hwrm_vnic_free_input req = {.req_type = 0 };
2309         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2310
2311         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2312                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2313                 return rc;
2314         }
2315
2316         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2317
2318         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2319
2320         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2321
2322         HWRM_CHECK_RESULT();
2323         HWRM_UNLOCK();
2324
2325         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2326         /* Configure default VNIC again if necessary. */
2327         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2328                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2329
2330         return rc;
2331 }
2332
2333 static int
2334 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2335 {
2336         int i;
2337         int rc = 0;
2338         int nr_ctxs = vnic->num_lb_ctxts;
2339         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2340         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2341
2342         for (i = 0; i < nr_ctxs; i++) {
2343                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2344
2345                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2346                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2347                 req.hash_mode_flags = vnic->hash_mode;
2348
2349                 req.hash_key_tbl_addr =
2350                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2351
2352                 req.ring_grp_tbl_addr =
2353                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2354                                          i * HW_HASH_INDEX_SIZE);
2355                 req.ring_table_pair_index = i;
2356                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2357
2358                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2359                                             BNXT_USE_CHIMP_MB);
2360
2361                 HWRM_CHECK_RESULT();
2362                 HWRM_UNLOCK();
2363         }
2364
2365         return rc;
2366 }
2367
2368 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2369                            struct bnxt_vnic_info *vnic)
2370 {
2371         int rc = 0;
2372         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2373         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2374
2375         if (!vnic->rss_table)
2376                 return 0;
2377
2378         if (BNXT_CHIP_P5(bp))
2379                 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2380
2381         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2382
2383         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2384         req.hash_mode_flags = vnic->hash_mode;
2385
2386         req.ring_grp_tbl_addr =
2387             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2388         req.hash_key_tbl_addr =
2389             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2390         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2391         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2392
2393         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2394
2395         HWRM_CHECK_RESULT();
2396         HWRM_UNLOCK();
2397
2398         return rc;
2399 }
2400
2401 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2402                         struct bnxt_vnic_info *vnic)
2403 {
2404         int rc = 0;
2405         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2406         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2407         uint16_t size;
2408
2409         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2410                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2411                 return rc;
2412         }
2413
2414         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2415
2416         req.flags = rte_cpu_to_le_32(
2417                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2418
2419         req.enables = rte_cpu_to_le_32(
2420                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2421
2422         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2423         size -= RTE_PKTMBUF_HEADROOM;
2424         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2425
2426         req.jumbo_thresh = rte_cpu_to_le_16(size);
2427         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2428
2429         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2430
2431         HWRM_CHECK_RESULT();
2432         HWRM_UNLOCK();
2433
2434         return rc;
2435 }
2436
2437 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2438                         struct bnxt_vnic_info *vnic, bool enable)
2439 {
2440         int rc = 0;
2441         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2442         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2443
2444         if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2445                 if (enable)
2446                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2447                 return -ENOTSUP;
2448         }
2449
2450         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2451                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2452                 return 0;
2453         }
2454
2455         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2456
2457         if (enable) {
2458                 req.enables = rte_cpu_to_le_32(
2459                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2460                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2461                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2462                 req.flags = rte_cpu_to_le_32(
2463                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2464                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2465                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2466                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2467                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2468                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2469                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2470                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2471                 req.min_agg_len = rte_cpu_to_le_32(512);
2472         }
2473         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2474
2475         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2476
2477         HWRM_CHECK_RESULT();
2478         HWRM_UNLOCK();
2479
2480         return rc;
2481 }
2482
2483 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2484 {
2485         struct hwrm_func_cfg_input req = {0};
2486         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2487         int rc;
2488
2489         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2490         req.enables = rte_cpu_to_le_32(
2491                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2492         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2493         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2494
2495         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2496
2497         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2498         HWRM_CHECK_RESULT();
2499         HWRM_UNLOCK();
2500
2501         bp->pf->vf_info[vf].random_mac = false;
2502
2503         return rc;
2504 }
2505
2506 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2507                                   uint64_t *dropped)
2508 {
2509         int rc = 0;
2510         struct hwrm_func_qstats_input req = {.req_type = 0};
2511         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2512
2513         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2514
2515         req.fid = rte_cpu_to_le_16(fid);
2516
2517         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2518
2519         HWRM_CHECK_RESULT();
2520
2521         if (dropped)
2522                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2523
2524         HWRM_UNLOCK();
2525
2526         return rc;
2527 }
2528
2529 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2530                           struct rte_eth_stats *stats,
2531                           struct hwrm_func_qstats_output *func_qstats)
2532 {
2533         int rc = 0;
2534         struct hwrm_func_qstats_input req = {.req_type = 0};
2535         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2536
2537         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2538
2539         req.fid = rte_cpu_to_le_16(fid);
2540
2541         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2542
2543         HWRM_CHECK_RESULT();
2544         if (func_qstats)
2545                 memcpy(func_qstats, resp,
2546                        sizeof(struct hwrm_func_qstats_output));
2547
2548         if (!stats)
2549                 goto exit;
2550
2551         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2552         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2553         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2554         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2555         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2556         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2557
2558         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2559         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2560         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2561         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2562         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2563         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2564
2565         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2566         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2567         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2568
2569 exit:
2570         HWRM_UNLOCK();
2571
2572         return rc;
2573 }
2574
2575 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2576 {
2577         int rc = 0;
2578         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2579         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2580
2581         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2582
2583         req.fid = rte_cpu_to_le_16(fid);
2584
2585         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2586
2587         HWRM_CHECK_RESULT();
2588         HWRM_UNLOCK();
2589
2590         return rc;
2591 }
2592
2593 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2594 {
2595         unsigned int i;
2596         int rc = 0;
2597
2598         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2599                 struct bnxt_tx_queue *txq;
2600                 struct bnxt_rx_queue *rxq;
2601                 struct bnxt_cp_ring_info *cpr;
2602
2603                 if (i >= bp->rx_cp_nr_rings) {
2604                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2605                         cpr = txq->cp_ring;
2606                 } else {
2607                         rxq = bp->rx_queues[i];
2608                         cpr = rxq->cp_ring;
2609                 }
2610
2611                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2612                 if (rc)
2613                         return rc;
2614         }
2615         return 0;
2616 }
2617
2618 static int
2619 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2620 {
2621         int rc;
2622         unsigned int i;
2623         struct bnxt_cp_ring_info *cpr;
2624
2625         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2626
2627                 cpr = bp->rx_queues[i]->cp_ring;
2628                 if (BNXT_HAS_RING_GRPS(bp))
2629                         bp->grp_info[i].fw_stats_ctx = -1;
2630                 rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2631                 if (rc)
2632                         return rc;
2633         }
2634
2635         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2636                 cpr = bp->tx_queues[i]->cp_ring;
2637                 rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2638                 if (rc)
2639                         return rc;
2640         }
2641
2642         return 0;
2643 }
2644
2645 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2646 {
2647         struct bnxt_cp_ring_info *cpr;
2648         unsigned int i;
2649         int rc = 0;
2650
2651         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2652                 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
2653
2654                 cpr = rxq->cp_ring;
2655                 if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE) {
2656                         rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr);
2657                         if (rc)
2658                                 return rc;
2659                 }
2660         }
2661
2662         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2663                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2664
2665                 cpr = txq->cp_ring;
2666                 if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE) {
2667                         rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr);
2668                         if (rc)
2669                                 return rc;
2670                 }
2671         }
2672
2673         return rc;
2674 }
2675
2676 static int
2677 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2678 {
2679         uint16_t idx;
2680         uint32_t rc = 0;
2681
2682         if (!BNXT_HAS_RING_GRPS(bp))
2683                 return 0;
2684
2685         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2686
2687                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2688                         continue;
2689
2690                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2691
2692                 if (rc)
2693                         return rc;
2694         }
2695         return rc;
2696 }
2697
2698 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2699 {
2700         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2701
2702         bnxt_hwrm_ring_free(bp, cp_ring,
2703                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ,
2704                             INVALID_HW_RING_ID);
2705         memset(cpr->cp_desc_ring, 0,
2706                cpr->cp_ring_struct->ring_size * sizeof(*cpr->cp_desc_ring));
2707         cpr->cp_raw_cons = 0;
2708 }
2709
2710 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2711 {
2712         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2713
2714         bnxt_hwrm_ring_free(bp, cp_ring,
2715                             HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL,
2716                             INVALID_HW_RING_ID);
2717         memset(cpr->cp_desc_ring, 0,
2718                cpr->cp_ring_struct->ring_size * sizeof(*cpr->cp_desc_ring));
2719         cpr->cp_raw_cons = 0;
2720 }
2721
2722 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2723 {
2724         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2725         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2726         struct bnxt_ring *ring = rxr->rx_ring_struct;
2727         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2728
2729         if (BNXT_HAS_RING_GRPS(bp))
2730                 bnxt_hwrm_ring_grp_free(bp, queue_index);
2731
2732         bnxt_hwrm_ring_free(bp, ring,
2733                             HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2734                             cpr->cp_ring_struct->fw_ring_id);
2735         if (BNXT_HAS_RING_GRPS(bp))
2736                 bp->grp_info[queue_index].rx_fw_ring_id = INVALID_HW_RING_ID;
2737
2738         ring = rxr->ag_ring_struct;
2739         bnxt_hwrm_ring_free(bp, ring,
2740                             BNXT_CHIP_P5(bp) ?
2741                             HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2742                             HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2743                             cpr->cp_ring_struct->fw_ring_id);
2744         if (BNXT_HAS_RING_GRPS(bp))
2745                 bp->grp_info[queue_index].ag_fw_ring_id = INVALID_HW_RING_ID;
2746
2747         bnxt_hwrm_stat_ctx_free(bp, cpr);
2748
2749         bnxt_free_cp_ring(bp, cpr);
2750
2751         if (BNXT_HAS_RING_GRPS(bp))
2752                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2753 }
2754
2755 int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int queue_index)
2756 {
2757         int rc;
2758         struct hwrm_ring_reset_input req = {.req_type = 0 };
2759         struct hwrm_ring_reset_output *resp = bp->hwrm_cmd_resp_addr;
2760
2761         HWRM_PREP(&req, HWRM_RING_RESET, BNXT_USE_CHIMP_MB);
2762
2763         req.ring_type = HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP;
2764         req.ring_id = rte_cpu_to_le_16(bp->grp_info[queue_index].fw_grp_id);
2765         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2766
2767         HWRM_CHECK_RESULT();
2768
2769         HWRM_UNLOCK();
2770
2771         return rc;
2772 }
2773
2774 static int
2775 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2776 {
2777         unsigned int i;
2778
2779         for (i = 0; i < bp->tx_cp_nr_rings; i++)
2780                 bnxt_free_hwrm_tx_ring(bp, i);
2781
2782         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2783                 bnxt_free_hwrm_rx_ring(bp, i);
2784
2785         return 0;
2786 }
2787
2788 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2789 {
2790         uint16_t i;
2791         uint32_t rc = 0;
2792
2793         if (!BNXT_HAS_RING_GRPS(bp))
2794                 return 0;
2795
2796         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2797                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2798                 if (rc)
2799                         return rc;
2800         }
2801         return rc;
2802 }
2803
2804 /*
2805  * HWRM utility functions
2806  */
2807
2808 void bnxt_free_hwrm_resources(struct bnxt *bp)
2809 {
2810         /* Release memzone */
2811         rte_free(bp->hwrm_cmd_resp_addr);
2812         rte_free(bp->hwrm_short_cmd_req_addr);
2813         bp->hwrm_cmd_resp_addr = NULL;
2814         bp->hwrm_short_cmd_req_addr = NULL;
2815         bp->hwrm_cmd_resp_dma_addr = 0;
2816         bp->hwrm_short_cmd_req_dma_addr = 0;
2817 }
2818
2819 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2820 {
2821         struct rte_pci_device *pdev = bp->pdev;
2822         char type[RTE_MEMZONE_NAMESIZE];
2823
2824         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2825                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2826         bp->max_resp_len = BNXT_PAGE_SIZE;
2827         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2828         if (bp->hwrm_cmd_resp_addr == NULL)
2829                 return -ENOMEM;
2830         bp->hwrm_cmd_resp_dma_addr =
2831                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2832         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2833                 PMD_DRV_LOG(ERR,
2834                         "unable to map response address to physical memory\n");
2835                 return -ENOMEM;
2836         }
2837         rte_spinlock_init(&bp->hwrm_lock);
2838
2839         return 0;
2840 }
2841
2842 int
2843 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2844 {
2845         int rc = 0;
2846
2847         if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2848                 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2849                 if (rc)
2850                         return rc;
2851         } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2852                 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2853                 if (rc)
2854                         return rc;
2855         }
2856
2857         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2858         return rc;
2859 }
2860
2861 static int
2862 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2863 {
2864         struct bnxt_filter_info *filter;
2865         int rc = 0;
2866
2867         STAILQ_FOREACH(filter, &vnic->filter, next) {
2868                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2869                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2870                 bnxt_free_filter(bp, filter);
2871         }
2872         return rc;
2873 }
2874
2875 static int
2876 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2877 {
2878         struct bnxt_filter_info *filter;
2879         struct rte_flow *flow;
2880         int rc = 0;
2881
2882         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2883                 flow = STAILQ_FIRST(&vnic->flow_list);
2884                 filter = flow->filter;
2885                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2886                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2887
2888                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2889                 rte_free(flow);
2890         }
2891         return rc;
2892 }
2893
2894 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2895 {
2896         struct bnxt_filter_info *filter;
2897         int rc = 0;
2898
2899         STAILQ_FOREACH(filter, &vnic->filter, next) {
2900                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2901                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2902                                                      filter);
2903                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2904                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2905                                                          filter);
2906                 else
2907                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2908                                                      filter);
2909                 if (rc)
2910                         break;
2911         }
2912         return rc;
2913 }
2914
2915 static void
2916 bnxt_free_tunnel_ports(struct bnxt *bp)
2917 {
2918         if (bp->vxlan_port_cnt)
2919                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2920                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2921
2922         if (bp->geneve_port_cnt)
2923                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2924                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2925 }
2926
2927 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2928 {
2929         int i;
2930
2931         if (bp->vnic_info == NULL)
2932                 return;
2933
2934         /*
2935          * Cleanup VNICs in reverse order, to make sure the L2 filter
2936          * from vnic0 is last to be cleaned up.
2937          */
2938         for (i = bp->max_vnics - 1; i >= 0; i--) {
2939                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2940
2941                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2942                         continue;
2943
2944                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2945
2946                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2947
2948                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2949
2950                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2951
2952                 bnxt_hwrm_vnic_free(bp, vnic);
2953
2954                 rte_free(vnic->fw_grp_ids);
2955         }
2956         /* Ring resources */
2957         bnxt_free_all_hwrm_rings(bp);
2958         bnxt_free_all_hwrm_ring_grps(bp);
2959         bnxt_free_all_hwrm_stat_ctxs(bp);
2960         bnxt_free_tunnel_ports(bp);
2961 }
2962
2963 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2964 {
2965         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2966
2967         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2968                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2969
2970         switch (conf_link_speed) {
2971         case ETH_LINK_SPEED_10M_HD:
2972         case ETH_LINK_SPEED_100M_HD:
2973                 /* FALLTHROUGH */
2974                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2975         }
2976         return hw_link_duplex;
2977 }
2978
2979 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2980 {
2981         return !conf_link;
2982 }
2983
2984 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2985                                           uint16_t pam4_link)
2986 {
2987         uint16_t eth_link_speed = 0;
2988
2989         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2990                 return ETH_LINK_SPEED_AUTONEG;
2991
2992         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2993         case ETH_LINK_SPEED_100M:
2994         case ETH_LINK_SPEED_100M_HD:
2995                 /* FALLTHROUGH */
2996                 eth_link_speed =
2997                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2998                 break;
2999         case ETH_LINK_SPEED_1G:
3000                 eth_link_speed =
3001                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
3002                 break;
3003         case ETH_LINK_SPEED_2_5G:
3004                 eth_link_speed =
3005                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
3006                 break;
3007         case ETH_LINK_SPEED_10G:
3008                 eth_link_speed =
3009                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
3010                 break;
3011         case ETH_LINK_SPEED_20G:
3012                 eth_link_speed =
3013                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
3014                 break;
3015         case ETH_LINK_SPEED_25G:
3016                 eth_link_speed =
3017                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
3018                 break;
3019         case ETH_LINK_SPEED_40G:
3020                 eth_link_speed =
3021                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
3022                 break;
3023         case ETH_LINK_SPEED_50G:
3024                 eth_link_speed = pam4_link ?
3025                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
3026                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
3027                 break;
3028         case ETH_LINK_SPEED_100G:
3029                 eth_link_speed = pam4_link ?
3030                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
3031                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
3032                 break;
3033         case ETH_LINK_SPEED_200G:
3034                 eth_link_speed =
3035                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3036                 break;
3037         default:
3038                 PMD_DRV_LOG(ERR,
3039                         "Unsupported link speed %d; default to AUTO\n",
3040                         conf_link_speed);
3041                 break;
3042         }
3043         return eth_link_speed;
3044 }
3045
3046 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
3047                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
3048                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
3049                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
3050                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
3051
3052 static int bnxt_validate_link_speed(struct bnxt *bp)
3053 {
3054         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
3055         uint16_t port_id = bp->eth_dev->data->port_id;
3056         uint32_t link_speed_capa;
3057         uint32_t one_speed;
3058
3059         if (link_speed == ETH_LINK_SPEED_AUTONEG)
3060                 return 0;
3061
3062         link_speed_capa = bnxt_get_speed_capabilities(bp);
3063
3064         if (link_speed & ETH_LINK_SPEED_FIXED) {
3065                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
3066
3067                 if (one_speed & (one_speed - 1)) {
3068                         PMD_DRV_LOG(ERR,
3069                                 "Invalid advertised speeds (%u) for port %u\n",
3070                                 link_speed, port_id);
3071                         return -EINVAL;
3072                 }
3073                 if ((one_speed & link_speed_capa) != one_speed) {
3074                         PMD_DRV_LOG(ERR,
3075                                 "Unsupported advertised speed (%u) for port %u\n",
3076                                 link_speed, port_id);
3077                         return -EINVAL;
3078                 }
3079         } else {
3080                 if (!(link_speed & link_speed_capa)) {
3081                         PMD_DRV_LOG(ERR,
3082                                 "Unsupported advertised speeds (%u) for port %u\n",
3083                                 link_speed, port_id);
3084                         return -EINVAL;
3085                 }
3086         }
3087         return 0;
3088 }
3089
3090 static uint16_t
3091 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
3092 {
3093         uint16_t ret = 0;
3094
3095         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
3096                 if (bp->link_info->support_speeds)
3097                         return bp->link_info->support_speeds;
3098                 link_speed = BNXT_SUPPORTED_SPEEDS;
3099         }
3100
3101         if (link_speed & ETH_LINK_SPEED_100M)
3102                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3103         if (link_speed & ETH_LINK_SPEED_100M_HD)
3104                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3105         if (link_speed & ETH_LINK_SPEED_1G)
3106                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
3107         if (link_speed & ETH_LINK_SPEED_2_5G)
3108                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
3109         if (link_speed & ETH_LINK_SPEED_10G)
3110                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
3111         if (link_speed & ETH_LINK_SPEED_20G)
3112                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
3113         if (link_speed & ETH_LINK_SPEED_25G)
3114                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
3115         if (link_speed & ETH_LINK_SPEED_40G)
3116                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
3117         if (link_speed & ETH_LINK_SPEED_50G)
3118                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
3119         if (link_speed & ETH_LINK_SPEED_100G)
3120                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
3121         if (link_speed & ETH_LINK_SPEED_200G)
3122                 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3123         return ret;
3124 }
3125
3126 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
3127 {
3128         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
3129
3130         switch (hw_link_speed) {
3131         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
3132                 eth_link_speed = ETH_SPEED_NUM_100M;
3133                 break;
3134         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
3135                 eth_link_speed = ETH_SPEED_NUM_1G;
3136                 break;
3137         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
3138                 eth_link_speed = ETH_SPEED_NUM_2_5G;
3139                 break;
3140         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
3141                 eth_link_speed = ETH_SPEED_NUM_10G;
3142                 break;
3143         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
3144                 eth_link_speed = ETH_SPEED_NUM_20G;
3145                 break;
3146         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
3147                 eth_link_speed = ETH_SPEED_NUM_25G;
3148                 break;
3149         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
3150                 eth_link_speed = ETH_SPEED_NUM_40G;
3151                 break;
3152         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
3153                 eth_link_speed = ETH_SPEED_NUM_50G;
3154                 break;
3155         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
3156                 eth_link_speed = ETH_SPEED_NUM_100G;
3157                 break;
3158         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3159                 eth_link_speed = ETH_SPEED_NUM_200G;
3160                 break;
3161         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3162         default:
3163                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3164                         hw_link_speed);
3165                 break;
3166         }
3167         return eth_link_speed;
3168 }
3169
3170 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3171 {
3172         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3173
3174         switch (hw_link_duplex) {
3175         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3176         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3177                 /* FALLTHROUGH */
3178                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3179                 break;
3180         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3181                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3182                 break;
3183         default:
3184                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3185                         hw_link_duplex);
3186                 break;
3187         }
3188         return eth_link_duplex;
3189 }
3190
3191 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3192 {
3193         int rc = 0;
3194         struct bnxt_link_info *link_info = bp->link_info;
3195
3196         rc = bnxt_hwrm_port_phy_qcaps(bp);
3197         if (rc)
3198                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3199
3200         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3201         if (rc) {
3202                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3203                 goto exit;
3204         }
3205
3206         if (link_info->link_speed)
3207                 link->link_speed =
3208                         bnxt_parse_hw_link_speed(link_info->link_speed);
3209         else
3210                 link->link_speed = ETH_SPEED_NUM_NONE;
3211         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3212         link->link_status = link_info->link_up;
3213         link->link_autoneg = link_info->auto_mode ==
3214                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3215                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3216 exit:
3217         return rc;
3218 }
3219
3220 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3221 {
3222         int rc = 0;
3223         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3224         struct bnxt_link_info link_req;
3225         uint16_t speed, autoneg;
3226
3227         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3228                 return 0;
3229
3230         rc = bnxt_validate_link_speed(bp);
3231         if (rc)
3232                 goto error;
3233
3234         memset(&link_req, 0, sizeof(link_req));
3235         link_req.link_up = link_up;
3236         if (!link_up)
3237                 goto port_phy_cfg;
3238
3239         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3240         if (BNXT_CHIP_P5(bp) &&
3241             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3242                 /* 40G is not supported as part of media auto detect.
3243                  * The speed should be forced and autoneg disabled
3244                  * to configure 40G speed.
3245                  */
3246                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3247                 autoneg = 0;
3248         }
3249
3250         /* No auto speeds and no auto_pam4_link. Disable autoneg */
3251         if (bp->link_info->auto_link_speed == 0 &&
3252             bp->link_info->link_signal_mode &&
3253             bp->link_info->auto_pam4_link_speeds == 0)
3254                 autoneg = 0;
3255
3256         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3257                                           bp->link_info->link_signal_mode);
3258         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3259         /* Autoneg can be done only when the FW allows. */
3260         if (autoneg == 1 && bp->link_info->support_auto_speeds) {
3261                 link_req.phy_flags |=
3262                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3263                 link_req.auto_link_speed_mask =
3264                         bnxt_parse_eth_link_speed_mask(bp,
3265                                                        dev_conf->link_speeds);
3266         } else {
3267                 if (bp->link_info->phy_type ==
3268                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3269                     bp->link_info->phy_type ==
3270                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3271                     bp->link_info->media_type ==
3272                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3273                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3274                         return -EINVAL;
3275                 }
3276
3277                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3278                 /* If user wants a particular speed try that first. */
3279                 if (speed)
3280                         link_req.link_speed = speed;
3281                 else if (bp->link_info->force_pam4_link_speed)
3282                         link_req.link_speed =
3283                                 bp->link_info->force_pam4_link_speed;
3284                 else if (bp->link_info->auto_pam4_link_speeds)
3285                         link_req.link_speed =
3286                                 bp->link_info->auto_pam4_link_speeds;
3287                 else if (bp->link_info->support_pam4_speeds)
3288                         link_req.link_speed =
3289                                 bp->link_info->support_pam4_speeds;
3290                 else if (bp->link_info->force_link_speed)
3291                         link_req.link_speed = bp->link_info->force_link_speed;
3292                 else
3293                         link_req.link_speed = bp->link_info->auto_link_speed;
3294                 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3295                  * zero. Use the auto_link_speed.
3296                  */
3297                 if (bp->link_info->auto_link_speed != 0 &&
3298                     bp->link_info->auto_pam4_link_speeds == 0)
3299                         link_req.link_speed = bp->link_info->auto_link_speed;
3300         }
3301         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3302         link_req.auto_pause = bp->link_info->auto_pause;
3303         link_req.force_pause = bp->link_info->force_pause;
3304
3305 port_phy_cfg:
3306         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3307         if (rc) {
3308                 PMD_DRV_LOG(ERR,
3309                         "Set link config failed with rc %d\n", rc);
3310         }
3311
3312 error:
3313         return rc;
3314 }
3315
3316 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3317 {
3318         struct hwrm_func_qcfg_input req = {0};
3319         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3320         uint16_t flags;
3321         int rc = 0;
3322         bp->func_svif = BNXT_SVIF_INVALID;
3323         uint16_t svif_info;
3324
3325         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3326         req.fid = rte_cpu_to_le_16(0xffff);
3327
3328         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3329
3330         HWRM_CHECK_RESULT();
3331
3332         bp->vlan = rte_le_to_cpu_16(resp->vlan) & ETH_VLAN_ID_MAX;
3333
3334         svif_info = rte_le_to_cpu_16(resp->svif_info);
3335         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3336                 bp->func_svif = svif_info &
3337                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3338
3339         flags = rte_le_to_cpu_16(resp->flags);
3340         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3341                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3342
3343         if (BNXT_VF(bp) &&
3344             !BNXT_VF_IS_TRUSTED(bp) &&
3345             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3346                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3347                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3348         } else if (BNXT_VF(bp) &&
3349                    BNXT_VF_IS_TRUSTED(bp) &&
3350                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3351                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3352                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3353         }
3354
3355         if (mtu)
3356                 *mtu = rte_le_to_cpu_16(resp->admin_mtu);
3357
3358         switch (resp->port_partition_type) {
3359         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3360         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3361         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3362                 /* FALLTHROUGH */
3363                 bp->flags |= BNXT_FLAG_NPAR_PF;
3364                 break;
3365         default:
3366                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3367                 break;
3368         }
3369
3370         bp->legacy_db_size =
3371                 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3372
3373         HWRM_UNLOCK();
3374
3375         return rc;
3376 }
3377
3378 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3379 {
3380         struct hwrm_func_qcfg_input req = {0};
3381         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3382         int rc;
3383
3384         if (!BNXT_VF_IS_TRUSTED(bp))
3385                 return 0;
3386
3387         if (!bp->parent)
3388                 return -EINVAL;
3389
3390         bp->parent->fid = BNXT_PF_FID_INVALID;
3391
3392         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3393
3394         req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3395
3396         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3397
3398         HWRM_CHECK_RESULT_SILENT();
3399
3400         memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3401         bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3402         bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3403         bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3404
3405         HWRM_UNLOCK();
3406
3407         return 0;
3408 }
3409
3410 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3411                                  uint16_t *vnic_id, uint16_t *svif)
3412 {
3413         struct hwrm_func_qcfg_input req = {0};
3414         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3415         uint16_t svif_info;
3416         int rc = 0;
3417
3418         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3419         req.fid = rte_cpu_to_le_16(fid);
3420
3421         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3422
3423         HWRM_CHECK_RESULT();
3424
3425         if (vnic_id)
3426                 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3427
3428         svif_info = rte_le_to_cpu_16(resp->svif_info);
3429         if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3430                 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3431
3432         HWRM_UNLOCK();
3433
3434         return rc;
3435 }
3436
3437 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3438 {
3439         struct hwrm_port_mac_qcfg_input req = {0};
3440         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3441         uint16_t port_svif_info;
3442         int rc;
3443
3444         bp->port_svif = BNXT_SVIF_INVALID;
3445
3446         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3447                 return 0;
3448
3449         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3450
3451         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3452
3453         HWRM_CHECK_RESULT_SILENT();
3454
3455         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3456         if (port_svif_info &
3457             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3458                 bp->port_svif = port_svif_info &
3459                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3460
3461         HWRM_UNLOCK();
3462
3463         return 0;
3464 }
3465
3466 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3467                                  struct bnxt_pf_resource_info *pf_resc)
3468 {
3469         struct hwrm_func_cfg_input req = {0};
3470         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3471         uint32_t enables;
3472         int rc;
3473
3474         enables = HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU |
3475                   HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU |
3476                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3477                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3478                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3479                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3480                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3481                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3482                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3483                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3484
3485         if (BNXT_HAS_RING_GRPS(bp)) {
3486                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3487                 req.num_hw_ring_grps =
3488                         rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3489         } else if (BNXT_HAS_NQ(bp)) {
3490                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3491                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3492         }
3493
3494         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3495         req.admin_mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3496         req.host_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu);
3497         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3498         req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3499         req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3500         req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3501         req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3502         req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3503         req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3504         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3505         req.fid = rte_cpu_to_le_16(0xffff);
3506         req.enables = rte_cpu_to_le_32(enables);
3507
3508         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3509
3510         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3511
3512         HWRM_CHECK_RESULT();
3513         HWRM_UNLOCK();
3514
3515         return rc;
3516 }
3517
3518 /* min values are the guaranteed resources and max values are subject
3519  * to availability. The strategy for now is to keep both min & max
3520  * values the same.
3521  */
3522 static void
3523 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3524                               struct hwrm_func_vf_resource_cfg_input *req,
3525                               int num_vfs)
3526 {
3527         req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3528                                                (num_vfs + 1));
3529         req->min_rsscos_ctx = req->max_rsscos_ctx;
3530         req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3531         req->min_stat_ctx = req->max_stat_ctx;
3532         req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3533                                                (num_vfs + 1));
3534         req->min_cmpl_rings = req->max_cmpl_rings;
3535         req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3536         req->min_tx_rings = req->max_tx_rings;
3537         req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3538         req->min_rx_rings = req->max_rx_rings;
3539         req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3540         req->min_l2_ctxs = req->max_l2_ctxs;
3541         /* TODO: For now, do not support VMDq/RFS on VFs. */
3542         req->max_vnics = rte_cpu_to_le_16(1);
3543         req->min_vnics = req->max_vnics;
3544         req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3545                                                  (num_vfs + 1));
3546         req->min_hw_ring_grps = req->max_hw_ring_grps;
3547         req->flags =
3548          rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
3549 }
3550
3551 static void
3552 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3553                               struct hwrm_func_cfg_input *req,
3554                               int num_vfs)
3555 {
3556         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU |
3557                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3558                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3559                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3560                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3561                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3562                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3563                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3564                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3565                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3566
3567         req->admin_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3568                                           RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3569                                           BNXT_NUM_VLANS);
3570         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3571         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3572                                                 (num_vfs + 1));
3573         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3574         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3575                                                (num_vfs + 1));
3576         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3577         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3578         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3579         /* TODO: For now, do not support VMDq/RFS on VFs. */
3580         req->num_vnics = rte_cpu_to_le_16(1);
3581         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3582                                                  (num_vfs + 1));
3583 }
3584
3585 /* Update the port wide resource values based on how many resources
3586  * got allocated to the VF.
3587  */
3588 static int bnxt_update_max_resources(struct bnxt *bp,
3589                                      int vf)
3590 {
3591         struct hwrm_func_qcfg_input req = {0};
3592         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3593         int rc;
3594
3595         /* Get the actual allocated values now */
3596         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3597         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3598         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3599         HWRM_CHECK_RESULT();
3600
3601         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3602         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3603         bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3604         bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3605         bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3606         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3607         bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3608
3609         HWRM_UNLOCK();
3610
3611         return 0;
3612 }
3613
3614 /* Update the PF resource values based on how many resources
3615  * got allocated to it.
3616  */
3617 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3618 {
3619         struct hwrm_func_qcfg_input req = {0};
3620         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3621         int rc;
3622
3623         /* Get the actual allocated values now */
3624         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3625         req.fid = rte_cpu_to_le_16(0xffff);
3626         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3627         HWRM_CHECK_RESULT();
3628
3629         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3630         bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3631         bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3632         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3633         bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3634         bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3635         bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3636         bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3637
3638         HWRM_UNLOCK();
3639
3640         return 0;
3641 }
3642
3643 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3644 {
3645         struct hwrm_func_qcfg_input req = {0};
3646         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3647         int rc;
3648
3649         /* Check for zero MAC address */
3650         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3651         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3652         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3653         HWRM_CHECK_RESULT();
3654         rc = rte_le_to_cpu_16(resp->vlan);
3655
3656         HWRM_UNLOCK();
3657
3658         return rc;
3659 }
3660
3661 static int bnxt_query_pf_resources(struct bnxt *bp,
3662                                    struct bnxt_pf_resource_info *pf_resc)
3663 {
3664         struct hwrm_func_qcfg_input req = {0};
3665         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3666         int rc;
3667
3668         /* And copy the allocated numbers into the pf struct */
3669         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3670         req.fid = rte_cpu_to_le_16(0xffff);
3671         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3672         HWRM_CHECK_RESULT();
3673
3674         pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3675         pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3676         pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3677         pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3678         pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3679         pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3680         pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3681         bp->pf->evb_mode = resp->evb_mode;
3682
3683         HWRM_UNLOCK();
3684
3685         return rc;
3686 }
3687
3688 static void
3689 bnxt_calculate_pf_resources(struct bnxt *bp,
3690                             struct bnxt_pf_resource_info *pf_resc,
3691                             int num_vfs)
3692 {
3693         if (!num_vfs) {
3694                 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3695                 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3696                 pf_resc->num_cp_rings = bp->max_cp_rings;
3697                 pf_resc->num_tx_rings = bp->max_tx_rings;
3698                 pf_resc->num_rx_rings = bp->max_rx_rings;
3699                 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3700                 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3701
3702                 return;
3703         }
3704
3705         pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3706                                    bp->max_rsscos_ctx % (num_vfs + 1);
3707         pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3708                                  bp->max_stat_ctx % (num_vfs + 1);
3709         pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3710                                 bp->max_cp_rings % (num_vfs + 1);
3711         pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3712                                 bp->max_tx_rings % (num_vfs + 1);
3713         pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3714                                 bp->max_rx_rings % (num_vfs + 1);
3715         pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3716                                bp->max_l2_ctx % (num_vfs + 1);
3717         pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3718                                     bp->max_ring_grps % (num_vfs + 1);
3719 }
3720
3721 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3722 {
3723         struct bnxt_pf_resource_info pf_resc = { 0 };
3724         int rc;
3725
3726         if (!BNXT_PF(bp)) {
3727                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3728                 return -EINVAL;
3729         }
3730
3731         rc = bnxt_hwrm_func_qcaps(bp);
3732         if (rc)
3733                 return rc;
3734
3735         bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3736
3737         bp->pf->func_cfg_flags &=
3738                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3739                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3740         bp->pf->func_cfg_flags |=
3741                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3742
3743         rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3744         if (rc)
3745                 return rc;
3746
3747         rc = bnxt_update_max_resources_pf_only(bp);
3748
3749         return rc;
3750 }
3751
3752 static int
3753 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3754 {
3755         size_t req_buf_sz, sz;
3756         int i, rc;
3757
3758         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3759         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3760                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3761         if (bp->pf->vf_req_buf == NULL) {
3762                 return -ENOMEM;
3763         }
3764
3765         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3766                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3767
3768         for (i = 0; i < num_vfs; i++)
3769                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3770                                              (i * HWRM_MAX_REQ_LEN);
3771
3772         rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3773         if (rc)
3774                 rte_free(bp->pf->vf_req_buf);
3775
3776         return rc;
3777 }
3778
3779 static int
3780 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3781 {
3782         struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3783         struct hwrm_func_vf_resource_cfg_input req = {0};
3784         int i, rc = 0;
3785
3786         bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3787         bp->pf->active_vfs = 0;
3788         for (i = 0; i < num_vfs; i++) {
3789                 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3790                 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3791                 rc = bnxt_hwrm_send_message(bp,
3792                                             &req,
3793                                             sizeof(req),
3794                                             BNXT_USE_CHIMP_MB);
3795                 if (rc || resp->error_code) {
3796                         PMD_DRV_LOG(ERR,
3797                                 "Failed to initialize VF %d\n", i);
3798                         PMD_DRV_LOG(ERR,
3799                                 "Not all VFs available. (%d, %d)\n",
3800                                 rc, resp->error_code);
3801                         HWRM_UNLOCK();
3802
3803                         /* If the first VF configuration itself fails,
3804                          * unregister the vf_fwd_request buffer.
3805                          */
3806                         if (i == 0)
3807                                 bnxt_hwrm_func_buf_unrgtr(bp);
3808                         break;
3809                 }
3810                 HWRM_UNLOCK();
3811
3812                 /* Update the max resource values based on the resource values
3813                  * allocated to the VF.
3814                  */
3815                 bnxt_update_max_resources(bp, i);
3816                 bp->pf->active_vfs++;
3817                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3818         }
3819
3820         return 0;
3821 }
3822
3823 static int
3824 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3825 {
3826         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3827         struct hwrm_func_cfg_input req = {0};
3828         int i, rc;
3829
3830         bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3831
3832         bp->pf->active_vfs = 0;
3833         for (i = 0; i < num_vfs; i++) {
3834                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3835                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3836                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3837                 rc = bnxt_hwrm_send_message(bp,
3838                                             &req,
3839                                             sizeof(req),
3840                                             BNXT_USE_CHIMP_MB);
3841
3842                 /* Clear enable flag for next pass */
3843                 req.enables &= ~rte_cpu_to_le_32(
3844                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3845
3846                 if (rc || resp->error_code) {
3847                         PMD_DRV_LOG(ERR,
3848                                 "Failed to initialize VF %d\n", i);
3849                         PMD_DRV_LOG(ERR,
3850                                 "Not all VFs available. (%d, %d)\n",
3851                                 rc, resp->error_code);
3852                         HWRM_UNLOCK();
3853
3854                         /* If the first VF configuration itself fails,
3855                          * unregister the vf_fwd_request buffer.
3856                          */
3857                         if (i == 0)
3858                                 bnxt_hwrm_func_buf_unrgtr(bp);
3859                         break;
3860                 }
3861
3862                 HWRM_UNLOCK();
3863
3864                 /* Update the max resource values based on the resource values
3865                  * allocated to the VF.
3866                  */
3867                 bnxt_update_max_resources(bp, i);
3868                 bp->pf->active_vfs++;
3869                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3870         }
3871
3872         return 0;
3873 }
3874
3875 static void
3876 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3877 {
3878         if (bp->flags & BNXT_FLAG_NEW_RM)
3879                 bnxt_process_vf_resc_config_new(bp, num_vfs);
3880         else
3881                 bnxt_process_vf_resc_config_old(bp, num_vfs);
3882 }
3883
3884 static void
3885 bnxt_update_pf_resources(struct bnxt *bp,
3886                          struct bnxt_pf_resource_info *pf_resc)
3887 {
3888         bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3889         bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3890         bp->max_cp_rings = pf_resc->num_cp_rings;
3891         bp->max_tx_rings = pf_resc->num_tx_rings;
3892         bp->max_rx_rings = pf_resc->num_rx_rings;
3893         bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3894 }
3895
3896 static int32_t
3897 bnxt_configure_pf_resources(struct bnxt *bp,
3898                             struct bnxt_pf_resource_info *pf_resc)
3899 {
3900         /*
3901          * We're using STD_TX_RING_MODE here which will limit the TX
3902          * rings. This will allow QoS to function properly. Not setting this
3903          * will cause PF rings to break bandwidth settings.
3904          */
3905         bp->pf->func_cfg_flags &=
3906                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3907                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3908         bp->pf->func_cfg_flags |=
3909                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3910         return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3911 }
3912
3913 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3914 {
3915         struct bnxt_pf_resource_info pf_resc = { 0 };
3916         int rc;
3917
3918         if (!BNXT_PF(bp)) {
3919                 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3920                 return -EINVAL;
3921         }
3922
3923         rc = bnxt_hwrm_func_qcaps(bp);
3924         if (rc)
3925                 return rc;
3926
3927         bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3928
3929         rc = bnxt_configure_pf_resources(bp, &pf_resc);
3930         if (rc)
3931                 return rc;
3932
3933         rc = bnxt_query_pf_resources(bp, &pf_resc);
3934         if (rc)
3935                 return rc;
3936
3937         /*
3938          * Now, create and register a buffer to hold forwarded VF requests
3939          */
3940         rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3941         if (rc)
3942                 return rc;
3943
3944         bnxt_configure_vf_resources(bp, num_vfs);
3945
3946         bnxt_update_pf_resources(bp, &pf_resc);
3947
3948         return 0;
3949 }
3950
3951 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3952 {
3953         struct hwrm_func_cfg_input req = {0};
3954         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3955         int rc;
3956
3957         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3958
3959         req.fid = rte_cpu_to_le_16(0xffff);
3960         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3961         req.evb_mode = bp->pf->evb_mode;
3962
3963         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3964         HWRM_CHECK_RESULT();
3965         HWRM_UNLOCK();
3966
3967         return rc;
3968 }
3969
3970 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3971                                 uint8_t tunnel_type)
3972 {
3973         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3974         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3975         int rc = 0;
3976
3977         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3978         req.tunnel_type = tunnel_type;
3979         req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3980         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3981         HWRM_CHECK_RESULT();
3982
3983         switch (tunnel_type) {
3984         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3985                 bp->vxlan_fw_dst_port_id =
3986                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3987                 bp->vxlan_port = port;
3988                 break;
3989         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3990                 bp->geneve_fw_dst_port_id =
3991                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3992                 bp->geneve_port = port;
3993                 break;
3994         default:
3995                 break;
3996         }
3997
3998         HWRM_UNLOCK();
3999
4000         return rc;
4001 }
4002
4003 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
4004                                 uint8_t tunnel_type)
4005 {
4006         struct hwrm_tunnel_dst_port_free_input req = {0};
4007         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
4008         int rc = 0;
4009
4010         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
4011
4012         req.tunnel_type = tunnel_type;
4013         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
4014         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4015
4016         HWRM_CHECK_RESULT();
4017         HWRM_UNLOCK();
4018
4019         if (tunnel_type ==
4020             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
4021                 bp->vxlan_port = 0;
4022                 bp->vxlan_port_cnt = 0;
4023         }
4024
4025         if (tunnel_type ==
4026             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
4027                 bp->geneve_port = 0;
4028                 bp->geneve_port_cnt = 0;
4029         }
4030
4031         return rc;
4032 }
4033
4034 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
4035                                         uint32_t flags)
4036 {
4037         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4038         struct hwrm_func_cfg_input req = {0};
4039         int rc;
4040
4041         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4042
4043         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4044         req.flags = rte_cpu_to_le_32(flags);
4045         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4046
4047         HWRM_CHECK_RESULT();
4048         HWRM_UNLOCK();
4049
4050         return rc;
4051 }
4052
4053 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
4054 {
4055         uint32_t *flag = flagp;
4056
4057         vnic->flags = *flag;
4058 }
4059
4060 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4061 {
4062         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
4063 }
4064
4065 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
4066 {
4067         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4068         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
4069         int rc;
4070
4071         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
4072
4073         req.req_buf_num_pages = rte_cpu_to_le_16(1);
4074         req.req_buf_page_size =
4075                 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
4076         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
4077         req.req_buf_page_addr0 =
4078                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
4079         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
4080                 PMD_DRV_LOG(ERR,
4081                         "unable to map buffer address to physical memory\n");
4082                 HWRM_UNLOCK();
4083                 return -ENOMEM;
4084         }
4085
4086         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4087
4088         HWRM_CHECK_RESULT();
4089         HWRM_UNLOCK();
4090
4091         return rc;
4092 }
4093
4094 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
4095 {
4096         int rc = 0;
4097         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
4098         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
4099
4100         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
4101                 return 0;
4102
4103         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
4104
4105         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4106
4107         HWRM_CHECK_RESULT();
4108         HWRM_UNLOCK();
4109
4110         return rc;
4111 }
4112
4113 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
4114 {
4115         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4116         struct hwrm_func_cfg_input req = {0};
4117         int rc;
4118
4119         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4120
4121         req.fid = rte_cpu_to_le_16(0xffff);
4122         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
4123         req.enables = rte_cpu_to_le_32(
4124                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4125         req.async_event_cr = rte_cpu_to_le_16(
4126                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4127         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4128
4129         HWRM_CHECK_RESULT();
4130         HWRM_UNLOCK();
4131
4132         return rc;
4133 }
4134
4135 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
4136 {
4137         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4138         struct hwrm_func_vf_cfg_input req = {0};
4139         int rc;
4140
4141         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4142
4143         req.enables = rte_cpu_to_le_32(
4144                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4145         req.async_event_cr = rte_cpu_to_le_16(
4146                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4147         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4148
4149         HWRM_CHECK_RESULT();
4150         HWRM_UNLOCK();
4151
4152         return rc;
4153 }
4154
4155 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4156 {
4157         struct hwrm_func_cfg_input req = {0};
4158         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4159         uint16_t dflt_vlan, fid;
4160         uint32_t func_cfg_flags;
4161         int rc = 0;
4162
4163         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4164
4165         if (is_vf) {
4166                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4167                 fid = bp->pf->vf_info[vf].fid;
4168                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4169         } else {
4170                 fid = rte_cpu_to_le_16(0xffff);
4171                 func_cfg_flags = bp->pf->func_cfg_flags;
4172                 dflt_vlan = bp->vlan;
4173         }
4174
4175         req.flags = rte_cpu_to_le_32(func_cfg_flags);
4176         req.fid = rte_cpu_to_le_16(fid);
4177         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4178         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4179
4180         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4181
4182         HWRM_CHECK_RESULT();
4183         HWRM_UNLOCK();
4184
4185         return rc;
4186 }
4187
4188 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4189                         uint16_t max_bw, uint16_t enables)
4190 {
4191         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4192         struct hwrm_func_cfg_input req = {0};
4193         int rc;
4194
4195         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4196
4197         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4198         req.enables |= rte_cpu_to_le_32(enables);
4199         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4200         req.max_bw = rte_cpu_to_le_32(max_bw);
4201         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4202
4203         HWRM_CHECK_RESULT();
4204         HWRM_UNLOCK();
4205
4206         return rc;
4207 }
4208
4209 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4210 {
4211         struct hwrm_func_cfg_input req = {0};
4212         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4213         int rc = 0;
4214
4215         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4216
4217         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4218         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4219         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4220         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4221
4222         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4223
4224         HWRM_CHECK_RESULT();
4225         HWRM_UNLOCK();
4226
4227         return rc;
4228 }
4229
4230 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4231 {
4232         int rc;
4233
4234         if (BNXT_PF(bp))
4235                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4236         else
4237                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4238
4239         return rc;
4240 }
4241
4242 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4243                               void *encaped, size_t ec_size)
4244 {
4245         int rc = 0;
4246         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4247         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4248
4249         if (ec_size > sizeof(req.encap_request))
4250                 return -1;
4251
4252         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4253
4254         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4255         memcpy(req.encap_request, encaped, ec_size);
4256
4257         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4258
4259         HWRM_CHECK_RESULT();
4260         HWRM_UNLOCK();
4261
4262         return rc;
4263 }
4264
4265 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4266                                        struct rte_ether_addr *mac)
4267 {
4268         struct hwrm_func_qcfg_input req = {0};
4269         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4270         int rc;
4271
4272         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4273
4274         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4275         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4276
4277         HWRM_CHECK_RESULT();
4278
4279         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4280
4281         HWRM_UNLOCK();
4282
4283         return rc;
4284 }
4285
4286 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4287                             void *encaped, size_t ec_size)
4288 {
4289         int rc = 0;
4290         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4291         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4292
4293         if (ec_size > sizeof(req.encap_request))
4294                 return -1;
4295
4296         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4297
4298         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4299         memcpy(req.encap_request, encaped, ec_size);
4300
4301         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4302
4303         HWRM_CHECK_RESULT();
4304         HWRM_UNLOCK();
4305
4306         return rc;
4307 }
4308
4309 static void bnxt_update_prev_stat(uint64_t *cntr, uint64_t *prev_cntr)
4310 {
4311         /* One of the HW stat values that make up this counter was zero as
4312          * returned by HW in this iteration, so use the previous
4313          * iteration's counter value
4314          */
4315         if (*prev_cntr && *cntr == 0)
4316                 *cntr = *prev_cntr;
4317         else
4318                 *prev_cntr = *cntr;
4319 }
4320
4321 int bnxt_hwrm_ring_stats(struct bnxt *bp, uint32_t cid, int idx,
4322                          struct bnxt_ring_stats *ring_stats, bool rx)
4323 {
4324         int rc = 0;
4325         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4326         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4327
4328         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4329
4330         req.stat_ctx_id = rte_cpu_to_le_32(cid);
4331
4332         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4333
4334         HWRM_CHECK_RESULT();
4335
4336         if (rx) {
4337                 struct bnxt_ring_stats *prev_stats = &bp->prev_rx_ring_stats[idx];
4338
4339                 ring_stats->rx_ucast_pkts = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4340                 bnxt_update_prev_stat(&ring_stats->rx_ucast_pkts,
4341                                       &prev_stats->rx_ucast_pkts);
4342
4343                 ring_stats->rx_mcast_pkts = rte_le_to_cpu_64(resp->rx_mcast_pkts);
4344                 bnxt_update_prev_stat(&ring_stats->rx_mcast_pkts,
4345                                       &prev_stats->rx_mcast_pkts);
4346
4347                 ring_stats->rx_bcast_pkts = rte_le_to_cpu_64(resp->rx_bcast_pkts);
4348                 bnxt_update_prev_stat(&ring_stats->rx_bcast_pkts,
4349                                       &prev_stats->rx_bcast_pkts);
4350
4351                 ring_stats->rx_ucast_bytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4352                 bnxt_update_prev_stat(&ring_stats->rx_ucast_bytes,
4353                                       &prev_stats->rx_ucast_bytes);
4354
4355                 ring_stats->rx_mcast_bytes = rte_le_to_cpu_64(resp->rx_mcast_bytes);
4356                 bnxt_update_prev_stat(&ring_stats->rx_mcast_bytes,
4357                                       &prev_stats->rx_mcast_bytes);
4358
4359                 ring_stats->rx_bcast_bytes = rte_le_to_cpu_64(resp->rx_bcast_bytes);
4360                 bnxt_update_prev_stat(&ring_stats->rx_bcast_bytes,
4361                                       &prev_stats->rx_bcast_bytes);
4362
4363                 ring_stats->rx_discard_pkts = rte_le_to_cpu_64(resp->rx_discard_pkts);
4364                 bnxt_update_prev_stat(&ring_stats->rx_discard_pkts,
4365                                       &prev_stats->rx_discard_pkts);
4366
4367                 ring_stats->rx_error_pkts = rte_le_to_cpu_64(resp->rx_error_pkts);
4368                 bnxt_update_prev_stat(&ring_stats->rx_error_pkts,
4369                                       &prev_stats->rx_error_pkts);
4370
4371                 ring_stats->rx_agg_pkts = rte_le_to_cpu_64(resp->rx_agg_pkts);
4372                 bnxt_update_prev_stat(&ring_stats->rx_agg_pkts,
4373                                       &prev_stats->rx_agg_pkts);
4374
4375                 ring_stats->rx_agg_bytes = rte_le_to_cpu_64(resp->rx_agg_bytes);
4376                 bnxt_update_prev_stat(&ring_stats->rx_agg_bytes,
4377                                       &prev_stats->rx_agg_bytes);
4378
4379                 ring_stats->rx_agg_events = rte_le_to_cpu_64(resp->rx_agg_events);
4380                 bnxt_update_prev_stat(&ring_stats->rx_agg_events,
4381                                       &prev_stats->rx_agg_events);
4382
4383                 ring_stats->rx_agg_aborts = rte_le_to_cpu_64(resp->rx_agg_aborts);
4384                 bnxt_update_prev_stat(&ring_stats->rx_agg_aborts,
4385                                       &prev_stats->rx_agg_aborts);
4386         } else {
4387                 struct bnxt_ring_stats *prev_stats = &bp->prev_tx_ring_stats[idx];
4388
4389                 ring_stats->tx_ucast_pkts = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4390                 bnxt_update_prev_stat(&ring_stats->tx_ucast_pkts,
4391                                       &prev_stats->tx_ucast_pkts);
4392
4393                 ring_stats->tx_mcast_pkts = rte_le_to_cpu_64(resp->tx_mcast_pkts);
4394                 bnxt_update_prev_stat(&ring_stats->tx_mcast_pkts,
4395                                       &prev_stats->tx_mcast_pkts);
4396
4397                 ring_stats->tx_bcast_pkts = rte_le_to_cpu_64(resp->tx_bcast_pkts);
4398                 bnxt_update_prev_stat(&ring_stats->tx_bcast_pkts,
4399                                       &prev_stats->tx_bcast_pkts);
4400
4401                 ring_stats->tx_ucast_bytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4402                 bnxt_update_prev_stat(&ring_stats->tx_ucast_bytes,
4403                                       &prev_stats->tx_ucast_bytes);
4404
4405                 ring_stats->tx_mcast_bytes = rte_le_to_cpu_64(resp->tx_mcast_bytes);
4406                 bnxt_update_prev_stat(&ring_stats->tx_mcast_bytes,
4407                                       &prev_stats->tx_mcast_bytes);
4408
4409                 ring_stats->tx_bcast_bytes = rte_le_to_cpu_64(resp->tx_bcast_bytes);
4410                 bnxt_update_prev_stat(&ring_stats->tx_bcast_bytes,
4411                                       &prev_stats->tx_bcast_bytes);
4412
4413                 ring_stats->tx_discard_pkts = rte_le_to_cpu_64(resp->tx_discard_pkts);
4414                 bnxt_update_prev_stat(&ring_stats->tx_discard_pkts,
4415                                       &prev_stats->tx_discard_pkts);
4416         }
4417
4418         HWRM_UNLOCK();
4419
4420         return rc;
4421 }
4422
4423 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4424 {
4425         struct hwrm_port_qstats_input req = {0};
4426         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4427         struct bnxt_pf_info *pf = bp->pf;
4428         int rc;
4429
4430         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4431
4432         req.port_id = rte_cpu_to_le_16(pf->port_id);
4433         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4434         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4435         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4436
4437         HWRM_CHECK_RESULT();
4438         HWRM_UNLOCK();
4439
4440         return rc;
4441 }
4442
4443 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4444 {
4445         struct hwrm_port_clr_stats_input req = {0};
4446         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4447         struct bnxt_pf_info *pf = bp->pf;
4448         int rc;
4449
4450         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4451         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4452             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4453                 return 0;
4454
4455         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4456
4457         req.port_id = rte_cpu_to_le_16(pf->port_id);
4458         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4459
4460         HWRM_CHECK_RESULT();
4461         HWRM_UNLOCK();
4462
4463         return rc;
4464 }
4465
4466 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4467 {
4468         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4469         struct hwrm_port_led_qcaps_input req = {0};
4470         int rc;
4471
4472         if (BNXT_VF(bp))
4473                 return 0;
4474
4475         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4476         req.port_id = bp->pf->port_id;
4477         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4478
4479         HWRM_CHECK_RESULT_SILENT();
4480
4481         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4482                 unsigned int i;
4483
4484                 bp->leds->num_leds = resp->num_leds;
4485                 memcpy(bp->leds, &resp->led0_id,
4486                         sizeof(bp->leds[0]) * bp->leds->num_leds);
4487                 for (i = 0; i < bp->leds->num_leds; i++) {
4488                         struct bnxt_led_info *led = &bp->leds[i];
4489
4490                         uint16_t caps = led->led_state_caps;
4491
4492                         if (!led->led_group_id ||
4493                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4494                                 bp->leds->num_leds = 0;
4495                                 break;
4496                         }
4497                 }
4498         }
4499
4500         HWRM_UNLOCK();
4501
4502         return rc;
4503 }
4504
4505 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4506 {
4507         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4508         struct hwrm_port_led_cfg_input req = {0};
4509         struct bnxt_led_cfg *led_cfg;
4510         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4511         uint16_t duration = 0;
4512         int rc, i;
4513
4514         if (!bp->leds->num_leds || BNXT_VF(bp))
4515                 return -EOPNOTSUPP;
4516
4517         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4518
4519         if (led_on) {
4520                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4521                 duration = rte_cpu_to_le_16(500);
4522         }
4523         req.port_id = bp->pf->port_id;
4524         req.num_leds = bp->leds->num_leds;
4525         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4526         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4527                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4528                 led_cfg->led_id = bp->leds[i].led_id;
4529                 led_cfg->led_state = led_state;
4530                 led_cfg->led_blink_on = duration;
4531                 led_cfg->led_blink_off = duration;
4532                 led_cfg->led_group_id = bp->leds[i].led_group_id;
4533         }
4534
4535         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4536
4537         HWRM_CHECK_RESULT();
4538         HWRM_UNLOCK();
4539
4540         return rc;
4541 }
4542
4543 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4544                                uint32_t *length)
4545 {
4546         int rc;
4547         struct hwrm_nvm_get_dir_info_input req = {0};
4548         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4549
4550         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4551
4552         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4553
4554         HWRM_CHECK_RESULT();
4555
4556         *entries = rte_le_to_cpu_32(resp->entries);
4557         *length = rte_le_to_cpu_32(resp->entry_length);
4558
4559         HWRM_UNLOCK();
4560         return rc;
4561 }
4562
4563 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4564 {
4565         int rc;
4566         uint32_t dir_entries;
4567         uint32_t entry_length;
4568         uint8_t *buf;
4569         size_t buflen;
4570         rte_iova_t dma_handle;
4571         struct hwrm_nvm_get_dir_entries_input req = {0};
4572         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4573
4574         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4575         if (rc != 0)
4576                 return rc;
4577
4578         *data++ = dir_entries;
4579         *data++ = entry_length;
4580         len -= 2;
4581         memset(data, 0xff, len);
4582
4583         buflen = dir_entries * entry_length;
4584         buf = rte_malloc("nvm_dir", buflen, 0);
4585         if (buf == NULL)
4586                 return -ENOMEM;
4587         dma_handle = rte_malloc_virt2iova(buf);
4588         if (dma_handle == RTE_BAD_IOVA) {
4589                 rte_free(buf);
4590                 PMD_DRV_LOG(ERR,
4591                         "unable to map response address to physical memory\n");
4592                 return -ENOMEM;
4593         }
4594         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4595         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4596         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4597
4598         if (rc == 0)
4599                 memcpy(data, buf, len > buflen ? buflen : len);
4600
4601         rte_free(buf);
4602         HWRM_CHECK_RESULT();
4603         HWRM_UNLOCK();
4604
4605         return rc;
4606 }
4607
4608 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4609                              uint32_t offset, uint32_t length,
4610                              uint8_t *data)
4611 {
4612         int rc;
4613         uint8_t *buf;
4614         rte_iova_t dma_handle;
4615         struct hwrm_nvm_read_input req = {0};
4616         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4617
4618         buf = rte_malloc("nvm_item", length, 0);
4619         if (!buf)
4620                 return -ENOMEM;
4621
4622         dma_handle = rte_malloc_virt2iova(buf);
4623         if (dma_handle == RTE_BAD_IOVA) {
4624                 rte_free(buf);
4625                 PMD_DRV_LOG(ERR,
4626                         "unable to map response address to physical memory\n");
4627                 return -ENOMEM;
4628         }
4629         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4630         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4631         req.dir_idx = rte_cpu_to_le_16(index);
4632         req.offset = rte_cpu_to_le_32(offset);
4633         req.len = rte_cpu_to_le_32(length);
4634         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4635         if (rc == 0)
4636                 memcpy(data, buf, length);
4637
4638         rte_free(buf);
4639         HWRM_CHECK_RESULT();
4640         HWRM_UNLOCK();
4641
4642         return rc;
4643 }
4644
4645 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4646 {
4647         int rc;
4648         struct hwrm_nvm_erase_dir_entry_input req = {0};
4649         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4650
4651         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4652         req.dir_idx = rte_cpu_to_le_16(index);
4653         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4654         HWRM_CHECK_RESULT();
4655         HWRM_UNLOCK();
4656
4657         return rc;
4658 }
4659
4660 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4661                           uint16_t dir_ordinal, uint16_t dir_ext,
4662                           uint16_t dir_attr, const uint8_t *data,
4663                           size_t data_len)
4664 {
4665         int rc;
4666         struct hwrm_nvm_write_input req = {0};
4667         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4668         rte_iova_t dma_handle;
4669         uint8_t *buf;
4670
4671         buf = rte_malloc("nvm_write", data_len, 0);
4672         if (!buf)
4673                 return -ENOMEM;
4674
4675         dma_handle = rte_malloc_virt2iova(buf);
4676         if (dma_handle == RTE_BAD_IOVA) {
4677                 rte_free(buf);
4678                 PMD_DRV_LOG(ERR,
4679                         "unable to map response address to physical memory\n");
4680                 return -ENOMEM;
4681         }
4682         memcpy(buf, data, data_len);
4683
4684         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4685
4686         req.dir_type = rte_cpu_to_le_16(dir_type);
4687         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4688         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4689         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4690         req.dir_data_length = rte_cpu_to_le_32(data_len);
4691         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4692
4693         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4694
4695         rte_free(buf);
4696         HWRM_CHECK_RESULT();
4697         HWRM_UNLOCK();
4698
4699         return rc;
4700 }
4701
4702 static void
4703 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4704 {
4705         uint32_t *count = cbdata;
4706
4707         *count = *count + 1;
4708 }
4709
4710 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4711                                      struct bnxt_vnic_info *vnic __rte_unused)
4712 {
4713         return 0;
4714 }
4715
4716 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4717 {
4718         uint32_t count = 0;
4719
4720         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4721             &count, bnxt_vnic_count_hwrm_stub);
4722
4723         return count;
4724 }
4725
4726 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4727                                         uint16_t *vnic_ids)
4728 {
4729         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4730         struct hwrm_func_vf_vnic_ids_query_output *resp =
4731                                                 bp->hwrm_cmd_resp_addr;
4732         int rc;
4733
4734         /* First query all VNIC ids */
4735         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4736
4737         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4738         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4739         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4740
4741         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4742                 HWRM_UNLOCK();
4743                 PMD_DRV_LOG(ERR,
4744                 "unable to map VNIC ID table address to physical memory\n");
4745                 return -ENOMEM;
4746         }
4747         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4748         HWRM_CHECK_RESULT();
4749         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4750
4751         HWRM_UNLOCK();
4752
4753         return rc;
4754 }
4755
4756 /*
4757  * This function queries the VNIC IDs  for a specified VF. It then calls
4758  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4759  * Then it calls the hwrm_cb function to program this new vnic configuration.
4760  */
4761 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4762         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4763         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4764 {
4765         struct bnxt_vnic_info vnic;
4766         int rc = 0;
4767         int i, num_vnic_ids;
4768         uint16_t *vnic_ids;
4769         size_t vnic_id_sz;
4770         size_t sz;
4771
4772         /* First query all VNIC ids */
4773         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4774         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4775                         RTE_CACHE_LINE_SIZE);
4776         if (vnic_ids == NULL)
4777                 return -ENOMEM;
4778
4779         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4780                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4781
4782         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4783
4784         if (num_vnic_ids < 0)
4785                 return num_vnic_ids;
4786
4787         /* Retrieve VNIC, update bd_stall then update */
4788
4789         for (i = 0; i < num_vnic_ids; i++) {
4790                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4791                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4792                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4793                 if (rc)
4794                         break;
4795                 if (vnic.mru <= 4)      /* Indicates unallocated */
4796                         continue;
4797
4798                 vnic_cb(&vnic, cbdata);
4799
4800                 rc = hwrm_cb(bp, &vnic);
4801                 if (rc)
4802                         break;
4803         }
4804
4805         rte_free(vnic_ids);
4806
4807         return rc;
4808 }
4809
4810 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4811                                               bool on)
4812 {
4813         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4814         struct hwrm_func_cfg_input req = {0};
4815         int rc;
4816
4817         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4818
4819         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4820         req.enables |= rte_cpu_to_le_32(
4821                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4822         req.vlan_antispoof_mode = on ?
4823                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4824                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4825         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4826
4827         HWRM_CHECK_RESULT();
4828         HWRM_UNLOCK();
4829
4830         return rc;
4831 }
4832
4833 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4834 {
4835         struct bnxt_vnic_info vnic;
4836         uint16_t *vnic_ids;
4837         size_t vnic_id_sz;
4838         int num_vnic_ids, i;
4839         size_t sz;
4840         int rc;
4841
4842         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4843         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4844                         RTE_CACHE_LINE_SIZE);
4845         if (vnic_ids == NULL)
4846                 return -ENOMEM;
4847
4848         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4849                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4850
4851         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4852         if (rc <= 0)
4853                 goto exit;
4854         num_vnic_ids = rc;
4855
4856         /*
4857          * Loop through to find the default VNIC ID.
4858          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4859          * by sending the hwrm_func_qcfg command to the firmware.
4860          */
4861         for (i = 0; i < num_vnic_ids; i++) {
4862                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4863                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4864                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4865                                         bp->pf->first_vf_id + vf);
4866                 if (rc)
4867                         goto exit;
4868                 if (vnic.func_default) {
4869                         rte_free(vnic_ids);
4870                         return vnic.fw_vnic_id;
4871                 }
4872         }
4873         /* Could not find a default VNIC. */
4874         PMD_DRV_LOG(ERR, "No default VNIC\n");
4875 exit:
4876         rte_free(vnic_ids);
4877         return rc;
4878 }
4879
4880 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4881                          uint16_t dst_id,
4882                          struct bnxt_filter_info *filter)
4883 {
4884         int rc = 0;
4885         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4886         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4887         uint32_t enables = 0;
4888
4889         if (filter->fw_em_filter_id != UINT64_MAX)
4890                 bnxt_hwrm_clear_em_filter(bp, filter);
4891
4892         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4893
4894         req.flags = rte_cpu_to_le_32(filter->flags);
4895
4896         enables = filter->enables |
4897               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4898         req.dst_id = rte_cpu_to_le_16(dst_id);
4899
4900         if (filter->ip_addr_type) {
4901                 req.ip_addr_type = filter->ip_addr_type;
4902                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4903         }
4904         if (enables &
4905             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4906                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4907         if (enables &
4908             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4909                 memcpy(req.src_macaddr, filter->src_macaddr,
4910                        RTE_ETHER_ADDR_LEN);
4911         if (enables &
4912             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4913                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4914                        RTE_ETHER_ADDR_LEN);
4915         if (enables &
4916             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4917                 req.ovlan_vid = filter->l2_ovlan;
4918         if (enables &
4919             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4920                 req.ivlan_vid = filter->l2_ivlan;
4921         if (enables &
4922             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4923                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4924         if (enables &
4925             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4926                 req.ip_protocol = filter->ip_protocol;
4927         if (enables &
4928             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4929                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4930         if (enables &
4931             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4932                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4933         if (enables &
4934             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4935                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4936         if (enables &
4937             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4938                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4939         if (enables &
4940             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4941                 req.mirror_vnic_id = filter->mirror_vnic_id;
4942
4943         req.enables = rte_cpu_to_le_32(enables);
4944
4945         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4946
4947         HWRM_CHECK_RESULT();
4948
4949         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4950         HWRM_UNLOCK();
4951
4952         return rc;
4953 }
4954
4955 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4956 {
4957         int rc = 0;
4958         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4959         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4960
4961         if (filter->fw_em_filter_id == UINT64_MAX)
4962                 return 0;
4963
4964         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4965
4966         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4967
4968         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4969
4970         HWRM_CHECK_RESULT();
4971         HWRM_UNLOCK();
4972
4973         filter->fw_em_filter_id = UINT64_MAX;
4974         filter->fw_l2_filter_id = UINT64_MAX;
4975
4976         return 0;
4977 }
4978
4979 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4980                          uint16_t dst_id,
4981                          struct bnxt_filter_info *filter)
4982 {
4983         int rc = 0;
4984         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4985         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4986                                                 bp->hwrm_cmd_resp_addr;
4987         uint32_t enables = 0;
4988
4989         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4990                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4991
4992         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4993
4994         req.flags = rte_cpu_to_le_32(filter->flags);
4995
4996         enables = filter->enables |
4997               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4998         req.dst_id = rte_cpu_to_le_16(dst_id);
4999
5000         if (filter->ip_addr_type) {
5001                 req.ip_addr_type = filter->ip_addr_type;
5002                 enables |=
5003                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
5004         }
5005         if (enables &
5006             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
5007                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
5008         if (enables &
5009             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
5010                 memcpy(req.src_macaddr, filter->src_macaddr,
5011                        RTE_ETHER_ADDR_LEN);
5012         if (enables &
5013             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
5014                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
5015         if (enables &
5016             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
5017                 req.ip_protocol = filter->ip_protocol;
5018         if (enables &
5019             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
5020                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
5021         if (enables &
5022             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
5023                 req.src_ipaddr_mask[0] =
5024                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
5025         if (enables &
5026             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
5027                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
5028         if (enables &
5029             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
5030                 req.dst_ipaddr_mask[0] =
5031                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
5032         if (enables &
5033             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
5034                 req.src_port = rte_cpu_to_le_16(filter->src_port);
5035         if (enables &
5036             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
5037                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
5038         if (enables &
5039             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
5040                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
5041         if (enables &
5042             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
5043                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
5044         if (enables &
5045             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
5046                 req.mirror_vnic_id = filter->mirror_vnic_id;
5047
5048         req.enables = rte_cpu_to_le_32(enables);
5049
5050         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5051
5052         HWRM_CHECK_RESULT();
5053
5054         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
5055         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
5056         HWRM_UNLOCK();
5057
5058         return rc;
5059 }
5060
5061 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
5062                                 struct bnxt_filter_info *filter)
5063 {
5064         int rc = 0;
5065         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
5066         struct hwrm_cfa_ntuple_filter_free_output *resp =
5067                                                 bp->hwrm_cmd_resp_addr;
5068
5069         if (filter->fw_ntuple_filter_id == UINT64_MAX)
5070                 return 0;
5071
5072         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
5073
5074         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
5075
5076         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5077
5078         HWRM_CHECK_RESULT();
5079         HWRM_UNLOCK();
5080
5081         filter->fw_ntuple_filter_id = UINT64_MAX;
5082
5083         return 0;
5084 }
5085
5086 static int
5087 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5088 {
5089         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5090         uint8_t *rxq_state = bp->eth_dev->data->rx_queue_state;
5091         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
5092         struct bnxt_rx_queue **rxqs = bp->rx_queues;
5093         uint16_t *ring_tbl = vnic->rss_table;
5094         int nr_ctxs = vnic->num_lb_ctxts;
5095         int max_rings = bp->rx_nr_rings;
5096         int i, j, k, cnt;
5097         int rc = 0;
5098
5099         for (i = 0, k = 0; i < nr_ctxs; i++) {
5100                 struct bnxt_rx_ring_info *rxr;
5101                 struct bnxt_cp_ring_info *cpr;
5102
5103                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
5104
5105                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
5106                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
5107                 req.hash_mode_flags = vnic->hash_mode;
5108
5109                 req.ring_grp_tbl_addr =
5110                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
5111                                      i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
5112                                      2 * sizeof(*ring_tbl));
5113                 req.hash_key_tbl_addr =
5114                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
5115
5116                 req.ring_table_pair_index = i;
5117                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
5118
5119                 for (j = 0; j < 64; j++) {
5120                         uint16_t ring_id;
5121
5122                         /* Find next active ring. */
5123                         for (cnt = 0; cnt < max_rings; cnt++) {
5124                                 if (rxq_state[k] != RTE_ETH_QUEUE_STATE_STOPPED)
5125                                         break;
5126                                 if (++k == max_rings)
5127                                         k = 0;
5128                         }
5129
5130                         /* Return if no rings are active. */
5131                         if (cnt == max_rings) {
5132                                 HWRM_UNLOCK();
5133                                 return 0;
5134                         }
5135
5136                         /* Add rx/cp ring pair to RSS table. */
5137                         rxr = rxqs[k]->rx_ring;
5138                         cpr = rxqs[k]->cp_ring;
5139
5140                         ring_id = rxr->rx_ring_struct->fw_ring_id;
5141                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5142                         ring_id = cpr->cp_ring_struct->fw_ring_id;
5143                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5144
5145                         if (++k == max_rings)
5146                                 k = 0;
5147                 }
5148                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5149                                             BNXT_USE_CHIMP_MB);
5150
5151                 HWRM_CHECK_RESULT();
5152                 HWRM_UNLOCK();
5153         }
5154
5155         return rc;
5156 }
5157
5158 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5159 {
5160         unsigned int rss_idx, fw_idx, i;
5161
5162         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5163                 return 0;
5164
5165         if (!(vnic->rss_table && vnic->hash_type))
5166                 return 0;
5167
5168         if (BNXT_CHIP_P5(bp))
5169                 return bnxt_vnic_rss_configure_p5(bp, vnic);
5170
5171         /*
5172          * Fill the RSS hash & redirection table with
5173          * ring group ids for all VNICs
5174          */
5175         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
5176              rss_idx++, fw_idx++) {
5177                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
5178                         fw_idx %= bp->rx_cp_nr_rings;
5179                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
5180                                 break;
5181                         fw_idx++;
5182                 }
5183
5184                 if (i == bp->rx_cp_nr_rings)
5185                         return 0;
5186
5187                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
5188         }
5189
5190         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
5191 }
5192
5193 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
5194         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5195 {
5196         uint16_t flags;
5197
5198         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
5199
5200         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5201         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
5202
5203         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5204         req->num_cmpl_dma_aggr_during_int =
5205                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
5206
5207         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
5208
5209         /* min timer set to 1/2 of interrupt timer */
5210         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
5211
5212         /* buf timer set to 1/4 of interrupt timer */
5213         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
5214
5215         req->cmpl_aggr_dma_tmr_during_int =
5216                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5217
5218         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5219                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5220         req->flags = rte_cpu_to_le_16(flags);
5221 }
5222
5223 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5224                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5225 {
5226         struct hwrm_ring_aggint_qcaps_input req = {0};
5227         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5228         uint32_t enables;
5229         uint16_t flags;
5230         int rc;
5231
5232         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5233         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5234         HWRM_CHECK_RESULT();
5235
5236         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5237         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5238
5239         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5240                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5241         agg_req->flags = rte_cpu_to_le_16(flags);
5242         enables =
5243          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5244          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5245         agg_req->enables = rte_cpu_to_le_32(enables);
5246
5247         HWRM_UNLOCK();
5248         return rc;
5249 }
5250
5251 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5252                         struct bnxt_coal *coal, uint16_t ring_id)
5253 {
5254         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5255         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5256                                                 bp->hwrm_cmd_resp_addr;
5257         int rc;
5258
5259         /* Set ring coalesce parameters only for 100G NICs */
5260         if (BNXT_CHIP_P5(bp)) {
5261                 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5262                         return -1;
5263         } else if (bnxt_stratus_device(bp)) {
5264                 bnxt_hwrm_set_coal_params(coal, &req);
5265         } else {
5266                 return 0;
5267         }
5268
5269         HWRM_PREP(&req,
5270                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5271                   BNXT_USE_CHIMP_MB);
5272         req.ring_id = rte_cpu_to_le_16(ring_id);
5273         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5274         HWRM_CHECK_RESULT();
5275         HWRM_UNLOCK();
5276         return 0;
5277 }
5278
5279 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5280 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5281 {
5282         struct hwrm_func_backing_store_qcaps_input req = {0};
5283         struct hwrm_func_backing_store_qcaps_output *resp =
5284                 bp->hwrm_cmd_resp_addr;
5285         struct bnxt_ctx_pg_info *ctx_pg;
5286         struct bnxt_ctx_mem_info *ctx;
5287         int total_alloc_len;
5288         int rc, i, tqm_rings;
5289
5290         if (!BNXT_CHIP_P5(bp) ||
5291             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5292             BNXT_VF(bp) ||
5293             bp->ctx)
5294                 return 0;
5295
5296         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5297         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5298         HWRM_CHECK_RESULT_SILENT();
5299
5300         total_alloc_len = sizeof(*ctx);
5301         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5302                           RTE_CACHE_LINE_SIZE);
5303         if (!ctx) {
5304                 rc = -ENOMEM;
5305                 goto ctx_err;
5306         }
5307
5308         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5309         ctx->qp_min_qp1_entries =
5310                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5311         ctx->qp_max_l2_entries =
5312                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5313         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5314         ctx->srq_max_l2_entries =
5315                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5316         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5317         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5318         ctx->cq_max_l2_entries =
5319                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5320         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5321         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5322         ctx->vnic_max_vnic_entries =
5323                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5324         ctx->vnic_max_ring_table_entries =
5325                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5326         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5327         ctx->stat_max_entries =
5328                 rte_le_to_cpu_32(resp->stat_max_entries);
5329         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5330         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5331         ctx->tqm_min_entries_per_ring =
5332                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5333         ctx->tqm_max_entries_per_ring =
5334                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5335         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5336         if (!ctx->tqm_entries_multiple)
5337                 ctx->tqm_entries_multiple = 1;
5338         ctx->mrav_max_entries =
5339                 rte_le_to_cpu_32(resp->mrav_max_entries);
5340         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5341         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5342         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5343         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5344
5345         ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
5346                                   RTE_MIN(ctx->tqm_fp_rings_count,
5347                                           BNXT_MAX_TQM_FP_LEGACY_RINGS) :
5348                                   bp->max_q;
5349
5350         /* Check if the ext ring count needs to be counted.
5351          * Ext ring count is available only with new FW so we should not
5352          * look at the field on older FW.
5353          */
5354         if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
5355             bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
5356                 ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
5357                 ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
5358                                                   ctx->tqm_fp_rings_count);
5359         }
5360
5361         tqm_rings = ctx->tqm_fp_rings_count + 1;
5362
5363         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5364                             sizeof(*ctx_pg) * tqm_rings,
5365                             RTE_CACHE_LINE_SIZE);
5366         if (!ctx_pg) {
5367                 rc = -ENOMEM;
5368                 goto ctx_err;
5369         }
5370         for (i = 0; i < tqm_rings; i++, ctx_pg++)
5371                 ctx->tqm_mem[i] = ctx_pg;
5372
5373         bp->ctx = ctx;
5374 ctx_err:
5375         HWRM_UNLOCK();
5376         return rc;
5377 }
5378
5379 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5380 {
5381         struct hwrm_func_backing_store_cfg_input req = {0};
5382         struct hwrm_func_backing_store_cfg_output *resp =
5383                 bp->hwrm_cmd_resp_addr;
5384         struct bnxt_ctx_mem_info *ctx = bp->ctx;
5385         struct bnxt_ctx_pg_info *ctx_pg;
5386         uint32_t *num_entries;
5387         uint64_t *pg_dir;
5388         uint8_t *pg_attr;
5389         uint32_t ena;
5390         int i, rc;
5391
5392         if (!ctx)
5393                 return 0;
5394
5395         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5396         req.enables = rte_cpu_to_le_32(enables);
5397
5398         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5399                 ctx_pg = &ctx->qp_mem;
5400                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5401                 req.qp_num_qp1_entries =
5402                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5403                 req.qp_num_l2_entries =
5404                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5405                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5406                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5407                                       &req.qpc_pg_size_qpc_lvl,
5408                                       &req.qpc_page_dir);
5409         }
5410
5411         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5412                 ctx_pg = &ctx->srq_mem;
5413                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5414                 req.srq_num_l2_entries =
5415                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5416                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5417                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5418                                       &req.srq_pg_size_srq_lvl,
5419                                       &req.srq_page_dir);
5420         }
5421
5422         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5423                 ctx_pg = &ctx->cq_mem;
5424                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5425                 req.cq_num_l2_entries =
5426                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5427                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5428                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5429                                       &req.cq_pg_size_cq_lvl,
5430                                       &req.cq_page_dir);
5431         }
5432
5433         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5434                 ctx_pg = &ctx->vnic_mem;
5435                 req.vnic_num_vnic_entries =
5436                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5437                 req.vnic_num_ring_table_entries =
5438                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5439                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5440                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5441                                       &req.vnic_pg_size_vnic_lvl,
5442                                       &req.vnic_page_dir);
5443         }
5444
5445         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5446                 ctx_pg = &ctx->stat_mem;
5447                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5448                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5449                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5450                                       &req.stat_pg_size_stat_lvl,
5451                                       &req.stat_page_dir);
5452         }
5453
5454         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5455         num_entries = &req.tqm_sp_num_entries;
5456         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5457         pg_dir = &req.tqm_sp_page_dir;
5458         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5459         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5460                 if (!(enables & ena))
5461                         continue;
5462
5463                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5464
5465                 ctx_pg = ctx->tqm_mem[i];
5466                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5467                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5468         }
5469
5470         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
5471                 /* DPDK does not need to configure MRAV and TIM type.
5472                  * So we are skipping over MRAV and TIM. Skip to configure
5473                  * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
5474                  */
5475                 ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
5476                 req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5477                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5478                                       &req.tqm_ring8_pg_size_tqm_ring_lvl,
5479                                       &req.tqm_ring8_page_dir);
5480         }
5481
5482         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5483         HWRM_CHECK_RESULT();
5484         HWRM_UNLOCK();
5485
5486         return rc;
5487 }
5488
5489 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5490 {
5491         struct hwrm_port_qstats_ext_input req = {0};
5492         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5493         struct bnxt_pf_info *pf = bp->pf;
5494         int rc;
5495
5496         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5497               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5498                 return 0;
5499
5500         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5501
5502         req.port_id = rte_cpu_to_le_16(pf->port_id);
5503         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5504                 req.tx_stat_host_addr =
5505                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5506                 req.tx_stat_size =
5507                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5508         }
5509         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5510                 req.rx_stat_host_addr =
5511                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5512                 req.rx_stat_size =
5513                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5514         }
5515         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5516
5517         if (rc) {
5518                 bp->fw_rx_port_stats_ext_size = 0;
5519                 bp->fw_tx_port_stats_ext_size = 0;
5520         } else {
5521                 bp->fw_rx_port_stats_ext_size =
5522                         rte_le_to_cpu_16(resp->rx_stat_size);
5523                 bp->fw_tx_port_stats_ext_size =
5524                         rte_le_to_cpu_16(resp->tx_stat_size);
5525         }
5526
5527         HWRM_CHECK_RESULT();
5528         HWRM_UNLOCK();
5529
5530         return rc;
5531 }
5532
5533 int
5534 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5535 {
5536         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5537         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5538                 bp->hwrm_cmd_resp_addr;
5539         int rc = 0;
5540
5541         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5542         req.tunnel_type = type;
5543         req.dest_fid = bp->fw_fid;
5544         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5545         HWRM_CHECK_RESULT();
5546
5547         HWRM_UNLOCK();
5548
5549         return rc;
5550 }
5551
5552 int
5553 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5554 {
5555         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5556         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5557                 bp->hwrm_cmd_resp_addr;
5558         int rc = 0;
5559
5560         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5561         req.tunnel_type = type;
5562         req.dest_fid = bp->fw_fid;
5563         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5564         HWRM_CHECK_RESULT();
5565
5566         HWRM_UNLOCK();
5567
5568         return rc;
5569 }
5570
5571 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5572 {
5573         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5574         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5575                 bp->hwrm_cmd_resp_addr;
5576         int rc = 0;
5577
5578         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5579         req.src_fid = bp->fw_fid;
5580         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5581         HWRM_CHECK_RESULT();
5582
5583         if (type)
5584                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5585
5586         HWRM_UNLOCK();
5587
5588         return rc;
5589 }
5590
5591 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5592                                    uint16_t *dst_fid)
5593 {
5594         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5595         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5596                 bp->hwrm_cmd_resp_addr;
5597         int rc = 0;
5598
5599         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5600         req.src_fid = bp->fw_fid;
5601         req.tunnel_type = tun_type;
5602         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5603         HWRM_CHECK_RESULT();
5604
5605         if (dst_fid)
5606                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5607
5608         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5609
5610         HWRM_UNLOCK();
5611
5612         return rc;
5613 }
5614
5615 int bnxt_hwrm_set_mac(struct bnxt *bp)
5616 {
5617         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5618         struct hwrm_func_vf_cfg_input req = {0};
5619         int rc = 0;
5620
5621         if (!BNXT_VF(bp))
5622                 return 0;
5623
5624         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5625
5626         req.enables =
5627                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5628         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5629
5630         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5631
5632         HWRM_CHECK_RESULT();
5633
5634         HWRM_UNLOCK();
5635
5636         return rc;
5637 }
5638
5639 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5640 {
5641         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5642         struct hwrm_func_drv_if_change_input req = {0};
5643         uint32_t flags;
5644         int rc;
5645
5646         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5647                 return 0;
5648
5649         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5650          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5651          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5652          */
5653         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5654                 return 0;
5655
5656         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5657
5658         if (up)
5659                 req.flags =
5660                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5661
5662         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5663
5664         HWRM_CHECK_RESULT();
5665         flags = rte_le_to_cpu_32(resp->flags);
5666         HWRM_UNLOCK();
5667
5668         if (!up)
5669                 return 0;
5670
5671         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5672                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5673                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5674         }
5675
5676         return 0;
5677 }
5678
5679 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5680 {
5681         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5682         struct bnxt_error_recovery_info *info = bp->recovery_info;
5683         struct hwrm_error_recovery_qcfg_input req = {0};
5684         uint32_t flags = 0;
5685         unsigned int i;
5686         int rc;
5687
5688         /* Older FW does not have error recovery support */
5689         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5690                 return 0;
5691
5692         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5693
5694         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5695
5696         HWRM_CHECK_RESULT();
5697
5698         flags = rte_le_to_cpu_32(resp->flags);
5699         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5700                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5701         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5702                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5703
5704         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5705             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5706                 rc = -EINVAL;
5707                 goto err;
5708         }
5709
5710         /* FW returned values are in units of 100msec */
5711         info->driver_polling_freq =
5712                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5713         info->master_func_wait_period =
5714                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5715         info->normal_func_wait_period =
5716                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5717         info->master_func_wait_period_after_reset =
5718                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5719         info->max_bailout_time_after_reset =
5720                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5721         info->status_regs[BNXT_FW_STATUS_REG] =
5722                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5723         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5724                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5725         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5726                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5727         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5728                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5729         info->reg_array_cnt =
5730                 rte_le_to_cpu_32(resp->reg_array_cnt);
5731
5732         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5733                 rc = -EINVAL;
5734                 goto err;
5735         }
5736
5737         for (i = 0; i < info->reg_array_cnt; i++) {
5738                 info->reset_reg[i] =
5739                         rte_le_to_cpu_32(resp->reset_reg[i]);
5740                 info->reset_reg_val[i] =
5741                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5742                 info->delay_after_reset[i] =
5743                         resp->delay_after_reset[i];
5744         }
5745 err:
5746         HWRM_UNLOCK();
5747
5748         /* Map the FW status registers */
5749         if (!rc)
5750                 rc = bnxt_map_fw_health_status_regs(bp);
5751
5752         if (rc) {
5753                 rte_free(bp->recovery_info);
5754                 bp->recovery_info = NULL;
5755         }
5756         return rc;
5757 }
5758
5759 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5760 {
5761         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5762         struct hwrm_fw_reset_input req = {0};
5763         int rc;
5764
5765         if (!BNXT_PF(bp))
5766                 return -EOPNOTSUPP;
5767
5768         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5769
5770         req.embedded_proc_type =
5771                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5772         req.selfrst_status =
5773                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5774         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5775
5776         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5777                                     BNXT_USE_KONG(bp));
5778
5779         HWRM_CHECK_RESULT();
5780         HWRM_UNLOCK();
5781
5782         return rc;
5783 }
5784
5785 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5786 {
5787         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5788         struct hwrm_port_ts_query_input req = {0};
5789         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5790         uint32_t flags = 0;
5791         int rc;
5792
5793         if (!ptp)
5794                 return 0;
5795
5796         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5797
5798         switch (path) {
5799         case BNXT_PTP_FLAGS_PATH_TX:
5800                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5801                 break;
5802         case BNXT_PTP_FLAGS_PATH_RX:
5803                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5804                 break;
5805         case BNXT_PTP_FLAGS_CURRENT_TIME:
5806                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5807                 break;
5808         }
5809
5810         req.flags = rte_cpu_to_le_32(flags);
5811         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5812
5813         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5814
5815         HWRM_CHECK_RESULT();
5816
5817         if (timestamp) {
5818                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5819                 *timestamp |=
5820                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5821         }
5822         HWRM_UNLOCK();
5823
5824         return rc;
5825 }
5826
5827 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5828 {
5829         int rc = 0;
5830
5831         struct hwrm_cfa_counter_qcaps_input req = {0};
5832         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5833
5834         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5835                 PMD_DRV_LOG(DEBUG,
5836                             "Not a PF or trusted VF. Command not supported\n");
5837                 return 0;
5838         }
5839
5840         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5841         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5842         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5843
5844         HWRM_CHECK_RESULT();
5845         if (max_fc)
5846                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5847         HWRM_UNLOCK();
5848
5849         return 0;
5850 }
5851
5852 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5853 {
5854         int rc = 0;
5855         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5856         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5857
5858         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5859                 PMD_DRV_LOG(DEBUG,
5860                             "Not a PF or trusted VF. Command not supported\n");
5861                 return 0;
5862         }
5863
5864         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5865
5866         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5867         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5868         req.page_dir = rte_cpu_to_le_64(dma_addr);
5869
5870         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5871
5872         HWRM_CHECK_RESULT();
5873         if (ctx_id) {
5874                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5875                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5876         }
5877         HWRM_UNLOCK();
5878
5879         return 0;
5880 }
5881
5882 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5883 {
5884         int rc = 0;
5885         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5886         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5887
5888         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5889                 PMD_DRV_LOG(DEBUG,
5890                             "Not a PF or trusted VF. Command not supported\n");
5891                 return 0;
5892         }
5893
5894         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5895
5896         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5897
5898         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5899
5900         HWRM_CHECK_RESULT();
5901         HWRM_UNLOCK();
5902
5903         return rc;
5904 }
5905
5906 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5907                               uint16_t cntr, uint16_t ctx_id,
5908                               uint32_t num_entries, bool enable)
5909 {
5910         struct hwrm_cfa_counter_cfg_input req = {0};
5911         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5912         uint16_t flags = 0;
5913         int rc;
5914
5915         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5916                 PMD_DRV_LOG(DEBUG,
5917                             "Not a PF or trusted VF. Command not supported\n");
5918                 return 0;
5919         }
5920
5921         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5922
5923         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5924         req.counter_type = rte_cpu_to_le_16(cntr);
5925         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5926                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5927         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5928         if (dir == BNXT_DIR_RX)
5929                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5930         else if (dir == BNXT_DIR_TX)
5931                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5932         req.flags = rte_cpu_to_le_16(flags);
5933         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5934         req.num_entries = rte_cpu_to_le_32(num_entries);
5935
5936         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5937         HWRM_CHECK_RESULT();
5938         HWRM_UNLOCK();
5939
5940         return 0;
5941 }
5942
5943 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5944                                  enum bnxt_flow_dir dir,
5945                                  uint16_t cntr,
5946                                  uint16_t num_entries)
5947 {
5948         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5949         struct hwrm_cfa_counter_qstats_input req = {0};
5950         uint16_t flow_ctx_id = 0;
5951         uint16_t flags = 0;
5952         int rc = 0;
5953
5954         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5955                 PMD_DRV_LOG(DEBUG,
5956                             "Not a PF or trusted VF. Command not supported\n");
5957                 return 0;
5958         }
5959
5960         if (dir == BNXT_DIR_RX) {
5961                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5962                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5963         } else if (dir == BNXT_DIR_TX) {
5964                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5965                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5966         }
5967
5968         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5969         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5970         req.counter_type = rte_cpu_to_le_16(cntr);
5971         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5972         req.num_entries = rte_cpu_to_le_16(num_entries);
5973         req.flags = rte_cpu_to_le_16(flags);
5974         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5975
5976         HWRM_CHECK_RESULT();
5977         HWRM_UNLOCK();
5978
5979         return 0;
5980 }
5981
5982 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5983                                 uint16_t *first_vf_id)
5984 {
5985         int rc = 0;
5986         struct hwrm_func_qcaps_input req = {.req_type = 0 };
5987         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5988
5989         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5990
5991         req.fid = rte_cpu_to_le_16(fid);
5992
5993         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5994
5995         HWRM_CHECK_RESULT();
5996
5997         if (first_vf_id)
5998                 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
5999
6000         HWRM_UNLOCK();
6001
6002         return rc;
6003 }
6004
6005 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
6006 {
6007         struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6008         struct hwrm_cfa_pair_alloc_input req = {0};
6009         int rc;
6010
6011         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6012                 PMD_DRV_LOG(DEBUG,
6013                             "Not a PF or trusted VF. Command not supported\n");
6014                 return 0;
6015         }
6016
6017         HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
6018         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6019         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6020                  bp->eth_dev->data->name, rep_bp->vf_id);
6021
6022         req.pf_b_id = rep_bp->parent_pf_idx;
6023         req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6024                                                 rte_cpu_to_le_16(rep_bp->vf_id);
6025         req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
6026         req.host_b_id = 1; /* TBD - Confirm if this is OK */
6027
6028         req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
6029                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
6030         req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
6031                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
6032         req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
6033                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
6034         req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
6035                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
6036
6037         req.q_ab = rep_bp->rep_q_r2f;
6038         req.q_ba = rep_bp->rep_q_f2r;
6039         req.fc_ab = rep_bp->rep_fc_r2f;
6040         req.fc_ba = rep_bp->rep_fc_f2r;
6041
6042         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6043         HWRM_CHECK_RESULT();
6044
6045         HWRM_UNLOCK();
6046         PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
6047                     BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
6048         return rc;
6049 }
6050
6051 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
6052 {
6053         struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
6054         struct hwrm_cfa_pair_free_input req = {0};
6055         int rc;
6056
6057         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6058                 PMD_DRV_LOG(DEBUG,
6059                             "Not a PF or trusted VF. Command not supported\n");
6060                 return 0;
6061         }
6062
6063         HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
6064         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6065                  bp->eth_dev->data->name, rep_bp->vf_id);
6066         req.pf_b_id = rep_bp->parent_pf_idx;
6067         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6068         req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6069                                                 rte_cpu_to_le_16(rep_bp->vf_id);
6070         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6071         HWRM_CHECK_RESULT();
6072         HWRM_UNLOCK();
6073         PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
6074                     rep_bp->vf_id);
6075         return rc;
6076 }
6077
6078 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
6079 {
6080         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
6081                                         bp->hwrm_cmd_resp_addr;
6082         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
6083         uint32_t flags = 0;
6084         int rc = 0;
6085
6086         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
6087                 return 0;
6088
6089         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6090                 PMD_DRV_LOG(DEBUG,
6091                             "Not a PF or trusted VF. Command not supported\n");
6092                 return 0;
6093         }
6094
6095         HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
6096         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6097
6098         HWRM_CHECK_RESULT();
6099         flags = rte_le_to_cpu_32(resp->flags);
6100         HWRM_UNLOCK();
6101
6102         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
6103                 bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
6104         else
6105                 bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
6106
6107         return rc;
6108 }
6109
6110 int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
6111                             uint32_t echo_req_data2)
6112 {
6113         struct hwrm_func_echo_response_input req = {0};
6114         struct hwrm_func_echo_response_output *resp = bp->hwrm_cmd_resp_addr;
6115         int rc;
6116
6117         HWRM_PREP(&req, HWRM_FUNC_ECHO_RESPONSE, BNXT_USE_CHIMP_MB);
6118         req.event_data1 = rte_cpu_to_le_32(echo_req_data1);
6119         req.event_data2 = rte_cpu_to_le_32(echo_req_data2);
6120
6121         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6122
6123         HWRM_CHECK_RESULT();
6124         HWRM_UNLOCK();
6125
6126         return rc;
6127 }
6128
6129 int bnxt_hwrm_poll_ver_get(struct bnxt *bp)
6130 {
6131         struct hwrm_ver_get_input req = {.req_type = 0 };
6132         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6133         int rc = 0;
6134
6135         bp->max_req_len = HWRM_MAX_REQ_LEN;
6136         bp->max_resp_len = BNXT_PAGE_SIZE;
6137         bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
6138
6139         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
6140         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6141         req.hwrm_intf_min = HWRM_VERSION_MINOR;
6142         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6143
6144         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6145
6146         HWRM_CHECK_RESULT_SILENT();
6147
6148         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY)
6149                 rc = -EAGAIN;
6150
6151         HWRM_UNLOCK();
6152
6153         return rc;
6154 }
6155
6156 int bnxt_hwrm_read_sfp_module_eeprom_info(struct bnxt *bp, uint16_t i2c_addr,
6157                                           uint16_t page_number, uint16_t start_addr,
6158                                           uint16_t data_length, uint8_t *buf)
6159 {
6160         struct hwrm_port_phy_i2c_read_output *resp = bp->hwrm_cmd_resp_addr;
6161         struct hwrm_port_phy_i2c_read_input req = {0};
6162         uint32_t enables = HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET;
6163         int rc, byte_offset = 0;
6164
6165         do {
6166                 uint16_t xfer_size;
6167
6168                 HWRM_PREP(&req, HWRM_PORT_PHY_I2C_READ, BNXT_USE_CHIMP_MB);
6169                 req.i2c_slave_addr = i2c_addr;
6170                 req.page_number = rte_cpu_to_le_16(page_number);
6171                 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
6172
6173                 xfer_size = RTE_MIN(data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
6174                 req.page_offset = rte_cpu_to_le_16(start_addr + byte_offset);
6175                 req.data_length = xfer_size;
6176                 req.enables = rte_cpu_to_le_32(start_addr + byte_offset ? enables : 0);
6177                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6178                 HWRM_CHECK_RESULT();
6179
6180                 memcpy(buf + byte_offset, resp->data, xfer_size);
6181
6182                 data_length -= xfer_size;
6183                 byte_offset += xfer_size;
6184
6185                 HWRM_UNLOCK();
6186         } while (data_length > 0);
6187
6188         return rc;
6189 }
6190
6191 void bnxt_free_hwrm_tx_ring(struct bnxt *bp, int queue_index)
6192 {
6193         struct bnxt_tx_queue *txq = bp->tx_queues[queue_index];
6194         struct bnxt_tx_ring_info *txr = txq->tx_ring;
6195         struct bnxt_ring *ring = txr->tx_ring_struct;
6196         struct bnxt_cp_ring_info *cpr = txq->cp_ring;
6197
6198         bnxt_hwrm_ring_free(bp, ring,
6199                             HWRM_RING_FREE_INPUT_RING_TYPE_TX,
6200                             cpr->cp_ring_struct->fw_ring_id);
6201         txr->tx_raw_prod = 0;
6202         txr->tx_raw_cons = 0;
6203         memset(txr->tx_desc_ring, 0,
6204                 txr->tx_ring_struct->ring_size * sizeof(*txr->tx_desc_ring));
6205         memset(txr->tx_buf_ring, 0,
6206                 txr->tx_ring_struct->ring_size * sizeof(*txr->tx_buf_ring));
6207
6208         bnxt_hwrm_stat_ctx_free(bp, cpr);
6209
6210         bnxt_free_cp_ring(bp, cpr);
6211 }
6212
6213 int bnxt_hwrm_config_host_mtu(struct bnxt *bp)
6214 {
6215         struct hwrm_func_cfg_input req = {0};
6216         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
6217         int rc;
6218
6219         if (!BNXT_PF(bp))
6220                 return 0;
6221
6222         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
6223
6224         req.fid = rte_cpu_to_le_16(0xffff);
6225         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU);
6226         req.host_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu);
6227
6228         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6229         HWRM_CHECK_RESULT();
6230         HWRM_UNLOCK();
6231
6232         return rc;
6233 }