ETH_RSS_NONFRAG_IPV6_UDP | \
ETH_RSS_LEVEL_MASK)
-#define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
- DEV_TX_OFFLOAD_IPV4_CKSUM | \
+#define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_IPV4_CKSUM | \
DEV_TX_OFFLOAD_TCP_CKSUM | \
DEV_TX_OFFLOAD_UDP_CKSUM | \
DEV_TX_OFFLOAD_TCP_TSO | \
DEV_TX_OFFLOAD_MULTI_SEGS)
#define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
- DEV_RX_OFFLOAD_VLAN_STRIP | \
DEV_RX_OFFLOAD_IPV4_CKSUM | \
DEV_RX_OFFLOAD_UDP_CKSUM | \
DEV_RX_OFFLOAD_TCP_CKSUM | \
#define BNXT_FW_CAP_ADV_FLOW_COUNTERS BIT(6)
#define BNXT_FW_CAP_LINK_ADMIN BIT(7)
#define BNXT_FW_CAP_TRUFLOW_EN BIT(8)
+#define BNXT_FW_CAP_VLAN_TX_INSERT BIT(9)
#define BNXT_TRUFLOW_EN(bp) ((bp)->fw_cap & BNXT_FW_CAP_TRUFLOW_EN)
pthread_mutex_t flow_lock;
#define BNXT_VNIC_CAP_COS_CLASSIFY BIT(0)
#define BNXT_VNIC_CAP_OUTER_RSS BIT(1)
#define BNXT_VNIC_CAP_RX_CMPL_V2 BIT(2)
+#define BNXT_VNIC_CAP_VLAN_RX_STRIP BIT(3)
unsigned int rx_nr_rings;
unsigned int rx_cp_nr_rings;
unsigned int rx_num_qs_per_vnic;
dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
+ if (bp->vnic_cap_flags & BNXT_VNIC_CAP_VLAN_RX_STRIP)
+ dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_VLAN_STRIP;
dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
dev_info->tx_queue_offload_capa;
+ if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT)
+ dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_VLAN_INSERT;
dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
+ if (!(flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED)) {
+ bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT;
+ PMD_DRV_LOG(DEBUG, "VLAN acceleration for TX is enabled\n");
+ }
unlock:
HWRM_UNLOCK();
if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
+ if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP) {
+ bp->vnic_cap_flags |= BNXT_VNIC_CAP_VLAN_RX_STRIP;
+ PMD_DRV_LOG(DEBUG, "Rx VLAN strip capability enabled\n");
+ }
+
bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
HWRM_UNLOCK();