1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
14 #include <netinet/in.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_atomic.h>
25 #include <rte_branch_prediction.h>
26 #include <rte_memory.h>
27 #include <rte_tailq.h>
29 #include <rte_alarm.h>
30 #include <rte_ether.h>
31 #include <rte_ethdev_driver.h>
32 #include <rte_ethdev_pci.h>
33 #include <rte_malloc.h>
34 #include <rte_random.h>
38 #include "cxgbe_pfvf.h"
41 * Macros needed to support the PCI Device ID Table ...
43 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
44 static const struct rte_pci_id cxgb4_pci_tbl[] = {
45 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
47 #define PCI_VENDOR_ID_CHELSIO 0x1425
49 #define CH_PCI_ID_TABLE_ENTRY(devid) \
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
52 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
57 *... and the PCI ID Table itself ...
59 #include "t4_pci_id_tbl.h"
61 #define CXGBE_TX_OFFLOADS (DEV_TX_OFFLOAD_VLAN_INSERT |\
62 DEV_TX_OFFLOAD_IPV4_CKSUM |\
63 DEV_TX_OFFLOAD_UDP_CKSUM |\
64 DEV_TX_OFFLOAD_TCP_CKSUM |\
65 DEV_TX_OFFLOAD_TCP_TSO)
67 #define CXGBE_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_STRIP |\
68 DEV_RX_OFFLOAD_CRC_STRIP |\
69 DEV_RX_OFFLOAD_IPV4_CKSUM |\
70 DEV_RX_OFFLOAD_JUMBO_FRAME |\
71 DEV_RX_OFFLOAD_UDP_CKSUM |\
72 DEV_RX_OFFLOAD_TCP_CKSUM)
74 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
77 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
78 uint16_t pkts_sent, pkts_remain;
79 uint16_t total_sent = 0;
82 CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n",
83 __func__, txq, tx_pkts, nb_pkts);
85 t4_os_lock(&txq->txq_lock);
86 /* free up desc from already completed tx */
87 reclaim_completed_tx(&txq->q);
88 while (total_sent < nb_pkts) {
89 pkts_remain = nb_pkts - total_sent;
91 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
92 ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent],
99 total_sent += pkts_sent;
100 /* reclaim as much as possible */
101 reclaim_completed_tx(&txq->q);
104 t4_os_unlock(&txq->txq_lock);
108 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
111 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
112 unsigned int work_done;
114 CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n",
115 __func__, rxq->rspq.cntxt_id, nb_pkts);
117 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
118 dev_err(adapter, "error in cxgbe poll\n");
120 CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done);
124 void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
125 struct rte_eth_dev_info *device_info)
127 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
128 struct adapter *adapter = pi->adapter;
129 int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
131 static const struct rte_eth_desc_lim cxgbe_desc_lim = {
132 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
133 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
137 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
138 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
139 device_info->max_rx_queues = max_queues;
140 device_info->max_tx_queues = max_queues;
141 device_info->max_mac_addrs = 1;
142 /* XXX: For now we support one MAC/port */
143 device_info->max_vfs = adapter->params.arch.vfcount;
144 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
146 device_info->rx_queue_offload_capa = 0UL;
147 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
149 device_info->tx_queue_offload_capa = 0UL;
150 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
152 device_info->reta_size = pi->rss_size;
153 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
154 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
156 device_info->rx_desc_lim = cxgbe_desc_lim;
157 device_info->tx_desc_lim = cxgbe_desc_lim;
158 cxgbe_get_speed_caps(pi, &device_info->speed_capa);
161 void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
163 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
164 struct adapter *adapter = pi->adapter;
166 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
167 1, -1, 1, -1, false);
170 void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
172 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
173 struct adapter *adapter = pi->adapter;
175 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
176 0, -1, 1, -1, false);
179 void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
181 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
182 struct adapter *adapter = pi->adapter;
184 /* TODO: address filters ?? */
186 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
187 -1, 1, 1, -1, false);
190 void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
192 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
193 struct adapter *adapter = pi->adapter;
195 /* TODO: address filters ?? */
197 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
198 -1, 0, 1, -1, false);
201 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
202 __rte_unused int wait_to_complete)
204 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
205 struct adapter *adapter = pi->adapter;
206 struct sge *s = &adapter->sge;
207 struct rte_eth_link *old_link = ð_dev->data->dev_link;
208 unsigned int work_done, budget = 4;
210 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
211 if (old_link->link_status == pi->link_cfg.link_ok)
212 return -1; /* link not changed */
214 eth_dev->data->dev_link.link_status = pi->link_cfg.link_ok;
215 eth_dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
216 eth_dev->data->dev_link.link_speed = pi->link_cfg.speed;
218 /* link has changed */
222 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
224 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
225 struct adapter *adapter = pi->adapter;
226 struct rte_eth_dev_info dev_info;
228 uint16_t new_mtu = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
230 cxgbe_dev_info_get(eth_dev, &dev_info);
232 /* Must accommodate at least ETHER_MIN_MTU */
233 if ((new_mtu < ETHER_MIN_MTU) || (new_mtu > dev_info.max_rx_pktlen))
236 /* set to jumbo mode if needed */
237 if (new_mtu > ETHER_MAX_LEN)
238 eth_dev->data->dev_conf.rxmode.offloads |=
239 DEV_RX_OFFLOAD_JUMBO_FRAME;
241 eth_dev->data->dev_conf.rxmode.offloads &=
242 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
244 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
247 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
255 void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
257 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
258 struct adapter *adapter = pi->adapter;
262 if (!(adapter->flags & FULL_INIT_DONE))
268 * We clear queues only if both tx and rx path of the port
271 t4_sge_eth_clear_queues(pi);
275 * It returns 0 on success.
277 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
279 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
280 struct adapter *adapter = pi->adapter;
286 * If we don't have a connection to the firmware there's nothing we
289 if (!(adapter->flags & FW_OK)) {
294 if (!(adapter->flags & FULL_INIT_DONE)) {
295 err = cxgbe_up(adapter);
300 cxgbe_enable_rx_queues(pi);
306 for (i = 0; i < pi->n_tx_qsets; i++) {
307 err = cxgbe_dev_tx_queue_start(eth_dev, i);
312 for (i = 0; i < pi->n_rx_qsets; i++) {
313 err = cxgbe_dev_rx_queue_start(eth_dev, i);
318 err = link_start(pi);
327 * Stop device: disable rx and tx functions to allow for reconfiguring.
329 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
331 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
332 struct adapter *adapter = pi->adapter;
336 if (!(adapter->flags & FULL_INIT_DONE))
342 * We clear queues only if both tx and rx path of the port
345 t4_sge_eth_clear_queues(pi);
348 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
350 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
351 struct adapter *adapter = pi->adapter;
352 uint64_t configured_offloads;
356 configured_offloads = eth_dev->data->dev_conf.rxmode.offloads;
357 if (!(configured_offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
358 dev_info(adapter, "can't disable hw crc strip\n");
359 eth_dev->data->dev_conf.rxmode.offloads |=
360 DEV_RX_OFFLOAD_CRC_STRIP;
363 if (!(adapter->flags & FW_QUEUE_BOUND)) {
364 err = setup_sge_fwevtq(adapter);
367 adapter->flags |= FW_QUEUE_BOUND;
370 err = cfg_queue_count(eth_dev);
377 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
380 struct sge_eth_txq *txq = (struct sge_eth_txq *)
381 (eth_dev->data->tx_queues[tx_queue_id]);
383 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
385 ret = t4_sge_eth_txq_start(txq);
387 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
392 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
395 struct sge_eth_txq *txq = (struct sge_eth_txq *)
396 (eth_dev->data->tx_queues[tx_queue_id]);
398 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
400 ret = t4_sge_eth_txq_stop(txq);
402 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
407 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
408 uint16_t queue_idx, uint16_t nb_desc,
409 unsigned int socket_id,
410 const struct rte_eth_txconf *tx_conf __rte_unused)
412 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
413 struct adapter *adapter = pi->adapter;
414 struct sge *s = &adapter->sge;
415 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
417 unsigned int temp_nb_desc;
419 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
420 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
421 socket_id, pi->first_qset);
423 /* Free up the existing queue */
424 if (eth_dev->data->tx_queues[queue_idx]) {
425 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
426 eth_dev->data->tx_queues[queue_idx] = NULL;
429 eth_dev->data->tx_queues[queue_idx] = (void *)txq;
433 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
435 temp_nb_desc = nb_desc;
436 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
437 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
438 __func__, CXGBE_MIN_RING_DESC_SIZE,
439 CXGBE_DEFAULT_TX_DESC_SIZE);
440 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
441 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
442 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
443 __func__, CXGBE_MIN_RING_DESC_SIZE,
444 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
448 txq->q.size = temp_nb_desc;
450 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
451 s->fw_evtq.cntxt_id, socket_id);
453 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
454 __func__, txq->q.cntxt_id, txq->q.abs_id, err);
458 void cxgbe_dev_tx_queue_release(void *q)
460 struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
463 struct port_info *pi = (struct port_info *)
464 (txq->eth_dev->data->dev_private);
465 struct adapter *adap = pi->adapter;
467 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
468 __func__, pi->port_id, txq->q.cntxt_id);
470 t4_sge_eth_txq_release(adap, txq);
474 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
477 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
478 struct adapter *adap = pi->adapter;
481 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
482 __func__, pi->port_id, rx_queue_id);
484 q = eth_dev->data->rx_queues[rx_queue_id];
486 ret = t4_sge_eth_rxq_start(adap, q);
488 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
493 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
496 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
497 struct adapter *adap = pi->adapter;
500 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
501 __func__, pi->port_id, rx_queue_id);
503 q = eth_dev->data->rx_queues[rx_queue_id];
504 ret = t4_sge_eth_rxq_stop(adap, q);
506 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
511 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
512 uint16_t queue_idx, uint16_t nb_desc,
513 unsigned int socket_id,
514 const struct rte_eth_rxconf *rx_conf __rte_unused,
515 struct rte_mempool *mp)
517 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
518 struct adapter *adapter = pi->adapter;
519 struct sge *s = &adapter->sge;
520 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
523 unsigned int temp_nb_desc;
524 struct rte_eth_dev_info dev_info;
525 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
527 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
528 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
531 cxgbe_dev_info_get(eth_dev, &dev_info);
533 /* Must accommodate at least ETHER_MIN_MTU */
534 if ((pkt_len < dev_info.min_rx_bufsize) ||
535 (pkt_len > dev_info.max_rx_pktlen)) {
536 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
537 __func__, dev_info.min_rx_bufsize,
538 dev_info.max_rx_pktlen);
542 /* Free up the existing queue */
543 if (eth_dev->data->rx_queues[queue_idx]) {
544 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
545 eth_dev->data->rx_queues[queue_idx] = NULL;
548 eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
552 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
554 temp_nb_desc = nb_desc;
555 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
556 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
557 __func__, CXGBE_MIN_RING_DESC_SIZE,
558 CXGBE_DEFAULT_RX_DESC_SIZE);
559 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
560 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
561 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
562 __func__, CXGBE_MIN_RING_DESC_SIZE,
563 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
567 rxq->rspq.size = temp_nb_desc;
568 if ((&rxq->fl) != NULL)
569 rxq->fl.size = temp_nb_desc;
571 /* Set to jumbo mode if necessary */
572 if (pkt_len > ETHER_MAX_LEN)
573 eth_dev->data->dev_conf.rxmode.offloads |=
574 DEV_RX_OFFLOAD_JUMBO_FRAME;
576 eth_dev->data->dev_conf.rxmode.offloads &=
577 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
579 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
580 &rxq->fl, t4_ethrx_handler,
582 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
583 queue_idx, socket_id);
585 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
586 __func__, err, pi->port_id, rxq->rspq.cntxt_id,
591 void cxgbe_dev_rx_queue_release(void *q)
593 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
594 struct sge_rspq *rq = &rxq->rspq;
597 struct port_info *pi = (struct port_info *)
598 (rq->eth_dev->data->dev_private);
599 struct adapter *adap = pi->adapter;
601 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
602 __func__, pi->port_id, rxq->rspq.cntxt_id);
604 t4_sge_eth_rxq_release(adap, rxq);
609 * Get port statistics.
611 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
612 struct rte_eth_stats *eth_stats)
614 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
615 struct adapter *adapter = pi->adapter;
616 struct sge *s = &adapter->sge;
617 struct port_stats ps;
620 cxgbe_stats_get(pi, &ps);
623 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 +
624 ps.rx_ovflow2 + ps.rx_ovflow3 +
625 ps.rx_trunc0 + ps.rx_trunc1 +
626 ps.rx_trunc2 + ps.rx_trunc3;
627 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err +
628 ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
632 eth_stats->opackets = ps.tx_frames;
633 eth_stats->obytes = ps.tx_octets;
634 eth_stats->oerrors = ps.tx_error_frames;
636 for (i = 0; i < pi->n_rx_qsets; i++) {
637 struct sge_eth_rxq *rxq =
638 &s->ethrxq[pi->first_qset + i];
640 eth_stats->q_ipackets[i] = rxq->stats.pkts;
641 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
642 eth_stats->ipackets += eth_stats->q_ipackets[i];
643 eth_stats->ibytes += eth_stats->q_ibytes[i];
646 for (i = 0; i < pi->n_tx_qsets; i++) {
647 struct sge_eth_txq *txq =
648 &s->ethtxq[pi->first_qset + i];
650 eth_stats->q_opackets[i] = txq->stats.pkts;
651 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
652 eth_stats->q_errors[i] = txq->stats.mapping_err;
658 * Reset port statistics.
660 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
662 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
663 struct adapter *adapter = pi->adapter;
664 struct sge *s = &adapter->sge;
667 cxgbe_stats_reset(pi);
668 for (i = 0; i < pi->n_rx_qsets; i++) {
669 struct sge_eth_rxq *rxq =
670 &s->ethrxq[pi->first_qset + i];
673 rxq->stats.rx_bytes = 0;
675 for (i = 0; i < pi->n_tx_qsets; i++) {
676 struct sge_eth_txq *txq =
677 &s->ethtxq[pi->first_qset + i];
680 txq->stats.tx_bytes = 0;
681 txq->stats.mapping_err = 0;
685 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
686 struct rte_eth_fc_conf *fc_conf)
688 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
689 struct link_config *lc = &pi->link_cfg;
690 int rx_pause, tx_pause;
692 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
693 rx_pause = lc->fc & PAUSE_RX;
694 tx_pause = lc->fc & PAUSE_TX;
696 if (rx_pause && tx_pause)
697 fc_conf->mode = RTE_FC_FULL;
699 fc_conf->mode = RTE_FC_RX_PAUSE;
701 fc_conf->mode = RTE_FC_TX_PAUSE;
703 fc_conf->mode = RTE_FC_NONE;
707 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
708 struct rte_eth_fc_conf *fc_conf)
710 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
711 struct adapter *adapter = pi->adapter;
712 struct link_config *lc = &pi->link_cfg;
714 if (lc->pcaps & FW_PORT_CAP32_ANEG) {
715 if (fc_conf->autoneg)
716 lc->requested_fc |= PAUSE_AUTONEG;
718 lc->requested_fc &= ~PAUSE_AUTONEG;
721 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
722 (fc_conf->mode & RTE_FC_RX_PAUSE))
723 lc->requested_fc |= PAUSE_RX;
725 lc->requested_fc &= ~PAUSE_RX;
727 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
728 (fc_conf->mode & RTE_FC_TX_PAUSE))
729 lc->requested_fc |= PAUSE_TX;
731 lc->requested_fc &= ~PAUSE_TX;
733 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
738 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
740 static const uint32_t ptypes[] = {
746 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
751 /* Update RSS hash configuration
753 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
754 struct rte_eth_rss_conf *rss_conf)
756 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
757 struct adapter *adapter = pi->adapter;
760 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
764 pi->rss_hf = rss_conf->rss_hf;
766 if (rss_conf->rss_key) {
767 u32 key[10], mod_key[10];
770 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
772 for (i = 9, j = 0; i >= 0; i--, j++)
773 mod_key[j] = cpu_to_be32(key[i]);
775 t4_write_rss_key(adapter, mod_key, -1);
781 /* Get RSS hash configuration
783 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
784 struct rte_eth_rss_conf *rss_conf)
786 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
787 struct adapter *adapter = pi->adapter;
792 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
798 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
799 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
800 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
801 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
804 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
805 rss_hf |= ETH_RSS_IPV6;
807 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
808 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
809 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
810 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
813 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
814 rss_hf |= ETH_RSS_IPV4;
816 rss_conf->rss_hf = rss_hf;
818 if (rss_conf->rss_key) {
819 u32 key[10], mod_key[10];
822 t4_read_rss_key(adapter, key);
824 for (i = 9, j = 0; i >= 0; i--, j++)
825 mod_key[j] = be32_to_cpu(key[i]);
827 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
833 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
840 * eeprom_ptov - translate a physical EEPROM address to virtual
841 * @phys_addr: the physical EEPROM address
842 * @fn: the PCI function number
843 * @sz: size of function-specific area
845 * Translate a physical EEPROM address to virtual. The first 1K is
846 * accessed through virtual addresses starting at 31K, the rest is
847 * accessed through virtual addresses starting at 0.
849 * The mapping is as follows:
850 * [0..1K) -> [31K..32K)
851 * [1K..1K+A) -> [31K-A..31K)
852 * [1K+A..ES) -> [0..ES-A-1K)
854 * where A = @fn * @sz, and ES = EEPROM size.
856 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
859 if (phys_addr < 1024)
860 return phys_addr + (31 << 10);
861 if (phys_addr < 1024 + fn)
862 return fn + phys_addr - 1024;
863 if (phys_addr < EEPROMSIZE)
864 return phys_addr - 1024 - fn;
865 if (phys_addr < EEPROMVSIZE)
866 return phys_addr - 1024;
870 /* The next two routines implement eeprom read/write from physical addresses.
872 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
874 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
877 vaddr = t4_seeprom_read(adap, vaddr, v);
878 return vaddr < 0 ? vaddr : 0;
881 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
883 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
886 vaddr = t4_seeprom_write(adap, vaddr, v);
887 return vaddr < 0 ? vaddr : 0;
890 #define EEPROM_MAGIC 0x38E2F10C
892 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
893 struct rte_dev_eeprom_info *e)
895 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
896 struct adapter *adapter = pi->adapter;
898 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
903 e->magic = EEPROM_MAGIC;
904 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
905 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
908 rte_memcpy(e->data, buf + e->offset, e->length);
913 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
914 struct rte_dev_eeprom_info *eeprom)
916 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
917 struct adapter *adapter = pi->adapter;
920 u32 aligned_offset, aligned_len, *p;
922 if (eeprom->magic != EEPROM_MAGIC)
925 aligned_offset = eeprom->offset & ~3;
926 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
928 if (adapter->pf > 0) {
929 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
931 if (aligned_offset < start ||
932 aligned_offset + aligned_len > start + EEPROMPFSIZE)
936 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
937 /* RMW possibly needed for first or last words.
939 buf = rte_zmalloc(NULL, aligned_len, 0);
942 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
943 if (!err && aligned_len > 4)
944 err = eeprom_rd_phys(adapter,
945 aligned_offset + aligned_len - 4,
946 (u32 *)&buf[aligned_len - 4]);
949 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
955 err = t4_seeprom_wp(adapter, false);
959 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
960 err = eeprom_wr_phys(adapter, aligned_offset, *p);
965 err = t4_seeprom_wp(adapter, true);
967 if (buf != eeprom->data)
972 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
974 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
975 struct adapter *adapter = pi->adapter;
977 return t4_get_regs_len(adapter) / sizeof(uint32_t);
980 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
981 struct rte_dev_reg_info *regs)
983 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
984 struct adapter *adapter = pi->adapter;
986 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
987 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
990 if (regs->data == NULL) {
991 regs->length = cxgbe_get_regs_len(eth_dev);
992 regs->width = sizeof(uint32_t);
997 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1002 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
1004 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
1005 struct adapter *adapter = pi->adapter;
1008 ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
1009 pi->xact_addr_filt, (u8 *)addr, true, true);
1011 dev_err(adapter, "failed to set mac addr; err = %d\n",
1015 pi->xact_addr_filt = ret;
1019 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1020 .dev_start = cxgbe_dev_start,
1021 .dev_stop = cxgbe_dev_stop,
1022 .dev_close = cxgbe_dev_close,
1023 .promiscuous_enable = cxgbe_dev_promiscuous_enable,
1024 .promiscuous_disable = cxgbe_dev_promiscuous_disable,
1025 .allmulticast_enable = cxgbe_dev_allmulticast_enable,
1026 .allmulticast_disable = cxgbe_dev_allmulticast_disable,
1027 .dev_configure = cxgbe_dev_configure,
1028 .dev_infos_get = cxgbe_dev_info_get,
1029 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1030 .link_update = cxgbe_dev_link_update,
1031 .mtu_set = cxgbe_dev_mtu_set,
1032 .tx_queue_setup = cxgbe_dev_tx_queue_setup,
1033 .tx_queue_start = cxgbe_dev_tx_queue_start,
1034 .tx_queue_stop = cxgbe_dev_tx_queue_stop,
1035 .tx_queue_release = cxgbe_dev_tx_queue_release,
1036 .rx_queue_setup = cxgbe_dev_rx_queue_setup,
1037 .rx_queue_start = cxgbe_dev_rx_queue_start,
1038 .rx_queue_stop = cxgbe_dev_rx_queue_stop,
1039 .rx_queue_release = cxgbe_dev_rx_queue_release,
1040 .stats_get = cxgbe_dev_stats_get,
1041 .stats_reset = cxgbe_dev_stats_reset,
1042 .flow_ctrl_get = cxgbe_flow_ctrl_get,
1043 .flow_ctrl_set = cxgbe_flow_ctrl_set,
1044 .get_eeprom_length = cxgbe_get_eeprom_length,
1045 .get_eeprom = cxgbe_get_eeprom,
1046 .set_eeprom = cxgbe_set_eeprom,
1047 .get_reg = cxgbe_get_regs,
1048 .rss_hash_update = cxgbe_dev_rss_hash_update,
1049 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get,
1050 .mac_addr_set = cxgbe_mac_addr_set,
1055 * It returns 0 on success.
1057 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1059 struct rte_pci_device *pci_dev;
1060 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1061 struct adapter *adapter = NULL;
1062 char name[RTE_ETH_NAME_MAX_LEN];
1067 eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1068 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1069 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1070 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1072 /* for secondary processes, we attach to ethdevs allocated by primary
1073 * and do minimal initialization.
1075 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1078 for (i = 1; i < MAX_NPORTS; i++) {
1079 struct rte_eth_dev *rest_eth_dev;
1080 char namei[RTE_ETH_NAME_MAX_LEN];
1082 snprintf(namei, sizeof(namei), "%s_%d",
1083 pci_dev->device.name, i);
1084 rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1086 rest_eth_dev->device = &pci_dev->device;
1087 rest_eth_dev->dev_ops =
1089 rest_eth_dev->rx_pkt_burst =
1090 eth_dev->rx_pkt_burst;
1091 rest_eth_dev->tx_pkt_burst =
1092 eth_dev->tx_pkt_burst;
1093 rte_eth_dev_probing_finish(rest_eth_dev);
1099 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1100 adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1104 adapter->use_unpacked_mode = 1;
1105 adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1106 if (!adapter->regs) {
1107 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1109 goto out_free_adapter;
1111 adapter->pdev = pci_dev;
1112 adapter->eth_dev = eth_dev;
1113 pi->adapter = adapter;
1115 err = cxgbe_probe(adapter);
1117 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1119 goto out_free_adapter;
1129 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1131 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1132 struct adapter *adap = pi->adapter;
1134 /* Free up other ports and all resources */
1139 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1140 struct rte_pci_device *pci_dev)
1142 return rte_eth_dev_pci_generic_probe(pci_dev,
1143 sizeof(struct port_info), eth_cxgbe_dev_init);
1146 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1148 return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit);
1151 static struct rte_pci_driver rte_cxgbe_pmd = {
1152 .id_table = cxgb4_pci_tbl,
1153 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1154 .probe = eth_cxgbe_pci_probe,
1155 .remove = eth_cxgbe_pci_remove,
1158 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1159 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1160 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");