drivers/net/cxgbe/cxgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5
   6 #include <sys/queue.h>
   7 #include <stdio.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <unistd.h>
  12 #include <stdarg.h>
  13 #include <inttypes.h>
  14 #include <netinet/in.h>
  15
  16 #include <rte_byteorder.h>
  17 #include <rte_common.h>
  18 #include <rte_cycles.h>
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_atomic.h>
  25 #include <rte_branch_prediction.h>
  26 #include <rte_memory.h>
  27 #include <rte_tailq.h>
  28 #include <rte_eal.h>
  29 #include <rte_alarm.h>
  30 #include <rte_ether.h>
  31 #include <rte_ethdev_driver.h>
  32 #include <rte_ethdev_pci.h>
  33 #include <rte_malloc.h>
  34 #include <rte_random.h>
  35 #include <rte_dev.h>
  36
  37 #include "cxgbe.h"
  38 #include "cxgbe_pfvf.h"
  39
  40 /*
  41  * Macros needed to support the PCI Device ID Table ...
  42  */
  43 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
  44         static const struct rte_pci_id cxgb4_pci_tbl[] = {
  45 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
  46
  47 #define PCI_VENDOR_ID_CHELSIO 0x1425
  48
  49 #define CH_PCI_ID_TABLE_ENTRY(devid) \
  50                 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
  51
  52 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
  53                 { .vendor_id = 0, } \
  54         }
  55
  56 /*
  57  *... and the PCI ID Table itself ...
  58  */
  59 #include "t4_pci_id_tbl.h"
  60
  61 #define CXGBE_TX_OFFLOADS (DEV_TX_OFFLOAD_VLAN_INSERT |\
  62                            DEV_TX_OFFLOAD_IPV4_CKSUM |\
  63                            DEV_TX_OFFLOAD_UDP_CKSUM |\
  64                            DEV_TX_OFFLOAD_TCP_CKSUM |\
  65                            DEV_TX_OFFLOAD_TCP_TSO)
  66
  67 #define CXGBE_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_STRIP |\
  68                            DEV_RX_OFFLOAD_CRC_STRIP |\
  69                            DEV_RX_OFFLOAD_IPV4_CKSUM |\
  70                            DEV_RX_OFFLOAD_JUMBO_FRAME |\
  71                            DEV_RX_OFFLOAD_UDP_CKSUM |\
  72                            DEV_RX_OFFLOAD_TCP_CKSUM)
  73
  74 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  75                          uint16_t nb_pkts)
  76 {
  77         struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
  78         uint16_t pkts_sent, pkts_remain;
  79         uint16_t total_sent = 0;
  80         int ret = 0;
  81
  82         CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n",
  83                        __func__, txq, tx_pkts, nb_pkts);
  84
  85         t4_os_lock(&txq->txq_lock);
  86         /* free up desc from already completed tx */
  87         reclaim_completed_tx(&txq->q);
  88         while (total_sent < nb_pkts) {
  89                 pkts_remain = nb_pkts - total_sent;
  90
  91                 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
  92                         ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent],
  93                                           nb_pkts);
  94                         if (ret < 0)
  95                                 break;
  96                 }
  97                 if (!pkts_sent)
  98                         break;
  99                 total_sent += pkts_sent;
 100                 /* reclaim as much as possible */
 101                 reclaim_completed_tx(&txq->q);
 102         }
 103
 104         t4_os_unlock(&txq->txq_lock);
 105         return total_sent;
 106 }
 107
 108 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 109                          uint16_t nb_pkts)
 110 {
 111         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
 112         unsigned int work_done;
 113
 114         CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n",
 115                        __func__, rxq->rspq.cntxt_id, nb_pkts);
 116
 117         if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
 118                 dev_err(adapter, "error in cxgbe poll\n");
 119
 120         CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done);
 121         return work_done;
 122 }
 123
 124 void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
 125                         struct rte_eth_dev_info *device_info)
 126 {
 127         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 128         struct adapter *adapter = pi->adapter;
 129         int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
 130
 131         static const struct rte_eth_desc_lim cxgbe_desc_lim = {
 132                 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
 133                 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
 134                 .nb_align = 1,
 135         };
 136
 137         device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
 138         device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
 139         device_info->max_rx_queues = max_queues;
 140         device_info->max_tx_queues = max_queues;
 141         device_info->max_mac_addrs = 1;
 142         /* XXX: For now we support one MAC/port */
 143         device_info->max_vfs = adapter->params.arch.vfcount;
 144         device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
 145
 146         device_info->rx_queue_offload_capa = 0UL;
 147         device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
 148
 149         device_info->tx_queue_offload_capa = 0UL;
 150         device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
 151
 152         device_info->reta_size = pi->rss_size;
 153         device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
 154         device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
 155
 156         device_info->rx_desc_lim = cxgbe_desc_lim;
 157         device_info->tx_desc_lim = cxgbe_desc_lim;
 158         cxgbe_get_speed_caps(pi, &device_info->speed_capa);
 159 }
 160
 161 void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
 162 {
 163         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 164         struct adapter *adapter = pi->adapter;
 165
 166         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 167                       1, -1, 1, -1, false);
 168 }
 169
 170 void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
 171 {
 172         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 173         struct adapter *adapter = pi->adapter;
 174
 175         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 176                       0, -1, 1, -1, false);
 177 }
 178
 179 void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
 180 {
 181         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 182         struct adapter *adapter = pi->adapter;
 183
 184         /* TODO: address filters ?? */
 185
 186         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 187                       -1, 1, 1, -1, false);
 188 }
 189
 190 void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
 191 {
 192         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 193         struct adapter *adapter = pi->adapter;
 194
 195         /* TODO: address filters ?? */
 196
 197         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 198                       -1, 0, 1, -1, false);
 199 }
 200
 201 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
 202                           __rte_unused int wait_to_complete)
 203 {
 204         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 205         struct adapter *adapter = pi->adapter;
 206         struct sge *s = &adapter->sge;
 207         struct rte_eth_link *old_link = &eth_dev->data->dev_link;
 208         unsigned int work_done, budget = 4;
 209
 210         cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 211         if (old_link->link_status == pi->link_cfg.link_ok)
 212                 return -1;  /* link not changed */
 213
 214         eth_dev->data->dev_link.link_status = pi->link_cfg.link_ok;
 215         eth_dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
 216         eth_dev->data->dev_link.link_speed = pi->link_cfg.speed;
 217
 218         /* link has changed */
 219         return 0;
 220 }
 221
 222 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
 223 {
 224         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 225         struct adapter *adapter = pi->adapter;
 226         struct rte_eth_dev_info dev_info;
 227         int err;
 228         uint16_t new_mtu = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
 229
 230         cxgbe_dev_info_get(eth_dev, &dev_info);
 231
 232         /* Must accommodate at least ETHER_MIN_MTU */
 233         if ((new_mtu < ETHER_MIN_MTU) || (new_mtu > dev_info.max_rx_pktlen))
 234                 return -EINVAL;
 235
 236         /* set to jumbo mode if needed */
 237         if (new_mtu > ETHER_MAX_LEN)
 238                 eth_dev->data->dev_conf.rxmode.offloads |=
 239                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 240         else
 241                 eth_dev->data->dev_conf.rxmode.offloads &=
 242                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 243
 244         err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
 245                             -1, -1, true);
 246         if (!err)
 247                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
 248
 249         return err;
 250 }
 251
 252 /*
 253  * Stop device.
 254  */
 255 void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
 256 {
 257         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 258         struct adapter *adapter = pi->adapter;
 259
 260         CXGBE_FUNC_TRACE();
 261
 262         if (!(adapter->flags & FULL_INIT_DONE))
 263                 return;
 264
 265         cxgbe_down(pi);
 266
 267         /*
 268          *  We clear queues only if both tx and rx path of the port
 269          *  have been disabled
 270          */
 271         t4_sge_eth_clear_queues(pi);
 272 }
 273
 274 /* Start the device.
 275  * It returns 0 on success.
 276  */
 277 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
 278 {
 279         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 280         struct adapter *adapter = pi->adapter;
 281         int err = 0, i;
 282
 283         CXGBE_FUNC_TRACE();
 284
 285         /*
 286          * If we don't have a connection to the firmware there's nothing we
 287          * can do.
 288          */
 289         if (!(adapter->flags & FW_OK)) {
 290                 err = -ENXIO;
 291                 goto out;
 292         }
 293
 294         if (!(adapter->flags & FULL_INIT_DONE)) {
 295                 err = cxgbe_up(adapter);
 296                 if (err < 0)
 297                         goto out;
 298         }
 299
 300         cxgbe_enable_rx_queues(pi);
 301
 302         err = setup_rss(pi);
 303         if (err)
 304                 goto out;
 305
 306         for (i = 0; i < pi->n_tx_qsets; i++) {
 307                 err = cxgbe_dev_tx_queue_start(eth_dev, i);
 308                 if (err)
 309                         goto out;
 310         }
 311
 312         for (i = 0; i < pi->n_rx_qsets; i++) {
 313                 err = cxgbe_dev_rx_queue_start(eth_dev, i);
 314                 if (err)
 315                         goto out;
 316         }
 317
 318         err = link_start(pi);
 319         if (err)
 320                 goto out;
 321
 322 out:
 323         return err;
 324 }
 325
 326 /*
 327  * Stop device: disable rx and tx functions to allow for reconfiguring.
 328  */
 329 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
 330 {
 331         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 332         struct adapter *adapter = pi->adapter;
 333
 334         CXGBE_FUNC_TRACE();
 335
 336         if (!(adapter->flags & FULL_INIT_DONE))
 337                 return;
 338
 339         cxgbe_down(pi);
 340
 341         /*
 342          *  We clear queues only if both tx and rx path of the port
 343          *  have been disabled
 344          */
 345         t4_sge_eth_clear_queues(pi);
 346 }
 347
 348 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
 349 {
 350         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 351         struct adapter *adapter = pi->adapter;
 352         uint64_t configured_offloads;
 353         int err;
 354
 355         CXGBE_FUNC_TRACE();
 356         configured_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 357         if (!(configured_offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
 358                 dev_info(adapter, "can't disable hw crc strip\n");
 359                 eth_dev->data->dev_conf.rxmode.offloads |=
 360                         DEV_RX_OFFLOAD_CRC_STRIP;
 361         }
 362
 363         if (!(adapter->flags & FW_QUEUE_BOUND)) {
 364                 err = setup_sge_fwevtq(adapter);
 365                 if (err)
 366                         return err;
 367                 adapter->flags |= FW_QUEUE_BOUND;
 368         }
 369
 370         err = cfg_queue_count(eth_dev);
 371         if (err)
 372                 return err;
 373
 374         return 0;
 375 }
 376
 377 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 378 {
 379         int ret;
 380         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 381                                   (eth_dev->data->tx_queues[tx_queue_id]);
 382
 383         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 384
 385         ret = t4_sge_eth_txq_start(txq);
 386         if (ret == 0)
 387                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 388
 389         return ret;
 390 }
 391
 392 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 393 {
 394         int ret;
 395         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 396                                   (eth_dev->data->tx_queues[tx_queue_id]);
 397
 398         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 399
 400         ret = t4_sge_eth_txq_stop(txq);
 401         if (ret == 0)
 402                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 403
 404         return ret;
 405 }
 406
 407 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
 408                              uint16_t queue_idx, uint16_t nb_desc,
 409                              unsigned int socket_id,
 410                              const struct rte_eth_txconf *tx_conf __rte_unused)
 411 {
 412         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 413         struct adapter *adapter = pi->adapter;
 414         struct sge *s = &adapter->sge;
 415         struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
 416         int err = 0;
 417         unsigned int temp_nb_desc;
 418
 419         dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
 420                   __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
 421                   socket_id, pi->first_qset);
 422
 423         /*  Free up the existing queue  */
 424         if (eth_dev->data->tx_queues[queue_idx]) {
 425                 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
 426                 eth_dev->data->tx_queues[queue_idx] = NULL;
 427         }
 428
 429         eth_dev->data->tx_queues[queue_idx] = (void *)txq;
 430
 431         /* Sanity Checking
 432          *
 433          * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
 434          */
 435         temp_nb_desc = nb_desc;
 436         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 437                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 438                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 439                          CXGBE_DEFAULT_TX_DESC_SIZE);
 440                 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
 441         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 442                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 443                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 444                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
 445                 return -(EINVAL);
 446         }
 447
 448         txq->q.size = temp_nb_desc;
 449
 450         err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
 451                                    s->fw_evtq.cntxt_id, socket_id);
 452
 453         dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
 454                   __func__, txq->q.cntxt_id, txq->q.abs_id, err);
 455         return err;
 456 }
 457
 458 void cxgbe_dev_tx_queue_release(void *q)
 459 {
 460         struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
 461
 462         if (txq) {
 463                 struct port_info *pi = (struct port_info *)
 464                                        (txq->eth_dev->data->dev_private);
 465                 struct adapter *adap = pi->adapter;
 466
 467                 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
 468                           __func__, pi->port_id, txq->q.cntxt_id);
 469
 470                 t4_sge_eth_txq_release(adap, txq);
 471         }
 472 }
 473
 474 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 475 {
 476         int ret;
 477         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 478         struct adapter *adap = pi->adapter;
 479         struct sge_rspq *q;
 480
 481         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 482                   __func__, pi->port_id, rx_queue_id);
 483
 484         q = eth_dev->data->rx_queues[rx_queue_id];
 485
 486         ret = t4_sge_eth_rxq_start(adap, q);
 487         if (ret == 0)
 488                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 489
 490         return ret;
 491 }
 492
 493 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 494 {
 495         int ret;
 496         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 497         struct adapter *adap = pi->adapter;
 498         struct sge_rspq *q;
 499
 500         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 501                   __func__, pi->port_id, rx_queue_id);
 502
 503         q = eth_dev->data->rx_queues[rx_queue_id];
 504         ret = t4_sge_eth_rxq_stop(adap, q);
 505         if (ret == 0)
 506                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 507
 508         return ret;
 509 }
 510
 511 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
 512                              uint16_t queue_idx, uint16_t nb_desc,
 513                              unsigned int socket_id,
 514                              const struct rte_eth_rxconf *rx_conf __rte_unused,
 515                              struct rte_mempool *mp)
 516 {
 517         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 518         struct adapter *adapter = pi->adapter;
 519         struct sge *s = &adapter->sge;
 520         struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
 521         int err = 0;
 522         int msi_idx = 0;
 523         unsigned int temp_nb_desc;
 524         struct rte_eth_dev_info dev_info;
 525         unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
 526
 527         dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
 528                   __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
 529                   socket_id, mp);
 530
 531         cxgbe_dev_info_get(eth_dev, &dev_info);
 532
 533         /* Must accommodate at least ETHER_MIN_MTU */
 534         if ((pkt_len < dev_info.min_rx_bufsize) ||
 535             (pkt_len > dev_info.max_rx_pktlen)) {
 536                 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
 537                         __func__, dev_info.min_rx_bufsize,
 538                         dev_info.max_rx_pktlen);
 539                 return -EINVAL;
 540         }
 541
 542         /*  Free up the existing queue  */
 543         if (eth_dev->data->rx_queues[queue_idx]) {
 544                 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
 545                 eth_dev->data->rx_queues[queue_idx] = NULL;
 546         }
 547
 548         eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
 549
 550         /* Sanity Checking
 551          *
 552          * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
 553          */
 554         temp_nb_desc = nb_desc;
 555         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 556                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 557                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 558                          CXGBE_DEFAULT_RX_DESC_SIZE);
 559                 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
 560         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 561                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 562                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 563                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
 564                 return -(EINVAL);
 565         }
 566
 567         rxq->rspq.size = temp_nb_desc;
 568         if ((&rxq->fl) != NULL)
 569                 rxq->fl.size = temp_nb_desc;
 570
 571         /* Set to jumbo mode if necessary */
 572         if (pkt_len > ETHER_MAX_LEN)
 573                 eth_dev->data->dev_conf.rxmode.offloads |=
 574                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 575         else
 576                 eth_dev->data->dev_conf.rxmode.offloads &=
 577                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 578
 579         err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
 580                                &rxq->fl, t4_ethrx_handler,
 581                                is_pf4(adapter) ?
 582                                t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
 583                                queue_idx, socket_id);
 584
 585         dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
 586                   __func__, err, pi->port_id, rxq->rspq.cntxt_id,
 587                   rxq->rspq.abs_id);
 588         return err;
 589 }
 590
 591 void cxgbe_dev_rx_queue_release(void *q)
 592 {
 593         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
 594         struct sge_rspq *rq = &rxq->rspq;
 595
 596         if (rq) {
 597                 struct port_info *pi = (struct port_info *)
 598                                        (rq->eth_dev->data->dev_private);
 599                 struct adapter *adap = pi->adapter;
 600
 601                 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 602                           __func__, pi->port_id, rxq->rspq.cntxt_id);
 603
 604                 t4_sge_eth_rxq_release(adap, rxq);
 605         }
 606 }
 607
 608 /*
 609  * Get port statistics.
 610  */
 611 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
 612                                 struct rte_eth_stats *eth_stats)
 613 {
 614         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 615         struct adapter *adapter = pi->adapter;
 616         struct sge *s = &adapter->sge;
 617         struct port_stats ps;
 618         unsigned int i;
 619
 620         cxgbe_stats_get(pi, &ps);
 621
 622         /* RX Stats */
 623         eth_stats->imissed  = ps.rx_ovflow0 + ps.rx_ovflow1 +
 624                               ps.rx_ovflow2 + ps.rx_ovflow3 +
 625                               ps.rx_trunc0 + ps.rx_trunc1 +
 626                               ps.rx_trunc2 + ps.rx_trunc3;
 627         eth_stats->ierrors  = ps.rx_symbol_err + ps.rx_fcs_err +
 628                               ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
 629                               ps.rx_len_err;
 630
 631         /* TX Stats */
 632         eth_stats->opackets = ps.tx_frames;
 633         eth_stats->obytes   = ps.tx_octets;
 634         eth_stats->oerrors  = ps.tx_error_frames;
 635
 636         for (i = 0; i < pi->n_rx_qsets; i++) {
 637                 struct sge_eth_rxq *rxq =
 638                         &s->ethrxq[pi->first_qset + i];
 639
 640                 eth_stats->q_ipackets[i] = rxq->stats.pkts;
 641                 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
 642                 eth_stats->ipackets += eth_stats->q_ipackets[i];
 643                 eth_stats->ibytes += eth_stats->q_ibytes[i];
 644         }
 645
 646         for (i = 0; i < pi->n_tx_qsets; i++) {
 647                 struct sge_eth_txq *txq =
 648                         &s->ethtxq[pi->first_qset + i];
 649
 650                 eth_stats->q_opackets[i] = txq->stats.pkts;
 651                 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
 652                 eth_stats->q_errors[i] = txq->stats.mapping_err;
 653         }
 654         return 0;
 655 }
 656
 657 /*
 658  * Reset port statistics.
 659  */
 660 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
 661 {
 662         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 663         struct adapter *adapter = pi->adapter;
 664         struct sge *s = &adapter->sge;
 665         unsigned int i;
 666
 667         cxgbe_stats_reset(pi);
 668         for (i = 0; i < pi->n_rx_qsets; i++) {
 669                 struct sge_eth_rxq *rxq =
 670                         &s->ethrxq[pi->first_qset + i];
 671
 672                 rxq->stats.pkts = 0;
 673                 rxq->stats.rx_bytes = 0;
 674         }
 675         for (i = 0; i < pi->n_tx_qsets; i++) {
 676                 struct sge_eth_txq *txq =
 677                         &s->ethtxq[pi->first_qset + i];
 678
 679                 txq->stats.pkts = 0;
 680                 txq->stats.tx_bytes = 0;
 681                 txq->stats.mapping_err = 0;
 682         }
 683 }
 684
 685 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
 686                                struct rte_eth_fc_conf *fc_conf)
 687 {
 688         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 689         struct link_config *lc = &pi->link_cfg;
 690         int rx_pause, tx_pause;
 691
 692         fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
 693         rx_pause = lc->fc & PAUSE_RX;
 694         tx_pause = lc->fc & PAUSE_TX;
 695
 696         if (rx_pause && tx_pause)
 697                 fc_conf->mode = RTE_FC_FULL;
 698         else if (rx_pause)
 699                 fc_conf->mode = RTE_FC_RX_PAUSE;
 700         else if (tx_pause)
 701                 fc_conf->mode = RTE_FC_TX_PAUSE;
 702         else
 703                 fc_conf->mode = RTE_FC_NONE;
 704         return 0;
 705 }
 706
 707 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
 708                                struct rte_eth_fc_conf *fc_conf)
 709 {
 710         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 711         struct adapter *adapter = pi->adapter;
 712         struct link_config *lc = &pi->link_cfg;
 713
 714         if (lc->pcaps & FW_PORT_CAP32_ANEG) {
 715                 if (fc_conf->autoneg)
 716                         lc->requested_fc |= PAUSE_AUTONEG;
 717                 else
 718                         lc->requested_fc &= ~PAUSE_AUTONEG;
 719         }
 720
 721         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
 722             (fc_conf->mode & RTE_FC_RX_PAUSE))
 723                 lc->requested_fc |= PAUSE_RX;
 724         else
 725                 lc->requested_fc &= ~PAUSE_RX;
 726
 727         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
 728             (fc_conf->mode & RTE_FC_TX_PAUSE))
 729                 lc->requested_fc |= PAUSE_TX;
 730         else
 731                 lc->requested_fc &= ~PAUSE_TX;
 732
 733         return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
 734                              &pi->link_cfg);
 735 }
 736
 737 const uint32_t *
 738 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
 739 {
 740         static const uint32_t ptypes[] = {
 741                 RTE_PTYPE_L3_IPV4,
 742                 RTE_PTYPE_L3_IPV6,
 743                 RTE_PTYPE_UNKNOWN
 744         };
 745
 746         if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
 747                 return ptypes;
 748         return NULL;
 749 }
 750
 751 /* Update RSS hash configuration
 752  */
 753 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
 754                                      struct rte_eth_rss_conf *rss_conf)
 755 {
 756         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 757         struct adapter *adapter = pi->adapter;
 758         int err;
 759
 760         err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
 761         if (err)
 762                 return err;
 763
 764         pi->rss_hf = rss_conf->rss_hf;
 765
 766         if (rss_conf->rss_key) {
 767                 u32 key[10], mod_key[10];
 768                 int i, j;
 769
 770                 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
 771
 772                 for (i = 9, j = 0; i >= 0; i--, j++)
 773                         mod_key[j] = cpu_to_be32(key[i]);
 774
 775                 t4_write_rss_key(adapter, mod_key, -1);
 776         }
 777
 778         return 0;
 779 }
 780
 781 /* Get RSS hash configuration
 782  */
 783 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 784                                        struct rte_eth_rss_conf *rss_conf)
 785 {
 786         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 787         struct adapter *adapter = pi->adapter;
 788         u64 rss_hf = 0;
 789         u64 flags = 0;
 790         int err;
 791
 792         err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
 793                                     &flags, NULL);
 794
 795         if (err)
 796                 return err;
 797
 798         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
 799                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
 800                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
 801                         rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
 802         }
 803
 804         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
 805                 rss_hf |= ETH_RSS_IPV6;
 806
 807         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
 808                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
 809                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
 810                         rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
 811         }
 812
 813         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
 814                 rss_hf |= ETH_RSS_IPV4;
 815
 816         rss_conf->rss_hf = rss_hf;
 817
 818         if (rss_conf->rss_key) {
 819                 u32 key[10], mod_key[10];
 820                 int i, j;
 821
 822                 t4_read_rss_key(adapter, key);
 823
 824                 for (i = 9, j = 0; i >= 0; i--, j++)
 825                         mod_key[j] = be32_to_cpu(key[i]);
 826
 827                 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
 828         }
 829
 830         return 0;
 831 }
 832
 833 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
 834 {
 835         RTE_SET_USED(dev);
 836         return EEPROMSIZE;
 837 }
 838
 839 /**
 840  * eeprom_ptov - translate a physical EEPROM address to virtual
 841  * @phys_addr: the physical EEPROM address
 842  * @fn: the PCI function number
 843  * @sz: size of function-specific area
 844  *
 845  * Translate a physical EEPROM address to virtual.  The first 1K is
 846  * accessed through virtual addresses starting at 31K, the rest is
 847  * accessed through virtual addresses starting at 0.
 848  *
 849  * The mapping is as follows:
 850  * [0..1K) -> [31K..32K)
 851  * [1K..1K+A) -> [31K-A..31K)
 852  * [1K+A..ES) -> [0..ES-A-1K)
 853  *
 854  * where A = @fn * @sz, and ES = EEPROM size.
 855  */
 856 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
 857 {
 858         fn *= sz;
 859         if (phys_addr < 1024)
 860                 return phys_addr + (31 << 10);
 861         if (phys_addr < 1024 + fn)
 862                 return fn + phys_addr - 1024;
 863         if (phys_addr < EEPROMSIZE)
 864                 return phys_addr - 1024 - fn;
 865         if (phys_addr < EEPROMVSIZE)
 866                 return phys_addr - 1024;
 867         return -EINVAL;
 868 }
 869
 870 /* The next two routines implement eeprom read/write from physical addresses.
 871  */
 872 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
 873 {
 874         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
 875
 876         if (vaddr >= 0)
 877                 vaddr = t4_seeprom_read(adap, vaddr, v);
 878         return vaddr < 0 ? vaddr : 0;
 879 }
 880
 881 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
 882 {
 883         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
 884
 885         if (vaddr >= 0)
 886                 vaddr = t4_seeprom_write(adap, vaddr, v);
 887         return vaddr < 0 ? vaddr : 0;
 888 }
 889
 890 #define EEPROM_MAGIC 0x38E2F10C
 891
 892 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
 893                             struct rte_dev_eeprom_info *e)
 894 {
 895         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 896         struct adapter *adapter = pi->adapter;
 897         u32 i, err = 0;
 898         u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
 899
 900         if (!buf)
 901                 return -ENOMEM;
 902
 903         e->magic = EEPROM_MAGIC;
 904         for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
 905                 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
 906
 907         if (!err)
 908                 rte_memcpy(e->data, buf + e->offset, e->length);
 909         rte_free(buf);
 910         return err;
 911 }
 912
 913 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
 914                             struct rte_dev_eeprom_info *eeprom)
 915 {
 916         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 917         struct adapter *adapter = pi->adapter;
 918         u8 *buf;
 919         int err = 0;
 920         u32 aligned_offset, aligned_len, *p;
 921
 922         if (eeprom->magic != EEPROM_MAGIC)
 923                 return -EINVAL;
 924
 925         aligned_offset = eeprom->offset & ~3;
 926         aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
 927
 928         if (adapter->pf > 0) {
 929                 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
 930
 931                 if (aligned_offset < start ||
 932                     aligned_offset + aligned_len > start + EEPROMPFSIZE)
 933                         return -EPERM;
 934         }
 935
 936         if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
 937                 /* RMW possibly needed for first or last words.
 938                  */
 939                 buf = rte_zmalloc(NULL, aligned_len, 0);
 940                 if (!buf)
 941                         return -ENOMEM;
 942                 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
 943                 if (!err && aligned_len > 4)
 944                         err = eeprom_rd_phys(adapter,
 945                                              aligned_offset + aligned_len - 4,
 946                                              (u32 *)&buf[aligned_len - 4]);
 947                 if (err)
 948                         goto out;
 949                 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
 950                            eeprom->length);
 951         } else {
 952                 buf = eeprom->data;
 953         }
 954
 955         err = t4_seeprom_wp(adapter, false);
 956         if (err)
 957                 goto out;
 958
 959         for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
 960                 err = eeprom_wr_phys(adapter, aligned_offset, *p);
 961                 aligned_offset += 4;
 962         }
 963
 964         if (!err)
 965                 err = t4_seeprom_wp(adapter, true);
 966 out:
 967         if (buf != eeprom->data)
 968                 rte_free(buf);
 969         return err;
 970 }
 971
 972 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
 973 {
 974         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 975         struct adapter *adapter = pi->adapter;
 976
 977         return t4_get_regs_len(adapter) / sizeof(uint32_t);
 978 }
 979
 980 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
 981                           struct rte_dev_reg_info *regs)
 982 {
 983         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 984         struct adapter *adapter = pi->adapter;
 985
 986         regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
 987                 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
 988                 (1 << 16);
 989
 990         if (regs->data == NULL) {
 991                 regs->length = cxgbe_get_regs_len(eth_dev);
 992                 regs->width = sizeof(uint32_t);
 993
 994                 return 0;
 995         }
 996
 997         t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
 998
 999         return 0;
1000 }
1001
1002 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
1003 {
1004         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
1005         struct adapter *adapter = pi->adapter;
1006         int ret;
1007
1008         ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
1009                             pi->xact_addr_filt, (u8 *)addr, true, true);
1010         if (ret < 0) {
1011                 dev_err(adapter, "failed to set mac addr; err = %d\n",
1012                         ret);
1013                 return ret;
1014         }
1015         pi->xact_addr_filt = ret;
1016         return 0;
1017 }
1018
1019 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1020         .dev_start              = cxgbe_dev_start,
1021         .dev_stop               = cxgbe_dev_stop,
1022         .dev_close              = cxgbe_dev_close,
1023         .promiscuous_enable     = cxgbe_dev_promiscuous_enable,
1024         .promiscuous_disable    = cxgbe_dev_promiscuous_disable,
1025         .allmulticast_enable    = cxgbe_dev_allmulticast_enable,
1026         .allmulticast_disable   = cxgbe_dev_allmulticast_disable,
1027         .dev_configure          = cxgbe_dev_configure,
1028         .dev_infos_get          = cxgbe_dev_info_get,
1029         .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1030         .link_update            = cxgbe_dev_link_update,
1031         .mtu_set                = cxgbe_dev_mtu_set,
1032         .tx_queue_setup         = cxgbe_dev_tx_queue_setup,
1033         .tx_queue_start         = cxgbe_dev_tx_queue_start,
1034         .tx_queue_stop          = cxgbe_dev_tx_queue_stop,
1035         .tx_queue_release       = cxgbe_dev_tx_queue_release,
1036         .rx_queue_setup         = cxgbe_dev_rx_queue_setup,
1037         .rx_queue_start         = cxgbe_dev_rx_queue_start,
1038         .rx_queue_stop          = cxgbe_dev_rx_queue_stop,
1039         .rx_queue_release       = cxgbe_dev_rx_queue_release,
1040         .stats_get              = cxgbe_dev_stats_get,
1041         .stats_reset            = cxgbe_dev_stats_reset,
1042         .flow_ctrl_get          = cxgbe_flow_ctrl_get,
1043         .flow_ctrl_set          = cxgbe_flow_ctrl_set,
1044         .get_eeprom_length      = cxgbe_get_eeprom_length,
1045         .get_eeprom             = cxgbe_get_eeprom,
1046         .set_eeprom             = cxgbe_set_eeprom,
1047         .get_reg                = cxgbe_get_regs,
1048         .rss_hash_update        = cxgbe_dev_rss_hash_update,
1049         .rss_hash_conf_get      = cxgbe_dev_rss_hash_conf_get,
1050         .mac_addr_set           = cxgbe_mac_addr_set,
1051 };
1052
1053 /*
1054  * Initialize driver
1055  * It returns 0 on success.
1056  */
1057 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1058 {
1059         struct rte_pci_device *pci_dev;
1060         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1061         struct adapter *adapter = NULL;
1062         char name[RTE_ETH_NAME_MAX_LEN];
1063         int err = 0;
1064
1065         CXGBE_FUNC_TRACE();
1066
1067         eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1068         eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1069         eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1070         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1071
1072         /* for secondary processes, we attach to ethdevs allocated by primary
1073          * and do minimal initialization.
1074          */
1075         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1076                 int i;
1077
1078                 for (i = 1; i < MAX_NPORTS; i++) {
1079                         struct rte_eth_dev *rest_eth_dev;
1080                         char namei[RTE_ETH_NAME_MAX_LEN];
1081
1082                         snprintf(namei, sizeof(namei), "%s_%d",
1083                                  pci_dev->device.name, i);
1084                         rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1085                         if (rest_eth_dev) {
1086                                 rest_eth_dev->device = &pci_dev->device;
1087                                 rest_eth_dev->dev_ops =
1088                                         eth_dev->dev_ops;
1089                                 rest_eth_dev->rx_pkt_burst =
1090                                         eth_dev->rx_pkt_burst;
1091                                 rest_eth_dev->tx_pkt_burst =
1092                                         eth_dev->tx_pkt_burst;
1093                                 rte_eth_dev_probing_finish(rest_eth_dev);
1094                         }
1095                 }
1096                 return 0;
1097         }
1098
1099         snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1100         adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1101         if (!adapter)
1102                 return -1;
1103
1104         adapter->use_unpacked_mode = 1;
1105         adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1106         if (!adapter->regs) {
1107                 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1108                 err = -ENOMEM;
1109                 goto out_free_adapter;
1110         }
1111         adapter->pdev = pci_dev;
1112         adapter->eth_dev = eth_dev;
1113         pi->adapter = adapter;
1114
1115         err = cxgbe_probe(adapter);
1116         if (err) {
1117                 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1118                         __func__, err);
1119                 goto out_free_adapter;
1120         }
1121
1122         return 0;
1123
1124 out_free_adapter:
1125         rte_free(adapter);
1126         return err;
1127 }
1128
1129 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1130 {
1131         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1132         struct adapter *adap = pi->adapter;
1133
1134         /* Free up other ports and all resources */
1135         cxgbe_close(adap);
1136         return 0;
1137 }
1138
1139 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1140         struct rte_pci_device *pci_dev)
1141 {
1142         return rte_eth_dev_pci_generic_probe(pci_dev,
1143                 sizeof(struct port_info), eth_cxgbe_dev_init);
1144 }
1145
1146 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1147 {
1148         return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit);
1149 }
1150
1151 static struct rte_pci_driver rte_cxgbe_pmd = {
1152         .id_table = cxgb4_pci_tbl,
1153         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1154         .probe = eth_cxgbe_pci_probe,
1155         .remove = eth_cxgbe_pci_remove,
1156 };
1157
1158 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1159 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1160 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");