drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_eal.h>
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memzone.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memcpy.h>
  52 #include <rte_alarm.h>
  53 #include <rte_dev.h>
  54 #include <rte_eth_ctrl.h>
  55 #include <rte_tailq.h>
  56 #include <rte_hash_crc.h>
  57
  58 #include "i40e_logs.h"
  59 #include "base/i40e_prototype.h"
  60 #include "base/i40e_adminq_cmd.h"
  61 #include "base/i40e_type.h"
  62 #include "base/i40e_register.h"
  63 #include "base/i40e_dcb.h"
  64 #include "i40e_ethdev.h"
  65 #include "i40e_rxtx.h"
  66 #include "i40e_pf.h"
  67 #include "i40e_regs.h"
  68
  69 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  70 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  71
  72 #define I40E_CLEAR_PXE_WAIT_MS     200
  73
  74 /* Maximun number of capability elements */
  75 #define I40E_MAX_CAP_ELE_NUM       128
  76
  77 /* Wait count and interval */
  78 #define I40E_CHK_Q_ENA_COUNT       1000
  79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  80
  81 /* Maximun number of VSI */
  82 #define I40E_MAX_NUM_VSIS          (384UL)
  83
  84 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  85
  86 /* Flow control default timer */
  87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  88
  89 /* Flow control default high water */
  90 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  91
  92 /* Flow control default low water */
  93 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  94
  95 /* Flow control enable fwd bit */
  96 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  97
  98 /* Receive Packet Buffer size */
  99 #define I40E_RXPBSIZE (968 * 1024)
 100
 101 /* Kilobytes shift */
 102 #define I40E_KILOSHIFT 10
 103
 104 /* Receive Average Packet Size in Byte*/
 105 #define I40E_PACKET_AVERAGE_SIZE 128
 106
 107 /* Mask of PF interrupt causes */
 108 #define I40E_PFINT_ICR0_ENA_MASK ( \
 109                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 110                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 113                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 114                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 118
 119 #define I40E_FLOW_TYPES ( \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 130         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 131
 132 /* Additional timesync values. */
 133 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 134 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 135 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 136 #define I40E_PRTTSYN_TSYNENA     0x80000000
 137 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 138 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 139
 140 #define I40E_MAX_PERCENT            100
 141 #define I40E_DEFAULT_DCB_APP_NUM    1
 142 #define I40E_DEFAULT_DCB_APP_PRIO   3
 143
 144 /**
 145  * Below are values for writing un-exposed registers suggested
 146  * by silicon experts
 147  */
 148 /* Destination MAC address */
 149 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 150 /* Source MAC address */
 151 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 153 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 155 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 156 /* Single VLAN tag in the inner L2 header */
 157 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 158 /* Source IPv4 address */
 159 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 160 /* Destination IPv4 address */
 161 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 162 /* Source IPv4 address for X722 */
 163 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 164 /* Destination IPv4 address for X722 */
 165 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 166 /* IPv4 Protocol for X722 */
 167 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 168 /* IPv4 Time to Live for X722 */
 169 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 170 /* IPv4 Type of Service (TOS) */
 171 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 172 /* IPv4 Protocol */
 173 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 174 /* IPv4 Time to Live */
 175 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 176 /* Source IPv6 address */
 177 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 178 /* Destination IPv6 address */
 179 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 180 /* IPv6 Traffic Class (TC) */
 181 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 182 /* IPv6 Next Header */
 183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 184 /* IPv6 Hop Limit */
 185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 186 /* Source L4 port */
 187 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 188 /* Destination L4 port */
 189 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 190 /* SCTP verification tag */
 191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 194 /* Source port of tunneling UDP */
 195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 196 /* Destination port of tunneling UDP */
 197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 198 /* UDP Tunneling ID, NVGRE/GRE key */
 199 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 200 /* Last ether type */
 201 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 202 /* Tunneling outer destination IPv4 address */
 203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 204 /* Tunneling outer destination IPv6 address */
 205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 206 /* 1st word of flex payload */
 207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 208 /* 2nd word of flex payload */
 209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 210 /* 3rd word of flex payload */
 211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 212 /* 4th word of flex payload */
 213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 214 /* 5th word of flex payload */
 215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 216 /* 6th word of flex payload */
 217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 218 /* 7th word of flex payload */
 219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 220 /* 8th word of flex payload */
 221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 222 /* all 8 words flex payload */
 223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 224 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 225
 226 #define I40E_TRANSLATE_INSET 0
 227 #define I40E_TRANSLATE_REG   1
 228
 229 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 230 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 231 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 232 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 234 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 235
 236 /* PCI offset for querying capability */
 237 #define PCI_DEV_CAP_REG            0xA4
 238 /* PCI offset for enabling/disabling Extended Tag */
 239 #define PCI_DEV_CTRL_REG           0xA8
 240 /* Bit mask of Extended Tag capability */
 241 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 242 /* Bit shift of Extended Tag enable/disable */
 243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 244 /* Bit mask of Extended Tag enable/disable */
 245 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 246
 247 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int i40e_dev_configure(struct rte_eth_dev *dev);
 250 static int i40e_dev_start(struct rte_eth_dev *dev);
 251 static void i40e_dev_stop(struct rte_eth_dev *dev);
 252 static void i40e_dev_close(struct rte_eth_dev *dev);
 253 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 254 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 255 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 256 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 257 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 258 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 259 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 260                                struct rte_eth_stats *stats);
 261 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 262                                struct rte_eth_xstat *xstats, unsigned n);
 263 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 264                                      struct rte_eth_xstat_name *xstats_names,
 265                                      unsigned limit);
 266 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 267 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 268                                             uint16_t queue_id,
 269                                             uint8_t stat_idx,
 270                                             uint8_t is_rx);
 271 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 272                                 char *fw_version, size_t fw_size);
 273 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 274                               struct rte_eth_dev_info *dev_info);
 275 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 276                                 uint16_t vlan_id,
 277                                 int on);
 278 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 279                               enum rte_vlan_type vlan_type,
 280                               uint16_t tpid);
 281 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 282 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 283                                       uint16_t queue,
 284                                       int on);
 285 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 286 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 287 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 288 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 289                               struct rte_eth_fc_conf *fc_conf);
 290 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 291                               struct rte_eth_fc_conf *fc_conf);
 292 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 293                                        struct rte_eth_pfc_conf *pfc_conf);
 294 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 295                             struct ether_addr *mac_addr,
 296                             uint32_t index,
 297                             uint32_t pool);
 298 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 299 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 300                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 301                                     uint16_t reta_size);
 302 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 303                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 304                                    uint16_t reta_size);
 305
 306 static int i40e_get_cap(struct i40e_hw *hw);
 307 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 308 static int i40e_pf_setup(struct i40e_pf *pf);
 309 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 310 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 311 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 312 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 313 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 314                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 315 static void i40e_stat_update_48(struct i40e_hw *hw,
 316                                uint32_t hireg,
 317                                uint32_t loreg,
 318                                bool offset_loaded,
 319                                uint64_t *offset,
 320                                uint64_t *stat);
 321 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 322 static void i40e_dev_interrupt_handler(void *param);
 323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 324                                 uint32_t base, uint32_t num);
 325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 327                         uint32_t base);
 328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 329                         uint16_t num);
 330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 331 static int i40e_veb_release(struct i40e_veb *veb);
 332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 333                                                 struct i40e_vsi *vsi);
 334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 336 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 337                                              struct i40e_macvlan_filter *mv_f,
 338                                              int num,
 339                                              uint16_t vlan);
 340 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 341 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 342                                     struct rte_eth_rss_conf *rss_conf);
 343 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 344                                       struct rte_eth_rss_conf *rss_conf);
 345 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 346                                         struct rte_eth_udp_tunnel *udp_tunnel);
 347 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 348                                         struct rte_eth_udp_tunnel *udp_tunnel);
 349 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 350 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 351                                 enum rte_filter_op filter_op,
 352                                 void *arg);
 353 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 354                                 enum rte_filter_type filter_type,
 355                                 enum rte_filter_op filter_op,
 356                                 void *arg);
 357 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 358                                   struct rte_eth_dcb_info *dcb_info);
 359 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 360 static void i40e_configure_registers(struct i40e_hw *hw);
 361 static void i40e_hw_init(struct rte_eth_dev *dev);
 362 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 363 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 364                         struct rte_eth_mirror_conf *mirror_conf,
 365                         uint8_t sw_id, uint8_t on);
 366 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 367
 368 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 369 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 370 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 371                                            struct timespec *timestamp,
 372                                            uint32_t flags);
 373 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 374                                            struct timespec *timestamp);
 375 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 376
 377 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 378
 379 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 380                                    struct timespec *timestamp);
 381 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 382                                     const struct timespec *timestamp);
 383
 384 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 385                                          uint16_t queue_id);
 386 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 387                                           uint16_t queue_id);
 388
 389 static int i40e_get_regs(struct rte_eth_dev *dev,
 390                          struct rte_dev_reg_info *regs);
 391
 392 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 393
 394 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 395                            struct rte_dev_eeprom_info *eeprom);
 396
 397 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 398                                       struct ether_addr *mac_addr);
 399
 400 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 401
 402 static int i40e_ethertype_filter_convert(
 403         const struct rte_eth_ethertype_filter *input,
 404         struct i40e_ethertype_filter *filter);
 405 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 406                                    struct i40e_ethertype_filter *filter);
 407
 408 static int i40e_tunnel_filter_convert(
 409         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 410         struct i40e_tunnel_filter *tunnel_filter);
 411 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 412                                 struct i40e_tunnel_filter *tunnel_filter);
 413 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 414
 415 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 416 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 417 static void i40e_filter_restore(struct i40e_pf *pf);
 418 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 419
 420 int i40e_logtype_init;
 421 int i40e_logtype_driver;
 422
 423 static const struct rte_pci_id pci_id_i40e_map[] = {
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 444         { .vendor_id = 0, /* sentinel */ },
 445 };
 446
 447 static const struct eth_dev_ops i40e_eth_dev_ops = {
 448         .dev_configure                = i40e_dev_configure,
 449         .dev_start                    = i40e_dev_start,
 450         .dev_stop                     = i40e_dev_stop,
 451         .dev_close                    = i40e_dev_close,
 452         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 453         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 454         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 455         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 456         .dev_set_link_up              = i40e_dev_set_link_up,
 457         .dev_set_link_down            = i40e_dev_set_link_down,
 458         .link_update                  = i40e_dev_link_update,
 459         .stats_get                    = i40e_dev_stats_get,
 460         .xstats_get                   = i40e_dev_xstats_get,
 461         .xstats_get_names             = i40e_dev_xstats_get_names,
 462         .stats_reset                  = i40e_dev_stats_reset,
 463         .xstats_reset                 = i40e_dev_stats_reset,
 464         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 465         .fw_version_get               = i40e_fw_version_get,
 466         .dev_infos_get                = i40e_dev_info_get,
 467         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 468         .vlan_filter_set              = i40e_vlan_filter_set,
 469         .vlan_tpid_set                = i40e_vlan_tpid_set,
 470         .vlan_offload_set             = i40e_vlan_offload_set,
 471         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 472         .vlan_pvid_set                = i40e_vlan_pvid_set,
 473         .rx_queue_start               = i40e_dev_rx_queue_start,
 474         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 475         .tx_queue_start               = i40e_dev_tx_queue_start,
 476         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 477         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 478         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 479         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 480         .rx_queue_release             = i40e_dev_rx_queue_release,
 481         .rx_queue_count               = i40e_dev_rx_queue_count,
 482         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 483         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 484         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 485         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 486         .tx_queue_release             = i40e_dev_tx_queue_release,
 487         .dev_led_on                   = i40e_dev_led_on,
 488         .dev_led_off                  = i40e_dev_led_off,
 489         .flow_ctrl_get                = i40e_flow_ctrl_get,
 490         .flow_ctrl_set                = i40e_flow_ctrl_set,
 491         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 492         .mac_addr_add                 = i40e_macaddr_add,
 493         .mac_addr_remove              = i40e_macaddr_remove,
 494         .reta_update                  = i40e_dev_rss_reta_update,
 495         .reta_query                   = i40e_dev_rss_reta_query,
 496         .rss_hash_update              = i40e_dev_rss_hash_update,
 497         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 498         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 499         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 500         .filter_ctrl                  = i40e_dev_filter_ctrl,
 501         .rxq_info_get                 = i40e_rxq_info_get,
 502         .txq_info_get                 = i40e_txq_info_get,
 503         .mirror_rule_set              = i40e_mirror_rule_set,
 504         .mirror_rule_reset            = i40e_mirror_rule_reset,
 505         .timesync_enable              = i40e_timesync_enable,
 506         .timesync_disable             = i40e_timesync_disable,
 507         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 508         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 509         .get_dcb_info                 = i40e_dev_get_dcb_info,
 510         .timesync_adjust_time         = i40e_timesync_adjust_time,
 511         .timesync_read_time           = i40e_timesync_read_time,
 512         .timesync_write_time          = i40e_timesync_write_time,
 513         .get_reg                      = i40e_get_regs,
 514         .get_eeprom_length            = i40e_get_eeprom_length,
 515         .get_eeprom                   = i40e_get_eeprom,
 516         .mac_addr_set                 = i40e_set_default_mac_addr,
 517         .mtu_set                      = i40e_dev_mtu_set,
 518         .tm_ops_get                   = i40e_tm_ops_get,
 519 };
 520
 521 /* store statistics names and its offset in stats structure */
 522 struct rte_i40e_xstats_name_off {
 523         char name[RTE_ETH_XSTATS_NAME_SIZE];
 524         unsigned offset;
 525 };
 526
 527 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 528         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 529         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 530         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 531         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 532         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 533                 rx_unknown_protocol)},
 534         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 535         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 536         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 537         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 538 };
 539
 540 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 541                 sizeof(rte_i40e_stats_strings[0]))
 542
 543 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 544         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 545                 tx_dropped_link_down)},
 546         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 547         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 548                 illegal_bytes)},
 549         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 550         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 551                 mac_local_faults)},
 552         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 553                 mac_remote_faults)},
 554         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 555                 rx_length_errors)},
 556         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 557         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 558         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 559         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 560         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 561         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_127)},
 563         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_255)},
 565         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_511)},
 567         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_1023)},
 569         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_1522)},
 571         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 572                 rx_size_big)},
 573         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 574                 rx_undersize)},
 575         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 576                 rx_oversize)},
 577         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 578                 mac_short_packet_dropped)},
 579         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 580                 rx_fragments)},
 581         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 582         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 583         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_127)},
 585         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_255)},
 587         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_511)},
 589         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_1023)},
 591         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_1522)},
 593         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 594                 tx_size_big)},
 595         {"rx_flow_director_atr_match_packets",
 596                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 597         {"rx_flow_director_sb_match_packets",
 598                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 599         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 600                 tx_lpi_status)},
 601         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 602                 rx_lpi_status)},
 603         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 604                 tx_lpi_count)},
 605         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 606                 rx_lpi_count)},
 607 };
 608
 609 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 610                 sizeof(rte_i40e_hw_port_strings[0]))
 611
 612 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 613         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 614                 priority_xon_rx)},
 615         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 616                 priority_xoff_rx)},
 617 };
 618
 619 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 620                 sizeof(rte_i40e_rxq_prio_strings[0]))
 621
 622 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 623         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xon_tx)},
 625         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 626                 priority_xoff_tx)},
 627         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 628                 priority_xon_2_xoff)},
 629 };
 630
 631 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 632                 sizeof(rte_i40e_txq_prio_strings[0]))
 633
 634 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 635         struct rte_pci_device *pci_dev)
 636 {
 637         return rte_eth_dev_pci_generic_probe(pci_dev,
 638                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 639 }
 640
 641 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 642 {
 643         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 644 }
 645
 646 static struct rte_pci_driver rte_i40e_pmd = {
 647         .id_table = pci_id_i40e_map,
 648         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 649         .probe = eth_i40e_pci_probe,
 650         .remove = eth_i40e_pci_remove,
 651 };
 652
 653 static inline int
 654 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 655                                      struct rte_eth_link *link)
 656 {
 657         struct rte_eth_link *dst = link;
 658         struct rte_eth_link *src = &(dev->data->dev_link);
 659
 660         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 661                                         *(uint64_t *)src) == 0)
 662                 return -1;
 663
 664         return 0;
 665 }
 666
 667 static inline int
 668 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 669                                       struct rte_eth_link *link)
 670 {
 671         struct rte_eth_link *dst = &(dev->data->dev_link);
 672         struct rte_eth_link *src = link;
 673
 674         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 675                                         *(uint64_t *)src) == 0)
 676                 return -1;
 677
 678         return 0;
 679 }
 680
 681 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 682 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 683 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 684
 685 #ifndef I40E_GLQF_ORT
 686 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 687 #endif
 688 #ifndef I40E_GLQF_PIT
 689 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 690 #endif
 691 #ifndef I40E_GLQF_L3_MAP
 692 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 693 #endif
 694
 695 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 696 {
 697         /*
 698          * Initialize registers for flexible payload, which should be set by NVM.
 699          * This should be removed from code once it is fixed in NVM.
 700          */
 701         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 702         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 703         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 704         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 705         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 706         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 707         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 708         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 709         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 710         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 711         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 712         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 713
 714         /* Initialize registers for parsing packet type of QinQ */
 715         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 716         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 717 }
 718
 719 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 720
 721 /*
 722  * Add a ethertype filter to drop all flow control frames transmitted
 723  * from VSIs.
 724 */
 725 static void
 726 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 727 {
 728         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 729         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 730                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 731                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 732         int ret;
 733
 734         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 735                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 736                                 pf->main_vsi_seid, 0,
 737                                 TRUE, NULL, NULL);
 738         if (ret)
 739                 PMD_INIT_LOG(ERR,
 740                         "Failed to add filter to drop flow control frames from VSIs.");
 741 }
 742
 743 static int
 744 floating_veb_list_handler(__rte_unused const char *key,
 745                           const char *floating_veb_value,
 746                           void *opaque)
 747 {
 748         int idx = 0;
 749         unsigned int count = 0;
 750         char *end = NULL;
 751         int min, max;
 752         bool *vf_floating_veb = opaque;
 753
 754         while (isblank(*floating_veb_value))
 755                 floating_veb_value++;
 756
 757         /* Reset floating VEB configuration for VFs */
 758         for (idx = 0; idx < I40E_MAX_VF; idx++)
 759                 vf_floating_veb[idx] = false;
 760
 761         min = I40E_MAX_VF;
 762         do {
 763                 while (isblank(*floating_veb_value))
 764                         floating_veb_value++;
 765                 if (*floating_veb_value == '\0')
 766                         return -1;
 767                 errno = 0;
 768                 idx = strtoul(floating_veb_value, &end, 10);
 769                 if (errno || end == NULL)
 770                         return -1;
 771                 while (isblank(*end))
 772                         end++;
 773                 if (*end == '-') {
 774                         min = idx;
 775                 } else if ((*end == ';') || (*end == '\0')) {
 776                         max = idx;
 777                         if (min == I40E_MAX_VF)
 778                                 min = idx;
 779                         if (max >= I40E_MAX_VF)
 780                                 max = I40E_MAX_VF - 1;
 781                         for (idx = min; idx <= max; idx++) {
 782                                 vf_floating_veb[idx] = true;
 783                                 count++;
 784                         }
 785                         min = I40E_MAX_VF;
 786                 } else {
 787                         return -1;
 788                 }
 789                 floating_veb_value = end + 1;
 790         } while (*end != '\0');
 791
 792         if (count == 0)
 793                 return -1;
 794
 795         return 0;
 796 }
 797
 798 static void
 799 config_vf_floating_veb(struct rte_devargs *devargs,
 800                        uint16_t floating_veb,
 801                        bool *vf_floating_veb)
 802 {
 803         struct rte_kvargs *kvlist;
 804         int i;
 805         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 806
 807         if (!floating_veb)
 808                 return;
 809         /* All the VFs attach to the floating VEB by default
 810          * when the floating VEB is enabled.
 811          */
 812         for (i = 0; i < I40E_MAX_VF; i++)
 813                 vf_floating_veb[i] = true;
 814
 815         if (devargs == NULL)
 816                 return;
 817
 818         kvlist = rte_kvargs_parse(devargs->args, NULL);
 819         if (kvlist == NULL)
 820                 return;
 821
 822         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 823                 rte_kvargs_free(kvlist);
 824                 return;
 825         }
 826         /* When the floating_veb_list parameter exists, all the VFs
 827          * will attach to the legacy VEB firstly, then configure VFs
 828          * to the floating VEB according to the floating_veb_list.
 829          */
 830         if (rte_kvargs_process(kvlist, floating_veb_list,
 831                                floating_veb_list_handler,
 832                                vf_floating_veb) < 0) {
 833                 rte_kvargs_free(kvlist);
 834                 return;
 835         }
 836         rte_kvargs_free(kvlist);
 837 }
 838
 839 static int
 840 i40e_check_floating_handler(__rte_unused const char *key,
 841                             const char *value,
 842                             __rte_unused void *opaque)
 843 {
 844         if (strcmp(value, "1"))
 845                 return -1;
 846
 847         return 0;
 848 }
 849
 850 static int
 851 is_floating_veb_supported(struct rte_devargs *devargs)
 852 {
 853         struct rte_kvargs *kvlist;
 854         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 855
 856         if (devargs == NULL)
 857                 return 0;
 858
 859         kvlist = rte_kvargs_parse(devargs->args, NULL);
 860         if (kvlist == NULL)
 861                 return 0;
 862
 863         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 864                 rte_kvargs_free(kvlist);
 865                 return 0;
 866         }
 867         /* Floating VEB is enabled when there's key-value:
 868          * enable_floating_veb=1
 869          */
 870         if (rte_kvargs_process(kvlist, floating_veb_key,
 871                                i40e_check_floating_handler, NULL) < 0) {
 872                 rte_kvargs_free(kvlist);
 873                 return 0;
 874         }
 875         rte_kvargs_free(kvlist);
 876
 877         return 1;
 878 }
 879
 880 static void
 881 config_floating_veb(struct rte_eth_dev *dev)
 882 {
 883         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 884         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 885         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 886
 887         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 888
 889         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 890                 pf->floating_veb =
 891                         is_floating_veb_supported(pci_dev->device.devargs);
 892                 config_vf_floating_veb(pci_dev->device.devargs,
 893                                        pf->floating_veb,
 894                                        pf->floating_veb_list);
 895         } else {
 896                 pf->floating_veb = false;
 897         }
 898 }
 899
 900 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 901 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 902
 903 static int
 904 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 905 {
 906         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 907         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 908         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 909         int ret;
 910
 911         struct rte_hash_parameters ethertype_hash_params = {
 912                 .name = ethertype_hash_name,
 913                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 914                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 915                 .hash_func = rte_hash_crc,
 916                 .hash_func_init_val = 0,
 917                 .socket_id = rte_socket_id(),
 918         };
 919
 920         /* Initialize ethertype filter rule list and hash */
 921         TAILQ_INIT(&ethertype_rule->ethertype_list);
 922         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 923                  "ethertype_%s", dev->device->name);
 924         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 925         if (!ethertype_rule->hash_table) {
 926                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 927                 return -EINVAL;
 928         }
 929         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 930                                        sizeof(struct i40e_ethertype_filter *) *
 931                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 932                                        0);
 933         if (!ethertype_rule->hash_map) {
 934                 PMD_INIT_LOG(ERR,
 935                              "Failed to allocate memory for ethertype hash map!");
 936                 ret = -ENOMEM;
 937                 goto err_ethertype_hash_map_alloc;
 938         }
 939
 940         return 0;
 941
 942 err_ethertype_hash_map_alloc:
 943         rte_hash_free(ethertype_rule->hash_table);
 944
 945         return ret;
 946 }
 947
 948 static int
 949 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 950 {
 951         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 952         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 953         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 954         int ret;
 955
 956         struct rte_hash_parameters tunnel_hash_params = {
 957                 .name = tunnel_hash_name,
 958                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 959                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 960                 .hash_func = rte_hash_crc,
 961                 .hash_func_init_val = 0,
 962                 .socket_id = rte_socket_id(),
 963         };
 964
 965         /* Initialize tunnel filter rule list and hash */
 966         TAILQ_INIT(&tunnel_rule->tunnel_list);
 967         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 968                  "tunnel_%s", dev->device->name);
 969         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 970         if (!tunnel_rule->hash_table) {
 971                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 972                 return -EINVAL;
 973         }
 974         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 975                                     sizeof(struct i40e_tunnel_filter *) *
 976                                     I40E_MAX_TUNNEL_FILTER_NUM,
 977                                     0);
 978         if (!tunnel_rule->hash_map) {
 979                 PMD_INIT_LOG(ERR,
 980                              "Failed to allocate memory for tunnel hash map!");
 981                 ret = -ENOMEM;
 982                 goto err_tunnel_hash_map_alloc;
 983         }
 984
 985         return 0;
 986
 987 err_tunnel_hash_map_alloc:
 988         rte_hash_free(tunnel_rule->hash_table);
 989
 990         return ret;
 991 }
 992
 993 static int
 994 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 995 {
 996         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 997         struct i40e_fdir_info *fdir_info = &pf->fdir;
 998         char fdir_hash_name[RTE_HASH_NAMESIZE];
 999         int ret;
1000
1001         struct rte_hash_parameters fdir_hash_params = {
1002                 .name = fdir_hash_name,
1003                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1004                 .key_len = sizeof(struct rte_eth_fdir_input),
1005                 .hash_func = rte_hash_crc,
1006                 .hash_func_init_val = 0,
1007                 .socket_id = rte_socket_id(),
1008         };
1009
1010         /* Initialize flow director filter rule list and hash */
1011         TAILQ_INIT(&fdir_info->fdir_list);
1012         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1013                  "fdir_%s", dev->device->name);
1014         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1015         if (!fdir_info->hash_table) {
1016                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1017                 return -EINVAL;
1018         }
1019         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1020                                           sizeof(struct i40e_fdir_filter *) *
1021                                           I40E_MAX_FDIR_FILTER_NUM,
1022                                           0);
1023         if (!fdir_info->hash_map) {
1024                 PMD_INIT_LOG(ERR,
1025                              "Failed to allocate memory for fdir hash map!");
1026                 ret = -ENOMEM;
1027                 goto err_fdir_hash_map_alloc;
1028         }
1029         return 0;
1030
1031 err_fdir_hash_map_alloc:
1032         rte_hash_free(fdir_info->hash_table);
1033
1034         return ret;
1035 }
1036
1037 static int
1038 eth_i40e_dev_init(struct rte_eth_dev *dev)
1039 {
1040         struct rte_pci_device *pci_dev;
1041         struct rte_intr_handle *intr_handle;
1042         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1043         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1044         struct i40e_vsi *vsi;
1045         int ret;
1046         uint32_t len;
1047         uint8_t aq_fail = 0;
1048
1049         PMD_INIT_FUNC_TRACE();
1050
1051         dev->dev_ops = &i40e_eth_dev_ops;
1052         dev->rx_pkt_burst = i40e_recv_pkts;
1053         dev->tx_pkt_burst = i40e_xmit_pkts;
1054         dev->tx_pkt_prepare = i40e_prep_pkts;
1055
1056         /* for secondary processes, we don't initialise any further as primary
1057          * has already done this work. Only check we don't need a different
1058          * RX function */
1059         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1060                 i40e_set_rx_function(dev);
1061                 i40e_set_tx_function(dev);
1062                 return 0;
1063         }
1064         i40e_set_default_ptype_table(dev);
1065         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1066         intr_handle = &pci_dev->intr_handle;
1067
1068         rte_eth_copy_pci_info(dev, pci_dev);
1069         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1070
1071         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1072         pf->adapter->eth_dev = dev;
1073         pf->dev_data = dev->data;
1074
1075         hw->back = I40E_PF_TO_ADAPTER(pf);
1076         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1077         if (!hw->hw_addr) {
1078                 PMD_INIT_LOG(ERR,
1079                         "Hardware is not available, as address is NULL");
1080                 return -ENODEV;
1081         }
1082
1083         hw->vendor_id = pci_dev->id.vendor_id;
1084         hw->device_id = pci_dev->id.device_id;
1085         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1086         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1087         hw->bus.device = pci_dev->addr.devid;
1088         hw->bus.func = pci_dev->addr.function;
1089         hw->adapter_stopped = 0;
1090
1091         /* Make sure all is clean before doing PF reset */
1092         i40e_clear_hw(hw);
1093
1094         /* Initialize the hardware */
1095         i40e_hw_init(dev);
1096
1097         /* Reset here to make sure all is clean for each PF */
1098         ret = i40e_pf_reset(hw);
1099         if (ret) {
1100                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1101                 return ret;
1102         }
1103
1104         /* Initialize the shared code (base driver) */
1105         ret = i40e_init_shared_code(hw);
1106         if (ret) {
1107                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1108                 return ret;
1109         }
1110
1111         /*
1112          * To work around the NVM issue, initialize registers
1113          * for flexible payload and packet type of QinQ by
1114          * software. It should be removed once issues are fixed
1115          * in NVM.
1116          */
1117         i40e_GLQF_reg_init(hw);
1118
1119         /* Initialize the input set for filters (hash and fd) to default value */
1120         i40e_filter_input_set_init(pf);
1121
1122         /* Initialize the parameters for adminq */
1123         i40e_init_adminq_parameter(hw);
1124         ret = i40e_init_adminq(hw);
1125         if (ret != I40E_SUCCESS) {
1126                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1127                 return -EIO;
1128         }
1129         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1130                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1131                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1132                      ((hw->nvm.version >> 12) & 0xf),
1133                      ((hw->nvm.version >> 4) & 0xff),
1134                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1135
1136         /* initialise the L3_MAP register */
1137         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1138                                    0x00000028,  NULL);
1139         if (ret)
1140                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1141
1142         /* Need the special FW version to support floating VEB */
1143         config_floating_veb(dev);
1144         /* Clear PXE mode */
1145         i40e_clear_pxe_mode(hw);
1146         i40e_dev_sync_phy_type(hw);
1147
1148         /*
1149          * On X710, performance number is far from the expectation on recent
1150          * firmware versions. The fix for this issue may not be integrated in
1151          * the following firmware version. So the workaround in software driver
1152          * is needed. It needs to modify the initial values of 3 internal only
1153          * registers. Note that the workaround can be removed when it is fixed
1154          * in firmware in the future.
1155          */
1156         i40e_configure_registers(hw);
1157
1158         /* Get hw capabilities */
1159         ret = i40e_get_cap(hw);
1160         if (ret != I40E_SUCCESS) {
1161                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1162                 goto err_get_capabilities;
1163         }
1164
1165         /* Initialize parameters for PF */
1166         ret = i40e_pf_parameter_init(dev);
1167         if (ret != 0) {
1168                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1169                 goto err_parameter_init;
1170         }
1171
1172         /* Initialize the queue management */
1173         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1174         if (ret < 0) {
1175                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1176                 goto err_qp_pool_init;
1177         }
1178         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1179                                 hw->func_caps.num_msix_vectors - 1);
1180         if (ret < 0) {
1181                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1182                 goto err_msix_pool_init;
1183         }
1184
1185         /* Initialize lan hmc */
1186         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1187                                 hw->func_caps.num_rx_qp, 0, 0);
1188         if (ret != I40E_SUCCESS) {
1189                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1190                 goto err_init_lan_hmc;
1191         }
1192
1193         /* Configure lan hmc */
1194         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1195         if (ret != I40E_SUCCESS) {
1196                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1197                 goto err_configure_lan_hmc;
1198         }
1199
1200         /* Get and check the mac address */
1201         i40e_get_mac_addr(hw, hw->mac.addr);
1202         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1203                 PMD_INIT_LOG(ERR, "mac address is not valid");
1204                 ret = -EIO;
1205                 goto err_get_mac_addr;
1206         }
1207         /* Copy the permanent MAC address */
1208         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1209                         (struct ether_addr *) hw->mac.perm_addr);
1210
1211         /* Disable flow control */
1212         hw->fc.requested_mode = I40E_FC_NONE;
1213         i40e_set_fc(hw, &aq_fail, TRUE);
1214
1215         /* Set the global registers with default ether type value */
1216         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1217         if (ret != I40E_SUCCESS) {
1218                 PMD_INIT_LOG(ERR,
1219                         "Failed to set the default outer VLAN ether type");
1220                 goto err_setup_pf_switch;
1221         }
1222
1223         /* PF setup, which includes VSI setup */
1224         ret = i40e_pf_setup(pf);
1225         if (ret) {
1226                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1227                 goto err_setup_pf_switch;
1228         }
1229
1230         /* reset all stats of the device, including pf and main vsi */
1231         i40e_dev_stats_reset(dev);
1232
1233         vsi = pf->main_vsi;
1234
1235         /* Disable double vlan by default */
1236         i40e_vsi_config_double_vlan(vsi, FALSE);
1237
1238         /* Disable S-TAG identification when floating_veb is disabled */
1239         if (!pf->floating_veb) {
1240                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1241                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1242                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1243                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1244                 }
1245         }
1246
1247         if (!vsi->max_macaddrs)
1248                 len = ETHER_ADDR_LEN;
1249         else
1250                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1251
1252         /* Should be after VSI initialized */
1253         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1254         if (!dev->data->mac_addrs) {
1255                 PMD_INIT_LOG(ERR,
1256                         "Failed to allocated memory for storing mac address");
1257                 goto err_mac_alloc;
1258         }
1259         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1260                                         &dev->data->mac_addrs[0]);
1261
1262         /* Init dcb to sw mode by default */
1263         ret = i40e_dcb_init_configure(dev, TRUE);
1264         if (ret != I40E_SUCCESS) {
1265                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1266                 pf->flags &= ~I40E_FLAG_DCB;
1267         }
1268         /* Update HW struct after DCB configuration */
1269         i40e_get_cap(hw);
1270
1271         /* initialize pf host driver to setup SRIOV resource if applicable */
1272         i40e_pf_host_init(dev);
1273
1274         /* register callback func to eal lib */
1275         rte_intr_callback_register(intr_handle,
1276                                    i40e_dev_interrupt_handler, dev);
1277
1278         /* configure and enable device interrupt */
1279         i40e_pf_config_irq0(hw, TRUE);
1280         i40e_pf_enable_irq0(hw);
1281
1282         /* enable uio intr after callback register */
1283         rte_intr_enable(intr_handle);
1284         /*
1285          * Add an ethertype filter to drop all flow control frames transmitted
1286          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1287          * frames to wire.
1288          */
1289         i40e_add_tx_flow_control_drop_filter(pf);
1290
1291         /* Set the max frame size to 0x2600 by default,
1292          * in case other drivers changed the default value.
1293          */
1294         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1295
1296         /* initialize mirror rule list */
1297         TAILQ_INIT(&pf->mirror_list);
1298
1299         /* initialize Traffic Manager configuration */
1300         i40e_tm_conf_init(dev);
1301
1302         ret = i40e_init_ethtype_filter_list(dev);
1303         if (ret < 0)
1304                 goto err_init_ethtype_filter_list;
1305         ret = i40e_init_tunnel_filter_list(dev);
1306         if (ret < 0)
1307                 goto err_init_tunnel_filter_list;
1308         ret = i40e_init_fdir_filter_list(dev);
1309         if (ret < 0)
1310                 goto err_init_fdir_filter_list;
1311
1312         return 0;
1313
1314 err_init_fdir_filter_list:
1315         rte_free(pf->tunnel.hash_table);
1316         rte_free(pf->tunnel.hash_map);
1317 err_init_tunnel_filter_list:
1318         rte_free(pf->ethertype.hash_table);
1319         rte_free(pf->ethertype.hash_map);
1320 err_init_ethtype_filter_list:
1321         rte_free(dev->data->mac_addrs);
1322 err_mac_alloc:
1323         i40e_vsi_release(pf->main_vsi);
1324 err_setup_pf_switch:
1325 err_get_mac_addr:
1326 err_configure_lan_hmc:
1327         (void)i40e_shutdown_lan_hmc(hw);
1328 err_init_lan_hmc:
1329         i40e_res_pool_destroy(&pf->msix_pool);
1330 err_msix_pool_init:
1331         i40e_res_pool_destroy(&pf->qp_pool);
1332 err_qp_pool_init:
1333 err_parameter_init:
1334 err_get_capabilities:
1335         (void)i40e_shutdown_adminq(hw);
1336
1337         return ret;
1338 }
1339
1340 static void
1341 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1342 {
1343         struct i40e_ethertype_filter *p_ethertype;
1344         struct i40e_ethertype_rule *ethertype_rule;
1345
1346         ethertype_rule = &pf->ethertype;
1347         /* Remove all ethertype filter rules and hash */
1348         if (ethertype_rule->hash_map)
1349                 rte_free(ethertype_rule->hash_map);
1350         if (ethertype_rule->hash_table)
1351                 rte_hash_free(ethertype_rule->hash_table);
1352
1353         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1354                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1355                              p_ethertype, rules);
1356                 rte_free(p_ethertype);
1357         }
1358 }
1359
1360 static void
1361 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1362 {
1363         struct i40e_tunnel_filter *p_tunnel;
1364         struct i40e_tunnel_rule *tunnel_rule;
1365
1366         tunnel_rule = &pf->tunnel;
1367         /* Remove all tunnel director rules and hash */
1368         if (tunnel_rule->hash_map)
1369                 rte_free(tunnel_rule->hash_map);
1370         if (tunnel_rule->hash_table)
1371                 rte_hash_free(tunnel_rule->hash_table);
1372
1373         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1374                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1375                 rte_free(p_tunnel);
1376         }
1377 }
1378
1379 static void
1380 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1381 {
1382         struct i40e_fdir_filter *p_fdir;
1383         struct i40e_fdir_info *fdir_info;
1384
1385         fdir_info = &pf->fdir;
1386         /* Remove all flow director rules and hash */
1387         if (fdir_info->hash_map)
1388                 rte_free(fdir_info->hash_map);
1389         if (fdir_info->hash_table)
1390                 rte_hash_free(fdir_info->hash_table);
1391
1392         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1393                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1394                 rte_free(p_fdir);
1395         }
1396 }
1397
1398 static int
1399 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1400 {
1401         struct i40e_pf *pf;
1402         struct rte_pci_device *pci_dev;
1403         struct rte_intr_handle *intr_handle;
1404         struct i40e_hw *hw;
1405         struct i40e_filter_control_settings settings;
1406         struct rte_flow *p_flow;
1407         int ret;
1408         uint8_t aq_fail = 0;
1409
1410         PMD_INIT_FUNC_TRACE();
1411
1412         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1413                 return 0;
1414
1415         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1416         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1417         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1418         intr_handle = &pci_dev->intr_handle;
1419
1420         if (hw->adapter_stopped == 0)
1421                 i40e_dev_close(dev);
1422
1423         dev->dev_ops = NULL;
1424         dev->rx_pkt_burst = NULL;
1425         dev->tx_pkt_burst = NULL;
1426
1427         /* Clear PXE mode */
1428         i40e_clear_pxe_mode(hw);
1429
1430         /* Unconfigure filter control */
1431         memset(&settings, 0, sizeof(settings));
1432         ret = i40e_set_filter_control(hw, &settings);
1433         if (ret)
1434                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1435                                         ret);
1436
1437         /* Disable flow control */
1438         hw->fc.requested_mode = I40E_FC_NONE;
1439         i40e_set_fc(hw, &aq_fail, TRUE);
1440
1441         /* uninitialize pf host driver */
1442         i40e_pf_host_uninit(dev);
1443
1444         rte_free(dev->data->mac_addrs);
1445         dev->data->mac_addrs = NULL;
1446
1447         /* disable uio intr before callback unregister */
1448         rte_intr_disable(intr_handle);
1449
1450         /* register callback func to eal lib */
1451         rte_intr_callback_unregister(intr_handle,
1452                                      i40e_dev_interrupt_handler, dev);
1453
1454         i40e_rm_ethtype_filter_list(pf);
1455         i40e_rm_tunnel_filter_list(pf);
1456         i40e_rm_fdir_filter_list(pf);
1457
1458         /* Remove all flows */
1459         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1460                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1461                 rte_free(p_flow);
1462         }
1463
1464         /* Remove all Traffic Manager configuration */
1465         i40e_tm_conf_uninit(dev);
1466
1467         return 0;
1468 }
1469
1470 static int
1471 i40e_dev_configure(struct rte_eth_dev *dev)
1472 {
1473         struct i40e_adapter *ad =
1474                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1475         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1476         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1477         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1478         int i, ret;
1479
1480         ret = i40e_dev_sync_phy_type(hw);
1481         if (ret)
1482                 return ret;
1483
1484         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1485          * bulk allocation or vector Rx preconditions we will reset it.
1486          */
1487         ad->rx_bulk_alloc_allowed = true;
1488         ad->rx_vec_allowed = true;
1489         ad->tx_simple_allowed = true;
1490         ad->tx_vec_allowed = true;
1491
1492         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1493                 ret = i40e_fdir_setup(pf);
1494                 if (ret != I40E_SUCCESS) {
1495                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1496                         return -ENOTSUP;
1497                 }
1498                 ret = i40e_fdir_configure(dev);
1499                 if (ret < 0) {
1500                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1501                         goto err;
1502                 }
1503         } else
1504                 i40e_fdir_teardown(pf);
1505
1506         ret = i40e_dev_init_vlan(dev);
1507         if (ret < 0)
1508                 goto err;
1509
1510         /* VMDQ setup.
1511          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1512          *  RSS setting have different requirements.
1513          *  General PMD driver call sequence are NIC init, configure,
1514          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1515          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1516          *  applicable. So, VMDQ setting has to be done before
1517          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1518          *  For RSS setting, it will try to calculate actual configured RX queue
1519          *  number, which will be available after rx_queue_setup(). dev_start()
1520          *  function is good to place RSS setup.
1521          */
1522         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1523                 ret = i40e_vmdq_setup(dev);
1524                 if (ret)
1525                         goto err;
1526         }
1527
1528         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1529                 ret = i40e_dcb_setup(dev);
1530                 if (ret) {
1531                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1532                         goto err_dcb;
1533                 }
1534         }
1535
1536         TAILQ_INIT(&pf->flow_list);
1537
1538         return 0;
1539
1540 err_dcb:
1541         /* need to release vmdq resource if exists */
1542         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1543                 i40e_vsi_release(pf->vmdq[i].vsi);
1544                 pf->vmdq[i].vsi = NULL;
1545         }
1546         rte_free(pf->vmdq);
1547         pf->vmdq = NULL;
1548 err:
1549         /* need to release fdir resource if exists */
1550         i40e_fdir_teardown(pf);
1551         return ret;
1552 }
1553
1554 void
1555 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1556 {
1557         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1558         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1559         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1560         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1561         uint16_t msix_vect = vsi->msix_intr;
1562         uint16_t i;
1563
1564         for (i = 0; i < vsi->nb_qps; i++) {
1565                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1566                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1567                 rte_wmb();
1568         }
1569
1570         if (vsi->type != I40E_VSI_SRIOV) {
1571                 if (!rte_intr_allow_others(intr_handle)) {
1572                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1573                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1574                         I40E_WRITE_REG(hw,
1575                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1576                                        0);
1577                 } else {
1578                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1579                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1580                         I40E_WRITE_REG(hw,
1581                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1582                                                        msix_vect - 1), 0);
1583                 }
1584         } else {
1585                 uint32_t reg;
1586                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1587                         vsi->user_param + (msix_vect - 1);
1588
1589                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1590                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1591         }
1592         I40E_WRITE_FLUSH(hw);
1593 }
1594
1595 static void
1596 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1597                        int base_queue, int nb_queue)
1598 {
1599         int i;
1600         uint32_t val;
1601         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1602
1603         /* Bind all RX queues to allocated MSIX interrupt */
1604         for (i = 0; i < nb_queue; i++) {
1605                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1606                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1607                         ((base_queue + i + 1) <<
1608                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1609                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1610                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1611
1612                 if (i == nb_queue - 1)
1613                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1614                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1615         }
1616
1617         /* Write first RX queue to Link list register as the head element */
1618         if (vsi->type != I40E_VSI_SRIOV) {
1619                 uint16_t interval =
1620                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1621
1622                 if (msix_vect == I40E_MISC_VEC_ID) {
1623                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1624                                        (base_queue <<
1625                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1626                                        (0x0 <<
1627                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1628                         I40E_WRITE_REG(hw,
1629                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1630                                        interval);
1631                 } else {
1632                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1633                                        (base_queue <<
1634                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1635                                        (0x0 <<
1636                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1637                         I40E_WRITE_REG(hw,
1638                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1639                                                        msix_vect - 1),
1640                                        interval);
1641                 }
1642         } else {
1643                 uint32_t reg;
1644
1645                 if (msix_vect == I40E_MISC_VEC_ID) {
1646                         I40E_WRITE_REG(hw,
1647                                        I40E_VPINT_LNKLST0(vsi->user_param),
1648                                        (base_queue <<
1649                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1650                                        (0x0 <<
1651                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1652                 } else {
1653                         /* num_msix_vectors_vf needs to minus irq0 */
1654                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1655                                 vsi->user_param + (msix_vect - 1);
1656
1657                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1658                                        (base_queue <<
1659                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1660                                        (0x0 <<
1661                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1662                 }
1663         }
1664
1665         I40E_WRITE_FLUSH(hw);
1666 }
1667
1668 void
1669 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1670 {
1671         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1672         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1673         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1674         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1675         uint16_t msix_vect = vsi->msix_intr;
1676         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1677         uint16_t queue_idx = 0;
1678         int record = 0;
1679         uint32_t val;
1680         int i;
1681
1682         for (i = 0; i < vsi->nb_qps; i++) {
1683                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1684                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1685         }
1686
1687         /* INTENA flag is not auto-cleared for interrupt */
1688         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1689         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1690                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1691                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1692         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1693
1694         /* VF bind interrupt */
1695         if (vsi->type == I40E_VSI_SRIOV) {
1696                 __vsi_queues_bind_intr(vsi, msix_vect,
1697                                        vsi->base_queue, vsi->nb_qps);
1698                 return;
1699         }
1700
1701         /* PF & VMDq bind interrupt */
1702         if (rte_intr_dp_is_en(intr_handle)) {
1703                 if (vsi->type == I40E_VSI_MAIN) {
1704                         queue_idx = 0;
1705                         record = 1;
1706                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1707                         struct i40e_vsi *main_vsi =
1708                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1709                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1710                         record = 1;
1711                 }
1712         }
1713
1714         for (i = 0; i < vsi->nb_used_qps; i++) {
1715                 if (nb_msix <= 1) {
1716                         if (!rte_intr_allow_others(intr_handle))
1717                                 /* allow to share MISC_VEC_ID */
1718                                 msix_vect = I40E_MISC_VEC_ID;
1719
1720                         /* no enough msix_vect, map all to one */
1721                         __vsi_queues_bind_intr(vsi, msix_vect,
1722                                                vsi->base_queue + i,
1723                                                vsi->nb_used_qps - i);
1724                         for (; !!record && i < vsi->nb_used_qps; i++)
1725                                 intr_handle->intr_vec[queue_idx + i] =
1726                                         msix_vect;
1727                         break;
1728                 }
1729                 /* 1:1 queue/msix_vect mapping */
1730                 __vsi_queues_bind_intr(vsi, msix_vect,
1731                                        vsi->base_queue + i, 1);
1732                 if (!!record)
1733                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1734
1735                 msix_vect++;
1736                 nb_msix--;
1737         }
1738 }
1739
1740 static void
1741 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1742 {
1743         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1744         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1745         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1746         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1747         uint16_t interval = i40e_calc_itr_interval(\
1748                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1749         uint16_t msix_intr, i;
1750
1751         if (rte_intr_allow_others(intr_handle))
1752                 for (i = 0; i < vsi->nb_msix; i++) {
1753                         msix_intr = vsi->msix_intr + i;
1754                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1755                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1756                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1757                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1758                                 (interval <<
1759                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1760                 }
1761         else
1762                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1763                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1764                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1765                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1766                                (interval <<
1767                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1768
1769         I40E_WRITE_FLUSH(hw);
1770 }
1771
1772 static void
1773 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1774 {
1775         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1776         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1777         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1778         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1779         uint16_t msix_intr, i;
1780
1781         if (rte_intr_allow_others(intr_handle))
1782                 for (i = 0; i < vsi->nb_msix; i++) {
1783                         msix_intr = vsi->msix_intr + i;
1784                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1785                                        0);
1786                 }
1787         else
1788                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1789
1790         I40E_WRITE_FLUSH(hw);
1791 }
1792
1793 static inline uint8_t
1794 i40e_parse_link_speeds(uint16_t link_speeds)
1795 {
1796         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1797
1798         if (link_speeds & ETH_LINK_SPEED_40G)
1799                 link_speed |= I40E_LINK_SPEED_40GB;
1800         if (link_speeds & ETH_LINK_SPEED_25G)
1801                 link_speed |= I40E_LINK_SPEED_25GB;
1802         if (link_speeds & ETH_LINK_SPEED_20G)
1803                 link_speed |= I40E_LINK_SPEED_20GB;
1804         if (link_speeds & ETH_LINK_SPEED_10G)
1805                 link_speed |= I40E_LINK_SPEED_10GB;
1806         if (link_speeds & ETH_LINK_SPEED_1G)
1807                 link_speed |= I40E_LINK_SPEED_1GB;
1808         if (link_speeds & ETH_LINK_SPEED_100M)
1809                 link_speed |= I40E_LINK_SPEED_100MB;
1810
1811         return link_speed;
1812 }
1813
1814 static int
1815 i40e_phy_conf_link(struct i40e_hw *hw,
1816                    uint8_t abilities,
1817                    uint8_t force_speed)
1818 {
1819         enum i40e_status_code status;
1820         struct i40e_aq_get_phy_abilities_resp phy_ab;
1821         struct i40e_aq_set_phy_config phy_conf;
1822         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1823                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1824                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1825                         I40E_AQ_PHY_FLAG_LOW_POWER;
1826         const uint8_t advt = I40E_LINK_SPEED_40GB |
1827                         I40E_LINK_SPEED_25GB |
1828                         I40E_LINK_SPEED_10GB |
1829                         I40E_LINK_SPEED_1GB |
1830                         I40E_LINK_SPEED_100MB;
1831         int ret = -ENOTSUP;
1832
1833
1834         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1835                                               NULL);
1836         if (status)
1837                 return ret;
1838
1839         memset(&phy_conf, 0, sizeof(phy_conf));
1840
1841         /* bits 0-2 use the values from get_phy_abilities_resp */
1842         abilities &= ~mask;
1843         abilities |= phy_ab.abilities & mask;
1844
1845         /* update ablities and speed */
1846         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1847                 phy_conf.link_speed = advt;
1848         else
1849                 phy_conf.link_speed = force_speed;
1850
1851         phy_conf.abilities = abilities;
1852
1853         /* use get_phy_abilities_resp value for the rest */
1854         phy_conf.phy_type = phy_ab.phy_type;
1855         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1856         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1857         phy_conf.eee_capability = phy_ab.eee_capability;
1858         phy_conf.eeer = phy_ab.eeer_val;
1859         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1860
1861         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1862                     phy_ab.abilities, phy_ab.link_speed);
1863         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1864                     phy_conf.abilities, phy_conf.link_speed);
1865
1866         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1867         if (status)
1868                 return ret;
1869
1870         return I40E_SUCCESS;
1871 }
1872
1873 static int
1874 i40e_apply_link_speed(struct rte_eth_dev *dev)
1875 {
1876         uint8_t speed;
1877         uint8_t abilities = 0;
1878         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1879         struct rte_eth_conf *conf = &dev->data->dev_conf;
1880
1881         speed = i40e_parse_link_speeds(conf->link_speeds);
1882         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1883         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1884                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1885         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1886
1887         /* Skip changing speed on 40G interfaces, FW does not support */
1888         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1889                 speed =  I40E_LINK_SPEED_UNKNOWN;
1890                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1891         }
1892
1893         return i40e_phy_conf_link(hw, abilities, speed);
1894 }
1895
1896 static int
1897 i40e_dev_start(struct rte_eth_dev *dev)
1898 {
1899         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1900         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1901         struct i40e_vsi *main_vsi = pf->main_vsi;
1902         int ret, i;
1903         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1904         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1905         uint32_t intr_vector = 0;
1906         struct i40e_vsi *vsi;
1907
1908         hw->adapter_stopped = 0;
1909
1910         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1911                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1912                              dev->data->port_id);
1913                 return -EINVAL;
1914         }
1915
1916         rte_intr_disable(intr_handle);
1917
1918         if ((rte_intr_cap_multiple(intr_handle) ||
1919              !RTE_ETH_DEV_SRIOV(dev).active) &&
1920             dev->data->dev_conf.intr_conf.rxq != 0) {
1921                 intr_vector = dev->data->nb_rx_queues;
1922                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1923                 if (ret)
1924                         return ret;
1925         }
1926
1927         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1928                 intr_handle->intr_vec =
1929                         rte_zmalloc("intr_vec",
1930                                     dev->data->nb_rx_queues * sizeof(int),
1931                                     0);
1932                 if (!intr_handle->intr_vec) {
1933                         PMD_INIT_LOG(ERR,
1934                                 "Failed to allocate %d rx_queues intr_vec",
1935                                 dev->data->nb_rx_queues);
1936                         return -ENOMEM;
1937                 }
1938         }
1939
1940         /* Initialize VSI */
1941         ret = i40e_dev_rxtx_init(pf);
1942         if (ret != I40E_SUCCESS) {
1943                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1944                 goto err_up;
1945         }
1946
1947         /* Map queues with MSIX interrupt */
1948         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1949                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1950         i40e_vsi_queues_bind_intr(main_vsi);
1951         i40e_vsi_enable_queues_intr(main_vsi);
1952
1953         /* Map VMDQ VSI queues with MSIX interrupt */
1954         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1955                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1956                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1957                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1958         }
1959
1960         /* enable FDIR MSIX interrupt */
1961         if (pf->fdir.fdir_vsi) {
1962                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1963                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1964         }
1965
1966         /* Enable all queues which have been configured */
1967         ret = i40e_dev_switch_queues(pf, TRUE);
1968         if (ret != I40E_SUCCESS) {
1969                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1970                 goto err_up;
1971         }
1972
1973         /* Enable receiving broadcast packets */
1974         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1975         if (ret != I40E_SUCCESS)
1976                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1977
1978         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1979                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1980                                                 true, NULL);
1981                 if (ret != I40E_SUCCESS)
1982                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1983         }
1984
1985         /* Enable the VLAN promiscuous mode. */
1986         if (pf->vfs) {
1987                 for (i = 0; i < pf->vf_num; i++) {
1988                         vsi = pf->vfs[i].vsi;
1989                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1990                                                      true, NULL);
1991                 }
1992         }
1993
1994         /* Apply link configure */
1995         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1996                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1997                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1998                                 ETH_LINK_SPEED_40G)) {
1999                 PMD_DRV_LOG(ERR, "Invalid link setting");
2000                 goto err_up;
2001         }
2002         ret = i40e_apply_link_speed(dev);
2003         if (I40E_SUCCESS != ret) {
2004                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2005                 goto err_up;
2006         }
2007
2008         if (!rte_intr_allow_others(intr_handle)) {
2009                 rte_intr_callback_unregister(intr_handle,
2010                                              i40e_dev_interrupt_handler,
2011                                              (void *)dev);
2012                 /* configure and enable device interrupt */
2013                 i40e_pf_config_irq0(hw, FALSE);
2014                 i40e_pf_enable_irq0(hw);
2015
2016                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2017                         PMD_INIT_LOG(INFO,
2018                                 "lsc won't enable because of no intr multiplex");
2019         } else {
2020                 ret = i40e_aq_set_phy_int_mask(hw,
2021                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2022                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2023                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2024                 if (ret != I40E_SUCCESS)
2025                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2026
2027                 /* Call get_link_info aq commond to enable/disable LSE */
2028                 i40e_dev_link_update(dev, 0);
2029         }
2030
2031         /* enable uio intr after callback register */
2032         rte_intr_enable(intr_handle);
2033
2034         i40e_filter_restore(pf);
2035
2036         if (!pf->tm_conf.committed)
2037                 PMD_DRV_LOG(WARNING,
2038                             "please call hierarchy_commit() "
2039                             "before starting the port");
2040
2041         return I40E_SUCCESS;
2042
2043 err_up:
2044         i40e_dev_switch_queues(pf, FALSE);
2045         i40e_dev_clear_queues(dev);
2046
2047         return ret;
2048 }
2049
2050 static void
2051 i40e_dev_stop(struct rte_eth_dev *dev)
2052 {
2053         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2054         struct i40e_vsi *main_vsi = pf->main_vsi;
2055         struct i40e_mirror_rule *p_mirror;
2056         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2057         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2058         int i;
2059
2060         /* Disable all queues */
2061         i40e_dev_switch_queues(pf, FALSE);
2062
2063         /* un-map queues with interrupt registers */
2064         i40e_vsi_disable_queues_intr(main_vsi);
2065         i40e_vsi_queues_unbind_intr(main_vsi);
2066
2067         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2068                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2069                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2070         }
2071
2072         if (pf->fdir.fdir_vsi) {
2073                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2074                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2075         }
2076         /* Clear all queues and release memory */
2077         i40e_dev_clear_queues(dev);
2078
2079         /* Set link down */
2080         i40e_dev_set_link_down(dev);
2081
2082         /* Remove all mirror rules */
2083         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2084                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2085                 rte_free(p_mirror);
2086         }
2087         pf->nb_mirror_rule = 0;
2088
2089         if (!rte_intr_allow_others(intr_handle))
2090                 /* resume to the default handler */
2091                 rte_intr_callback_register(intr_handle,
2092                                            i40e_dev_interrupt_handler,
2093                                            (void *)dev);
2094
2095         /* Clean datapath event and queue/vec mapping */
2096         rte_intr_efd_disable(intr_handle);
2097         if (intr_handle->intr_vec) {
2098                 rte_free(intr_handle->intr_vec);
2099                 intr_handle->intr_vec = NULL;
2100         }
2101
2102         /* reset hierarchy commit */
2103         pf->tm_conf.committed = false;
2104 }
2105
2106 static void
2107 i40e_dev_close(struct rte_eth_dev *dev)
2108 {
2109         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2110         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2111         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2112         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2113         uint32_t reg;
2114         int i;
2115
2116         PMD_INIT_FUNC_TRACE();
2117
2118         i40e_dev_stop(dev);
2119         hw->adapter_stopped = 1;
2120         i40e_dev_free_queues(dev);
2121
2122         /* Disable interrupt */
2123         i40e_pf_disable_irq0(hw);
2124         rte_intr_disable(intr_handle);
2125
2126         /* shutdown and destroy the HMC */
2127         i40e_shutdown_lan_hmc(hw);
2128
2129         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2130                 i40e_vsi_release(pf->vmdq[i].vsi);
2131                 pf->vmdq[i].vsi = NULL;
2132         }
2133         rte_free(pf->vmdq);
2134         pf->vmdq = NULL;
2135
2136         /* release all the existing VSIs and VEBs */
2137         i40e_fdir_teardown(pf);
2138         i40e_vsi_release(pf->main_vsi);
2139
2140         /* shutdown the adminq */
2141         i40e_aq_queue_shutdown(hw, true);
2142         i40e_shutdown_adminq(hw);
2143
2144         i40e_res_pool_destroy(&pf->qp_pool);
2145         i40e_res_pool_destroy(&pf->msix_pool);
2146
2147         /* force a PF reset to clean anything leftover */
2148         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2149         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2150                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2151         I40E_WRITE_FLUSH(hw);
2152 }
2153
2154 static void
2155 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2156 {
2157         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2158         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2159         struct i40e_vsi *vsi = pf->main_vsi;
2160         int status;
2161
2162         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2163                                                      true, NULL, true);
2164         if (status != I40E_SUCCESS)
2165                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2166
2167         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2168                                                         TRUE, NULL);
2169         if (status != I40E_SUCCESS)
2170                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2171
2172 }
2173
2174 static void
2175 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2176 {
2177         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2178         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2179         struct i40e_vsi *vsi = pf->main_vsi;
2180         int status;
2181
2182         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2183                                                      false, NULL, true);
2184         if (status != I40E_SUCCESS)
2185                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2186
2187         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2188                                                         false, NULL);
2189         if (status != I40E_SUCCESS)
2190                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2191 }
2192
2193 static void
2194 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2195 {
2196         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2197         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2198         struct i40e_vsi *vsi = pf->main_vsi;
2199         int ret;
2200
2201         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2202         if (ret != I40E_SUCCESS)
2203                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2204 }
2205
2206 static void
2207 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2208 {
2209         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2210         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2211         struct i40e_vsi *vsi = pf->main_vsi;
2212         int ret;
2213
2214         if (dev->data->promiscuous == 1)
2215                 return; /* must remain in all_multicast mode */
2216
2217         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2218                                 vsi->seid, FALSE, NULL);
2219         if (ret != I40E_SUCCESS)
2220                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2221 }
2222
2223 /*
2224  * Set device link up.
2225  */
2226 static int
2227 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2228 {
2229         /* re-apply link speed setting */
2230         return i40e_apply_link_speed(dev);
2231 }
2232
2233 /*
2234  * Set device link down.
2235  */
2236 static int
2237 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2238 {
2239         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2240         uint8_t abilities = 0;
2241         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2242
2243         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2244         return i40e_phy_conf_link(hw, abilities, speed);
2245 }
2246
2247 int
2248 i40e_dev_link_update(struct rte_eth_dev *dev,
2249                      int wait_to_complete)
2250 {
2251 #define CHECK_INTERVAL 100  /* 100ms */
2252 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2253         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2254         struct i40e_link_status link_status;
2255         struct rte_eth_link link, old;
2256         int status;
2257         unsigned rep_cnt = MAX_REPEAT_TIME;
2258         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2259
2260         memset(&link, 0, sizeof(link));
2261         memset(&old, 0, sizeof(old));
2262         memset(&link_status, 0, sizeof(link_status));
2263         rte_i40e_dev_atomic_read_link_status(dev, &old);
2264
2265         do {
2266                 /* Get link status information from hardware */
2267                 status = i40e_aq_get_link_info(hw, enable_lse,
2268                                                 &link_status, NULL);
2269                 if (status != I40E_SUCCESS) {
2270                         link.link_speed = ETH_SPEED_NUM_100M;
2271                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2272                         PMD_DRV_LOG(ERR, "Failed to get link info");
2273                         goto out;
2274                 }
2275
2276                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2277                 if (!wait_to_complete || link.link_status)
2278                         break;
2279
2280                 rte_delay_ms(CHECK_INTERVAL);
2281         } while (--rep_cnt);
2282
2283         if (!link.link_status)
2284                 goto out;
2285
2286         /* i40e uses full duplex only */
2287         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2288
2289         /* Parse the link status */
2290         switch (link_status.link_speed) {
2291         case I40E_LINK_SPEED_100MB:
2292                 link.link_speed = ETH_SPEED_NUM_100M;
2293                 break;
2294         case I40E_LINK_SPEED_1GB:
2295                 link.link_speed = ETH_SPEED_NUM_1G;
2296                 break;
2297         case I40E_LINK_SPEED_10GB:
2298                 link.link_speed = ETH_SPEED_NUM_10G;
2299                 break;
2300         case I40E_LINK_SPEED_20GB:
2301                 link.link_speed = ETH_SPEED_NUM_20G;
2302                 break;
2303         case I40E_LINK_SPEED_25GB:
2304                 link.link_speed = ETH_SPEED_NUM_25G;
2305                 break;
2306         case I40E_LINK_SPEED_40GB:
2307                 link.link_speed = ETH_SPEED_NUM_40G;
2308                 break;
2309         default:
2310                 link.link_speed = ETH_SPEED_NUM_100M;
2311                 break;
2312         }
2313
2314         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2315                         ETH_LINK_SPEED_FIXED);
2316
2317 out:
2318         rte_i40e_dev_atomic_write_link_status(dev, &link);
2319         if (link.link_status == old.link_status)
2320                 return -1;
2321
2322         i40e_notify_all_vfs_link_status(dev);
2323
2324         return 0;
2325 }
2326
2327 /* Get all the statistics of a VSI */
2328 void
2329 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2330 {
2331         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2332         struct i40e_eth_stats *nes = &vsi->eth_stats;
2333         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2334         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2335
2336         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2337                             vsi->offset_loaded, &oes->rx_bytes,
2338                             &nes->rx_bytes);
2339         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2340                             vsi->offset_loaded, &oes->rx_unicast,
2341                             &nes->rx_unicast);
2342         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2343                             vsi->offset_loaded, &oes->rx_multicast,
2344                             &nes->rx_multicast);
2345         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2346                             vsi->offset_loaded, &oes->rx_broadcast,
2347                             &nes->rx_broadcast);
2348         /* exclude CRC bytes */
2349         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2350                 nes->rx_broadcast) * ETHER_CRC_LEN;
2351
2352         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2353                             &oes->rx_discards, &nes->rx_discards);
2354         /* GLV_REPC not supported */
2355         /* GLV_RMPC not supported */
2356         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2357                             &oes->rx_unknown_protocol,
2358                             &nes->rx_unknown_protocol);
2359         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2360                             vsi->offset_loaded, &oes->tx_bytes,
2361                             &nes->tx_bytes);
2362         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2363                             vsi->offset_loaded, &oes->tx_unicast,
2364                             &nes->tx_unicast);
2365         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2366                             vsi->offset_loaded, &oes->tx_multicast,
2367                             &nes->tx_multicast);
2368         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2369                             vsi->offset_loaded,  &oes->tx_broadcast,
2370                             &nes->tx_broadcast);
2371         /* GLV_TDPC not supported */
2372         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2373                             &oes->tx_errors, &nes->tx_errors);
2374         vsi->offset_loaded = true;
2375
2376         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2377                     vsi->vsi_id);
2378         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2379         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2380         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2381         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2382         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2383         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2384                     nes->rx_unknown_protocol);
2385         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2386         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2387         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2388         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2389         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2390         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2391         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2392                     vsi->vsi_id);
2393 }
2394
2395 static void
2396 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2397 {
2398         unsigned int i;
2399         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2400         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2401
2402         /* Get rx/tx bytes of internal transfer packets */
2403         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2404                         I40E_GLV_GORCL(hw->port),
2405                         pf->offset_loaded,
2406                         &pf->internal_stats_offset.rx_bytes,
2407                         &pf->internal_stats.rx_bytes);
2408
2409         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2410                         I40E_GLV_GOTCL(hw->port),
2411                         pf->offset_loaded,
2412                         &pf->internal_stats_offset.tx_bytes,
2413                         &pf->internal_stats.tx_bytes);
2414         /* Get total internal rx packet count */
2415         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2416                             I40E_GLV_UPRCL(hw->port),
2417                             pf->offset_loaded,
2418                             &pf->internal_stats_offset.rx_unicast,
2419                             &pf->internal_stats.rx_unicast);
2420         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2421                             I40E_GLV_MPRCL(hw->port),
2422                             pf->offset_loaded,
2423                             &pf->internal_stats_offset.rx_multicast,
2424                             &pf->internal_stats.rx_multicast);
2425         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2426                             I40E_GLV_BPRCL(hw->port),
2427                             pf->offset_loaded,
2428                             &pf->internal_stats_offset.rx_broadcast,
2429                             &pf->internal_stats.rx_broadcast);
2430
2431         /* exclude CRC size */
2432         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2433                 pf->internal_stats.rx_multicast +
2434                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2435
2436         /* Get statistics of struct i40e_eth_stats */
2437         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2438                             I40E_GLPRT_GORCL(hw->port),
2439                             pf->offset_loaded, &os->eth.rx_bytes,
2440                             &ns->eth.rx_bytes);
2441         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2442                             I40E_GLPRT_UPRCL(hw->port),
2443                             pf->offset_loaded, &os->eth.rx_unicast,
2444                             &ns->eth.rx_unicast);
2445         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2446                             I40E_GLPRT_MPRCL(hw->port),
2447                             pf->offset_loaded, &os->eth.rx_multicast,
2448                             &ns->eth.rx_multicast);
2449         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2450                             I40E_GLPRT_BPRCL(hw->port),
2451                             pf->offset_loaded, &os->eth.rx_broadcast,
2452                             &ns->eth.rx_broadcast);
2453         /* Workaround: CRC size should not be included in byte statistics,
2454          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2455          */
2456         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2457                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2458
2459         /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2460          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2461          * value.
2462          */
2463         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2464                 ns->eth.rx_bytes = 0;
2465         /* exlude internal rx bytes */
2466         else
2467                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2468
2469         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2470                             pf->offset_loaded, &os->eth.rx_discards,
2471                             &ns->eth.rx_discards);
2472         /* GLPRT_REPC not supported */
2473         /* GLPRT_RMPC not supported */
2474         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2475                             pf->offset_loaded,
2476                             &os->eth.rx_unknown_protocol,
2477                             &ns->eth.rx_unknown_protocol);
2478         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2479                             I40E_GLPRT_GOTCL(hw->port),
2480                             pf->offset_loaded, &os->eth.tx_bytes,
2481                             &ns->eth.tx_bytes);
2482         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2483                             I40E_GLPRT_UPTCL(hw->port),
2484                             pf->offset_loaded, &os->eth.tx_unicast,
2485                             &ns->eth.tx_unicast);
2486         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2487                             I40E_GLPRT_MPTCL(hw->port),
2488                             pf->offset_loaded, &os->eth.tx_multicast,
2489                             &ns->eth.tx_multicast);
2490         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2491                             I40E_GLPRT_BPTCL(hw->port),
2492                             pf->offset_loaded, &os->eth.tx_broadcast,
2493                             &ns->eth.tx_broadcast);
2494         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2495                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2496
2497         /* exclude internal tx bytes */
2498         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2499                 ns->eth.tx_bytes = 0;
2500         else
2501                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2502
2503         /* GLPRT_TEPC not supported */
2504
2505         /* additional port specific stats */
2506         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2507                             pf->offset_loaded, &os->tx_dropped_link_down,
2508                             &ns->tx_dropped_link_down);
2509         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2510                             pf->offset_loaded, &os->crc_errors,
2511                             &ns->crc_errors);
2512         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2513                             pf->offset_loaded, &os->illegal_bytes,
2514                             &ns->illegal_bytes);
2515         /* GLPRT_ERRBC not supported */
2516         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2517                             pf->offset_loaded, &os->mac_local_faults,
2518                             &ns->mac_local_faults);
2519         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2520                             pf->offset_loaded, &os->mac_remote_faults,
2521                             &ns->mac_remote_faults);
2522         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2523                             pf->offset_loaded, &os->rx_length_errors,
2524                             &ns->rx_length_errors);
2525         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2526                             pf->offset_loaded, &os->link_xon_rx,
2527                             &ns->link_xon_rx);
2528         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2529                             pf->offset_loaded, &os->link_xoff_rx,
2530                             &ns->link_xoff_rx);
2531         for (i = 0; i < 8; i++) {
2532                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2533                                     pf->offset_loaded,
2534                                     &os->priority_xon_rx[i],
2535                                     &ns->priority_xon_rx[i]);
2536                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2537                                     pf->offset_loaded,
2538                                     &os->priority_xoff_rx[i],
2539                                     &ns->priority_xoff_rx[i]);
2540         }
2541         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2542                             pf->offset_loaded, &os->link_xon_tx,
2543                             &ns->link_xon_tx);
2544         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2545                             pf->offset_loaded, &os->link_xoff_tx,
2546                             &ns->link_xoff_tx);
2547         for (i = 0; i < 8; i++) {
2548                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2549                                     pf->offset_loaded,
2550                                     &os->priority_xon_tx[i],
2551                                     &ns->priority_xon_tx[i]);
2552                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2553                                     pf->offset_loaded,
2554                                     &os->priority_xoff_tx[i],
2555                                     &ns->priority_xoff_tx[i]);
2556                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2557                                     pf->offset_loaded,
2558                                     &os->priority_xon_2_xoff[i],
2559                                     &ns->priority_xon_2_xoff[i]);
2560         }
2561         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2562                             I40E_GLPRT_PRC64L(hw->port),
2563                             pf->offset_loaded, &os->rx_size_64,
2564                             &ns->rx_size_64);
2565         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2566                             I40E_GLPRT_PRC127L(hw->port),
2567                             pf->offset_loaded, &os->rx_size_127,
2568                             &ns->rx_size_127);
2569         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2570                             I40E_GLPRT_PRC255L(hw->port),
2571                             pf->offset_loaded, &os->rx_size_255,
2572                             &ns->rx_size_255);
2573         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2574                             I40E_GLPRT_PRC511L(hw->port),
2575                             pf->offset_loaded, &os->rx_size_511,
2576                             &ns->rx_size_511);
2577         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2578                             I40E_GLPRT_PRC1023L(hw->port),
2579                             pf->offset_loaded, &os->rx_size_1023,
2580                             &ns->rx_size_1023);
2581         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2582                             I40E_GLPRT_PRC1522L(hw->port),
2583                             pf->offset_loaded, &os->rx_size_1522,
2584                             &ns->rx_size_1522);
2585         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2586                             I40E_GLPRT_PRC9522L(hw->port),
2587                             pf->offset_loaded, &os->rx_size_big,
2588                             &ns->rx_size_big);
2589         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2590                             pf->offset_loaded, &os->rx_undersize,
2591                             &ns->rx_undersize);
2592         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2593                             pf->offset_loaded, &os->rx_fragments,
2594                             &ns->rx_fragments);
2595         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2596                             pf->offset_loaded, &os->rx_oversize,
2597                             &ns->rx_oversize);
2598         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2599                             pf->offset_loaded, &os->rx_jabber,
2600                             &ns->rx_jabber);
2601         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2602                             I40E_GLPRT_PTC64L(hw->port),
2603                             pf->offset_loaded, &os->tx_size_64,
2604                             &ns->tx_size_64);
2605         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2606                             I40E_GLPRT_PTC127L(hw->port),
2607                             pf->offset_loaded, &os->tx_size_127,
2608                             &ns->tx_size_127);
2609         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2610                             I40E_GLPRT_PTC255L(hw->port),
2611                             pf->offset_loaded, &os->tx_size_255,
2612                             &ns->tx_size_255);
2613         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2614                             I40E_GLPRT_PTC511L(hw->port),
2615                             pf->offset_loaded, &os->tx_size_511,
2616                             &ns->tx_size_511);
2617         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2618                             I40E_GLPRT_PTC1023L(hw->port),
2619                             pf->offset_loaded, &os->tx_size_1023,
2620                             &ns->tx_size_1023);
2621         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2622                             I40E_GLPRT_PTC1522L(hw->port),
2623                             pf->offset_loaded, &os->tx_size_1522,
2624                             &ns->tx_size_1522);
2625         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2626                             I40E_GLPRT_PTC9522L(hw->port),
2627                             pf->offset_loaded, &os->tx_size_big,
2628                             &ns->tx_size_big);
2629         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2630                            pf->offset_loaded,
2631                            &os->fd_sb_match, &ns->fd_sb_match);
2632         /* GLPRT_MSPDC not supported */
2633         /* GLPRT_XEC not supported */
2634
2635         pf->offset_loaded = true;
2636
2637         if (pf->main_vsi)
2638                 i40e_update_vsi_stats(pf->main_vsi);
2639 }
2640
2641 /* Get all statistics of a port */
2642 static void
2643 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2644 {
2645         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2646         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2647         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2648         unsigned i;
2649
2650         /* call read registers - updates values, now write them to struct */
2651         i40e_read_stats_registers(pf, hw);
2652
2653         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2654                         pf->main_vsi->eth_stats.rx_multicast +
2655                         pf->main_vsi->eth_stats.rx_broadcast -
2656                         pf->main_vsi->eth_stats.rx_discards;
2657         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2658                         pf->main_vsi->eth_stats.tx_multicast +
2659                         pf->main_vsi->eth_stats.tx_broadcast;
2660         stats->ibytes   = ns->eth.rx_bytes;
2661         stats->obytes   = ns->eth.tx_bytes;
2662         stats->oerrors  = ns->eth.tx_errors +
2663                         pf->main_vsi->eth_stats.tx_errors;
2664
2665         /* Rx Errors */
2666         stats->imissed  = ns->eth.rx_discards +
2667                         pf->main_vsi->eth_stats.rx_discards;
2668         stats->ierrors  = ns->crc_errors +
2669                         ns->rx_length_errors + ns->rx_undersize +
2670                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2671
2672         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2673         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2674         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2675         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2676         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2677         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2678         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2679                     ns->eth.rx_unknown_protocol);
2680         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2681         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2682         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2683         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2684         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2685         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2686
2687         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2688                     ns->tx_dropped_link_down);
2689         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2690         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2691                     ns->illegal_bytes);
2692         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2693         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2694                     ns->mac_local_faults);
2695         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2696                     ns->mac_remote_faults);
2697         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2698                     ns->rx_length_errors);
2699         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2700         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2701         for (i = 0; i < 8; i++) {
2702                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2703                                 i, ns->priority_xon_rx[i]);
2704                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2705                                 i, ns->priority_xoff_rx[i]);
2706         }
2707         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2708         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2709         for (i = 0; i < 8; i++) {
2710                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2711                                 i, ns->priority_xon_tx[i]);
2712                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2713                                 i, ns->priority_xoff_tx[i]);
2714                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2715                                 i, ns->priority_xon_2_xoff[i]);
2716         }
2717         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2718         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2719         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2720         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2721         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2722         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2723         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2724         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2725         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2726         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2727         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2728         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2729         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2730         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2731         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2732         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2733         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2734         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2735         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2736                         ns->mac_short_packet_dropped);
2737         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2738                     ns->checksum_error);
2739         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2740         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2741 }
2742
2743 /* Reset the statistics */
2744 static void
2745 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2746 {
2747         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2748         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2749
2750         /* Mark PF and VSI stats to update the offset, aka "reset" */
2751         pf->offset_loaded = false;
2752         if (pf->main_vsi)
2753                 pf->main_vsi->offset_loaded = false;
2754
2755         /* read the stats, reading current register values into offset */
2756         i40e_read_stats_registers(pf, hw);
2757 }
2758
2759 static uint32_t
2760 i40e_xstats_calc_num(void)
2761 {
2762         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2763                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2764                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2765 }
2766
2767 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2768                                      struct rte_eth_xstat_name *xstats_names,
2769                                      __rte_unused unsigned limit)
2770 {
2771         unsigned count = 0;
2772         unsigned i, prio;
2773
2774         if (xstats_names == NULL)
2775                 return i40e_xstats_calc_num();
2776
2777         /* Note: limit checked in rte_eth_xstats_names() */
2778
2779         /* Get stats from i40e_eth_stats struct */
2780         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2781                 snprintf(xstats_names[count].name,
2782                          sizeof(xstats_names[count].name),
2783                          "%s", rte_i40e_stats_strings[i].name);
2784                 count++;
2785         }
2786
2787         /* Get individiual stats from i40e_hw_port struct */
2788         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2789                 snprintf(xstats_names[count].name,
2790                         sizeof(xstats_names[count].name),
2791                          "%s", rte_i40e_hw_port_strings[i].name);
2792                 count++;
2793         }
2794
2795         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2796                 for (prio = 0; prio < 8; prio++) {
2797                         snprintf(xstats_names[count].name,
2798                                  sizeof(xstats_names[count].name),
2799                                  "rx_priority%u_%s", prio,
2800                                  rte_i40e_rxq_prio_strings[i].name);
2801                         count++;
2802                 }
2803         }
2804
2805         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2806                 for (prio = 0; prio < 8; prio++) {
2807                         snprintf(xstats_names[count].name,
2808                                  sizeof(xstats_names[count].name),
2809                                  "tx_priority%u_%s", prio,
2810                                  rte_i40e_txq_prio_strings[i].name);
2811                         count++;
2812                 }
2813         }
2814         return count;
2815 }
2816
2817 static int
2818 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2819                     unsigned n)
2820 {
2821         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2822         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2823         unsigned i, count, prio;
2824         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2825
2826         count = i40e_xstats_calc_num();
2827         if (n < count)
2828                 return count;
2829
2830         i40e_read_stats_registers(pf, hw);
2831
2832         if (xstats == NULL)
2833                 return 0;
2834
2835         count = 0;
2836
2837         /* Get stats from i40e_eth_stats struct */
2838         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2839                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2840                         rte_i40e_stats_strings[i].offset);
2841                 xstats[count].id = count;
2842                 count++;
2843         }
2844
2845         /* Get individiual stats from i40e_hw_port struct */
2846         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2847                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2848                         rte_i40e_hw_port_strings[i].offset);
2849                 xstats[count].id = count;
2850                 count++;
2851         }
2852
2853         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2854                 for (prio = 0; prio < 8; prio++) {
2855                         xstats[count].value =
2856                                 *(uint64_t *)(((char *)hw_stats) +
2857                                 rte_i40e_rxq_prio_strings[i].offset +
2858                                 (sizeof(uint64_t) * prio));
2859                         xstats[count].id = count;
2860                         count++;
2861                 }
2862         }
2863
2864         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2865                 for (prio = 0; prio < 8; prio++) {
2866                         xstats[count].value =
2867                                 *(uint64_t *)(((char *)hw_stats) +
2868                                 rte_i40e_txq_prio_strings[i].offset +
2869                                 (sizeof(uint64_t) * prio));
2870                         xstats[count].id = count;
2871                         count++;
2872                 }
2873         }
2874
2875         return count;
2876 }
2877
2878 static int
2879 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2880                                  __rte_unused uint16_t queue_id,
2881                                  __rte_unused uint8_t stat_idx,
2882                                  __rte_unused uint8_t is_rx)
2883 {
2884         PMD_INIT_FUNC_TRACE();
2885
2886         return -ENOSYS;
2887 }
2888
2889 static int
2890 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2891 {
2892         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2893         u32 full_ver;
2894         u8 ver, patch;
2895         u16 build;
2896         int ret;
2897
2898         full_ver = hw->nvm.oem_ver;
2899         ver = (u8)(full_ver >> 24);
2900         build = (u16)((full_ver >> 8) & 0xffff);
2901         patch = (u8)(full_ver & 0xff);
2902
2903         ret = snprintf(fw_version, fw_size,
2904                  "%d.%d%d 0x%08x %d.%d.%d",
2905                  ((hw->nvm.version >> 12) & 0xf),
2906                  ((hw->nvm.version >> 4) & 0xff),
2907                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2908                  ver, build, patch);
2909
2910         ret += 1; /* add the size of '\0' */
2911         if (fw_size < (u32)ret)
2912                 return ret;
2913         else
2914                 return 0;
2915 }
2916
2917 static void
2918 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2919 {
2920         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2921         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2922         struct i40e_vsi *vsi = pf->main_vsi;
2923         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2924
2925         dev_info->pci_dev = pci_dev;
2926         dev_info->max_rx_queues = vsi->nb_qps;
2927         dev_info->max_tx_queues = vsi->nb_qps;
2928         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2929         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2930         dev_info->max_mac_addrs = vsi->max_macaddrs;
2931         dev_info->max_vfs = pci_dev->max_vfs;
2932         dev_info->rx_offload_capa =
2933                 DEV_RX_OFFLOAD_VLAN_STRIP |
2934                 DEV_RX_OFFLOAD_QINQ_STRIP |
2935                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2936                 DEV_RX_OFFLOAD_UDP_CKSUM |
2937                 DEV_RX_OFFLOAD_TCP_CKSUM;
2938         dev_info->tx_offload_capa =
2939                 DEV_TX_OFFLOAD_VLAN_INSERT |
2940                 DEV_TX_OFFLOAD_QINQ_INSERT |
2941                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2942                 DEV_TX_OFFLOAD_UDP_CKSUM |
2943                 DEV_TX_OFFLOAD_TCP_CKSUM |
2944                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2945                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2946                 DEV_TX_OFFLOAD_TCP_TSO |
2947                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2948                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2949                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2950                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2951         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2952                                                 sizeof(uint32_t);
2953         dev_info->reta_size = pf->hash_lut_size;
2954         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2955
2956         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2957                 .rx_thresh = {
2958                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2959                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2960                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2961                 },
2962                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2963                 .rx_drop_en = 0,
2964         };
2965
2966         dev_info->default_txconf = (struct rte_eth_txconf) {
2967                 .tx_thresh = {
2968                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2969                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2970                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2971                 },
2972                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2973                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2974                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2975                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2976         };
2977
2978         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2979                 .nb_max = I40E_MAX_RING_DESC,
2980                 .nb_min = I40E_MIN_RING_DESC,
2981                 .nb_align = I40E_ALIGN_RING_DESC,
2982         };
2983
2984         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2985                 .nb_max = I40E_MAX_RING_DESC,
2986                 .nb_min = I40E_MIN_RING_DESC,
2987                 .nb_align = I40E_ALIGN_RING_DESC,
2988                 .nb_seg_max = I40E_TX_MAX_SEG,
2989                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2990         };
2991
2992         if (pf->flags & I40E_FLAG_VMDQ) {
2993                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2994                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2995                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2996                                                 pf->max_nb_vmdq_vsi;
2997                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2998                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2999                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3000         }
3001
3002         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3003                 /* For XL710 */
3004                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3005         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3006                 /* For XXV710 */
3007                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3008         else
3009                 /* For X710 */
3010                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3011 }
3012
3013 static int
3014 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3015 {
3016         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3017         struct i40e_vsi *vsi = pf->main_vsi;
3018         PMD_INIT_FUNC_TRACE();
3019
3020         if (on)
3021                 return i40e_vsi_add_vlan(vsi, vlan_id);
3022         else
3023                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3024 }
3025
3026 static int
3027 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3028                                 enum rte_vlan_type vlan_type,
3029                                 uint16_t tpid, int qinq)
3030 {
3031         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3032         uint64_t reg_r = 0;
3033         uint64_t reg_w = 0;
3034         uint16_t reg_id = 3;
3035         int ret;
3036
3037         if (qinq) {
3038                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3039                         reg_id = 2;
3040         }
3041
3042         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3043                                           &reg_r, NULL);
3044         if (ret != I40E_SUCCESS) {
3045                 PMD_DRV_LOG(ERR,
3046                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3047                            reg_id);
3048                 return -EIO;
3049         }
3050         PMD_DRV_LOG(DEBUG,
3051                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3052                     reg_id, reg_r);
3053
3054         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3055         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3056         if (reg_r == reg_w) {
3057                 PMD_DRV_LOG(DEBUG, "No need to write");
3058                 return 0;
3059         }
3060
3061         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3062                                            reg_w, NULL);
3063         if (ret != I40E_SUCCESS) {
3064                 PMD_DRV_LOG(ERR,
3065                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3066                             reg_id);
3067                 return -EIO;
3068         }
3069         PMD_DRV_LOG(DEBUG,
3070                     "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3071                     reg_w, reg_id);
3072
3073         return 0;
3074 }
3075
3076 static int
3077 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3078                    enum rte_vlan_type vlan_type,
3079                    uint16_t tpid)
3080 {
3081         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3082         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3083         int ret = 0;
3084
3085         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3086              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3087             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3088                 PMD_DRV_LOG(ERR,
3089                             "Unsupported vlan type.");
3090                 return -EINVAL;
3091         }
3092         /* 802.1ad frames ability is added in NVM API 1.7*/
3093         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3094                 if (qinq) {
3095                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3096                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3097                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3098                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3099                 } else {
3100                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3101                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3102                 }
3103                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3104                 if (ret != I40E_SUCCESS) {
3105                         PMD_DRV_LOG(ERR,
3106                                     "Set switch config failed aq_err: %d",
3107                                     hw->aq.asq_last_status);
3108                         ret = -EIO;
3109                 }
3110         } else
3111                 /* If NVM API < 1.7, keep the register setting */
3112                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3113                                                       tpid, qinq);
3114
3115         return ret;
3116 }
3117
3118 static void
3119 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3120 {
3121         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3122         struct i40e_vsi *vsi = pf->main_vsi;
3123
3124         if (mask & ETH_VLAN_FILTER_MASK) {
3125                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3126                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3127                 else
3128                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3129         }
3130
3131         if (mask & ETH_VLAN_STRIP_MASK) {
3132                 /* Enable or disable VLAN stripping */
3133                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3134                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3135                 else
3136                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3137         }
3138
3139         if (mask & ETH_VLAN_EXTEND_MASK) {
3140                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3141                         i40e_vsi_config_double_vlan(vsi, TRUE);
3142                         /* Set global registers with default ethertype. */
3143                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3144                                            ETHER_TYPE_VLAN);
3145                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3146                                            ETHER_TYPE_VLAN);
3147                 }
3148                 else
3149                         i40e_vsi_config_double_vlan(vsi, FALSE);
3150         }
3151 }
3152
3153 static void
3154 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3155                           __rte_unused uint16_t queue,
3156                           __rte_unused int on)
3157 {
3158         PMD_INIT_FUNC_TRACE();
3159 }
3160
3161 static int
3162 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3163 {
3164         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3165         struct i40e_vsi *vsi = pf->main_vsi;
3166         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3167         struct i40e_vsi_vlan_pvid_info info;
3168
3169         memset(&info, 0, sizeof(info));
3170         info.on = on;
3171         if (info.on)
3172                 info.config.pvid = pvid;
3173         else {
3174                 info.config.reject.tagged =
3175                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3176                 info.config.reject.untagged =
3177                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3178         }
3179
3180         return i40e_vsi_vlan_pvid_set(vsi, &info);
3181 }
3182
3183 static int
3184 i40e_dev_led_on(struct rte_eth_dev *dev)
3185 {
3186         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3187         uint32_t mode = i40e_led_get(hw);
3188
3189         if (mode == 0)
3190                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3191
3192         return 0;
3193 }
3194
3195 static int
3196 i40e_dev_led_off(struct rte_eth_dev *dev)
3197 {
3198         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3199         uint32_t mode = i40e_led_get(hw);
3200
3201         if (mode != 0)
3202                 i40e_led_set(hw, 0, false);
3203
3204         return 0;
3205 }
3206
3207 static int
3208 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3209 {
3210         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3211         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3212
3213         fc_conf->pause_time = pf->fc_conf.pause_time;
3214         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3215         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3216
3217          /* Return current mode according to actual setting*/
3218         switch (hw->fc.current_mode) {
3219         case I40E_FC_FULL:
3220                 fc_conf->mode = RTE_FC_FULL;
3221                 break;
3222         case I40E_FC_TX_PAUSE:
3223                 fc_conf->mode = RTE_FC_TX_PAUSE;
3224                 break;
3225         case I40E_FC_RX_PAUSE:
3226                 fc_conf->mode = RTE_FC_RX_PAUSE;
3227                 break;
3228         case I40E_FC_NONE:
3229         default:
3230                 fc_conf->mode = RTE_FC_NONE;
3231         };
3232
3233         return 0;
3234 }
3235
3236 static int
3237 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3238 {
3239         uint32_t mflcn_reg, fctrl_reg, reg;
3240         uint32_t max_high_water;
3241         uint8_t i, aq_failure;
3242         int err;
3243         struct i40e_hw *hw;
3244         struct i40e_pf *pf;
3245         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3246                 [RTE_FC_NONE] = I40E_FC_NONE,
3247                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3248                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3249                 [RTE_FC_FULL] = I40E_FC_FULL
3250         };
3251
3252         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3253
3254         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3255         if ((fc_conf->high_water > max_high_water) ||
3256                         (fc_conf->high_water < fc_conf->low_water)) {
3257                 PMD_INIT_LOG(ERR,
3258                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3259                         max_high_water);
3260                 return -EINVAL;
3261         }
3262
3263         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3264         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3265         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3266
3267         pf->fc_conf.pause_time = fc_conf->pause_time;
3268         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3269         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3270
3271         PMD_INIT_FUNC_TRACE();
3272
3273         /* All the link flow control related enable/disable register
3274          * configuration is handle by the F/W
3275          */
3276         err = i40e_set_fc(hw, &aq_failure, true);
3277         if (err < 0)
3278                 return -ENOSYS;
3279
3280         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3281                 /* Configure flow control refresh threshold,
3282                  * the value for stat_tx_pause_refresh_timer[8]
3283                  * is used for global pause operation.
3284                  */
3285
3286                 I40E_WRITE_REG(hw,
3287                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3288                                pf->fc_conf.pause_time);
3289
3290                 /* configure the timer value included in transmitted pause
3291                  * frame,
3292                  * the value for stat_tx_pause_quanta[8] is used for global
3293                  * pause operation
3294                  */
3295                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3296                                pf->fc_conf.pause_time);
3297
3298                 fctrl_reg = I40E_READ_REG(hw,
3299                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3300
3301                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3302                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3303                 else
3304                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3305
3306                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3307                                fctrl_reg);
3308         } else {
3309                 /* Configure pause time (2 TCs per register) */
3310                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3311                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3312                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3313
3314                 /* Configure flow control refresh threshold value */
3315                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3316                                pf->fc_conf.pause_time / 2);
3317
3318                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3319
3320                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3321                  *depending on configuration
3322                  */
3323                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3324                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3325                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3326                 } else {
3327                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3328                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3329                 }
3330
3331                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3332         }
3333
3334         /* config the water marker both based on the packets and bytes */
3335         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3336                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3337                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3338         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3339                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3340                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3341         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3342                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3343                        << I40E_KILOSHIFT);
3344         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3345                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3346                        << I40E_KILOSHIFT);
3347
3348         I40E_WRITE_FLUSH(hw);
3349
3350         return 0;
3351 }
3352
3353 static int
3354 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3355                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3356 {
3357         PMD_INIT_FUNC_TRACE();
3358
3359         return -ENOSYS;
3360 }
3361
3362 /* Add a MAC address, and update filters */
3363 static int
3364 i40e_macaddr_add(struct rte_eth_dev *dev,
3365                  struct ether_addr *mac_addr,
3366                  __rte_unused uint32_t index,
3367                  uint32_t pool)
3368 {
3369         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3370         struct i40e_mac_filter_info mac_filter;
3371         struct i40e_vsi *vsi;
3372         int ret;
3373
3374         /* If VMDQ not enabled or configured, return */
3375         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3376                           !pf->nb_cfg_vmdq_vsi)) {
3377                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3378                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3379                         pool);
3380                 return -ENOTSUP;
3381         }
3382
3383         if (pool > pf->nb_cfg_vmdq_vsi) {
3384                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3385                                 pool, pf->nb_cfg_vmdq_vsi);
3386                 return -EINVAL;
3387         }
3388
3389         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3390         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3391                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3392         else
3393                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3394
3395         if (pool == 0)
3396                 vsi = pf->main_vsi;
3397         else
3398                 vsi = pf->vmdq[pool - 1].vsi;
3399
3400         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3401         if (ret != I40E_SUCCESS) {
3402                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3403                 return -ENODEV;
3404         }
3405         return 0;
3406 }
3407
3408 /* Remove a MAC address, and update filters */
3409 static void
3410 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3411 {
3412         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3413         struct i40e_vsi *vsi;
3414         struct rte_eth_dev_data *data = dev->data;
3415         struct ether_addr *macaddr;
3416         int ret;
3417         uint32_t i;
3418         uint64_t pool_sel;
3419
3420         macaddr = &(data->mac_addrs[index]);
3421
3422         pool_sel = dev->data->mac_pool_sel[index];
3423
3424         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3425                 if (pool_sel & (1ULL << i)) {
3426                         if (i == 0)
3427                                 vsi = pf->main_vsi;
3428                         else {
3429                                 /* No VMDQ pool enabled or configured */
3430                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3431                                         (i > pf->nb_cfg_vmdq_vsi)) {
3432                                         PMD_DRV_LOG(ERR,
3433                                                 "No VMDQ pool enabled/configured");
3434                                         return;
3435                                 }
3436                                 vsi = pf->vmdq[i - 1].vsi;
3437                         }
3438                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3439
3440                         if (ret) {
3441                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3442                                 return;
3443                         }
3444                 }
3445         }
3446 }
3447
3448 /* Set perfect match or hash match of MAC and VLAN for a VF */
3449 static int
3450 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3451                  struct rte_eth_mac_filter *filter,
3452                  bool add)
3453 {
3454         struct i40e_hw *hw;
3455         struct i40e_mac_filter_info mac_filter;
3456         struct ether_addr old_mac;
3457         struct ether_addr *new_mac;
3458         struct i40e_pf_vf *vf = NULL;
3459         uint16_t vf_id;
3460         int ret;
3461
3462         if (pf == NULL) {
3463                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3464                 return -EINVAL;
3465         }
3466         hw = I40E_PF_TO_HW(pf);
3467
3468         if (filter == NULL) {
3469                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3470                 return -EINVAL;
3471         }
3472
3473         new_mac = &filter->mac_addr;
3474
3475         if (is_zero_ether_addr(new_mac)) {
3476                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3477                 return -EINVAL;
3478         }
3479
3480         vf_id = filter->dst_id;
3481
3482         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3483                 PMD_DRV_LOG(ERR, "Invalid argument.");
3484                 return -EINVAL;
3485         }
3486         vf = &pf->vfs[vf_id];
3487
3488         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3489                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3490                 return -EINVAL;
3491         }
3492
3493         if (add) {
3494                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3495                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3496                                 ETHER_ADDR_LEN);
3497                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3498                                  ETHER_ADDR_LEN);
3499
3500                 mac_filter.filter_type = filter->filter_type;
3501                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3502                 if (ret != I40E_SUCCESS) {
3503                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3504                         return -1;
3505                 }
3506                 ether_addr_copy(new_mac, &pf->dev_addr);
3507         } else {
3508                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3509                                 ETHER_ADDR_LEN);
3510                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3511                 if (ret != I40E_SUCCESS) {
3512                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3513                         return -1;
3514                 }
3515
3516                 /* Clear device address as it has been removed */
3517                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3518                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3519         }
3520
3521         return 0;
3522 }
3523
3524 /* MAC filter handle */
3525 static int
3526 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3527                 void *arg)
3528 {
3529         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3530         struct rte_eth_mac_filter *filter;
3531         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3532         int ret = I40E_NOT_SUPPORTED;
3533
3534         filter = (struct rte_eth_mac_filter *)(arg);
3535
3536         switch (filter_op) {
3537         case RTE_ETH_FILTER_NOP:
3538                 ret = I40E_SUCCESS;
3539                 break;
3540         case RTE_ETH_FILTER_ADD:
3541                 i40e_pf_disable_irq0(hw);
3542                 if (filter->is_vf)
3543                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3544                 i40e_pf_enable_irq0(hw);
3545                 break;
3546         case RTE_ETH_FILTER_DELETE:
3547                 i40e_pf_disable_irq0(hw);
3548                 if (filter->is_vf)
3549                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3550                 i40e_pf_enable_irq0(hw);
3551                 break;
3552         default:
3553                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3554                 ret = I40E_ERR_PARAM;
3555                 break;
3556         }
3557
3558         return ret;
3559 }
3560
3561 static int
3562 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3563 {
3564         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3565         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3566         int ret;
3567
3568         if (!lut)
3569                 return -EINVAL;
3570
3571         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3572                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3573                                           lut, lut_size);
3574                 if (ret) {
3575                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3576                         return ret;
3577                 }
3578         } else {
3579                 uint32_t *lut_dw = (uint32_t *)lut;
3580                 uint16_t i, lut_size_dw = lut_size / 4;
3581
3582                 for (i = 0; i < lut_size_dw; i++)
3583                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3584         }
3585
3586         return 0;
3587 }
3588
3589 static int
3590 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3591 {
3592         struct i40e_pf *pf;
3593         struct i40e_hw *hw;
3594         int ret;
3595
3596         if (!vsi || !lut)
3597                 return -EINVAL;
3598
3599         pf = I40E_VSI_TO_PF(vsi);
3600         hw = I40E_VSI_TO_HW(vsi);
3601
3602         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3603                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3604                                           lut, lut_size);
3605                 if (ret) {
3606                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3607                         return ret;
3608                 }
3609         } else {
3610                 uint32_t *lut_dw = (uint32_t *)lut;
3611                 uint16_t i, lut_size_dw = lut_size / 4;
3612
3613                 for (i = 0; i < lut_size_dw; i++)
3614                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3615                 I40E_WRITE_FLUSH(hw);
3616         }
3617
3618         return 0;
3619 }
3620
3621 static int
3622 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3623                          struct rte_eth_rss_reta_entry64 *reta_conf,
3624                          uint16_t reta_size)
3625 {
3626         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3627         uint16_t i, lut_size = pf->hash_lut_size;
3628         uint16_t idx, shift;
3629         uint8_t *lut;
3630         int ret;
3631
3632         if (reta_size != lut_size ||
3633                 reta_size > ETH_RSS_RETA_SIZE_512) {
3634                 PMD_DRV_LOG(ERR,
3635                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3636                         reta_size, lut_size);
3637                 return -EINVAL;
3638         }
3639
3640         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3641         if (!lut) {
3642                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3643                 return -ENOMEM;
3644         }
3645         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3646         if (ret)
3647                 goto out;
3648         for (i = 0; i < reta_size; i++) {
3649                 idx = i / RTE_RETA_GROUP_SIZE;
3650                 shift = i % RTE_RETA_GROUP_SIZE;
3651                 if (reta_conf[idx].mask & (1ULL << shift))
3652                         lut[i] = reta_conf[idx].reta[shift];
3653         }
3654         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3655
3656 out:
3657         rte_free(lut);
3658
3659         return ret;
3660 }
3661
3662 static int
3663 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3664                         struct rte_eth_rss_reta_entry64 *reta_conf,
3665                         uint16_t reta_size)
3666 {
3667         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3668         uint16_t i, lut_size = pf->hash_lut_size;
3669         uint16_t idx, shift;
3670         uint8_t *lut;
3671         int ret;
3672
3673         if (reta_size != lut_size ||
3674                 reta_size > ETH_RSS_RETA_SIZE_512) {
3675                 PMD_DRV_LOG(ERR,
3676                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3677                         reta_size, lut_size);
3678                 return -EINVAL;
3679         }
3680
3681         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3682         if (!lut) {
3683                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3684                 return -ENOMEM;
3685         }
3686
3687         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3688         if (ret)
3689                 goto out;
3690         for (i = 0; i < reta_size; i++) {
3691                 idx = i / RTE_RETA_GROUP_SIZE;
3692                 shift = i % RTE_RETA_GROUP_SIZE;
3693                 if (reta_conf[idx].mask & (1ULL << shift))
3694                         reta_conf[idx].reta[shift] = lut[i];
3695         }
3696
3697 out:
3698         rte_free(lut);
3699
3700         return ret;
3701 }
3702
3703 /**
3704  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3705  * @hw:   pointer to the HW structure
3706  * @mem:  pointer to mem struct to fill out
3707  * @size: size of memory requested
3708  * @alignment: what to align the allocation to
3709  **/
3710 enum i40e_status_code
3711 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3712                         struct i40e_dma_mem *mem,
3713                         u64 size,
3714                         u32 alignment)
3715 {
3716         const struct rte_memzone *mz = NULL;
3717         char z_name[RTE_MEMZONE_NAMESIZE];
3718
3719         if (!mem)
3720                 return I40E_ERR_PARAM;
3721
3722         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3723         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3724                                          alignment, RTE_PGSIZE_2M);
3725         if (!mz)
3726                 return I40E_ERR_NO_MEMORY;
3727
3728         mem->size = size;
3729         mem->va = mz->addr;
3730         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3731         mem->zone = (const void *)mz;
3732         PMD_DRV_LOG(DEBUG,
3733                 "memzone %s allocated with physical address: %"PRIu64,
3734                 mz->name, mem->pa);
3735
3736         return I40E_SUCCESS;
3737 }
3738
3739 /**
3740  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3741  * @hw:   pointer to the HW structure
3742  * @mem:  ptr to mem struct to free
3743  **/
3744 enum i40e_status_code
3745 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3746                     struct i40e_dma_mem *mem)
3747 {
3748         if (!mem)
3749                 return I40E_ERR_PARAM;
3750
3751         PMD_DRV_LOG(DEBUG,
3752                 "memzone %s to be freed with physical address: %"PRIu64,
3753                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3754         rte_memzone_free((const struct rte_memzone *)mem->zone);
3755         mem->zone = NULL;
3756         mem->va = NULL;
3757         mem->pa = (u64)0;
3758
3759         return I40E_SUCCESS;
3760 }
3761
3762 /**
3763  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3764  * @hw:   pointer to the HW structure
3765  * @mem:  pointer to mem struct to fill out
3766  * @size: size of memory requested
3767  **/
3768 enum i40e_status_code
3769 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3770                          struct i40e_virt_mem *mem,
3771                          u32 size)
3772 {
3773         if (!mem)
3774                 return I40E_ERR_PARAM;
3775
3776         mem->size = size;
3777         mem->va = rte_zmalloc("i40e", size, 0);
3778
3779         if (mem->va)
3780                 return I40E_SUCCESS;
3781         else
3782                 return I40E_ERR_NO_MEMORY;
3783 }
3784
3785 /**
3786  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3787  * @hw:   pointer to the HW structure
3788  * @mem:  pointer to mem struct to free
3789  **/
3790 enum i40e_status_code
3791 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3792                      struct i40e_virt_mem *mem)
3793 {
3794         if (!mem)
3795                 return I40E_ERR_PARAM;
3796
3797         rte_free(mem->va);
3798         mem->va = NULL;
3799
3800         return I40E_SUCCESS;
3801 }
3802
3803 void
3804 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3805 {
3806         rte_spinlock_init(&sp->spinlock);
3807 }
3808
3809 void
3810 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3811 {
3812         rte_spinlock_lock(&sp->spinlock);
3813 }
3814
3815 void
3816 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3817 {
3818         rte_spinlock_unlock(&sp->spinlock);
3819 }
3820
3821 void
3822 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3823 {
3824         return;
3825 }
3826
3827 /**
3828  * Get the hardware capabilities, which will be parsed
3829  * and saved into struct i40e_hw.
3830  */
3831 static int
3832 i40e_get_cap(struct i40e_hw *hw)
3833 {
3834         struct i40e_aqc_list_capabilities_element_resp *buf;
3835         uint16_t len, size = 0;
3836         int ret;
3837
3838         /* Calculate a huge enough buff for saving response data temporarily */
3839         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3840                                                 I40E_MAX_CAP_ELE_NUM;
3841         buf = rte_zmalloc("i40e", len, 0);
3842         if (!buf) {
3843                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3844                 return I40E_ERR_NO_MEMORY;
3845         }
3846
3847         /* Get, parse the capabilities and save it to hw */
3848         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3849                         i40e_aqc_opc_list_func_capabilities, NULL);
3850         if (ret != I40E_SUCCESS)
3851                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3852
3853         /* Free the temporary buffer after being used */
3854         rte_free(buf);
3855
3856         return ret;
3857 }
3858
3859 static int
3860 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3861 {
3862         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3863         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3864         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3865         uint16_t qp_count = 0, vsi_count = 0;
3866
3867         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3868                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3869                 return -EINVAL;
3870         }
3871         /* Add the parameter init for LFC */
3872         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3873         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3874         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3875
3876         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3877         pf->max_num_vsi = hw->func_caps.num_vsis;
3878         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3879         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3880         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3881
3882         /* FDir queue/VSI allocation */
3883         pf->fdir_qp_offset = 0;
3884         if (hw->func_caps.fd) {
3885                 pf->flags |= I40E_FLAG_FDIR;
3886                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3887         } else {
3888                 pf->fdir_nb_qps = 0;
3889         }
3890         qp_count += pf->fdir_nb_qps;
3891         vsi_count += 1;
3892
3893         /* LAN queue/VSI allocation */
3894         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3895         if (!hw->func_caps.rss) {
3896                 pf->lan_nb_qps = 1;
3897         } else {
3898                 pf->flags |= I40E_FLAG_RSS;
3899                 if (hw->mac.type == I40E_MAC_X722)
3900                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3901                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3902         }
3903         qp_count += pf->lan_nb_qps;
3904         vsi_count += 1;
3905
3906         /* VF queue/VSI allocation */
3907         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3908         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3909                 pf->flags |= I40E_FLAG_SRIOV;
3910                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3911                 pf->vf_num = pci_dev->max_vfs;
3912                 PMD_DRV_LOG(DEBUG,
3913                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3914                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3915         } else {
3916                 pf->vf_nb_qps = 0;
3917                 pf->vf_num = 0;
3918         }
3919         qp_count += pf->vf_nb_qps * pf->vf_num;
3920         vsi_count += pf->vf_num;
3921
3922         /* VMDq queue/VSI allocation */
3923         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3924         pf->vmdq_nb_qps = 0;
3925         pf->max_nb_vmdq_vsi = 0;
3926         if (hw->func_caps.vmdq) {
3927                 if (qp_count < hw->func_caps.num_tx_qp &&
3928                         vsi_count < hw->func_caps.num_vsis) {
3929                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3930                                 qp_count) / pf->vmdq_nb_qp_max;
3931
3932                         /* Limit the maximum number of VMDq vsi to the maximum
3933                          * ethdev can support
3934                          */
3935                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3936                                 hw->func_caps.num_vsis - vsi_count);
3937                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3938                                 ETH_64_POOLS);
3939                         if (pf->max_nb_vmdq_vsi) {
3940                                 pf->flags |= I40E_FLAG_VMDQ;
3941                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3942                                 PMD_DRV_LOG(DEBUG,
3943                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3944                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3945                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3946                         } else {
3947                                 PMD_DRV_LOG(INFO,
3948                                         "No enough queues left for VMDq");
3949                         }
3950                 } else {
3951                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3952                 }
3953         }
3954         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3955         vsi_count += pf->max_nb_vmdq_vsi;
3956
3957         if (hw->func_caps.dcb)
3958                 pf->flags |= I40E_FLAG_DCB;
3959
3960         if (qp_count > hw->func_caps.num_tx_qp) {
3961                 PMD_DRV_LOG(ERR,
3962                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3963                         qp_count, hw->func_caps.num_tx_qp);
3964                 return -EINVAL;
3965         }
3966         if (vsi_count > hw->func_caps.num_vsis) {
3967                 PMD_DRV_LOG(ERR,
3968                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3969                         vsi_count, hw->func_caps.num_vsis);
3970                 return -EINVAL;
3971         }
3972
3973         return 0;
3974 }
3975
3976 static int
3977 i40e_pf_get_switch_config(struct i40e_pf *pf)
3978 {
3979         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3980         struct i40e_aqc_get_switch_config_resp *switch_config;
3981         struct i40e_aqc_switch_config_element_resp *element;
3982         uint16_t start_seid = 0, num_reported;
3983         int ret;
3984
3985         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3986                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3987         if (!switch_config) {
3988                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3989                 return -ENOMEM;
3990         }
3991
3992         /* Get the switch configurations */
3993         ret = i40e_aq_get_switch_config(hw, switch_config,
3994                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3995         if (ret != I40E_SUCCESS) {
3996                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3997                 goto fail;
3998         }
3999         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4000         if (num_reported != 1) { /* The number should be 1 */
4001                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4002                 goto fail;
4003         }
4004
4005         /* Parse the switch configuration elements */
4006         element = &(switch_config->element[0]);
4007         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4008                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4009                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4010         } else
4011                 PMD_DRV_LOG(INFO, "Unknown element type");
4012
4013 fail:
4014         rte_free(switch_config);
4015
4016         return ret;
4017 }
4018
4019 static int
4020 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4021                         uint32_t num)
4022 {
4023         struct pool_entry *entry;
4024
4025         if (pool == NULL || num == 0)
4026                 return -EINVAL;
4027
4028         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4029         if (entry == NULL) {
4030                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4031                 return -ENOMEM;
4032         }
4033
4034         /* queue heap initialize */
4035         pool->num_free = num;
4036         pool->num_alloc = 0;
4037         pool->base = base;
4038         LIST_INIT(&pool->alloc_list);
4039         LIST_INIT(&pool->free_list);
4040
4041         /* Initialize element  */
4042         entry->base = 0;
4043         entry->len = num;
4044
4045         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4046         return 0;
4047 }
4048
4049 static void
4050 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4051 {
4052         struct pool_entry *entry, *next_entry;
4053
4054         if (pool == NULL)
4055                 return;
4056
4057         for (entry = LIST_FIRST(&pool->alloc_list);
4058                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4059                         entry = next_entry) {
4060                 LIST_REMOVE(entry, next);
4061                 rte_free(entry);
4062         }
4063
4064         for (entry = LIST_FIRST(&pool->free_list);
4065                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4066                         entry = next_entry) {
4067                 LIST_REMOVE(entry, next);
4068                 rte_free(entry);
4069         }
4070
4071         pool->num_free = 0;
4072         pool->num_alloc = 0;
4073         pool->base = 0;
4074         LIST_INIT(&pool->alloc_list);
4075         LIST_INIT(&pool->free_list);
4076 }
4077
4078 static int
4079 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4080                        uint32_t base)
4081 {
4082         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4083         uint32_t pool_offset;
4084         int insert;
4085
4086         if (pool == NULL) {
4087                 PMD_DRV_LOG(ERR, "Invalid parameter");
4088                 return -EINVAL;
4089         }
4090
4091         pool_offset = base - pool->base;
4092         /* Lookup in alloc list */
4093         LIST_FOREACH(entry, &pool->alloc_list, next) {
4094                 if (entry->base == pool_offset) {
4095                         valid_entry = entry;
4096                         LIST_REMOVE(entry, next);
4097                         break;
4098                 }
4099         }
4100
4101         /* Not find, return */
4102         if (valid_entry == NULL) {
4103                 PMD_DRV_LOG(ERR, "Failed to find entry");
4104                 return -EINVAL;
4105         }
4106
4107         /**
4108          * Found it, move it to free list  and try to merge.
4109          * In order to make merge easier, always sort it by qbase.
4110          * Find adjacent prev and last entries.
4111          */
4112         prev = next = NULL;
4113         LIST_FOREACH(entry, &pool->free_list, next) {
4114                 if (entry->base > valid_entry->base) {
4115                         next = entry;
4116                         break;
4117                 }
4118                 prev = entry;
4119         }
4120
4121         insert = 0;
4122         /* Try to merge with next one*/
4123         if (next != NULL) {
4124                 /* Merge with next one */
4125                 if (valid_entry->base + valid_entry->len == next->base) {
4126                         next->base = valid_entry->base;
4127                         next->len += valid_entry->len;
4128                         rte_free(valid_entry);
4129                         valid_entry = next;
4130                         insert = 1;
4131                 }
4132         }
4133
4134         if (prev != NULL) {
4135                 /* Merge with previous one */
4136                 if (prev->base + prev->len == valid_entry->base) {
4137                         prev->len += valid_entry->len;
4138                         /* If it merge with next one, remove next node */
4139                         if (insert == 1) {
4140                                 LIST_REMOVE(valid_entry, next);
4141                                 rte_free(valid_entry);
4142                         } else {
4143                                 rte_free(valid_entry);
4144                                 insert = 1;
4145                         }
4146                 }
4147         }
4148
4149         /* Not find any entry to merge, insert */
4150         if (insert == 0) {
4151                 if (prev != NULL)
4152                         LIST_INSERT_AFTER(prev, valid_entry, next);
4153                 else if (next != NULL)
4154                         LIST_INSERT_BEFORE(next, valid_entry, next);
4155                 else /* It's empty list, insert to head */
4156                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4157         }
4158
4159         pool->num_free += valid_entry->len;
4160         pool->num_alloc -= valid_entry->len;
4161
4162         return 0;
4163 }
4164
4165 static int
4166 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4167                        uint16_t num)
4168 {
4169         struct pool_entry *entry, *valid_entry;
4170
4171         if (pool == NULL || num == 0) {
4172                 PMD_DRV_LOG(ERR, "Invalid parameter");
4173                 return -EINVAL;
4174         }
4175
4176         if (pool->num_free < num) {
4177                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4178                             num, pool->num_free);
4179                 return -ENOMEM;
4180         }
4181
4182         valid_entry = NULL;
4183         /* Lookup  in free list and find most fit one */
4184         LIST_FOREACH(entry, &pool->free_list, next) {
4185                 if (entry->len >= num) {
4186                         /* Find best one */
4187                         if (entry->len == num) {
4188                                 valid_entry = entry;
4189                                 break;
4190                         }
4191                         if (valid_entry == NULL || valid_entry->len > entry->len)
4192                                 valid_entry = entry;
4193                 }
4194         }
4195
4196         /* Not find one to satisfy the request, return */
4197         if (valid_entry == NULL) {
4198                 PMD_DRV_LOG(ERR, "No valid entry found");
4199                 return -ENOMEM;
4200         }
4201         /**
4202          * The entry have equal queue number as requested,
4203          * remove it from alloc_list.
4204          */
4205         if (valid_entry->len == num) {
4206                 LIST_REMOVE(valid_entry, next);
4207         } else {
4208                 /**
4209                  * The entry have more numbers than requested,
4210                  * create a new entry for alloc_list and minus its
4211                  * queue base and number in free_list.
4212                  */
4213                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4214                 if (entry == NULL) {
4215                         PMD_DRV_LOG(ERR,
4216                                 "Failed to allocate memory for resource pool");
4217                         return -ENOMEM;
4218                 }
4219                 entry->base = valid_entry->base;
4220                 entry->len = num;
4221                 valid_entry->base += num;
4222                 valid_entry->len -= num;
4223                 valid_entry = entry;
4224         }
4225
4226         /* Insert it into alloc list, not sorted */
4227         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4228
4229         pool->num_free -= valid_entry->len;
4230         pool->num_alloc += valid_entry->len;
4231
4232         return valid_entry->base + pool->base;
4233 }
4234
4235 /**
4236  * bitmap_is_subset - Check whether src2 is subset of src1
4237  **/
4238 static inline int
4239 bitmap_is_subset(uint8_t src1, uint8_t src2)
4240 {
4241         return !((src1 ^ src2) & src2);
4242 }
4243
4244 static enum i40e_status_code
4245 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4246 {
4247         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4248
4249         /* If DCB is not supported, only default TC is supported */
4250         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4251                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4252                 return I40E_NOT_SUPPORTED;
4253         }
4254
4255         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4256                 PMD_DRV_LOG(ERR,
4257                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4258                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4259                 return I40E_NOT_SUPPORTED;
4260         }
4261         return I40E_SUCCESS;
4262 }
4263
4264 int
4265 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4266                                 struct i40e_vsi_vlan_pvid_info *info)
4267 {
4268         struct i40e_hw *hw;
4269         struct i40e_vsi_context ctxt;
4270         uint8_t vlan_flags = 0;
4271         int ret;
4272
4273         if (vsi == NULL || info == NULL) {
4274                 PMD_DRV_LOG(ERR, "invalid parameters");
4275                 return I40E_ERR_PARAM;
4276         }
4277
4278         if (info->on) {
4279                 vsi->info.pvid = info->config.pvid;
4280                 /**
4281                  * If insert pvid is enabled, only tagged pkts are
4282                  * allowed to be sent out.
4283                  */
4284                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4285                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4286         } else {
4287                 vsi->info.pvid = 0;
4288                 if (info->config.reject.tagged == 0)
4289                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4290
4291                 if (info->config.reject.untagged == 0)
4292                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4293         }
4294         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4295                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4296         vsi->info.port_vlan_flags |= vlan_flags;
4297         vsi->info.valid_sections =
4298                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4299         memset(&ctxt, 0, sizeof(ctxt));
4300         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4301         ctxt.seid = vsi->seid;
4302
4303         hw = I40E_VSI_TO_HW(vsi);
4304         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4305         if (ret != I40E_SUCCESS)
4306                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4307
4308         return ret;
4309 }
4310
4311 static int
4312 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4313 {
4314         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4315         int i, ret;
4316         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4317
4318         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4319         if (ret != I40E_SUCCESS)
4320                 return ret;
4321
4322         if (!vsi->seid) {
4323                 PMD_DRV_LOG(ERR, "seid not valid");
4324                 return -EINVAL;
4325         }
4326
4327         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4328         tc_bw_data.tc_valid_bits = enabled_tcmap;
4329         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4330                 tc_bw_data.tc_bw_credits[i] =
4331                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4332
4333         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4334         if (ret != I40E_SUCCESS) {
4335                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4336                 return ret;
4337         }
4338
4339         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4340                                         sizeof(vsi->info.qs_handle));
4341         return I40E_SUCCESS;
4342 }
4343
4344 static enum i40e_status_code
4345 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4346                                  struct i40e_aqc_vsi_properties_data *info,
4347                                  uint8_t enabled_tcmap)
4348 {
4349         enum i40e_status_code ret;
4350         int i, total_tc = 0;
4351         uint16_t qpnum_per_tc, bsf, qp_idx;
4352
4353         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4354         if (ret != I40E_SUCCESS)
4355                 return ret;
4356
4357         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4358                 if (enabled_tcmap & (1 << i))
4359                         total_tc++;
4360         if (total_tc == 0)
4361                 total_tc = 1;
4362         vsi->enabled_tc = enabled_tcmap;
4363
4364         /* Number of queues per enabled TC */
4365         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4366         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4367         bsf = rte_bsf32(qpnum_per_tc);
4368
4369         /* Adjust the queue number to actual queues that can be applied */
4370         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4371                 vsi->nb_qps = qpnum_per_tc * total_tc;
4372
4373         /**
4374          * Configure TC and queue mapping parameters, for enabled TC,
4375          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4376          * default queue will serve it.
4377          */
4378         qp_idx = 0;
4379         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4380                 if (vsi->enabled_tc & (1 << i)) {
4381                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4382                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4383                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4384                         qp_idx += qpnum_per_tc;
4385                 } else
4386                         info->tc_mapping[i] = 0;
4387         }
4388
4389         /* Associate queue number with VSI */
4390         if (vsi->type == I40E_VSI_SRIOV) {
4391                 info->mapping_flags |=
4392                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4393                 for (i = 0; i < vsi->nb_qps; i++)
4394                         info->queue_mapping[i] =
4395                                 rte_cpu_to_le_16(vsi->base_queue + i);
4396         } else {
4397                 info->mapping_flags |=
4398                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4399                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4400         }
4401         info->valid_sections |=
4402                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4403
4404         return I40E_SUCCESS;
4405 }
4406
4407 static int
4408 i40e_veb_release(struct i40e_veb *veb)
4409 {
4410         struct i40e_vsi *vsi;
4411         struct i40e_hw *hw;
4412
4413         if (veb == NULL)
4414                 return -EINVAL;
4415
4416         if (!TAILQ_EMPTY(&veb->head)) {
4417                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4418                 return -EACCES;
4419         }
4420         /* associate_vsi field is NULL for floating VEB */
4421         if (veb->associate_vsi != NULL) {
4422                 vsi = veb->associate_vsi;
4423                 hw = I40E_VSI_TO_HW(vsi);
4424
4425                 vsi->uplink_seid = veb->uplink_seid;
4426                 vsi->veb = NULL;
4427         } else {
4428                 veb->associate_pf->main_vsi->floating_veb = NULL;
4429                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4430         }
4431
4432         i40e_aq_delete_element(hw, veb->seid, NULL);
4433         rte_free(veb);
4434         return I40E_SUCCESS;
4435 }
4436
4437 /* Setup a veb */
4438 static struct i40e_veb *
4439 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4440 {
4441         struct i40e_veb *veb;
4442         int ret;
4443         struct i40e_hw *hw;
4444
4445         if (pf == NULL) {
4446                 PMD_DRV_LOG(ERR,
4447                             "veb setup failed, associated PF shouldn't null");
4448                 return NULL;
4449         }
4450         hw = I40E_PF_TO_HW(pf);
4451
4452         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4453         if (!veb) {
4454                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4455                 goto fail;
4456         }
4457
4458         veb->associate_vsi = vsi;
4459         veb->associate_pf = pf;
4460         TAILQ_INIT(&veb->head);
4461         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4462
4463         /* create floating veb if vsi is NULL */
4464         if (vsi != NULL) {
4465                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4466                                       I40E_DEFAULT_TCMAP, false,
4467                                       &veb->seid, false, NULL);
4468         } else {
4469                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4470                                       true, &veb->seid, false, NULL);
4471         }
4472
4473         if (ret != I40E_SUCCESS) {
4474                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4475                             hw->aq.asq_last_status);
4476                 goto fail;
4477         }
4478         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4479
4480         /* get statistics index */
4481         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4482                                 &veb->stats_idx, NULL, NULL, NULL);
4483         if (ret != I40E_SUCCESS) {
4484                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4485                             hw->aq.asq_last_status);
4486                 goto fail;
4487         }
4488         /* Get VEB bandwidth, to be implemented */
4489         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4490         if (vsi)
4491                 vsi->uplink_seid = veb->seid;
4492
4493         return veb;
4494 fail:
4495         rte_free(veb);
4496         return NULL;
4497 }
4498
4499 int
4500 i40e_vsi_release(struct i40e_vsi *vsi)
4501 {
4502         struct i40e_pf *pf;
4503         struct i40e_hw *hw;
4504         struct i40e_vsi_list *vsi_list;
4505         void *temp;
4506         int ret;
4507         struct i40e_mac_filter *f;
4508         uint16_t user_param;
4509
4510         if (!vsi)
4511                 return I40E_SUCCESS;
4512
4513         if (!vsi->adapter)
4514                 return -EFAULT;
4515
4516         user_param = vsi->user_param;
4517
4518         pf = I40E_VSI_TO_PF(vsi);
4519         hw = I40E_VSI_TO_HW(vsi);
4520
4521         /* VSI has child to attach, release child first */
4522         if (vsi->veb) {
4523                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4524                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4525                                 return -1;
4526                 }
4527                 i40e_veb_release(vsi->veb);
4528         }
4529
4530         if (vsi->floating_veb) {
4531                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4532                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4533                                 return -1;
4534                 }
4535         }
4536
4537         /* Remove all macvlan filters of the VSI */
4538         i40e_vsi_remove_all_macvlan_filter(vsi);
4539         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4540                 rte_free(f);
4541
4542         if (vsi->type != I40E_VSI_MAIN &&
4543             ((vsi->type != I40E_VSI_SRIOV) ||
4544             !pf->floating_veb_list[user_param])) {
4545                 /* Remove vsi from parent's sibling list */
4546                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4547                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4548                         return I40E_ERR_PARAM;
4549                 }
4550                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4551                                 &vsi->sib_vsi_list, list);
4552
4553                 /* Remove all switch element of the VSI */
4554                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4555                 if (ret != I40E_SUCCESS)
4556                         PMD_DRV_LOG(ERR, "Failed to delete element");
4557         }
4558
4559         if ((vsi->type == I40E_VSI_SRIOV) &&
4560             pf->floating_veb_list[user_param]) {
4561                 /* Remove vsi from parent's sibling list */
4562                 if (vsi->parent_vsi == NULL ||
4563                     vsi->parent_vsi->floating_veb == NULL) {
4564                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4565                         return I40E_ERR_PARAM;
4566                 }
4567                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4568                              &vsi->sib_vsi_list, list);
4569
4570                 /* Remove all switch element of the VSI */
4571                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4572                 if (ret != I40E_SUCCESS)
4573                         PMD_DRV_LOG(ERR, "Failed to delete element");
4574         }
4575
4576         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4577
4578         if (vsi->type != I40E_VSI_SRIOV)
4579                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4580         rte_free(vsi);
4581
4582         return I40E_SUCCESS;
4583 }
4584
4585 static int
4586 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4587 {
4588         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4589         struct i40e_aqc_remove_macvlan_element_data def_filter;
4590         struct i40e_mac_filter_info filter;
4591         int ret;
4592
4593         if (vsi->type != I40E_VSI_MAIN)
4594                 return I40E_ERR_CONFIG;
4595         memset(&def_filter, 0, sizeof(def_filter));
4596         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4597                                         ETH_ADDR_LEN);
4598         def_filter.vlan_tag = 0;
4599         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4600                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4601         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4602         if (ret != I40E_SUCCESS) {
4603                 struct i40e_mac_filter *f;
4604                 struct ether_addr *mac;
4605
4606                 PMD_DRV_LOG(DEBUG,
4607                             "Cannot remove the default macvlan filter");
4608                 /* It needs to add the permanent mac into mac list */
4609                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4610                 if (f == NULL) {
4611                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4612                         return I40E_ERR_NO_MEMORY;
4613                 }
4614                 mac = &f->mac_info.mac_addr;
4615                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4616                                 ETH_ADDR_LEN);
4617                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4618                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4619                 vsi->mac_num++;
4620
4621                 return ret;
4622         }
4623         (void)rte_memcpy(&filter.mac_addr,
4624                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4625         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4626         return i40e_vsi_add_mac(vsi, &filter);
4627 }
4628
4629 /*
4630  * i40e_vsi_get_bw_config - Query VSI BW Information
4631  * @vsi: the VSI to be queried
4632  *
4633  * Returns 0 on success, negative value on failure
4634  */
4635 static enum i40e_status_code
4636 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4637 {
4638         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4639         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4640         struct i40e_hw *hw = &vsi->adapter->hw;
4641         i40e_status ret;
4642         int i;
4643         uint32_t bw_max;
4644
4645         memset(&bw_config, 0, sizeof(bw_config));
4646         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4647         if (ret != I40E_SUCCESS) {
4648                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4649                             hw->aq.asq_last_status);
4650                 return ret;
4651         }
4652
4653         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4654         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4655                                         &ets_sla_config, NULL);
4656         if (ret != I40E_SUCCESS) {
4657                 PMD_DRV_LOG(ERR,
4658                         "VSI failed to get TC bandwdith configuration %u",
4659                         hw->aq.asq_last_status);
4660                 return ret;
4661         }
4662
4663         /* store and print out BW info */
4664         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4665         vsi->bw_info.bw_max = bw_config.max_bw;
4666         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4667         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4668         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4669                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4670                      I40E_16_BIT_WIDTH);
4671         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4672                 vsi->bw_info.bw_ets_share_credits[i] =
4673                                 ets_sla_config.share_credits[i];
4674                 vsi->bw_info.bw_ets_credits[i] =
4675                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4676                 /* 4 bits per TC, 4th bit is reserved */
4677                 vsi->bw_info.bw_ets_max[i] =
4678                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4679                                   RTE_LEN2MASK(3, uint8_t));
4680                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4681                             vsi->bw_info.bw_ets_share_credits[i]);
4682                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4683                             vsi->bw_info.bw_ets_credits[i]);
4684                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4685                             vsi->bw_info.bw_ets_max[i]);
4686         }
4687
4688         return I40E_SUCCESS;
4689 }
4690
4691 /* i40e_enable_pf_lb
4692  * @pf: pointer to the pf structure
4693  *
4694  * allow loopback on pf
4695  */
4696 static inline void
4697 i40e_enable_pf_lb(struct i40e_pf *pf)
4698 {
4699         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4700         struct i40e_vsi_context ctxt;
4701         int ret;
4702
4703         /* Use the FW API if FW >= v5.0 */
4704         if (hw->aq.fw_maj_ver < 5) {
4705                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4706                 return;
4707         }
4708
4709         memset(&ctxt, 0, sizeof(ctxt));
4710         ctxt.seid = pf->main_vsi_seid;
4711         ctxt.pf_num = hw->pf_id;
4712         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4713         if (ret) {
4714                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4715                             ret, hw->aq.asq_last_status);
4716                 return;
4717         }
4718         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4719         ctxt.info.valid_sections =
4720                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4721         ctxt.info.switch_id |=
4722                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4723
4724         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4725         if (ret)
4726                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4727                             hw->aq.asq_last_status);
4728 }
4729
4730 /* Setup a VSI */
4731 struct i40e_vsi *
4732 i40e_vsi_setup(struct i40e_pf *pf,
4733                enum i40e_vsi_type type,
4734                struct i40e_vsi *uplink_vsi,
4735                uint16_t user_param)
4736 {
4737         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4738         struct i40e_vsi *vsi;
4739         struct i40e_mac_filter_info filter;
4740         int ret;
4741         struct i40e_vsi_context ctxt;
4742         struct ether_addr broadcast =
4743                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4744
4745         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4746             uplink_vsi == NULL) {
4747                 PMD_DRV_LOG(ERR,
4748                         "VSI setup failed, VSI link shouldn't be NULL");
4749                 return NULL;
4750         }
4751
4752         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4753                 PMD_DRV_LOG(ERR,
4754                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4755                 return NULL;
4756         }
4757
4758         /* two situations
4759          * 1.type is not MAIN and uplink vsi is not NULL
4760          * If uplink vsi didn't setup VEB, create one first under veb field
4761          * 2.type is SRIOV and the uplink is NULL
4762          * If floating VEB is NULL, create one veb under floating veb field
4763          */
4764
4765         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4766             uplink_vsi->veb == NULL) {
4767                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4768
4769                 if (uplink_vsi->veb == NULL) {
4770                         PMD_DRV_LOG(ERR, "VEB setup failed");
4771                         return NULL;
4772                 }
4773                 /* set ALLOWLOOPBACk on pf, when veb is created */
4774                 i40e_enable_pf_lb(pf);
4775         }
4776
4777         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4778             pf->main_vsi->floating_veb == NULL) {
4779                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4780
4781                 if (pf->main_vsi->floating_veb == NULL) {
4782                         PMD_DRV_LOG(ERR, "VEB setup failed");
4783                         return NULL;
4784                 }
4785         }
4786
4787         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4788         if (!vsi) {
4789                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4790                 return NULL;
4791         }
4792         TAILQ_INIT(&vsi->mac_list);
4793         vsi->type = type;
4794         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4795         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4796         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4797         vsi->user_param = user_param;
4798         vsi->vlan_anti_spoof_on = 0;
4799         vsi->vlan_filter_on = 0;
4800         /* Allocate queues */
4801         switch (vsi->type) {
4802         case I40E_VSI_MAIN  :
4803                 vsi->nb_qps = pf->lan_nb_qps;
4804                 break;
4805         case I40E_VSI_SRIOV :
4806                 vsi->nb_qps = pf->vf_nb_qps;
4807                 break;
4808         case I40E_VSI_VMDQ2:
4809                 vsi->nb_qps = pf->vmdq_nb_qps;
4810                 break;
4811         case I40E_VSI_FDIR:
4812                 vsi->nb_qps = pf->fdir_nb_qps;
4813                 break;
4814         default:
4815                 goto fail_mem;
4816         }
4817         /*
4818          * The filter status descriptor is reported in rx queue 0,
4819          * while the tx queue for fdir filter programming has no
4820          * such constraints, can be non-zero queues.
4821          * To simplify it, choose FDIR vsi use queue 0 pair.
4822          * To make sure it will use queue 0 pair, queue allocation
4823          * need be done before this function is called
4824          */
4825         if (type != I40E_VSI_FDIR) {
4826                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4827                         if (ret < 0) {
4828                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4829                                                 vsi->seid, ret);
4830                                 goto fail_mem;
4831                         }
4832                         vsi->base_queue = ret;
4833         } else
4834                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4835
4836         /* VF has MSIX interrupt in VF range, don't allocate here */
4837         if (type == I40E_VSI_MAIN) {
4838                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4839                                           RTE_MIN(vsi->nb_qps,
4840                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4841                 if (ret < 0) {
4842                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4843                                     vsi->seid, ret);
4844                         goto fail_queue_alloc;
4845                 }
4846                 vsi->msix_intr = ret;
4847                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4848         } else if (type != I40E_VSI_SRIOV) {
4849                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4850                 if (ret < 0) {
4851                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4852                         goto fail_queue_alloc;
4853                 }
4854                 vsi->msix_intr = ret;
4855                 vsi->nb_msix = 1;
4856         } else {
4857                 vsi->msix_intr = 0;
4858                 vsi->nb_msix = 0;
4859         }
4860
4861         /* Add VSI */
4862         if (type == I40E_VSI_MAIN) {
4863                 /* For main VSI, no need to add since it's default one */
4864                 vsi->uplink_seid = pf->mac_seid;
4865                 vsi->seid = pf->main_vsi_seid;
4866                 /* Bind queues with specific MSIX interrupt */
4867                 /**
4868                  * Needs 2 interrupt at least, one for misc cause which will
4869                  * enabled from OS side, Another for queues binding the
4870                  * interrupt from device side only.
4871                  */
4872
4873                 /* Get default VSI parameters from hardware */
4874                 memset(&ctxt, 0, sizeof(ctxt));
4875                 ctxt.seid = vsi->seid;
4876                 ctxt.pf_num = hw->pf_id;
4877                 ctxt.uplink_seid = vsi->uplink_seid;
4878                 ctxt.vf_num = 0;
4879                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4880                 if (ret != I40E_SUCCESS) {
4881                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4882                         goto fail_msix_alloc;
4883                 }
4884                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4885                         sizeof(struct i40e_aqc_vsi_properties_data));
4886                 vsi->vsi_id = ctxt.vsi_number;
4887                 vsi->info.valid_sections = 0;
4888
4889                 /* Configure tc, enabled TC0 only */
4890                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4891                         I40E_SUCCESS) {
4892                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4893                         goto fail_msix_alloc;
4894                 }
4895
4896                 /* TC, queue mapping */
4897                 memset(&ctxt, 0, sizeof(ctxt));
4898                 vsi->info.valid_sections |=
4899                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4900                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4901                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4902                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4903                         sizeof(struct i40e_aqc_vsi_properties_data));
4904                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4905                                                 I40E_DEFAULT_TCMAP);
4906                 if (ret != I40E_SUCCESS) {
4907                         PMD_DRV_LOG(ERR,
4908                                 "Failed to configure TC queue mapping");
4909                         goto fail_msix_alloc;
4910                 }
4911                 ctxt.seid = vsi->seid;
4912                 ctxt.pf_num = hw->pf_id;
4913                 ctxt.uplink_seid = vsi->uplink_seid;
4914                 ctxt.vf_num = 0;
4915
4916                 /* Update VSI parameters */
4917                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4918                 if (ret != I40E_SUCCESS) {
4919                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4920                         goto fail_msix_alloc;
4921                 }
4922
4923                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4924                                                 sizeof(vsi->info.tc_mapping));
4925                 (void)rte_memcpy(&vsi->info.queue_mapping,
4926                                 &ctxt.info.queue_mapping,
4927                         sizeof(vsi->info.queue_mapping));
4928                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4929                 vsi->info.valid_sections = 0;
4930
4931                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4932                                 ETH_ADDR_LEN);
4933
4934                 /**
4935                  * Updating default filter settings are necessary to prevent
4936                  * reception of tagged packets.
4937                  * Some old firmware configurations load a default macvlan
4938                  * filter which accepts both tagged and untagged packets.
4939                  * The updating is to use a normal filter instead if needed.
4940                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4941                  * The firmware with correct configurations load the default
4942                  * macvlan filter which is expected and cannot be removed.
4943                  */
4944                 i40e_update_default_filter_setting(vsi);
4945                 i40e_config_qinq(hw, vsi);
4946         } else if (type == I40E_VSI_SRIOV) {
4947                 memset(&ctxt, 0, sizeof(ctxt));
4948                 /**
4949                  * For other VSI, the uplink_seid equals to uplink VSI's
4950                  * uplink_seid since they share same VEB
4951                  */
4952                 if (uplink_vsi == NULL)
4953                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4954                 else
4955                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4956                 ctxt.pf_num = hw->pf_id;
4957                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4958                 ctxt.uplink_seid = vsi->uplink_seid;
4959                 ctxt.connection_type = 0x1;
4960                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4961
4962                 /* Use the VEB configuration if FW >= v5.0 */
4963                 if (hw->aq.fw_maj_ver >= 5) {
4964                         /* Configure switch ID */
4965                         ctxt.info.valid_sections |=
4966                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4967                         ctxt.info.switch_id =
4968                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4969                 }
4970
4971                 /* Configure port/vlan */
4972                 ctxt.info.valid_sections |=
4973                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4974                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4975                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4976                                                 hw->func_caps.enabled_tcmap);
4977                 if (ret != I40E_SUCCESS) {
4978                         PMD_DRV_LOG(ERR,
4979                                 "Failed to configure TC queue mapping");
4980                         goto fail_msix_alloc;
4981                 }
4982
4983                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4984                 ctxt.info.valid_sections |=
4985                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4986                 /**
4987                  * Since VSI is not created yet, only configure parameter,
4988                  * will add vsi below.
4989                  */
4990
4991                 i40e_config_qinq(hw, vsi);
4992         } else if (type == I40E_VSI_VMDQ2) {
4993                 memset(&ctxt, 0, sizeof(ctxt));
4994                 /*
4995                  * For other VSI, the uplink_seid equals to uplink VSI's
4996                  * uplink_seid since they share same VEB
4997                  */
4998                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4999                 ctxt.pf_num = hw->pf_id;
5000                 ctxt.vf_num = 0;
5001                 ctxt.uplink_seid = vsi->uplink_seid;
5002                 ctxt.connection_type = 0x1;
5003                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5004
5005                 ctxt.info.valid_sections |=
5006                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5007                 /* user_param carries flag to enable loop back */
5008                 if (user_param) {
5009                         ctxt.info.switch_id =
5010                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5011                         ctxt.info.switch_id |=
5012                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5013                 }
5014
5015                 /* Configure port/vlan */
5016                 ctxt.info.valid_sections |=
5017                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5018                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5019                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5020                                                 I40E_DEFAULT_TCMAP);
5021                 if (ret != I40E_SUCCESS) {
5022                         PMD_DRV_LOG(ERR,
5023                                 "Failed to configure TC queue mapping");
5024                         goto fail_msix_alloc;
5025                 }
5026                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5027                 ctxt.info.valid_sections |=
5028                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5029         } else if (type == I40E_VSI_FDIR) {
5030                 memset(&ctxt, 0, sizeof(ctxt));
5031                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5032                 ctxt.pf_num = hw->pf_id;
5033                 ctxt.vf_num = 0;
5034                 ctxt.uplink_seid = vsi->uplink_seid;
5035                 ctxt.connection_type = 0x1;     /* regular data port */
5036                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5037                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5038                                                 I40E_DEFAULT_TCMAP);
5039                 if (ret != I40E_SUCCESS) {
5040                         PMD_DRV_LOG(ERR,
5041                                 "Failed to configure TC queue mapping.");
5042                         goto fail_msix_alloc;
5043                 }
5044                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5045                 ctxt.info.valid_sections |=
5046                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5047         } else {
5048                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5049                 goto fail_msix_alloc;
5050         }
5051
5052         if (vsi->type != I40E_VSI_MAIN) {
5053                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5054                 if (ret != I40E_SUCCESS) {
5055                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5056                                     hw->aq.asq_last_status);
5057                         goto fail_msix_alloc;
5058                 }
5059                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5060                 vsi->info.valid_sections = 0;
5061                 vsi->seid = ctxt.seid;
5062                 vsi->vsi_id = ctxt.vsi_number;
5063                 vsi->sib_vsi_list.vsi = vsi;
5064                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5065                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5066                                           &vsi->sib_vsi_list, list);
5067                 } else {
5068                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5069                                           &vsi->sib_vsi_list, list);
5070                 }
5071         }
5072
5073         /* MAC/VLAN configuration */
5074         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5075         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5076
5077         ret = i40e_vsi_add_mac(vsi, &filter);
5078         if (ret != I40E_SUCCESS) {
5079                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5080                 goto fail_msix_alloc;
5081         }
5082
5083         /* Get VSI BW information */
5084         i40e_vsi_get_bw_config(vsi);
5085         return vsi;
5086 fail_msix_alloc:
5087         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5088 fail_queue_alloc:
5089         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5090 fail_mem:
5091         rte_free(vsi);
5092         return NULL;
5093 }
5094
5095 /* Configure vlan filter on or off */
5096 int
5097 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5098 {
5099         int i, num;
5100         struct i40e_mac_filter *f;
5101         void *temp;
5102         struct i40e_mac_filter_info *mac_filter;
5103         enum rte_mac_filter_type desired_filter;
5104         int ret = I40E_SUCCESS;
5105
5106         if (on) {
5107                 /* Filter to match MAC and VLAN */
5108                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5109         } else {
5110                 /* Filter to match only MAC */
5111                 desired_filter = RTE_MAC_PERFECT_MATCH;
5112         }
5113
5114         num = vsi->mac_num;
5115
5116         mac_filter = rte_zmalloc("mac_filter_info_data",
5117                                  num * sizeof(*mac_filter), 0);
5118         if (mac_filter == NULL) {
5119                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5120                 return I40E_ERR_NO_MEMORY;
5121         }
5122
5123         i = 0;
5124
5125         /* Remove all existing mac */
5126         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5127                 mac_filter[i] = f->mac_info;
5128                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5129                 if (ret) {
5130                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5131                                     on ? "enable" : "disable");
5132                         goto DONE;
5133                 }
5134                 i++;
5135         }
5136
5137         /* Override with new filter */
5138         for (i = 0; i < num; i++) {
5139                 mac_filter[i].filter_type = desired_filter;
5140                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5141                 if (ret) {
5142                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5143                                     on ? "enable" : "disable");
5144                         goto DONE;
5145                 }
5146         }
5147
5148 DONE:
5149         rte_free(mac_filter);
5150         return ret;
5151 }
5152
5153 /* Configure vlan stripping on or off */
5154 int
5155 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5156 {
5157         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5158         struct i40e_vsi_context ctxt;
5159         uint8_t vlan_flags;
5160         int ret = I40E_SUCCESS;
5161
5162         /* Check if it has been already on or off */
5163         if (vsi->info.valid_sections &
5164                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5165                 if (on) {
5166                         if ((vsi->info.port_vlan_flags &
5167                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5168                                 return 0; /* already on */
5169                 } else {
5170                         if ((vsi->info.port_vlan_flags &
5171                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5172                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5173                                 return 0; /* already off */
5174                 }
5175         }
5176
5177         if (on)
5178                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5179         else
5180                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5181         vsi->info.valid_sections =
5182                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5183         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5184         vsi->info.port_vlan_flags |= vlan_flags;
5185         ctxt.seid = vsi->seid;
5186         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5187         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5188         if (ret)
5189                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5190                             on ? "enable" : "disable");
5191
5192         return ret;
5193 }
5194
5195 static int
5196 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5197 {
5198         struct rte_eth_dev_data *data = dev->data;
5199         int ret;
5200         int mask = 0;
5201
5202         /* Apply vlan offload setting */
5203         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5204         i40e_vlan_offload_set(dev, mask);
5205
5206         /* Apply double-vlan setting, not implemented yet */
5207
5208         /* Apply pvid setting */
5209         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5210                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5211         if (ret)
5212                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5213
5214         return ret;
5215 }
5216
5217 static int
5218 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5219 {
5220         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5221
5222         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5223 }
5224
5225 static int
5226 i40e_update_flow_control(struct i40e_hw *hw)
5227 {
5228 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5229         struct i40e_link_status link_status;
5230         uint32_t rxfc = 0, txfc = 0, reg;
5231         uint8_t an_info;
5232         int ret;
5233
5234         memset(&link_status, 0, sizeof(link_status));
5235         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5236         if (ret != I40E_SUCCESS) {
5237                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5238                 goto write_reg; /* Disable flow control */
5239         }
5240
5241         an_info = hw->phy.link_info.an_info;
5242         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5243                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5244                 ret = I40E_ERR_NOT_READY;
5245                 goto write_reg; /* Disable flow control */
5246         }
5247         /**
5248          * If link auto negotiation is enabled, flow control needs to
5249          * be configured according to it
5250          */
5251         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5252         case I40E_LINK_PAUSE_RXTX:
5253                 rxfc = 1;
5254                 txfc = 1;
5255                 hw->fc.current_mode = I40E_FC_FULL;
5256                 break;
5257         case I40E_AQ_LINK_PAUSE_RX:
5258                 rxfc = 1;
5259                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5260                 break;
5261         case I40E_AQ_LINK_PAUSE_TX:
5262                 txfc = 1;
5263                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5264                 break;
5265         default:
5266                 hw->fc.current_mode = I40E_FC_NONE;
5267                 break;
5268         }
5269
5270 write_reg:
5271         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5272                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5273         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5274         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5275         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5276         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5277
5278         return ret;
5279 }
5280
5281 /* PF setup */
5282 static int
5283 i40e_pf_setup(struct i40e_pf *pf)
5284 {
5285         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5286         struct i40e_filter_control_settings settings;
5287         struct i40e_vsi *vsi;
5288         int ret;
5289
5290         /* Clear all stats counters */
5291         pf->offset_loaded = FALSE;
5292         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5293         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5294         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5295         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5296
5297         ret = i40e_pf_get_switch_config(pf);
5298         if (ret != I40E_SUCCESS) {
5299                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5300                 return ret;
5301         }
5302         if (pf->flags & I40E_FLAG_FDIR) {
5303                 /* make queue allocated first, let FDIR use queue pair 0*/
5304                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5305                 if (ret != I40E_FDIR_QUEUE_ID) {
5306                         PMD_DRV_LOG(ERR,
5307                                 "queue allocation fails for FDIR: ret =%d",
5308                                 ret);
5309                         pf->flags &= ~I40E_FLAG_FDIR;
5310                 }
5311         }
5312         /*  main VSI setup */
5313         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5314         if (!vsi) {
5315                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5316                 return I40E_ERR_NOT_READY;
5317         }
5318         pf->main_vsi = vsi;
5319
5320         /* Configure filter control */
5321         memset(&settings, 0, sizeof(settings));
5322         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5323                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5324         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5325                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5326         else {
5327                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5328                         hw->func_caps.rss_table_size);
5329                 return I40E_ERR_PARAM;
5330         }
5331         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5332                 hw->func_caps.rss_table_size);
5333         pf->hash_lut_size = hw->func_caps.rss_table_size;
5334
5335         /* Enable ethtype and macvlan filters */
5336         settings.enable_ethtype = TRUE;
5337         settings.enable_macvlan = TRUE;
5338         ret = i40e_set_filter_control(hw, &settings);
5339         if (ret)
5340                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5341                                                                 ret);
5342
5343         /* Update flow control according to the auto negotiation */
5344         i40e_update_flow_control(hw);
5345
5346         return I40E_SUCCESS;
5347 }
5348
5349 int
5350 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5351 {
5352         uint32_t reg;
5353         uint16_t j;
5354
5355         /**
5356          * Set or clear TX Queue Disable flags,
5357          * which is required by hardware.
5358          */
5359         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5360         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5361
5362         /* Wait until the request is finished */
5363         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5364                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5365                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5366                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5367                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5368                                                         & 0x1))) {
5369                         break;
5370                 }
5371         }
5372         if (on) {
5373                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5374                         return I40E_SUCCESS; /* already on, skip next steps */
5375
5376                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5377                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5378         } else {
5379                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5380                         return I40E_SUCCESS; /* already off, skip next steps */
5381                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5382         }
5383         /* Write the register */
5384         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5385         /* Check the result */
5386         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5387                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5388                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5389                 if (on) {
5390                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5391                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5392                                 break;
5393                 } else {
5394                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5395                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5396                                 break;
5397                 }
5398         }
5399         /* Check if it is timeout */
5400         if (j >= I40E_CHK_Q_ENA_COUNT) {
5401                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5402                             (on ? "enable" : "disable"), q_idx);
5403                 return I40E_ERR_TIMEOUT;
5404         }
5405
5406         return I40E_SUCCESS;
5407 }
5408
5409 /* Swith on or off the tx queues */
5410 static int
5411 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5412 {
5413         struct rte_eth_dev_data *dev_data = pf->dev_data;
5414         struct i40e_tx_queue *txq;
5415         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5416         uint16_t i;
5417         int ret;
5418
5419         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5420                 txq = dev_data->tx_queues[i];
5421                 /* Don't operate the queue if not configured or
5422                  * if starting only per queue */
5423                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5424                         continue;
5425                 if (on)
5426                         ret = i40e_dev_tx_queue_start(dev, i);
5427                 else
5428                         ret = i40e_dev_tx_queue_stop(dev, i);
5429                 if ( ret != I40E_SUCCESS)
5430                         return ret;
5431         }
5432
5433         return I40E_SUCCESS;
5434 }
5435
5436 int
5437 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5438 {
5439         uint32_t reg;
5440         uint16_t j;
5441
5442         /* Wait until the request is finished */
5443         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5444                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5445                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5446                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5447                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5448                         break;
5449         }
5450
5451         if (on) {
5452                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5453                         return I40E_SUCCESS; /* Already on, skip next steps */
5454                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5455         } else {
5456                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5457                         return I40E_SUCCESS; /* Already off, skip next steps */
5458                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5459         }
5460
5461         /* Write the register */
5462         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5463         /* Check the result */
5464         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5465                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5466                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5467                 if (on) {
5468                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5469                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5470                                 break;
5471                 } else {
5472                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5473                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5474                                 break;
5475                 }
5476         }
5477
5478         /* Check if it is timeout */
5479         if (j >= I40E_CHK_Q_ENA_COUNT) {
5480                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5481                             (on ? "enable" : "disable"), q_idx);
5482                 return I40E_ERR_TIMEOUT;
5483         }
5484
5485         return I40E_SUCCESS;
5486 }
5487 /* Switch on or off the rx queues */
5488 static int
5489 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5490 {
5491         struct rte_eth_dev_data *dev_data = pf->dev_data;
5492         struct i40e_rx_queue *rxq;
5493         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5494         uint16_t i;
5495         int ret;
5496
5497         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5498                 rxq = dev_data->rx_queues[i];
5499                 /* Don't operate the queue if not configured or
5500                  * if starting only per queue */
5501                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5502                         continue;
5503                 if (on)
5504                         ret = i40e_dev_rx_queue_start(dev, i);
5505                 else
5506                         ret = i40e_dev_rx_queue_stop(dev, i);
5507                 if (ret != I40E_SUCCESS)
5508                         return ret;
5509         }
5510
5511         return I40E_SUCCESS;
5512 }
5513
5514 /* Switch on or off all the rx/tx queues */
5515 int
5516 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5517 {
5518         int ret;
5519
5520         if (on) {
5521                 /* enable rx queues before enabling tx queues */
5522                 ret = i40e_dev_switch_rx_queues(pf, on);
5523                 if (ret) {
5524                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5525                         return ret;
5526                 }
5527                 ret = i40e_dev_switch_tx_queues(pf, on);
5528         } else {
5529                 /* Stop tx queues before stopping rx queues */
5530                 ret = i40e_dev_switch_tx_queues(pf, on);
5531                 if (ret) {
5532                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5533                         return ret;
5534                 }
5535                 ret = i40e_dev_switch_rx_queues(pf, on);
5536         }
5537
5538         return ret;
5539 }
5540
5541 /* Initialize VSI for TX */
5542 static int
5543 i40e_dev_tx_init(struct i40e_pf *pf)
5544 {
5545         struct rte_eth_dev_data *data = pf->dev_data;
5546         uint16_t i;
5547         uint32_t ret = I40E_SUCCESS;
5548         struct i40e_tx_queue *txq;
5549
5550         for (i = 0; i < data->nb_tx_queues; i++) {
5551                 txq = data->tx_queues[i];
5552                 if (!txq || !txq->q_set)
5553                         continue;
5554                 ret = i40e_tx_queue_init(txq);
5555                 if (ret != I40E_SUCCESS)
5556                         break;
5557         }
5558         if (ret == I40E_SUCCESS)
5559                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5560                                      ->eth_dev);
5561
5562         return ret;
5563 }
5564
5565 /* Initialize VSI for RX */
5566 static int
5567 i40e_dev_rx_init(struct i40e_pf *pf)
5568 {
5569         struct rte_eth_dev_data *data = pf->dev_data;
5570         int ret = I40E_SUCCESS;
5571         uint16_t i;
5572         struct i40e_rx_queue *rxq;
5573
5574         i40e_pf_config_mq_rx(pf);
5575         for (i = 0; i < data->nb_rx_queues; i++) {
5576                 rxq = data->rx_queues[i];
5577                 if (!rxq || !rxq->q_set)
5578                         continue;
5579
5580                 ret = i40e_rx_queue_init(rxq);
5581                 if (ret != I40E_SUCCESS) {
5582                         PMD_DRV_LOG(ERR,
5583                                 "Failed to do RX queue initialization");
5584                         break;
5585                 }
5586         }
5587         if (ret == I40E_SUCCESS)
5588                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5589                                      ->eth_dev);
5590
5591         return ret;
5592 }
5593
5594 static int
5595 i40e_dev_rxtx_init(struct i40e_pf *pf)
5596 {
5597         int err;
5598
5599         err = i40e_dev_tx_init(pf);
5600         if (err) {
5601                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5602                 return err;
5603         }
5604         err = i40e_dev_rx_init(pf);
5605         if (err) {
5606                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5607                 return err;
5608         }
5609
5610         return err;
5611 }
5612
5613 static int
5614 i40e_vmdq_setup(struct rte_eth_dev *dev)
5615 {
5616         struct rte_eth_conf *conf = &dev->data->dev_conf;
5617         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5618         int i, err, conf_vsis, j, loop;
5619         struct i40e_vsi *vsi;
5620         struct i40e_vmdq_info *vmdq_info;
5621         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5622         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5623
5624         /*
5625          * Disable interrupt to avoid message from VF. Furthermore, it will
5626          * avoid race condition in VSI creation/destroy.
5627          */
5628         i40e_pf_disable_irq0(hw);
5629
5630         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5631                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5632                 return -ENOTSUP;
5633         }
5634
5635         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5636         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5637                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5638                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5639                         pf->max_nb_vmdq_vsi);
5640                 return -ENOTSUP;
5641         }
5642
5643         if (pf->vmdq != NULL) {
5644                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5645                 return 0;
5646         }
5647
5648         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5649                                 sizeof(*vmdq_info) * conf_vsis, 0);
5650
5651         if (pf->vmdq == NULL) {
5652                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5653                 return -ENOMEM;
5654         }
5655
5656         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5657
5658         /* Create VMDQ VSI */
5659         for (i = 0; i < conf_vsis; i++) {
5660                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5661                                 vmdq_conf->enable_loop_back);
5662                 if (vsi == NULL) {
5663                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5664                         err = -1;
5665                         goto err_vsi_setup;
5666                 }
5667                 vmdq_info = &pf->vmdq[i];
5668                 vmdq_info->pf = pf;
5669                 vmdq_info->vsi = vsi;
5670         }
5671         pf->nb_cfg_vmdq_vsi = conf_vsis;
5672
5673         /* Configure Vlan */
5674         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5675         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5676                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5677                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5678                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5679                                         vmdq_conf->pool_map[i].vlan_id, j);
5680
5681                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5682                                                 vmdq_conf->pool_map[i].vlan_id);
5683                                 if (err) {
5684                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5685                                         err = -1;
5686                                         goto err_vsi_setup;
5687                                 }
5688                         }
5689                 }
5690         }
5691
5692         i40e_pf_enable_irq0(hw);
5693
5694         return 0;
5695
5696 err_vsi_setup:
5697         for (i = 0; i < conf_vsis; i++)
5698                 if (pf->vmdq[i].vsi == NULL)
5699                         break;
5700                 else
5701                         i40e_vsi_release(pf->vmdq[i].vsi);
5702
5703         rte_free(pf->vmdq);
5704         pf->vmdq = NULL;
5705         i40e_pf_enable_irq0(hw);
5706         return err;
5707 }
5708
5709 static void
5710 i40e_stat_update_32(struct i40e_hw *hw,
5711                    uint32_t reg,
5712                    bool offset_loaded,
5713                    uint64_t *offset,
5714                    uint64_t *stat)
5715 {
5716         uint64_t new_data;
5717
5718         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5719         if (!offset_loaded)
5720                 *offset = new_data;
5721
5722         if (new_data >= *offset)
5723                 *stat = (uint64_t)(new_data - *offset);
5724         else
5725                 *stat = (uint64_t)((new_data +
5726                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5727 }
5728
5729 static void
5730 i40e_stat_update_48(struct i40e_hw *hw,
5731                    uint32_t hireg,
5732                    uint32_t loreg,
5733                    bool offset_loaded,
5734                    uint64_t *offset,
5735                    uint64_t *stat)
5736 {
5737         uint64_t new_data;
5738
5739         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5740         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5741                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5742
5743         if (!offset_loaded)
5744                 *offset = new_data;
5745
5746         if (new_data >= *offset)
5747                 *stat = new_data - *offset;
5748         else
5749                 *stat = (uint64_t)((new_data +
5750                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5751
5752         *stat &= I40E_48_BIT_MASK;
5753 }
5754
5755 /* Disable IRQ0 */
5756 void
5757 i40e_pf_disable_irq0(struct i40e_hw *hw)
5758 {
5759         /* Disable all interrupt types */
5760         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5761         I40E_WRITE_FLUSH(hw);
5762 }
5763
5764 /* Enable IRQ0 */
5765 void
5766 i40e_pf_enable_irq0(struct i40e_hw *hw)
5767 {
5768         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5769                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5770                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5771                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5772         I40E_WRITE_FLUSH(hw);
5773 }
5774
5775 static void
5776 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5777 {
5778         /* read pending request and disable first */
5779         i40e_pf_disable_irq0(hw);
5780         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5781         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5782                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5783
5784         if (no_queue)
5785                 /* Link no queues with irq0 */
5786                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5787                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5788 }
5789
5790 static void
5791 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5792 {
5793         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5794         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5795         int i;
5796         uint16_t abs_vf_id;
5797         uint32_t index, offset, val;
5798
5799         if (!pf->vfs)
5800                 return;
5801         /**
5802          * Try to find which VF trigger a reset, use absolute VF id to access
5803          * since the reg is global register.
5804          */
5805         for (i = 0; i < pf->vf_num; i++) {
5806                 abs_vf_id = hw->func_caps.vf_base_id + i;
5807                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5808                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5809                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5810                 /* VFR event occurred */
5811                 if (val & (0x1 << offset)) {
5812                         int ret;
5813
5814                         /* Clear the event first */
5815                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5816                                                         (0x1 << offset));
5817                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5818                         /**
5819                          * Only notify a VF reset event occurred,
5820                          * don't trigger another SW reset
5821                          */
5822                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5823                         if (ret != I40E_SUCCESS)
5824                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5825                 }
5826         }
5827 }
5828
5829 static void
5830 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5831 {
5832         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5833         int i;
5834
5835         for (i = 0; i < pf->vf_num; i++)
5836                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5837 }
5838
5839 static void
5840 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5841 {
5842         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5843         struct i40e_arq_event_info info;
5844         uint16_t pending, opcode;
5845         int ret;
5846
5847         info.buf_len = I40E_AQ_BUF_SZ;
5848         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5849         if (!info.msg_buf) {
5850                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5851                 return;
5852         }
5853
5854         pending = 1;
5855         while (pending) {
5856                 ret = i40e_clean_arq_element(hw, &info, &pending);
5857
5858                 if (ret != I40E_SUCCESS) {
5859                         PMD_DRV_LOG(INFO,
5860                                 "Failed to read msg from AdminQ, aq_err: %u",
5861                                 hw->aq.asq_last_status);
5862                         break;
5863                 }
5864                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5865
5866                 switch (opcode) {
5867                 case i40e_aqc_opc_send_msg_to_pf:
5868                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5869                         i40e_pf_host_handle_vf_msg(dev,
5870                                         rte_le_to_cpu_16(info.desc.retval),
5871                                         rte_le_to_cpu_32(info.desc.cookie_high),
5872                                         rte_le_to_cpu_32(info.desc.cookie_low),
5873                                         info.msg_buf,
5874                                         info.msg_len);
5875                         break;
5876                 case i40e_aqc_opc_get_link_status:
5877                         ret = i40e_dev_link_update(dev, 0);
5878                         if (!ret)
5879                                 _rte_eth_dev_callback_process(dev,
5880                                         RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5881                         break;
5882                 default:
5883                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5884                                     opcode);
5885                         break;
5886                 }
5887         }
5888         rte_free(info.msg_buf);
5889 }
5890
5891 /**
5892  * Interrupt handler triggered by NIC  for handling
5893  * specific interrupt.
5894  *
5895  * @param handle
5896  *  Pointer to interrupt handle.
5897  * @param param
5898  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5899  *
5900  * @return
5901  *  void
5902  */
5903 static void
5904 i40e_dev_interrupt_handler(void *param)
5905 {
5906         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5907         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5908         uint32_t icr0;
5909
5910         /* Disable interrupt */
5911         i40e_pf_disable_irq0(hw);
5912
5913         /* read out interrupt causes */
5914         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5915
5916         /* No interrupt event indicated */
5917         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5918                 PMD_DRV_LOG(INFO, "No interrupt event");
5919                 goto done;
5920         }
5921         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5922                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5923         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5924                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5925         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5926                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5927         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5928                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5929         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5930                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5931         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5932                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5933         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5934                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5935
5936         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5937                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5938                 i40e_dev_handle_vfr_event(dev);
5939         }
5940         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5941                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5942                 i40e_dev_handle_aq_msg(dev);
5943         }
5944
5945 done:
5946         /* Enable interrupt */
5947         i40e_pf_enable_irq0(hw);
5948         rte_intr_enable(dev->intr_handle);
5949 }
5950
5951 int
5952 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5953                          struct i40e_macvlan_filter *filter,
5954                          int total)
5955 {
5956         int ele_num, ele_buff_size;
5957         int num, actual_num, i;
5958         uint16_t flags;
5959         int ret = I40E_SUCCESS;
5960         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5961         struct i40e_aqc_add_macvlan_element_data *req_list;
5962
5963         if (filter == NULL  || total == 0)
5964                 return I40E_ERR_PARAM;
5965         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5966         ele_buff_size = hw->aq.asq_buf_size;
5967
5968         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5969         if (req_list == NULL) {
5970                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5971                 return I40E_ERR_NO_MEMORY;
5972         }
5973
5974         num = 0;
5975         do {
5976                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5977                 memset(req_list, 0, ele_buff_size);
5978
5979                 for (i = 0; i < actual_num; i++) {
5980                         (void)rte_memcpy(req_list[i].mac_addr,
5981                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5982                         req_list[i].vlan_tag =
5983                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5984
5985                         switch (filter[num + i].filter_type) {
5986                         case RTE_MAC_PERFECT_MATCH:
5987                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5988                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5989                                 break;
5990                         case RTE_MACVLAN_PERFECT_MATCH:
5991                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5992                                 break;
5993                         case RTE_MAC_HASH_MATCH:
5994                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5995                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5996                                 break;
5997                         case RTE_MACVLAN_HASH_MATCH:
5998                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5999                                 break;
6000                         default:
6001                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6002                                 ret = I40E_ERR_PARAM;
6003                                 goto DONE;
6004                         }
6005
6006                         req_list[i].queue_number = 0;
6007
6008                         req_list[i].flags = rte_cpu_to_le_16(flags);
6009                 }
6010
6011                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6012                                                 actual_num, NULL);
6013                 if (ret != I40E_SUCCESS) {
6014                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6015                         goto DONE;
6016                 }
6017                 num += actual_num;
6018         } while (num < total);
6019
6020 DONE:
6021         rte_free(req_list);
6022         return ret;
6023 }
6024
6025 int
6026 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6027                             struct i40e_macvlan_filter *filter,
6028                             int total)
6029 {
6030         int ele_num, ele_buff_size;
6031         int num, actual_num, i;
6032         uint16_t flags;
6033         int ret = I40E_SUCCESS;
6034         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6035         struct i40e_aqc_remove_macvlan_element_data *req_list;
6036
6037         if (filter == NULL  || total == 0)
6038                 return I40E_ERR_PARAM;
6039
6040         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6041         ele_buff_size = hw->aq.asq_buf_size;
6042
6043         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6044         if (req_list == NULL) {
6045                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6046                 return I40E_ERR_NO_MEMORY;
6047         }
6048
6049         num = 0;
6050         do {
6051                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6052                 memset(req_list, 0, ele_buff_size);
6053
6054                 for (i = 0; i < actual_num; i++) {
6055                         (void)rte_memcpy(req_list[i].mac_addr,
6056                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6057                         req_list[i].vlan_tag =
6058                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6059
6060                         switch (filter[num + i].filter_type) {
6061                         case RTE_MAC_PERFECT_MATCH:
6062                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6063                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6064                                 break;
6065                         case RTE_MACVLAN_PERFECT_MATCH:
6066                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6067                                 break;
6068                         case RTE_MAC_HASH_MATCH:
6069                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6070                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6071                                 break;
6072                         case RTE_MACVLAN_HASH_MATCH:
6073                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6074                                 break;
6075                         default:
6076                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6077                                 ret = I40E_ERR_PARAM;
6078                                 goto DONE;
6079                         }
6080                         req_list[i].flags = rte_cpu_to_le_16(flags);
6081                 }
6082
6083                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6084                                                 actual_num, NULL);
6085                 if (ret != I40E_SUCCESS) {
6086                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6087                         goto DONE;
6088                 }
6089                 num += actual_num;
6090         } while (num < total);
6091
6092 DONE:
6093         rte_free(req_list);
6094         return ret;
6095 }
6096
6097 /* Find out specific MAC filter */
6098 static struct i40e_mac_filter *
6099 i40e_find_mac_filter(struct i40e_vsi *vsi,
6100                          struct ether_addr *macaddr)
6101 {
6102         struct i40e_mac_filter *f;
6103
6104         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6105                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6106                         return f;
6107         }
6108
6109         return NULL;
6110 }
6111
6112 static bool
6113 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6114                          uint16_t vlan_id)
6115 {
6116         uint32_t vid_idx, vid_bit;
6117
6118         if (vlan_id > ETH_VLAN_ID_MAX)
6119                 return 0;
6120
6121         vid_idx = I40E_VFTA_IDX(vlan_id);
6122         vid_bit = I40E_VFTA_BIT(vlan_id);
6123
6124         if (vsi->vfta[vid_idx] & vid_bit)
6125                 return 1;
6126         else
6127                 return 0;
6128 }
6129
6130 static void
6131 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6132                        uint16_t vlan_id, bool on)
6133 {
6134         uint32_t vid_idx, vid_bit;
6135
6136         vid_idx = I40E_VFTA_IDX(vlan_id);
6137         vid_bit = I40E_VFTA_BIT(vlan_id);
6138
6139         if (on)
6140                 vsi->vfta[vid_idx] |= vid_bit;
6141         else
6142                 vsi->vfta[vid_idx] &= ~vid_bit;
6143 }
6144
6145 void
6146 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6147                      uint16_t vlan_id, bool on)
6148 {
6149         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6150         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6151         int ret;
6152
6153         if (vlan_id > ETH_VLAN_ID_MAX)
6154                 return;
6155
6156         i40e_store_vlan_filter(vsi, vlan_id, on);
6157
6158         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6159                 return;
6160
6161         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6162
6163         if (on) {
6164                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6165                                        &vlan_data, 1, NULL);
6166                 if (ret != I40E_SUCCESS)
6167                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6168         } else {
6169                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6170                                           &vlan_data, 1, NULL);
6171                 if (ret != I40E_SUCCESS)
6172                         PMD_DRV_LOG(ERR,
6173                                     "Failed to remove vlan filter");
6174         }
6175 }
6176
6177 /**
6178  * Find all vlan options for specific mac addr,
6179  * return with actual vlan found.
6180  */
6181 int
6182 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6183                            struct i40e_macvlan_filter *mv_f,
6184                            int num, struct ether_addr *addr)
6185 {
6186         int i;
6187         uint32_t j, k;
6188
6189         /**
6190          * Not to use i40e_find_vlan_filter to decrease the loop time,
6191          * although the code looks complex.
6192           */
6193         if (num < vsi->vlan_num)
6194                 return I40E_ERR_PARAM;
6195
6196         i = 0;
6197         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6198                 if (vsi->vfta[j]) {
6199                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6200                                 if (vsi->vfta[j] & (1 << k)) {
6201                                         if (i > num - 1) {
6202                                                 PMD_DRV_LOG(ERR,
6203                                                         "vlan number doesn't match");
6204                                                 return I40E_ERR_PARAM;
6205                                         }
6206                                         (void)rte_memcpy(&mv_f[i].macaddr,
6207                                                         addr, ETH_ADDR_LEN);
6208                                         mv_f[i].vlan_id =
6209                                                 j * I40E_UINT32_BIT_SIZE + k;
6210                                         i++;
6211                                 }
6212                         }
6213                 }
6214         }
6215         return I40E_SUCCESS;
6216 }
6217
6218 static inline int
6219 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6220                            struct i40e_macvlan_filter *mv_f,
6221                            int num,
6222                            uint16_t vlan)
6223 {
6224         int i = 0;
6225         struct i40e_mac_filter *f;
6226
6227         if (num < vsi->mac_num)
6228                 return I40E_ERR_PARAM;
6229
6230         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6231                 if (i > num - 1) {
6232                         PMD_DRV_LOG(ERR, "buffer number not match");
6233                         return I40E_ERR_PARAM;
6234                 }
6235                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6236                                 ETH_ADDR_LEN);
6237                 mv_f[i].vlan_id = vlan;
6238                 mv_f[i].filter_type = f->mac_info.filter_type;
6239                 i++;
6240         }
6241
6242         return I40E_SUCCESS;
6243 }
6244
6245 static int
6246 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6247 {
6248         int i, j, num;
6249         struct i40e_mac_filter *f;
6250         struct i40e_macvlan_filter *mv_f;
6251         int ret = I40E_SUCCESS;
6252
6253         if (vsi == NULL || vsi->mac_num == 0)
6254                 return I40E_ERR_PARAM;
6255
6256         /* Case that no vlan is set */
6257         if (vsi->vlan_num == 0)
6258                 num = vsi->mac_num;
6259         else
6260                 num = vsi->mac_num * vsi->vlan_num;
6261
6262         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6263         if (mv_f == NULL) {
6264                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6265                 return I40E_ERR_NO_MEMORY;
6266         }
6267
6268         i = 0;
6269         if (vsi->vlan_num == 0) {
6270                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6271                         (void)rte_memcpy(&mv_f[i].macaddr,
6272                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6273                         mv_f[i].filter_type = f->mac_info.filter_type;
6274                         mv_f[i].vlan_id = 0;
6275                         i++;
6276                 }
6277         } else {
6278                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6279                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6280                                         vsi->vlan_num, &f->mac_info.mac_addr);
6281                         if (ret != I40E_SUCCESS)
6282                                 goto DONE;
6283                         for (j = i; j < i + vsi->vlan_num; j++)
6284                                 mv_f[j].filter_type = f->mac_info.filter_type;
6285                         i += vsi->vlan_num;
6286                 }
6287         }
6288
6289         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6290 DONE:
6291         rte_free(mv_f);
6292
6293         return ret;
6294 }
6295
6296 int
6297 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6298 {
6299         struct i40e_macvlan_filter *mv_f;
6300         int mac_num;
6301         int ret = I40E_SUCCESS;
6302
6303         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6304                 return I40E_ERR_PARAM;
6305
6306         /* If it's already set, just return */
6307         if (i40e_find_vlan_filter(vsi,vlan))
6308                 return I40E_SUCCESS;
6309
6310         mac_num = vsi->mac_num;
6311
6312         if (mac_num == 0) {
6313                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6314                 return I40E_ERR_PARAM;
6315         }
6316
6317         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6318
6319         if (mv_f == NULL) {
6320                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6321                 return I40E_ERR_NO_MEMORY;
6322         }
6323
6324         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6325
6326         if (ret != I40E_SUCCESS)
6327                 goto DONE;
6328
6329         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6330
6331         if (ret != I40E_SUCCESS)
6332                 goto DONE;
6333
6334         i40e_set_vlan_filter(vsi, vlan, 1);
6335
6336         vsi->vlan_num++;
6337         ret = I40E_SUCCESS;
6338 DONE:
6339         rte_free(mv_f);
6340         return ret;
6341 }
6342
6343 int
6344 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6345 {
6346         struct i40e_macvlan_filter *mv_f;
6347         int mac_num;
6348         int ret = I40E_SUCCESS;
6349
6350         /**
6351          * Vlan 0 is the generic filter for untagged packets
6352          * and can't be removed.
6353          */
6354         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6355                 return I40E_ERR_PARAM;
6356
6357         /* If can't find it, just return */
6358         if (!i40e_find_vlan_filter(vsi, vlan))
6359                 return I40E_ERR_PARAM;
6360
6361         mac_num = vsi->mac_num;
6362
6363         if (mac_num == 0) {
6364                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6365                 return I40E_ERR_PARAM;
6366         }
6367
6368         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6369
6370         if (mv_f == NULL) {
6371                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6372                 return I40E_ERR_NO_MEMORY;
6373         }
6374
6375         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6376
6377         if (ret != I40E_SUCCESS)
6378                 goto DONE;
6379
6380         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6381
6382         if (ret != I40E_SUCCESS)
6383                 goto DONE;
6384
6385         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6386         if (vsi->vlan_num == 1) {
6387                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6388                 if (ret != I40E_SUCCESS)
6389                         goto DONE;
6390
6391                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6392                 if (ret != I40E_SUCCESS)
6393                         goto DONE;
6394         }
6395
6396         i40e_set_vlan_filter(vsi, vlan, 0);
6397
6398         vsi->vlan_num--;
6399         ret = I40E_SUCCESS;
6400 DONE:
6401         rte_free(mv_f);
6402         return ret;
6403 }
6404
6405 int
6406 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6407 {
6408         struct i40e_mac_filter *f;
6409         struct i40e_macvlan_filter *mv_f;
6410         int i, vlan_num = 0;
6411         int ret = I40E_SUCCESS;
6412
6413         /* If it's add and we've config it, return */
6414         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6415         if (f != NULL)
6416                 return I40E_SUCCESS;
6417         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6418                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6419
6420                 /**
6421                  * If vlan_num is 0, that's the first time to add mac,
6422                  * set mask for vlan_id 0.
6423                  */
6424                 if (vsi->vlan_num == 0) {
6425                         i40e_set_vlan_filter(vsi, 0, 1);
6426                         vsi->vlan_num = 1;
6427                 }
6428                 vlan_num = vsi->vlan_num;
6429         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6430                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6431                 vlan_num = 1;
6432
6433         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6434         if (mv_f == NULL) {
6435                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6436                 return I40E_ERR_NO_MEMORY;
6437         }
6438
6439         for (i = 0; i < vlan_num; i++) {
6440                 mv_f[i].filter_type = mac_filter->filter_type;
6441                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6442                                 ETH_ADDR_LEN);
6443         }
6444
6445         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6446                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6447                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6448                                         &mac_filter->mac_addr);
6449                 if (ret != I40E_SUCCESS)
6450                         goto DONE;
6451         }
6452
6453         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6454         if (ret != I40E_SUCCESS)
6455                 goto DONE;
6456
6457         /* Add the mac addr into mac list */
6458         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6459         if (f == NULL) {
6460                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6461                 ret = I40E_ERR_NO_MEMORY;
6462                 goto DONE;
6463         }
6464         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6465                         ETH_ADDR_LEN);
6466         f->mac_info.filter_type = mac_filter->filter_type;
6467         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6468         vsi->mac_num++;
6469
6470         ret = I40E_SUCCESS;
6471 DONE:
6472         rte_free(mv_f);
6473
6474         return ret;
6475 }
6476
6477 int
6478 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6479 {
6480         struct i40e_mac_filter *f;
6481         struct i40e_macvlan_filter *mv_f;
6482         int i, vlan_num;
6483         enum rte_mac_filter_type filter_type;
6484         int ret = I40E_SUCCESS;
6485
6486         /* Can't find it, return an error */
6487         f = i40e_find_mac_filter(vsi, addr);
6488         if (f == NULL)
6489                 return I40E_ERR_PARAM;
6490
6491         vlan_num = vsi->vlan_num;
6492         filter_type = f->mac_info.filter_type;
6493         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6494                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6495                 if (vlan_num == 0) {
6496                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6497                         return I40E_ERR_PARAM;
6498                 }
6499         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6500                         filter_type == RTE_MAC_HASH_MATCH)
6501                 vlan_num = 1;
6502
6503         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6504         if (mv_f == NULL) {
6505                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6506                 return I40E_ERR_NO_MEMORY;
6507         }
6508
6509         for (i = 0; i < vlan_num; i++) {
6510                 mv_f[i].filter_type = filter_type;
6511                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6512                                 ETH_ADDR_LEN);
6513         }
6514         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6515                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6516                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6517                 if (ret != I40E_SUCCESS)
6518                         goto DONE;
6519         }
6520
6521         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6522         if (ret != I40E_SUCCESS)
6523                 goto DONE;
6524
6525         /* Remove the mac addr into mac list */
6526         TAILQ_REMOVE(&vsi->mac_list, f, next);
6527         rte_free(f);
6528         vsi->mac_num--;
6529
6530         ret = I40E_SUCCESS;
6531 DONE:
6532         rte_free(mv_f);
6533         return ret;
6534 }
6535
6536 /* Configure hash enable flags for RSS */
6537 uint64_t
6538 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6539 {
6540         uint64_t hena = 0;
6541
6542         if (!flags)
6543                 return hena;
6544
6545         if (flags & ETH_RSS_FRAG_IPV4)
6546                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6547         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6548                 if (type == I40E_MAC_X722) {
6549                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6550                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6551                 } else
6552                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6553         }
6554         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6555                 if (type == I40E_MAC_X722) {
6556                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6557                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6558                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6559                 } else
6560                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6561         }
6562         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6563                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6564         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6565                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6566         if (flags & ETH_RSS_FRAG_IPV6)
6567                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6568         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6569                 if (type == I40E_MAC_X722) {
6570                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6571                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6572                 } else
6573                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6574         }
6575         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6576                 if (type == I40E_MAC_X722) {
6577                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6578                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6579                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6580                 } else
6581                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6582         }
6583         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6584                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6585         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6586                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6587         if (flags & ETH_RSS_L2_PAYLOAD)
6588                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6589
6590         return hena;
6591 }
6592
6593 /* Parse the hash enable flags */
6594 uint64_t
6595 i40e_parse_hena(uint64_t flags)
6596 {
6597         uint64_t rss_hf = 0;
6598
6599         if (!flags)
6600                 return rss_hf;
6601         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6602                 rss_hf |= ETH_RSS_FRAG_IPV4;
6603         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6604                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6605         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6606                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6607         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6608                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6609         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6610                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6611         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6612                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6613         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6614                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6615         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6616                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6617         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6618                 rss_hf |= ETH_RSS_FRAG_IPV6;
6619         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6620                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6621         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6622                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6623         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6624                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6625         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6626                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6627         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6628                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6629         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6630                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6631         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6632                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6633         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6634                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6635
6636         return rss_hf;
6637 }
6638
6639 /* Disable RSS */
6640 static void
6641 i40e_pf_disable_rss(struct i40e_pf *pf)
6642 {
6643         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6644         uint64_t hena;
6645
6646         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6647         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6648         if (hw->mac.type == I40E_MAC_X722)
6649                 hena &= ~I40E_RSS_HENA_ALL_X722;
6650         else
6651                 hena &= ~I40E_RSS_HENA_ALL;
6652         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6653         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6654         I40E_WRITE_FLUSH(hw);
6655 }
6656
6657 static int
6658 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6659 {
6660         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6661         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6662         int ret = 0;
6663
6664         if (!key || key_len == 0) {
6665                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6666                 return 0;
6667         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6668                 sizeof(uint32_t)) {
6669                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6670                 return -EINVAL;
6671         }
6672
6673         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6674                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6675                         (struct i40e_aqc_get_set_rss_key_data *)key;
6676
6677                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6678                 if (ret)
6679                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6680         } else {
6681                 uint32_t *hash_key = (uint32_t *)key;
6682                 uint16_t i;
6683
6684                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6685                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6686                 I40E_WRITE_FLUSH(hw);
6687         }
6688
6689         return ret;
6690 }
6691
6692 static int
6693 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6694 {
6695         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6696         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6697         int ret;
6698
6699         if (!key || !key_len)
6700                 return -EINVAL;
6701
6702         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6703                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6704                         (struct i40e_aqc_get_set_rss_key_data *)key);
6705                 if (ret) {
6706                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6707                         return ret;
6708                 }
6709         } else {
6710                 uint32_t *key_dw = (uint32_t *)key;
6711                 uint16_t i;
6712
6713                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6714                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6715         }
6716         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6717
6718         return 0;
6719 }
6720
6721 static int
6722 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6723 {
6724         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6725         uint64_t rss_hf;
6726         uint64_t hena;
6727         int ret;
6728
6729         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6730                                rss_conf->rss_key_len);
6731         if (ret)
6732                 return ret;
6733
6734         rss_hf = rss_conf->rss_hf;
6735         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6736         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6737         if (hw->mac.type == I40E_MAC_X722)
6738                 hena &= ~I40E_RSS_HENA_ALL_X722;
6739         else
6740                 hena &= ~I40E_RSS_HENA_ALL;
6741         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6742         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6743         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6744         I40E_WRITE_FLUSH(hw);
6745
6746         return 0;
6747 }
6748
6749 static int
6750 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6751                          struct rte_eth_rss_conf *rss_conf)
6752 {
6753         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6754         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6755         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6756         uint64_t hena;
6757
6758         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6759         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6760         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6761                  ? I40E_RSS_HENA_ALL_X722
6762                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6763                 if (rss_hf != 0) /* Enable RSS */
6764                         return -EINVAL;
6765                 return 0; /* Nothing to do */
6766         }
6767         /* RSS enabled */
6768         if (rss_hf == 0) /* Disable RSS */
6769                 return -EINVAL;
6770
6771         return i40e_hw_rss_hash_set(pf, rss_conf);
6772 }
6773
6774 static int
6775 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6776                            struct rte_eth_rss_conf *rss_conf)
6777 {
6778         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6779         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6780         uint64_t hena;
6781
6782         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6783                          &rss_conf->rss_key_len);
6784
6785         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6786         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6787         rss_conf->rss_hf = i40e_parse_hena(hena);
6788
6789         return 0;
6790 }
6791
6792 static int
6793 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6794 {
6795         switch (filter_type) {
6796         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6797                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6798                 break;
6799         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6800                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6801                 break;
6802         case RTE_TUNNEL_FILTER_IMAC_TENID:
6803                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6804                 break;
6805         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6806                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6807                 break;
6808         case ETH_TUNNEL_FILTER_IMAC:
6809                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6810                 break;
6811         case ETH_TUNNEL_FILTER_OIP:
6812                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6813                 break;
6814         case ETH_TUNNEL_FILTER_IIP:
6815                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6816                 break;
6817         default:
6818                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6819                 return -EINVAL;
6820         }
6821
6822         return 0;
6823 }
6824
6825 /* Convert tunnel filter structure */
6826 static int
6827 i40e_tunnel_filter_convert(
6828         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6829         struct i40e_tunnel_filter *tunnel_filter)
6830 {
6831         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6832                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6833         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6834                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6835         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6836         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6837              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6838             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6839                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6840         else
6841                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6842         tunnel_filter->input.flags = cld_filter->element.flags;
6843         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6844         tunnel_filter->queue = cld_filter->element.queue_number;
6845         rte_memcpy(tunnel_filter->input.general_fields,
6846                    cld_filter->general_fields,
6847                    sizeof(cld_filter->general_fields));
6848
6849         return 0;
6850 }
6851
6852 /* Check if there exists the tunnel filter */
6853 struct i40e_tunnel_filter *
6854 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6855                              const struct i40e_tunnel_filter_input *input)
6856 {
6857         int ret;
6858
6859         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6860         if (ret < 0)
6861                 return NULL;
6862
6863         return tunnel_rule->hash_map[ret];
6864 }
6865
6866 /* Add a tunnel filter into the SW list */
6867 static int
6868 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6869                              struct i40e_tunnel_filter *tunnel_filter)
6870 {
6871         struct i40e_tunnel_rule *rule = &pf->tunnel;
6872         int ret;
6873
6874         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6875         if (ret < 0) {
6876                 PMD_DRV_LOG(ERR,
6877                             "Failed to insert tunnel filter to hash table %d!",
6878                             ret);
6879                 return ret;
6880         }
6881         rule->hash_map[ret] = tunnel_filter;
6882
6883         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6884
6885         return 0;
6886 }
6887
6888 /* Delete a tunnel filter from the SW list */
6889 int
6890 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6891                           struct i40e_tunnel_filter_input *input)
6892 {
6893         struct i40e_tunnel_rule *rule = &pf->tunnel;
6894         struct i40e_tunnel_filter *tunnel_filter;
6895         int ret;
6896
6897         ret = rte_hash_del_key(rule->hash_table, input);
6898         if (ret < 0) {
6899                 PMD_DRV_LOG(ERR,
6900                             "Failed to delete tunnel filter to hash table %d!",
6901                             ret);
6902                 return ret;
6903         }
6904         tunnel_filter = rule->hash_map[ret];
6905         rule->hash_map[ret] = NULL;
6906
6907         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6908         rte_free(tunnel_filter);
6909
6910         return 0;
6911 }
6912
6913 int
6914 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6915                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6916                         uint8_t add)
6917 {
6918         uint16_t ip_type;
6919         uint32_t ipv4_addr;
6920         uint8_t i, tun_type = 0;
6921         /* internal varialbe to convert ipv6 byte order */
6922         uint32_t convert_ipv6[4];
6923         int val, ret = 0;
6924         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6925         struct i40e_vsi *vsi = pf->main_vsi;
6926         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6927         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6928         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6929         struct i40e_tunnel_filter *tunnel, *node;
6930         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6931
6932         cld_filter = rte_zmalloc("tunnel_filter",
6933                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6934         0);
6935
6936         if (NULL == cld_filter) {
6937                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6938                 return -ENOMEM;
6939         }
6940         pfilter = cld_filter;
6941
6942         ether_addr_copy(&tunnel_filter->outer_mac,
6943                         (struct ether_addr *)&pfilter->element.outer_mac);
6944         ether_addr_copy(&tunnel_filter->inner_mac,
6945                         (struct ether_addr *)&pfilter->element.inner_mac);
6946
6947         pfilter->element.inner_vlan =
6948                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6949         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6950                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6951                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6952                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6953                                 &rte_cpu_to_le_32(ipv4_addr),
6954                                 sizeof(pfilter->element.ipaddr.v4.data));
6955         } else {
6956                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6957                 for (i = 0; i < 4; i++) {
6958                         convert_ipv6[i] =
6959                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6960                 }
6961                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6962                            &convert_ipv6,
6963                            sizeof(pfilter->element.ipaddr.v6.data));
6964         }
6965
6966         /* check tunneled type */
6967         switch (tunnel_filter->tunnel_type) {
6968         case RTE_TUNNEL_TYPE_VXLAN:
6969                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6970                 break;
6971         case RTE_TUNNEL_TYPE_NVGRE:
6972                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6973                 break;
6974         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6975                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6976                 break;
6977         default:
6978                 /* Other tunnel types is not supported. */
6979                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6980                 rte_free(cld_filter);
6981                 return -EINVAL;
6982         }
6983
6984         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6985                                        &pfilter->element.flags);
6986         if (val < 0) {
6987                 rte_free(cld_filter);
6988                 return -EINVAL;
6989         }
6990
6991         pfilter->element.flags |= rte_cpu_to_le_16(
6992                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6993                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6994         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6995         pfilter->element.queue_number =
6996                 rte_cpu_to_le_16(tunnel_filter->queue_id);
6997
6998         /* Check if there is the filter in SW list */
6999         memset(&check_filter, 0, sizeof(check_filter));
7000         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7001         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7002         if (add && node) {
7003                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7004                 return -EINVAL;
7005         }
7006
7007         if (!add && !node) {
7008                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7009                 return -EINVAL;
7010         }
7011
7012         if (add) {
7013                 ret = i40e_aq_add_cloud_filters(hw,
7014                                         vsi->seid, &cld_filter->element, 1);
7015                 if (ret < 0) {
7016                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7017                         return -ENOTSUP;
7018                 }
7019                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7020                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7021                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7022         } else {
7023                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7024                                                    &cld_filter->element, 1);
7025                 if (ret < 0) {
7026                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7027                         return -ENOTSUP;
7028                 }
7029                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7030         }
7031
7032         rte_free(cld_filter);
7033         return ret;
7034 }
7035
7036 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7037 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7038 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7039 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7040 #define I40E_TR_GRE_KEY_MASK                    0x400
7041 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7042 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7043
7044 static enum
7045 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7046 {
7047         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7048         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7049         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7050         enum i40e_status_code status = I40E_SUCCESS;
7051
7052         memset(&filter_replace, 0,
7053                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7054         memset(&filter_replace_buf, 0,
7055                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7056
7057         /* create L1 filter */
7058         filter_replace.old_filter_type =
7059                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7060         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7061         filter_replace.tr_bit = 0;
7062
7063         /* Prepare the buffer, 3 entries */
7064         filter_replace_buf.data[0] =
7065                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7066         filter_replace_buf.data[0] |=
7067                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7068         filter_replace_buf.data[2] = 0xFF;
7069         filter_replace_buf.data[3] = 0xFF;
7070         filter_replace_buf.data[4] =
7071                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7072         filter_replace_buf.data[4] |=
7073                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7074         filter_replace_buf.data[7] = 0xF0;
7075         filter_replace_buf.data[8]
7076                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7077         filter_replace_buf.data[8] |=
7078                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7079         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7080                 I40E_TR_GENEVE_KEY_MASK |
7081                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7082         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7083                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7084                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7085
7086         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7087                                                &filter_replace_buf);
7088         return status;
7089 }
7090
7091 static enum
7092 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7093 {
7094         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7095         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7096         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7097         enum i40e_status_code status = I40E_SUCCESS;
7098
7099         /* For MPLSoUDP */
7100         memset(&filter_replace, 0,
7101                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7102         memset(&filter_replace_buf, 0,
7103                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7104         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7105                 I40E_AQC_MIRROR_CLOUD_FILTER;
7106         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7107         filter_replace.new_filter_type =
7108                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7109         /* Prepare the buffer, 2 entries */
7110         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7111         filter_replace_buf.data[0] |=
7112                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7113         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7114         filter_replace_buf.data[4] |=
7115                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7116         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7117                                                &filter_replace_buf);
7118         if (status < 0)
7119                 return status;
7120
7121         /* For MPLSoGRE */
7122         memset(&filter_replace, 0,
7123                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7124         memset(&filter_replace_buf, 0,
7125                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7126
7127         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7128                 I40E_AQC_MIRROR_CLOUD_FILTER;
7129         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7130         filter_replace.new_filter_type =
7131                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7132         /* Prepare the buffer, 2 entries */
7133         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7134         filter_replace_buf.data[0] |=
7135                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7136         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7137         filter_replace_buf.data[4] |=
7138                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7139
7140         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7141                                                &filter_replace_buf);
7142         return status;
7143 }
7144
7145 int
7146 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7147                       struct i40e_tunnel_filter_conf *tunnel_filter,
7148                       uint8_t add)
7149 {
7150         uint16_t ip_type;
7151         uint32_t ipv4_addr;
7152         uint8_t i, tun_type = 0;
7153         /* internal variable to convert ipv6 byte order */
7154         uint32_t convert_ipv6[4];
7155         int val, ret = 0;
7156         struct i40e_pf_vf *vf = NULL;
7157         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7158         struct i40e_vsi *vsi;
7159         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7160         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7161         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7162         struct i40e_tunnel_filter *tunnel, *node;
7163         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7164         uint32_t teid_le;
7165         bool big_buffer = 0;
7166
7167         cld_filter = rte_zmalloc("tunnel_filter",
7168                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7169                          0);
7170
7171         if (cld_filter == NULL) {
7172                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7173                 return -ENOMEM;
7174         }
7175         pfilter = cld_filter;
7176
7177         ether_addr_copy(&tunnel_filter->outer_mac,
7178                         (struct ether_addr *)&pfilter->element.outer_mac);
7179         ether_addr_copy(&tunnel_filter->inner_mac,
7180                         (struct ether_addr *)&pfilter->element.inner_mac);
7181
7182         pfilter->element.inner_vlan =
7183                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7184         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7185                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7186                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7187                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7188                                 &rte_cpu_to_le_32(ipv4_addr),
7189                                 sizeof(pfilter->element.ipaddr.v4.data));
7190         } else {
7191                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7192                 for (i = 0; i < 4; i++) {
7193                         convert_ipv6[i] =
7194                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7195                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7196                 }
7197                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7198                            &convert_ipv6,
7199                            sizeof(pfilter->element.ipaddr.v6.data));
7200         }
7201
7202         /* check tunneled type */
7203         switch (tunnel_filter->tunnel_type) {
7204         case I40E_TUNNEL_TYPE_VXLAN:
7205                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7206                 break;
7207         case I40E_TUNNEL_TYPE_NVGRE:
7208                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7209                 break;
7210         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7211                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7212                 break;
7213         case I40E_TUNNEL_TYPE_MPLSoUDP:
7214                 if (!pf->mpls_replace_flag) {
7215                         i40e_replace_mpls_l1_filter(pf);
7216                         i40e_replace_mpls_cloud_filter(pf);
7217                         pf->mpls_replace_flag = 1;
7218                 }
7219                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7220                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7221                         teid_le >> 4;
7222                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7223                         (teid_le & 0xF) << 12;
7224                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7225                         0x40;
7226                 big_buffer = 1;
7227                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7228                 break;
7229         case I40E_TUNNEL_TYPE_MPLSoGRE:
7230                 if (!pf->mpls_replace_flag) {
7231                         i40e_replace_mpls_l1_filter(pf);
7232                         i40e_replace_mpls_cloud_filter(pf);
7233                         pf->mpls_replace_flag = 1;
7234                 }
7235                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7236                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7237                         teid_le >> 4;
7238                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7239                         (teid_le & 0xF) << 12;
7240                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7241                         0x0;
7242                 big_buffer = 1;
7243                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7244                 break;
7245         case I40E_TUNNEL_TYPE_QINQ:
7246                 if (!pf->qinq_replace_flag) {
7247                         ret = i40e_cloud_filter_qinq_create(pf);
7248                         if (ret < 0)
7249                                 PMD_DRV_LOG(DEBUG,
7250                                             "QinQ tunnel filter already created.");
7251                         pf->qinq_replace_flag = 1;
7252                 }
7253                 /*      Add in the General fields the values of
7254                  *      the Outer and Inner VLAN
7255                  *      Big Buffer should be set, see changes in
7256                  *      i40e_aq_add_cloud_filters
7257                  */
7258                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7259                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7260                 big_buffer = 1;
7261                 break;
7262         default:
7263                 /* Other tunnel types is not supported. */
7264                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7265                 rte_free(cld_filter);
7266                 return -EINVAL;
7267         }
7268
7269         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7270                 pfilter->element.flags =
7271                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7272         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7273                 pfilter->element.flags =
7274                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7275         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7276                 pfilter->element.flags |=
7277                         I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7278         else {
7279                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7280                                                 &pfilter->element.flags);
7281                 if (val < 0) {
7282                         rte_free(cld_filter);
7283                         return -EINVAL;
7284                 }
7285         }
7286
7287         pfilter->element.flags |= rte_cpu_to_le_16(
7288                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7289                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7290         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7291         pfilter->element.queue_number =
7292                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7293
7294         if (!tunnel_filter->is_to_vf)
7295                 vsi = pf->main_vsi;
7296         else {
7297                 if (tunnel_filter->vf_id >= pf->vf_num) {
7298                         PMD_DRV_LOG(ERR, "Invalid argument.");
7299                         return -EINVAL;
7300                 }
7301                 vf = &pf->vfs[tunnel_filter->vf_id];
7302                 vsi = vf->vsi;
7303         }
7304
7305         /* Check if there is the filter in SW list */
7306         memset(&check_filter, 0, sizeof(check_filter));
7307         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7308         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7309         check_filter.vf_id = tunnel_filter->vf_id;
7310         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7311         if (add && node) {
7312                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7313                 return -EINVAL;
7314         }
7315
7316         if (!add && !node) {
7317                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7318                 return -EINVAL;
7319         }
7320
7321         if (add) {
7322                 if (big_buffer)
7323                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7324                                                    vsi->seid, cld_filter, 1);
7325                 else
7326                         ret = i40e_aq_add_cloud_filters(hw,
7327                                         vsi->seid, &cld_filter->element, 1);
7328                 if (ret < 0) {
7329                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7330                         return -ENOTSUP;
7331                 }
7332                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7333                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7334                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7335         } else {
7336                 if (big_buffer)
7337                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7338                                 hw, vsi->seid, cld_filter, 1);
7339                 else
7340                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7341                                                    &cld_filter->element, 1);
7342                 if (ret < 0) {
7343                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7344                         return -ENOTSUP;
7345                 }
7346                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7347         }
7348
7349         rte_free(cld_filter);
7350         return ret;
7351 }
7352
7353 static int
7354 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7355 {
7356         uint8_t i;
7357
7358         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7359                 if (pf->vxlan_ports[i] == port)
7360                         return i;
7361         }
7362
7363         return -1;
7364 }
7365
7366 static int
7367 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7368 {
7369         int  idx, ret;
7370         uint8_t filter_idx;
7371         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7372
7373         idx = i40e_get_vxlan_port_idx(pf, port);
7374
7375         /* Check if port already exists */
7376         if (idx >= 0) {
7377                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7378                 return -EINVAL;
7379         }
7380
7381         /* Now check if there is space to add the new port */
7382         idx = i40e_get_vxlan_port_idx(pf, 0);
7383         if (idx < 0) {
7384                 PMD_DRV_LOG(ERR,
7385                         "Maximum number of UDP ports reached, not adding port %d",
7386                         port);
7387                 return -ENOSPC;
7388         }
7389
7390         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7391                                         &filter_idx, NULL);
7392         if (ret < 0) {
7393                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7394                 return -1;
7395         }
7396
7397         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7398                          port,  filter_idx);
7399
7400         /* New port: add it and mark its index in the bitmap */
7401         pf->vxlan_ports[idx] = port;
7402         pf->vxlan_bitmap |= (1 << idx);
7403
7404         if (!(pf->flags & I40E_FLAG_VXLAN))
7405                 pf->flags |= I40E_FLAG_VXLAN;
7406
7407         return 0;
7408 }
7409
7410 static int
7411 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7412 {
7413         int idx;
7414         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7415
7416         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7417                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7418                 return -EINVAL;
7419         }
7420
7421         idx = i40e_get_vxlan_port_idx(pf, port);
7422
7423         if (idx < 0) {
7424                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7425                 return -EINVAL;
7426         }
7427
7428         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7429                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7430                 return -1;
7431         }
7432
7433         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7434                         port, idx);
7435
7436         pf->vxlan_ports[idx] = 0;
7437         pf->vxlan_bitmap &= ~(1 << idx);
7438
7439         if (!pf->vxlan_bitmap)
7440                 pf->flags &= ~I40E_FLAG_VXLAN;
7441
7442         return 0;
7443 }
7444
7445 /* Add UDP tunneling port */
7446 static int
7447 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7448                              struct rte_eth_udp_tunnel *udp_tunnel)
7449 {
7450         int ret = 0;
7451         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7452
7453         if (udp_tunnel == NULL)
7454                 return -EINVAL;
7455
7456         switch (udp_tunnel->prot_type) {
7457         case RTE_TUNNEL_TYPE_VXLAN:
7458                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7459                 break;
7460
7461         case RTE_TUNNEL_TYPE_GENEVE:
7462         case RTE_TUNNEL_TYPE_TEREDO:
7463                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7464                 ret = -1;
7465                 break;
7466
7467         default:
7468                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7469                 ret = -1;
7470                 break;
7471         }
7472
7473         return ret;
7474 }
7475
7476 /* Remove UDP tunneling port */
7477 static int
7478 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7479                              struct rte_eth_udp_tunnel *udp_tunnel)
7480 {
7481         int ret = 0;
7482         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7483
7484         if (udp_tunnel == NULL)
7485                 return -EINVAL;
7486
7487         switch (udp_tunnel->prot_type) {
7488         case RTE_TUNNEL_TYPE_VXLAN:
7489                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7490                 break;
7491         case RTE_TUNNEL_TYPE_GENEVE:
7492         case RTE_TUNNEL_TYPE_TEREDO:
7493                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7494                 ret = -1;
7495                 break;
7496         default:
7497                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7498                 ret = -1;
7499                 break;
7500         }
7501
7502         return ret;
7503 }
7504
7505 /* Calculate the maximum number of contiguous PF queues that are configured */
7506 static int
7507 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7508 {
7509         struct rte_eth_dev_data *data = pf->dev_data;
7510         int i, num;
7511         struct i40e_rx_queue *rxq;
7512
7513         num = 0;
7514         for (i = 0; i < pf->lan_nb_qps; i++) {
7515                 rxq = data->rx_queues[i];
7516                 if (rxq && rxq->q_set)
7517                         num++;
7518                 else
7519                         break;
7520         }
7521
7522         return num;
7523 }
7524
7525 /* Configure RSS */
7526 static int
7527 i40e_pf_config_rss(struct i40e_pf *pf)
7528 {
7529         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7530         struct rte_eth_rss_conf rss_conf;
7531         uint32_t i, lut = 0;
7532         uint16_t j, num;
7533
7534         /*
7535          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7536          * It's necessary to calculate the actual PF queues that are configured.
7537          */
7538         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7539                 num = i40e_pf_calc_configured_queues_num(pf);
7540         else
7541                 num = pf->dev_data->nb_rx_queues;
7542
7543         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7544         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7545                         num);
7546
7547         if (num == 0) {
7548                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7549                 return -ENOTSUP;
7550         }
7551
7552         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7553                 if (j == num)
7554                         j = 0;
7555                 lut = (lut << 8) | (j & ((0x1 <<
7556                         hw->func_caps.rss_table_entry_width) - 1));
7557                 if ((i & 3) == 3)
7558                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7559         }
7560
7561         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7562         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7563                 i40e_pf_disable_rss(pf);
7564                 return 0;
7565         }
7566         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7567                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7568                 /* Random default keys */
7569                 static uint32_t rss_key_default[] = {0x6b793944,
7570                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7571                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7572                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7573
7574                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7575                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7576                                                         sizeof(uint32_t);
7577         }
7578
7579         return i40e_hw_rss_hash_set(pf, &rss_conf);
7580 }
7581
7582 static int
7583 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7584                                struct rte_eth_tunnel_filter_conf *filter)
7585 {
7586         if (pf == NULL || filter == NULL) {
7587                 PMD_DRV_LOG(ERR, "Invalid parameter");
7588                 return -EINVAL;
7589         }
7590
7591         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7592                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7593                 return -EINVAL;
7594         }
7595
7596         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7597                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7598                 return -EINVAL;
7599         }
7600
7601         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7602                 (is_zero_ether_addr(&filter->outer_mac))) {
7603                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7604                 return -EINVAL;
7605         }
7606
7607         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7608                 (is_zero_ether_addr(&filter->inner_mac))) {
7609                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7610                 return -EINVAL;
7611         }
7612
7613         return 0;
7614 }
7615
7616 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7617 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7618 static int
7619 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7620 {
7621         uint32_t val, reg;
7622         int ret = -EINVAL;
7623
7624         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7625         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7626
7627         if (len == 3) {
7628                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7629         } else if (len == 4) {
7630                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7631         } else {
7632                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7633                 return ret;
7634         }
7635
7636         if (reg != val) {
7637                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7638                                                    reg, NULL);
7639                 if (ret != 0)
7640                         return ret;
7641         } else {
7642                 ret = 0;
7643         }
7644         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7645                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7646
7647         return ret;
7648 }
7649
7650 static int
7651 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7652 {
7653         int ret = -EINVAL;
7654
7655         if (!hw || !cfg)
7656                 return -EINVAL;
7657
7658         switch (cfg->cfg_type) {
7659         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7660                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7661                 break;
7662         default:
7663                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7664                 break;
7665         }
7666
7667         return ret;
7668 }
7669
7670 static int
7671 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7672                                enum rte_filter_op filter_op,
7673                                void *arg)
7674 {
7675         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7676         int ret = I40E_ERR_PARAM;
7677
7678         switch (filter_op) {
7679         case RTE_ETH_FILTER_SET:
7680                 ret = i40e_dev_global_config_set(hw,
7681                         (struct rte_eth_global_cfg *)arg);
7682                 break;
7683         default:
7684                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7685                 break;
7686         }
7687
7688         return ret;
7689 }
7690
7691 static int
7692 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7693                           enum rte_filter_op filter_op,
7694                           void *arg)
7695 {
7696         struct rte_eth_tunnel_filter_conf *filter;
7697         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7698         int ret = I40E_SUCCESS;
7699
7700         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7701
7702         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7703                 return I40E_ERR_PARAM;
7704
7705         switch (filter_op) {
7706         case RTE_ETH_FILTER_NOP:
7707                 if (!(pf->flags & I40E_FLAG_VXLAN))
7708                         ret = I40E_NOT_SUPPORTED;
7709                 break;
7710         case RTE_ETH_FILTER_ADD:
7711                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7712                 break;
7713         case RTE_ETH_FILTER_DELETE:
7714                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7715                 break;
7716         default:
7717                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7718                 ret = I40E_ERR_PARAM;
7719                 break;
7720         }
7721
7722         return ret;
7723 }
7724
7725 static int
7726 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7727 {
7728         int ret = 0;
7729         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7730
7731         /* RSS setup */
7732         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7733                 ret = i40e_pf_config_rss(pf);
7734         else
7735                 i40e_pf_disable_rss(pf);
7736
7737         return ret;
7738 }
7739
7740 /* Get the symmetric hash enable configurations per port */
7741 static void
7742 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7743 {
7744         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7745
7746         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7747 }
7748
7749 /* Set the symmetric hash enable configurations per port */
7750 static void
7751 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7752 {
7753         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7754
7755         if (enable > 0) {
7756                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7757                         PMD_DRV_LOG(INFO,
7758                                 "Symmetric hash has already been enabled");
7759                         return;
7760                 }
7761                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7762         } else {
7763                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7764                         PMD_DRV_LOG(INFO,
7765                                 "Symmetric hash has already been disabled");
7766                         return;
7767                 }
7768                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7769         }
7770         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7771         I40E_WRITE_FLUSH(hw);
7772 }
7773
7774 /*
7775  * Get global configurations of hash function type and symmetric hash enable
7776  * per flow type (pctype). Note that global configuration means it affects all
7777  * the ports on the same NIC.
7778  */
7779 static int
7780 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7781                                    struct rte_eth_hash_global_conf *g_cfg)
7782 {
7783         uint32_t reg, mask = I40E_FLOW_TYPES;
7784         uint16_t i;
7785         enum i40e_filter_pctype pctype;
7786
7787         memset(g_cfg, 0, sizeof(*g_cfg));
7788         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7789         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7790                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7791         else
7792                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7793         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7794                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7795
7796         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7797                 if (!(mask & (1UL << i)))
7798                         continue;
7799                 mask &= ~(1UL << i);
7800                 /* Bit set indicats the coresponding flow type is supported */
7801                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7802                 /* if flowtype is invalid, continue */
7803                 if (!I40E_VALID_FLOW(i))
7804                         continue;
7805                 pctype = i40e_flowtype_to_pctype(i);
7806                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7807                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7808                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7809         }
7810
7811         return 0;
7812 }
7813
7814 static int
7815 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7816 {
7817         uint32_t i;
7818         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7819
7820         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7821                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7822                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7823                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7824                                                 g_cfg->hash_func);
7825                 return -EINVAL;
7826         }
7827
7828         /*
7829          * As i40e supports less than 32 flow types, only first 32 bits need to
7830          * be checked.
7831          */
7832         mask0 = g_cfg->valid_bit_mask[0];
7833         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7834                 if (i == 0) {
7835                         /* Check if any unsupported flow type configured */
7836                         if ((mask0 | i40e_mask) ^ i40e_mask)
7837                                 goto mask_err;
7838                 } else {
7839                         if (g_cfg->valid_bit_mask[i])
7840                                 goto mask_err;
7841                 }
7842         }
7843
7844         return 0;
7845
7846 mask_err:
7847         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7848
7849         return -EINVAL;
7850 }
7851
7852 /*
7853  * Set global configurations of hash function type and symmetric hash enable
7854  * per flow type (pctype). Note any modifying global configuration will affect
7855  * all the ports on the same NIC.
7856  */
7857 static int
7858 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7859                                    struct rte_eth_hash_global_conf *g_cfg)
7860 {
7861         int ret;
7862         uint16_t i;
7863         uint32_t reg;
7864         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7865         enum i40e_filter_pctype pctype;
7866
7867         /* Check the input parameters */
7868         ret = i40e_hash_global_config_check(g_cfg);
7869         if (ret < 0)
7870                 return ret;
7871
7872         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7873                 if (!(mask0 & (1UL << i)))
7874                         continue;
7875                 mask0 &= ~(1UL << i);
7876                 /* if flowtype is invalid, continue */
7877                 if (!I40E_VALID_FLOW(i))
7878                         continue;
7879                 pctype = i40e_flowtype_to_pctype(i);
7880                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7881                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7882                 if (hw->mac.type == I40E_MAC_X722) {
7883                         if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7884                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7885                                   I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7886                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7887                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7888                                   reg);
7889                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7890                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7891                                   reg);
7892                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7893                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7894                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7895                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7896                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7897                                   reg);
7898                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7899                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7900                                   I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7901                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7902                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7903                                   reg);
7904                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7905                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7906                                   reg);
7907                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7908                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7909                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7910                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7911                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7912                                   reg);
7913                         } else {
7914                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7915                                   reg);
7916                         }
7917                 } else {
7918                         i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7919                 }
7920         }
7921
7922         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7923         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7924                 /* Toeplitz */
7925                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7926                         PMD_DRV_LOG(DEBUG,
7927                                 "Hash function already set to Toeplitz");
7928                         goto out;
7929                 }
7930                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7931         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7932                 /* Simple XOR */
7933                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7934                         PMD_DRV_LOG(DEBUG,
7935                                 "Hash function already set to Simple XOR");
7936                         goto out;
7937                 }
7938                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7939         } else
7940                 /* Use the default, and keep it as it is */
7941                 goto out;
7942
7943         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7944
7945 out:
7946         I40E_WRITE_FLUSH(hw);
7947
7948         return 0;
7949 }
7950
7951 /**
7952  * Valid input sets for hash and flow director filters per PCTYPE
7953  */
7954 static uint64_t
7955 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7956                 enum rte_filter_type filter)
7957 {
7958         uint64_t valid;
7959
7960         static const uint64_t valid_hash_inset_table[] = {
7961                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7962                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7963                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7964                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7965                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7966                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7967                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7968                         I40E_INSET_FLEX_PAYLOAD,
7969                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7970                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7971                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7972                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7973                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7974                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7975                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7976                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7977                         I40E_INSET_FLEX_PAYLOAD,
7978                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7979                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7980                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7981                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7982                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7983                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7984                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7985                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7986                         I40E_INSET_FLEX_PAYLOAD,
7987                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7988                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7989                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7990                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7991                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7992                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7993                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7994                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7995                         I40E_INSET_FLEX_PAYLOAD,
7996                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7997                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7998                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7999                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8000                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8001                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8002                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8003                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8004                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8005                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8006                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8007                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8008                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8009                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8010                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8011                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8012                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8013                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8014                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8015                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8016                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8017                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8018                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8019                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8020                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8021                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8022                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8023                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8024                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8025                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8026                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8027                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8028                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8029                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8030                         I40E_INSET_FLEX_PAYLOAD,
8031                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8032                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8033                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8034                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8035                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8036                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8037                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8038                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8039                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8040                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8041                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8042                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8043                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8044                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8045                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8046                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8047                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8048                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8049                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8050                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8051                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8052                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8053                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8054                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8055                         I40E_INSET_FLEX_PAYLOAD,
8056                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8057                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8058                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8059                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8060                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8061                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8062                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8063                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8064                         I40E_INSET_FLEX_PAYLOAD,
8065                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8066                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8067                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8068                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8069                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8070                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8071                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8072                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8073                         I40E_INSET_FLEX_PAYLOAD,
8074                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8075                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8076                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8077                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8078                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8079                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8080                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8081                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8082                         I40E_INSET_FLEX_PAYLOAD,
8083                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8084                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8085                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8086                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8087                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8088                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8089                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8090                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8091                         I40E_INSET_FLEX_PAYLOAD,
8092                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8093                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8094                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8095                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8096                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8097                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8098                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8099                         I40E_INSET_FLEX_PAYLOAD,
8100                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8101                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8102                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8103                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8104                         I40E_INSET_FLEX_PAYLOAD,
8105         };
8106
8107         /**
8108          * Flow director supports only fields defined in
8109          * union rte_eth_fdir_flow.
8110          */
8111         static const uint64_t valid_fdir_inset_table[] = {
8112                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8113                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8114                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8115                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8116                 I40E_INSET_IPV4_TTL,
8117                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8118                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8119                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8120                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8121                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8122                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8123                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8124                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8125                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8126                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8127                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8128                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8129                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8130                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8131                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8132                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8133                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8134                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8135                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8136                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8137                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8138                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8139                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8140                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8141                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8142                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8143                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8144                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8145                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8146                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8147                 I40E_INSET_SCTP_VT,
8148                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8149                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8150                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8151                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8152                 I40E_INSET_IPV4_TTL,
8153                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8154                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8155                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8156                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8157                 I40E_INSET_IPV6_HOP_LIMIT,
8158                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8159                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8160                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8161                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8162                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8163                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8164                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8165                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8166                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8167                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8168                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8169                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8170                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8171                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8172                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8173                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8174                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8175                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8176                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8177                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8178                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8179                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8180                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8181                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8182                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8183                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8184                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8185                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8186                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8187                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8188                 I40E_INSET_SCTP_VT,
8189                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8190                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8191                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8192                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8193                 I40E_INSET_IPV6_HOP_LIMIT,
8194                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8195                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8196                 I40E_INSET_LAST_ETHER_TYPE,
8197         };
8198
8199         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8200                 return 0;
8201         if (filter == RTE_ETH_FILTER_HASH)
8202                 valid = valid_hash_inset_table[pctype];
8203         else
8204                 valid = valid_fdir_inset_table[pctype];
8205
8206         return valid;
8207 }
8208
8209 /**
8210  * Validate if the input set is allowed for a specific PCTYPE
8211  */
8212 int
8213 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8214                 enum rte_filter_type filter, uint64_t inset)
8215 {
8216         uint64_t valid;
8217
8218         valid = i40e_get_valid_input_set(pctype, filter);
8219         if (inset & (~valid))
8220                 return -EINVAL;
8221
8222         return 0;
8223 }
8224
8225 /* default input set fields combination per pctype */
8226 uint64_t
8227 i40e_get_default_input_set(uint16_t pctype)
8228 {
8229         static const uint64_t default_inset_table[] = {
8230                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8231                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8232                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8233                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8234                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8235                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8236                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8237                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8238                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8239                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8240                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8241                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8242                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8243                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8244                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8245                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8246                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8247                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8248                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8249                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8250                         I40E_INSET_SCTP_VT,
8251                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8252                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8253                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8254                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8255                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8256                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8257                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8258                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8259                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8260                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8261                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8262                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8263                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8264                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8265                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8266                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8267                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8268                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8269                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8270                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8271                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8272                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8273                         I40E_INSET_SCTP_VT,
8274                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8275                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8276                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8277                         I40E_INSET_LAST_ETHER_TYPE,
8278         };
8279
8280         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8281                 return 0;
8282
8283         return default_inset_table[pctype];
8284 }
8285
8286 /**
8287  * Parse the input set from index to logical bit masks
8288  */
8289 static int
8290 i40e_parse_input_set(uint64_t *inset,
8291                      enum i40e_filter_pctype pctype,
8292                      enum rte_eth_input_set_field *field,
8293                      uint16_t size)
8294 {
8295         uint16_t i, j;
8296         int ret = -EINVAL;
8297
8298         static const struct {
8299                 enum rte_eth_input_set_field field;
8300                 uint64_t inset;
8301         } inset_convert_table[] = {
8302                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8303                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8304                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8305                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8306                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8307                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8308                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8309                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8310                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8311                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8312                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8313                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8314                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8315                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8316                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8317                         I40E_INSET_IPV6_NEXT_HDR},
8318                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8319                         I40E_INSET_IPV6_HOP_LIMIT},
8320                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8321                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8322                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8323                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8324                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8325                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8326                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8327                         I40E_INSET_SCTP_VT},
8328                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8329                         I40E_INSET_TUNNEL_DMAC},
8330                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8331                         I40E_INSET_VLAN_TUNNEL},
8332                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8333                         I40E_INSET_TUNNEL_ID},
8334                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8335                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8336                         I40E_INSET_FLEX_PAYLOAD_W1},
8337                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8338                         I40E_INSET_FLEX_PAYLOAD_W2},
8339                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8340                         I40E_INSET_FLEX_PAYLOAD_W3},
8341                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8342                         I40E_INSET_FLEX_PAYLOAD_W4},
8343                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8344                         I40E_INSET_FLEX_PAYLOAD_W5},
8345                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8346                         I40E_INSET_FLEX_PAYLOAD_W6},
8347                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8348                         I40E_INSET_FLEX_PAYLOAD_W7},
8349                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8350                         I40E_INSET_FLEX_PAYLOAD_W8},
8351         };
8352
8353         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8354                 return ret;
8355
8356         /* Only one item allowed for default or all */
8357         if (size == 1) {
8358                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8359                         *inset = i40e_get_default_input_set(pctype);
8360                         return 0;
8361                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8362                         *inset = I40E_INSET_NONE;
8363                         return 0;
8364                 }
8365         }
8366
8367         for (i = 0, *inset = 0; i < size; i++) {
8368                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8369                         if (field[i] == inset_convert_table[j].field) {
8370                                 *inset |= inset_convert_table[j].inset;
8371                                 break;
8372                         }
8373                 }
8374
8375                 /* It contains unsupported input set, return immediately */
8376                 if (j == RTE_DIM(inset_convert_table))
8377                         return ret;
8378         }
8379
8380         return 0;
8381 }
8382
8383 /**
8384  * Translate the input set from bit masks to register aware bit masks
8385  * and vice versa
8386  */
8387 uint64_t
8388 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8389 {
8390         uint64_t val = 0;
8391         uint16_t i;
8392
8393         struct inset_map {
8394                 uint64_t inset;
8395                 uint64_t inset_reg;
8396         };
8397
8398         static const struct inset_map inset_map_common[] = {
8399                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8400                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8401                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8402                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8403                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8404                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8405                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8406                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8407                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8408                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8409                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8410                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8411                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8412                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8413                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8414                 {I40E_INSET_TUNNEL_DMAC,
8415                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8416                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8417                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8418                 {I40E_INSET_TUNNEL_SRC_PORT,
8419                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8420                 {I40E_INSET_TUNNEL_DST_PORT,
8421                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8422                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8423                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8424                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8425                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8426                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8427                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8428                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8429                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8430                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8431         };
8432
8433     /* some different registers map in x722*/
8434         static const struct inset_map inset_map_diff_x722[] = {
8435                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8436                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8437                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8438                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8439         };
8440
8441         static const struct inset_map inset_map_diff_not_x722[] = {
8442                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8443                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8444                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8445                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8446         };
8447
8448         if (input == 0)
8449                 return val;
8450
8451         /* Translate input set to register aware inset */
8452         if (type == I40E_MAC_X722) {
8453                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8454                         if (input & inset_map_diff_x722[i].inset)
8455                                 val |= inset_map_diff_x722[i].inset_reg;
8456                 }
8457         } else {
8458                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8459                         if (input & inset_map_diff_not_x722[i].inset)
8460                                 val |= inset_map_diff_not_x722[i].inset_reg;
8461                 }
8462         }
8463
8464         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8465                 if (input & inset_map_common[i].inset)
8466                         val |= inset_map_common[i].inset_reg;
8467         }
8468
8469         return val;
8470 }
8471
8472 int
8473 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8474 {
8475         uint8_t i, idx = 0;
8476         uint64_t inset_need_mask = inset;
8477
8478         static const struct {
8479                 uint64_t inset;
8480                 uint32_t mask;
8481         } inset_mask_map[] = {
8482                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8483                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8484                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8485                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8486                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8487                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8488                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8489                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8490         };
8491
8492         if (!inset || !mask || !nb_elem)
8493                 return 0;
8494
8495         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8496                 /* Clear the inset bit, if no MASK is required,
8497                  * for example proto + ttl
8498                  */
8499                 if ((inset & inset_mask_map[i].inset) ==
8500                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8501                         inset_need_mask &= ~inset_mask_map[i].inset;
8502                 if (!inset_need_mask)
8503                         return 0;
8504         }
8505         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8506                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8507                     inset_mask_map[i].inset) {
8508                         if (idx >= nb_elem) {
8509                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8510                                 return -EINVAL;
8511                         }
8512                         mask[idx] = inset_mask_map[i].mask;
8513                         idx++;
8514                 }
8515         }
8516
8517         return idx;
8518 }
8519
8520 void
8521 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8522 {
8523         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8524
8525         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8526         if (reg != val)
8527                 i40e_write_rx_ctl(hw, addr, val);
8528         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8529                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8530 }
8531
8532 static void
8533 i40e_filter_input_set_init(struct i40e_pf *pf)
8534 {
8535         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8536         enum i40e_filter_pctype pctype;
8537         uint64_t input_set, inset_reg;
8538         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8539         int num, i;
8540
8541         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8542              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8543                 if (hw->mac.type == I40E_MAC_X722) {
8544                         if (!I40E_VALID_PCTYPE_X722(pctype))
8545                                 continue;
8546                 } else {
8547                         if (!I40E_VALID_PCTYPE(pctype))
8548                                 continue;
8549                 }
8550
8551                 input_set = i40e_get_default_input_set(pctype);
8552
8553                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8554                                                    I40E_INSET_MASK_NUM_REG);
8555                 if (num < 0)
8556                         return;
8557                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8558                                         input_set);
8559
8560                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8561                                       (uint32_t)(inset_reg & UINT32_MAX));
8562                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8563                                      (uint32_t)((inset_reg >>
8564                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8565                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8566                                       (uint32_t)(inset_reg & UINT32_MAX));
8567                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8568                                      (uint32_t)((inset_reg >>
8569                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8570
8571                 for (i = 0; i < num; i++) {
8572                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8573                                              mask_reg[i]);
8574                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8575                                              mask_reg[i]);
8576                 }
8577                 /*clear unused mask registers of the pctype */
8578                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8579                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8580                                              0);
8581                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8582                                              0);
8583                 }
8584                 I40E_WRITE_FLUSH(hw);
8585
8586                 /* store the default input set */
8587                 pf->hash_input_set[pctype] = input_set;
8588                 pf->fdir.input_set[pctype] = input_set;
8589         }
8590 }
8591
8592 int
8593 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8594                          struct rte_eth_input_set_conf *conf)
8595 {
8596         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8597         enum i40e_filter_pctype pctype;
8598         uint64_t input_set, inset_reg = 0;
8599         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8600         int ret, i, num;
8601
8602         if (!conf) {
8603                 PMD_DRV_LOG(ERR, "Invalid pointer");
8604                 return -EFAULT;
8605         }
8606         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8607             conf->op != RTE_ETH_INPUT_SET_ADD) {
8608                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8609                 return -EINVAL;
8610         }
8611
8612         if (!I40E_VALID_FLOW(conf->flow_type)) {
8613                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8614                 return -EINVAL;
8615         }
8616
8617         if (hw->mac.type == I40E_MAC_X722) {
8618                 /* get translated pctype value in fd pctype register */
8619                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8620                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8621                         conf->flow_type)));
8622         } else
8623                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8624
8625         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8626                                    conf->inset_size);
8627         if (ret) {
8628                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8629                 return -EINVAL;
8630         }
8631         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8632                                     input_set) != 0) {
8633                 PMD_DRV_LOG(ERR, "Invalid input set");
8634                 return -EINVAL;
8635         }
8636         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8637                 /* get inset value in register */
8638                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8639                 inset_reg <<= I40E_32_BIT_WIDTH;
8640                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8641                 input_set |= pf->hash_input_set[pctype];
8642         }
8643         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8644                                            I40E_INSET_MASK_NUM_REG);
8645         if (num < 0)
8646                 return -EINVAL;
8647
8648         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8649
8650         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8651                               (uint32_t)(inset_reg & UINT32_MAX));
8652         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8653                              (uint32_t)((inset_reg >>
8654                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8655
8656         for (i = 0; i < num; i++)
8657                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8658                                      mask_reg[i]);
8659         /*clear unused mask registers of the pctype */
8660         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8661                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8662                                      0);
8663         I40E_WRITE_FLUSH(hw);
8664
8665         pf->hash_input_set[pctype] = input_set;
8666         return 0;
8667 }
8668
8669 int
8670 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8671                          struct rte_eth_input_set_conf *conf)
8672 {
8673         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8674         enum i40e_filter_pctype pctype;
8675         uint64_t input_set, inset_reg = 0;
8676         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8677         int ret, i, num;
8678
8679         if (!hw || !conf) {
8680                 PMD_DRV_LOG(ERR, "Invalid pointer");
8681                 return -EFAULT;
8682         }
8683         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8684             conf->op != RTE_ETH_INPUT_SET_ADD) {
8685                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8686                 return -EINVAL;
8687         }
8688
8689         if (!I40E_VALID_FLOW(conf->flow_type)) {
8690                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8691                 return -EINVAL;
8692         }
8693
8694         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8695
8696         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8697                                    conf->inset_size);
8698         if (ret) {
8699                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8700                 return -EINVAL;
8701         }
8702         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8703                                     input_set) != 0) {
8704                 PMD_DRV_LOG(ERR, "Invalid input set");
8705                 return -EINVAL;
8706         }
8707
8708         /* get inset value in register */
8709         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8710         inset_reg <<= I40E_32_BIT_WIDTH;
8711         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8712
8713         /* Can not change the inset reg for flex payload for fdir,
8714          * it is done by writing I40E_PRTQF_FD_FLXINSET
8715          * in i40e_set_flex_mask_on_pctype.
8716          */
8717         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8718                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8719         else
8720                 input_set |= pf->fdir.input_set[pctype];
8721         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8722                                            I40E_INSET_MASK_NUM_REG);
8723         if (num < 0)
8724                 return -EINVAL;
8725
8726         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8727
8728         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8729                               (uint32_t)(inset_reg & UINT32_MAX));
8730         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8731                              (uint32_t)((inset_reg >>
8732                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8733
8734         for (i = 0; i < num; i++)
8735                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8736                                      mask_reg[i]);
8737         /*clear unused mask registers of the pctype */
8738         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8739                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8740                                      0);
8741         I40E_WRITE_FLUSH(hw);
8742
8743         pf->fdir.input_set[pctype] = input_set;
8744         return 0;
8745 }
8746
8747 static int
8748 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8749 {
8750         int ret = 0;
8751
8752         if (!hw || !info) {
8753                 PMD_DRV_LOG(ERR, "Invalid pointer");
8754                 return -EFAULT;
8755         }
8756
8757         switch (info->info_type) {
8758         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8759                 i40e_get_symmetric_hash_enable_per_port(hw,
8760                                         &(info->info.enable));
8761                 break;
8762         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8763                 ret = i40e_get_hash_filter_global_config(hw,
8764                                 &(info->info.global_conf));
8765                 break;
8766         default:
8767                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8768                                                         info->info_type);
8769                 ret = -EINVAL;
8770                 break;
8771         }
8772
8773         return ret;
8774 }
8775
8776 static int
8777 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8778 {
8779         int ret = 0;
8780
8781         if (!hw || !info) {
8782                 PMD_DRV_LOG(ERR, "Invalid pointer");
8783                 return -EFAULT;
8784         }
8785
8786         switch (info->info_type) {
8787         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8788                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8789                 break;
8790         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8791                 ret = i40e_set_hash_filter_global_config(hw,
8792                                 &(info->info.global_conf));
8793                 break;
8794         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8795                 ret = i40e_hash_filter_inset_select(hw,
8796                                                &(info->info.input_set_conf));
8797                 break;
8798
8799         default:
8800                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8801                                                         info->info_type);
8802                 ret = -EINVAL;
8803                 break;
8804         }
8805
8806         return ret;
8807 }
8808
8809 /* Operations for hash function */
8810 static int
8811 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8812                       enum rte_filter_op filter_op,
8813                       void *arg)
8814 {
8815         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8816         int ret = 0;
8817
8818         switch (filter_op) {
8819         case RTE_ETH_FILTER_NOP:
8820                 break;
8821         case RTE_ETH_FILTER_GET:
8822                 ret = i40e_hash_filter_get(hw,
8823                         (struct rte_eth_hash_filter_info *)arg);
8824                 break;
8825         case RTE_ETH_FILTER_SET:
8826                 ret = i40e_hash_filter_set(hw,
8827                         (struct rte_eth_hash_filter_info *)arg);
8828                 break;
8829         default:
8830                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8831                                                                 filter_op);
8832                 ret = -ENOTSUP;
8833                 break;
8834         }
8835
8836         return ret;
8837 }
8838
8839 /* Convert ethertype filter structure */
8840 static int
8841 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8842                               struct i40e_ethertype_filter *filter)
8843 {
8844         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8845         filter->input.ether_type = input->ether_type;
8846         filter->flags = input->flags;
8847         filter->queue = input->queue;
8848
8849         return 0;
8850 }
8851
8852 /* Check if there exists the ehtertype filter */
8853 struct i40e_ethertype_filter *
8854 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8855                                 const struct i40e_ethertype_filter_input *input)
8856 {
8857         int ret;
8858
8859         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8860         if (ret < 0)
8861                 return NULL;
8862
8863         return ethertype_rule->hash_map[ret];
8864 }
8865
8866 /* Add ethertype filter in SW list */
8867 static int
8868 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8869                                 struct i40e_ethertype_filter *filter)
8870 {
8871         struct i40e_ethertype_rule *rule = &pf->ethertype;
8872         int ret;
8873
8874         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8875         if (ret < 0) {
8876                 PMD_DRV_LOG(ERR,
8877                             "Failed to insert ethertype filter"
8878                             " to hash table %d!",
8879                             ret);
8880                 return ret;
8881         }
8882         rule->hash_map[ret] = filter;
8883
8884         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8885
8886         return 0;
8887 }
8888
8889 /* Delete ethertype filter in SW list */
8890 int
8891 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8892                              struct i40e_ethertype_filter_input *input)
8893 {
8894         struct i40e_ethertype_rule *rule = &pf->ethertype;
8895         struct i40e_ethertype_filter *filter;
8896         int ret;
8897
8898         ret = rte_hash_del_key(rule->hash_table, input);
8899         if (ret < 0) {
8900                 PMD_DRV_LOG(ERR,
8901                             "Failed to delete ethertype filter"
8902                             " to hash table %d!",
8903                             ret);
8904                 return ret;
8905         }
8906         filter = rule->hash_map[ret];
8907         rule->hash_map[ret] = NULL;
8908
8909         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8910         rte_free(filter);
8911
8912         return 0;
8913 }
8914
8915 /*
8916  * Configure ethertype filter, which can director packet by filtering
8917  * with mac address and ether_type or only ether_type
8918  */
8919 int
8920 i40e_ethertype_filter_set(struct i40e_pf *pf,
8921                         struct rte_eth_ethertype_filter *filter,
8922                         bool add)
8923 {
8924         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8925         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8926         struct i40e_ethertype_filter *ethertype_filter, *node;
8927         struct i40e_ethertype_filter check_filter;
8928         struct i40e_control_filter_stats stats;
8929         uint16_t flags = 0;
8930         int ret;
8931
8932         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8933                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8934                 return -EINVAL;
8935         }
8936         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8937                 filter->ether_type == ETHER_TYPE_IPv6) {
8938                 PMD_DRV_LOG(ERR,
8939                         "unsupported ether_type(0x%04x) in control packet filter.",
8940                         filter->ether_type);
8941                 return -EINVAL;
8942         }
8943         if (filter->ether_type == ETHER_TYPE_VLAN)
8944                 PMD_DRV_LOG(WARNING,
8945                         "filter vlan ether_type in first tag is not supported.");
8946
8947         /* Check if there is the filter in SW list */
8948         memset(&check_filter, 0, sizeof(check_filter));
8949         i40e_ethertype_filter_convert(filter, &check_filter);
8950         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8951                                                &check_filter.input);
8952         if (add && node) {
8953                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8954                 return -EINVAL;
8955         }
8956
8957         if (!add && !node) {
8958                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8959                 return -EINVAL;
8960         }
8961
8962         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8963                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8964         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8965                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8966         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8967
8968         memset(&stats, 0, sizeof(stats));
8969         ret = i40e_aq_add_rem_control_packet_filter(hw,
8970                         filter->mac_addr.addr_bytes,
8971                         filter->ether_type, flags,
8972                         pf->main_vsi->seid,
8973                         filter->queue, add, &stats, NULL);
8974
8975         PMD_DRV_LOG(INFO,
8976                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8977                 ret, stats.mac_etype_used, stats.etype_used,
8978                 stats.mac_etype_free, stats.etype_free);
8979         if (ret < 0)
8980                 return -ENOSYS;
8981
8982         /* Add or delete a filter in SW list */
8983         if (add) {
8984                 ethertype_filter = rte_zmalloc("ethertype_filter",
8985                                        sizeof(*ethertype_filter), 0);
8986                 rte_memcpy(ethertype_filter, &check_filter,
8987                            sizeof(check_filter));
8988                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8989         } else {
8990                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8991         }
8992
8993         return ret;
8994 }
8995
8996 /*
8997  * Handle operations for ethertype filter.
8998  */
8999 static int
9000 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9001                                 enum rte_filter_op filter_op,
9002                                 void *arg)
9003 {
9004         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9005         int ret = 0;
9006
9007         if (filter_op == RTE_ETH_FILTER_NOP)
9008                 return ret;
9009
9010         if (arg == NULL) {
9011                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9012                             filter_op);
9013                 return -EINVAL;
9014         }
9015
9016         switch (filter_op) {
9017         case RTE_ETH_FILTER_ADD:
9018                 ret = i40e_ethertype_filter_set(pf,
9019                         (struct rte_eth_ethertype_filter *)arg,
9020                         TRUE);
9021                 break;
9022         case RTE_ETH_FILTER_DELETE:
9023                 ret = i40e_ethertype_filter_set(pf,
9024                         (struct rte_eth_ethertype_filter *)arg,
9025                         FALSE);
9026                 break;
9027         default:
9028                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9029                 ret = -ENOSYS;
9030                 break;
9031         }
9032         return ret;
9033 }
9034
9035 static int
9036 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9037                      enum rte_filter_type filter_type,
9038                      enum rte_filter_op filter_op,
9039                      void *arg)
9040 {
9041         int ret = 0;
9042
9043         if (dev == NULL)
9044                 return -EINVAL;
9045
9046         switch (filter_type) {
9047         case RTE_ETH_FILTER_NONE:
9048                 /* For global configuration */
9049                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9050                 break;
9051         case RTE_ETH_FILTER_HASH:
9052                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9053                 break;
9054         case RTE_ETH_FILTER_MACVLAN:
9055                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9056                 break;
9057         case RTE_ETH_FILTER_ETHERTYPE:
9058                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9059                 break;
9060         case RTE_ETH_FILTER_TUNNEL:
9061                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9062                 break;
9063         case RTE_ETH_FILTER_FDIR:
9064                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9065                 break;
9066         case RTE_ETH_FILTER_GENERIC:
9067                 if (filter_op != RTE_ETH_FILTER_GET)
9068                         return -EINVAL;
9069                 *(const void **)arg = &i40e_flow_ops;
9070                 break;
9071         default:
9072                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9073                                                         filter_type);
9074                 ret = -EINVAL;
9075                 break;
9076         }
9077
9078         return ret;
9079 }
9080
9081 /*
9082  * Check and enable Extended Tag.
9083  * Enabling Extended Tag is important for 40G performance.
9084  */
9085 static void
9086 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9087 {
9088         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9089         uint32_t buf = 0;
9090         int ret;
9091
9092         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9093                                       PCI_DEV_CAP_REG);
9094         if (ret < 0) {
9095                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9096                             PCI_DEV_CAP_REG);
9097                 return;
9098         }
9099         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9100                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9101                 return;
9102         }
9103
9104         buf = 0;
9105         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9106                                       PCI_DEV_CTRL_REG);
9107         if (ret < 0) {
9108                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9109                             PCI_DEV_CTRL_REG);
9110                 return;
9111         }
9112         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9113                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9114                 return;
9115         }
9116         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9117         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9118                                        PCI_DEV_CTRL_REG);
9119         if (ret < 0) {
9120                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9121                             PCI_DEV_CTRL_REG);
9122                 return;
9123         }
9124 }
9125
9126 /*
9127  * As some registers wouldn't be reset unless a global hardware reset,
9128  * hardware initialization is needed to put those registers into an
9129  * expected initial state.
9130  */
9131 static void
9132 i40e_hw_init(struct rte_eth_dev *dev)
9133 {
9134         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9135
9136         i40e_enable_extended_tag(dev);
9137
9138         /* clear the PF Queue Filter control register */
9139         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9140
9141         /* Disable symmetric hash per port */
9142         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9143 }
9144
9145 enum i40e_filter_pctype
9146 i40e_flowtype_to_pctype(uint16_t flow_type)
9147 {
9148         static const enum i40e_filter_pctype pctype_table[] = {
9149                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9150                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9151                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9152                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9153                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9154                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9155                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9156                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9157                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9158                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9159                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9160                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9161                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9162                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9163                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9164                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9165                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9166                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9167                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9168         };
9169
9170         return pctype_table[flow_type];
9171 }
9172
9173 uint16_t
9174 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9175 {
9176         static const uint16_t flowtype_table[] = {
9177                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9178                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9179                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9180                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9181                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9182                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9183                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9184                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9185                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9186                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9187                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9188                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9189                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9190                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9191                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9192                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9193                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9194                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9195                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9196                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9197                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9198                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9199                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9200                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9201                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9202                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9203                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9204                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9205                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9206                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9207                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9208         };
9209
9210         return flowtype_table[pctype];
9211 }
9212
9213 /*
9214  * On X710, performance number is far from the expectation on recent firmware
9215  * versions; on XL710, performance number is also far from the expectation on
9216  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9217  * mode is enabled and port MAC address is equal to the packet destination MAC
9218  * address. The fix for this issue may not be integrated in the following
9219  * firmware version. So the workaround in software driver is needed. It needs
9220  * to modify the initial values of 3 internal only registers for both X710 and
9221  * XL710. Note that the values for X710 or XL710 could be different, and the
9222  * workaround can be removed when it is fixed in firmware in the future.
9223  */
9224
9225 /* For both X710 and XL710 */
9226 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9227 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x20000200
9228 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9229
9230 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9231 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9232
9233 /* For X722 */
9234 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9235 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9236
9237 /* For X710 */
9238 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9239 /* For XL710 */
9240 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9241 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9242
9243 static int
9244 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9245 {
9246         enum i40e_status_code status;
9247         struct i40e_aq_get_phy_abilities_resp phy_ab;
9248         int ret = -ENOTSUP;
9249
9250         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9251                                               NULL);
9252
9253         if (status) {
9254                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9255                         status);
9256                 return ret;
9257         }
9258
9259         return 0;
9260 }
9261
9262 static void
9263 i40e_configure_registers(struct i40e_hw *hw)
9264 {
9265         static struct {
9266                 uint32_t addr;
9267                 uint64_t val;
9268         } reg_table[] = {
9269                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9270                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9271                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9272         };
9273         uint64_t reg;
9274         uint32_t i;
9275         int ret;
9276
9277         for (i = 0; i < RTE_DIM(reg_table); i++) {
9278                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9279                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9280                                 reg_table[i].val =
9281                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9282                         else /* For X710/XL710/XXV710 */
9283                                 if (hw->aq.fw_maj_ver < 6)
9284                                         reg_table[i].val =
9285                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9286                                 else
9287                                         reg_table[i].val =
9288                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9289                 }
9290
9291                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9292                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9293                                 reg_table[i].val =
9294                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9295                         else /* For X710/XL710/XXV710 */
9296                                 reg_table[i].val =
9297                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9298                 }
9299
9300                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9301                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9302                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9303                                 reg_table[i].val =
9304                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9305                         else /* For X710 */
9306                                 reg_table[i].val =
9307                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9308                 }
9309
9310                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9311                                                         &reg, NULL);
9312                 if (ret < 0) {
9313                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9314                                                         reg_table[i].addr);
9315                         break;
9316                 }
9317                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9318                                                 reg_table[i].addr, reg);
9319                 if (reg == reg_table[i].val)
9320                         continue;
9321
9322                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9323                                                 reg_table[i].val, NULL);
9324                 if (ret < 0) {
9325                         PMD_DRV_LOG(ERR,
9326                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9327                                 reg_table[i].val, reg_table[i].addr);
9328                         break;
9329                 }
9330                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9331                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9332         }
9333 }
9334
9335 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9336 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9337 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9338 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9339 static int
9340 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9341 {
9342         uint32_t reg;
9343         int ret;
9344
9345         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9346                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9347                 return -EINVAL;
9348         }
9349
9350         /* Configure for double VLAN RX stripping */
9351         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9352         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9353                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9354                 ret = i40e_aq_debug_write_register(hw,
9355                                                    I40E_VSI_TSR(vsi->vsi_id),
9356                                                    reg, NULL);
9357                 if (ret < 0) {
9358                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9359                                     vsi->vsi_id);
9360                         return I40E_ERR_CONFIG;
9361                 }
9362         }
9363
9364         /* Configure for double VLAN TX insertion */
9365         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9366         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9367                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9368                 ret = i40e_aq_debug_write_register(hw,
9369                                                    I40E_VSI_L2TAGSTXVALID(
9370                                                    vsi->vsi_id), reg, NULL);
9371                 if (ret < 0) {
9372                         PMD_DRV_LOG(ERR,
9373                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9374                                 vsi->vsi_id);
9375                         return I40E_ERR_CONFIG;
9376                 }
9377         }
9378
9379         return 0;
9380 }
9381
9382 /**
9383  * i40e_aq_add_mirror_rule
9384  * @hw: pointer to the hardware structure
9385  * @seid: VEB seid to add mirror rule to
9386  * @dst_id: destination vsi seid
9387  * @entries: Buffer which contains the entities to be mirrored
9388  * @count: number of entities contained in the buffer
9389  * @rule_id:the rule_id of the rule to be added
9390  *
9391  * Add a mirror rule for a given veb.
9392  *
9393  **/
9394 static enum i40e_status_code
9395 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9396                         uint16_t seid, uint16_t dst_id,
9397                         uint16_t rule_type, uint16_t *entries,
9398                         uint16_t count, uint16_t *rule_id)
9399 {
9400         struct i40e_aq_desc desc;
9401         struct i40e_aqc_add_delete_mirror_rule cmd;
9402         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9403                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9404                 &desc.params.raw;
9405         uint16_t buff_len;
9406         enum i40e_status_code status;
9407
9408         i40e_fill_default_direct_cmd_desc(&desc,
9409                                           i40e_aqc_opc_add_mirror_rule);
9410         memset(&cmd, 0, sizeof(cmd));
9411
9412         buff_len = sizeof(uint16_t) * count;
9413         desc.datalen = rte_cpu_to_le_16(buff_len);
9414         if (buff_len > 0)
9415                 desc.flags |= rte_cpu_to_le_16(
9416                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9417         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9418                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9419         cmd.num_entries = rte_cpu_to_le_16(count);
9420         cmd.seid = rte_cpu_to_le_16(seid);
9421         cmd.destination = rte_cpu_to_le_16(dst_id);
9422
9423         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9424         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9425         PMD_DRV_LOG(INFO,
9426                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9427                 hw->aq.asq_last_status, resp->rule_id,
9428                 resp->mirror_rules_used, resp->mirror_rules_free);
9429         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9430
9431         return status;
9432 }
9433
9434 /**
9435  * i40e_aq_del_mirror_rule
9436  * @hw: pointer to the hardware structure
9437  * @seid: VEB seid to add mirror rule to
9438  * @entries: Buffer which contains the entities to be mirrored
9439  * @count: number of entities contained in the buffer
9440  * @rule_id:the rule_id of the rule to be delete
9441  *
9442  * Delete a mirror rule for a given veb.
9443  *
9444  **/
9445 static enum i40e_status_code
9446 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9447                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9448                 uint16_t count, uint16_t rule_id)
9449 {
9450         struct i40e_aq_desc desc;
9451         struct i40e_aqc_add_delete_mirror_rule cmd;
9452         uint16_t buff_len = 0;
9453         enum i40e_status_code status;
9454         void *buff = NULL;
9455
9456         i40e_fill_default_direct_cmd_desc(&desc,
9457                                           i40e_aqc_opc_delete_mirror_rule);
9458         memset(&cmd, 0, sizeof(cmd));
9459         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9460                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9461                                                           I40E_AQ_FLAG_RD));
9462                 cmd.num_entries = count;
9463                 buff_len = sizeof(uint16_t) * count;
9464                 desc.datalen = rte_cpu_to_le_16(buff_len);
9465                 buff = (void *)entries;
9466         } else
9467                 /* rule id is filled in destination field for deleting mirror rule */
9468                 cmd.destination = rte_cpu_to_le_16(rule_id);
9469
9470         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9471                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9472         cmd.seid = rte_cpu_to_le_16(seid);
9473
9474         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9475         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9476
9477         return status;
9478 }
9479
9480 /**
9481  * i40e_mirror_rule_set
9482  * @dev: pointer to the hardware structure
9483  * @mirror_conf: mirror rule info
9484  * @sw_id: mirror rule's sw_id
9485  * @on: enable/disable
9486  *
9487  * set a mirror rule.
9488  *
9489  **/
9490 static int
9491 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9492                         struct rte_eth_mirror_conf *mirror_conf,
9493                         uint8_t sw_id, uint8_t on)
9494 {
9495         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9496         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9497         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9498         struct i40e_mirror_rule *parent = NULL;
9499         uint16_t seid, dst_seid, rule_id;
9500         uint16_t i, j = 0;
9501         int ret;
9502
9503         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9504
9505         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9506                 PMD_DRV_LOG(ERR,
9507                         "mirror rule can not be configured without veb or vfs.");
9508                 return -ENOSYS;
9509         }
9510         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9511                 PMD_DRV_LOG(ERR, "mirror table is full.");
9512                 return -ENOSPC;
9513         }
9514         if (mirror_conf->dst_pool > pf->vf_num) {
9515                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9516                                  mirror_conf->dst_pool);
9517                 return -EINVAL;
9518         }
9519
9520         seid = pf->main_vsi->veb->seid;
9521
9522         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9523                 if (sw_id <= it->index) {
9524                         mirr_rule = it;
9525                         break;
9526                 }
9527                 parent = it;
9528         }
9529         if (mirr_rule && sw_id == mirr_rule->index) {
9530                 if (on) {
9531                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9532                         return -EEXIST;
9533                 } else {
9534                         ret = i40e_aq_del_mirror_rule(hw, seid,
9535                                         mirr_rule->rule_type,
9536                                         mirr_rule->entries,
9537                                         mirr_rule->num_entries, mirr_rule->id);
9538                         if (ret < 0) {
9539                                 PMD_DRV_LOG(ERR,
9540                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9541                                         ret, hw->aq.asq_last_status);
9542                                 return -ENOSYS;
9543                         }
9544                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9545                         rte_free(mirr_rule);
9546                         pf->nb_mirror_rule--;
9547                         return 0;
9548                 }
9549         } else if (!on) {
9550                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9551                 return -ENOENT;
9552         }
9553
9554         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9555                                 sizeof(struct i40e_mirror_rule) , 0);
9556         if (!mirr_rule) {
9557                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9558                 return I40E_ERR_NO_MEMORY;
9559         }
9560         switch (mirror_conf->rule_type) {
9561         case ETH_MIRROR_VLAN:
9562                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9563                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9564                                 mirr_rule->entries[j] =
9565                                         mirror_conf->vlan.vlan_id[i];
9566                                 j++;
9567                         }
9568                 }
9569                 if (j == 0) {
9570                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9571                         rte_free(mirr_rule);
9572                         return -EINVAL;
9573                 }
9574                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9575                 break;
9576         case ETH_MIRROR_VIRTUAL_POOL_UP:
9577         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9578                 /* check if the specified pool bit is out of range */
9579                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9580                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9581                         rte_free(mirr_rule);
9582                         return -EINVAL;
9583                 }
9584                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9585                         if (mirror_conf->pool_mask & (1ULL << i)) {
9586                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9587                                 j++;
9588                         }
9589                 }
9590                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9591                         /* add pf vsi to entries */
9592                         mirr_rule->entries[j] = pf->main_vsi_seid;
9593                         j++;
9594                 }
9595                 if (j == 0) {
9596                         PMD_DRV_LOG(ERR, "pool is not specified.");
9597                         rte_free(mirr_rule);
9598                         return -EINVAL;
9599                 }
9600                 /* egress and ingress in aq commands means from switch but not port */
9601                 mirr_rule->rule_type =
9602                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9603                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9604                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9605                 break;
9606         case ETH_MIRROR_UPLINK_PORT:
9607                 /* egress and ingress in aq commands means from switch but not port*/
9608                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9609                 break;
9610         case ETH_MIRROR_DOWNLINK_PORT:
9611                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9612                 break;
9613         default:
9614                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9615                         mirror_conf->rule_type);
9616                 rte_free(mirr_rule);
9617                 return -EINVAL;
9618         }
9619
9620         /* If the dst_pool is equal to vf_num, consider it as PF */
9621         if (mirror_conf->dst_pool == pf->vf_num)
9622                 dst_seid = pf->main_vsi_seid;
9623         else
9624                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9625
9626         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9627                                       mirr_rule->rule_type, mirr_rule->entries,
9628                                       j, &rule_id);
9629         if (ret < 0) {
9630                 PMD_DRV_LOG(ERR,
9631                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9632                         ret, hw->aq.asq_last_status);
9633                 rte_free(mirr_rule);
9634                 return -ENOSYS;
9635         }
9636
9637         mirr_rule->index = sw_id;
9638         mirr_rule->num_entries = j;
9639         mirr_rule->id = rule_id;
9640         mirr_rule->dst_vsi_seid = dst_seid;
9641
9642         if (parent)
9643                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9644         else
9645                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9646
9647         pf->nb_mirror_rule++;
9648         return 0;
9649 }
9650
9651 /**
9652  * i40e_mirror_rule_reset
9653  * @dev: pointer to the device
9654  * @sw_id: mirror rule's sw_id
9655  *
9656  * reset a mirror rule.
9657  *
9658  **/
9659 static int
9660 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9661 {
9662         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9663         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9664         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9665         uint16_t seid;
9666         int ret;
9667
9668         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9669
9670         seid = pf->main_vsi->veb->seid;
9671
9672         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9673                 if (sw_id == it->index) {
9674                         mirr_rule = it;
9675                         break;
9676                 }
9677         }
9678         if (mirr_rule) {
9679                 ret = i40e_aq_del_mirror_rule(hw, seid,
9680                                 mirr_rule->rule_type,
9681                                 mirr_rule->entries,
9682                                 mirr_rule->num_entries, mirr_rule->id);
9683                 if (ret < 0) {
9684                         PMD_DRV_LOG(ERR,
9685                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9686                                 ret, hw->aq.asq_last_status);
9687                         return -ENOSYS;
9688                 }
9689                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9690                 rte_free(mirr_rule);
9691                 pf->nb_mirror_rule--;
9692         } else {
9693                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9694                 return -ENOENT;
9695         }
9696         return 0;
9697 }
9698
9699 static uint64_t
9700 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9701 {
9702         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9703         uint64_t systim_cycles;
9704
9705         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9706         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9707                         << 32;
9708
9709         return systim_cycles;
9710 }
9711
9712 static uint64_t
9713 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9714 {
9715         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9716         uint64_t rx_tstamp;
9717
9718         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9719         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9720                         << 32;
9721
9722         return rx_tstamp;
9723 }
9724
9725 static uint64_t
9726 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9727 {
9728         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9729         uint64_t tx_tstamp;
9730
9731         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9732         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9733                         << 32;
9734
9735         return tx_tstamp;
9736 }
9737
9738 static void
9739 i40e_start_timecounters(struct rte_eth_dev *dev)
9740 {
9741         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9742         struct i40e_adapter *adapter =
9743                         (struct i40e_adapter *)dev->data->dev_private;
9744         struct rte_eth_link link;
9745         uint32_t tsync_inc_l;
9746         uint32_t tsync_inc_h;
9747
9748         /* Get current link speed. */
9749         memset(&link, 0, sizeof(link));
9750         i40e_dev_link_update(dev, 1);
9751         rte_i40e_dev_atomic_read_link_status(dev, &link);
9752
9753         switch (link.link_speed) {
9754         case ETH_SPEED_NUM_40G:
9755                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9756                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9757                 break;
9758         case ETH_SPEED_NUM_10G:
9759                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9760                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9761                 break;
9762         case ETH_SPEED_NUM_1G:
9763                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9764                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9765                 break;
9766         default:
9767                 tsync_inc_l = 0x0;
9768                 tsync_inc_h = 0x0;
9769         }
9770
9771         /* Set the timesync increment value. */
9772         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9773         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9774
9775         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9776         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9777         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9778
9779         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9780         adapter->systime_tc.cc_shift = 0;
9781         adapter->systime_tc.nsec_mask = 0;
9782
9783         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9784         adapter->rx_tstamp_tc.cc_shift = 0;
9785         adapter->rx_tstamp_tc.nsec_mask = 0;
9786
9787         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9788         adapter->tx_tstamp_tc.cc_shift = 0;
9789         adapter->tx_tstamp_tc.nsec_mask = 0;
9790 }
9791
9792 static int
9793 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9794 {
9795         struct i40e_adapter *adapter =
9796                         (struct i40e_adapter *)dev->data->dev_private;
9797
9798         adapter->systime_tc.nsec += delta;
9799         adapter->rx_tstamp_tc.nsec += delta;
9800         adapter->tx_tstamp_tc.nsec += delta;
9801
9802         return 0;
9803 }
9804
9805 static int
9806 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9807 {
9808         uint64_t ns;
9809         struct i40e_adapter *adapter =
9810                         (struct i40e_adapter *)dev->data->dev_private;
9811
9812         ns = rte_timespec_to_ns(ts);
9813
9814         /* Set the timecounters to a new value. */
9815         adapter->systime_tc.nsec = ns;
9816         adapter->rx_tstamp_tc.nsec = ns;
9817         adapter->tx_tstamp_tc.nsec = ns;
9818
9819         return 0;
9820 }
9821
9822 static int
9823 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9824 {
9825         uint64_t ns, systime_cycles;
9826         struct i40e_adapter *adapter =
9827                         (struct i40e_adapter *)dev->data->dev_private;
9828
9829         systime_cycles = i40e_read_systime_cyclecounter(dev);
9830         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9831         *ts = rte_ns_to_timespec(ns);
9832
9833         return 0;
9834 }
9835
9836 static int
9837 i40e_timesync_enable(struct rte_eth_dev *dev)
9838 {
9839         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9840         uint32_t tsync_ctl_l;
9841         uint32_t tsync_ctl_h;
9842
9843         /* Stop the timesync system time. */
9844         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9845         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9846         /* Reset the timesync system time value. */
9847         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9848         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9849
9850         i40e_start_timecounters(dev);
9851
9852         /* Clear timesync registers. */
9853         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9854         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9855         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9856         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9857         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9858         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9859
9860         /* Enable timestamping of PTP packets. */
9861         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9862         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9863
9864         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9865         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9866         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9867
9868         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9869         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9870
9871         return 0;
9872 }
9873
9874 static int
9875 i40e_timesync_disable(struct rte_eth_dev *dev)
9876 {
9877         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9878         uint32_t tsync_ctl_l;
9879         uint32_t tsync_ctl_h;
9880
9881         /* Disable timestamping of transmitted PTP packets. */
9882         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9883         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9884
9885         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9886         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9887
9888         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9889         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9890
9891         /* Reset the timesync increment value. */
9892         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9893         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9894
9895         return 0;
9896 }
9897
9898 static int
9899 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9900                                 struct timespec *timestamp, uint32_t flags)
9901 {
9902         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9903         struct i40e_adapter *adapter =
9904                 (struct i40e_adapter *)dev->data->dev_private;
9905
9906         uint32_t sync_status;
9907         uint32_t index = flags & 0x03;
9908         uint64_t rx_tstamp_cycles;
9909         uint64_t ns;
9910
9911         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9912         if ((sync_status & (1 << index)) == 0)
9913                 return -EINVAL;
9914
9915         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9916         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9917         *timestamp = rte_ns_to_timespec(ns);
9918
9919         return 0;
9920 }
9921
9922 static int
9923 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9924                                 struct timespec *timestamp)
9925 {
9926         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9927         struct i40e_adapter *adapter =
9928                 (struct i40e_adapter *)dev->data->dev_private;
9929
9930         uint32_t sync_status;
9931         uint64_t tx_tstamp_cycles;
9932         uint64_t ns;
9933
9934         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9935         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9936                 return -EINVAL;
9937
9938         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9939         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9940         *timestamp = rte_ns_to_timespec(ns);
9941
9942         return 0;
9943 }
9944
9945 /*
9946  * i40e_parse_dcb_configure - parse dcb configure from user
9947  * @dev: the device being configured
9948  * @dcb_cfg: pointer of the result of parse
9949  * @*tc_map: bit map of enabled traffic classes
9950  *
9951  * Returns 0 on success, negative value on failure
9952  */
9953 static int
9954 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9955                          struct i40e_dcbx_config *dcb_cfg,
9956                          uint8_t *tc_map)
9957 {
9958         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9959         uint8_t i, tc_bw, bw_lf;
9960
9961         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9962
9963         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9964         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9965                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9966                 return -EINVAL;
9967         }
9968
9969         /* assume each tc has the same bw */
9970         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9971         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9972                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9973         /* to ensure the sum of tcbw is equal to 100 */
9974         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9975         for (i = 0; i < bw_lf; i++)
9976                 dcb_cfg->etscfg.tcbwtable[i]++;
9977
9978         /* assume each tc has the same Transmission Selection Algorithm */
9979         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9980                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9981
9982         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9983                 dcb_cfg->etscfg.prioritytable[i] =
9984                                 dcb_rx_conf->dcb_tc[i];
9985
9986         /* FW needs one App to configure HW */
9987         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9988         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9989         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9990         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9991
9992         if (dcb_rx_conf->nb_tcs == 0)
9993                 *tc_map = 1; /* tc0 only */
9994         else
9995                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9996
9997         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9998                 dcb_cfg->pfc.willing = 0;
9999                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10000                 dcb_cfg->pfc.pfcenable = *tc_map;
10001         }
10002         return 0;
10003 }
10004
10005
10006 static enum i40e_status_code
10007 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10008                               struct i40e_aqc_vsi_properties_data *info,
10009                               uint8_t enabled_tcmap)
10010 {
10011         enum i40e_status_code ret;
10012         int i, total_tc = 0;
10013         uint16_t qpnum_per_tc, bsf, qp_idx;
10014         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10015         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10016         uint16_t used_queues;
10017
10018         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10019         if (ret != I40E_SUCCESS)
10020                 return ret;
10021
10022         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10023                 if (enabled_tcmap & (1 << i))
10024                         total_tc++;
10025         }
10026         if (total_tc == 0)
10027                 total_tc = 1;
10028         vsi->enabled_tc = enabled_tcmap;
10029
10030         /* different VSI has different queues assigned */
10031         if (vsi->type == I40E_VSI_MAIN)
10032                 used_queues = dev_data->nb_rx_queues -
10033                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10034         else if (vsi->type == I40E_VSI_VMDQ2)
10035                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10036         else {
10037                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10038                 return I40E_ERR_NO_AVAILABLE_VSI;
10039         }
10040
10041         qpnum_per_tc = used_queues / total_tc;
10042         /* Number of queues per enabled TC */
10043         if (qpnum_per_tc == 0) {
10044                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10045                 return I40E_ERR_INVALID_QP_ID;
10046         }
10047         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10048                                 I40E_MAX_Q_PER_TC);
10049         bsf = rte_bsf32(qpnum_per_tc);
10050
10051         /**
10052          * Configure TC and queue mapping parameters, for enabled TC,
10053          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10054          * default queue will serve it.
10055          */
10056         qp_idx = 0;
10057         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10058                 if (vsi->enabled_tc & (1 << i)) {
10059                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10060                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10061                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10062                         qp_idx += qpnum_per_tc;
10063                 } else
10064                         info->tc_mapping[i] = 0;
10065         }
10066
10067         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10068         if (vsi->type == I40E_VSI_SRIOV) {
10069                 info->mapping_flags |=
10070                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10071                 for (i = 0; i < vsi->nb_qps; i++)
10072                         info->queue_mapping[i] =
10073                                 rte_cpu_to_le_16(vsi->base_queue + i);
10074         } else {
10075                 info->mapping_flags |=
10076                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10077                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10078         }
10079         info->valid_sections |=
10080                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10081
10082         return I40E_SUCCESS;
10083 }
10084
10085 /*
10086  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10087  * @veb: VEB to be configured
10088  * @tc_map: enabled TC bitmap
10089  *
10090  * Returns 0 on success, negative value on failure
10091  */
10092 static enum i40e_status_code
10093 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10094 {
10095         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10096         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10097         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10098         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10099         enum i40e_status_code ret = I40E_SUCCESS;
10100         int i;
10101         uint32_t bw_max;
10102
10103         /* Check if enabled_tc is same as existing or new TCs */
10104         if (veb->enabled_tc == tc_map)
10105                 return ret;
10106
10107         /* configure tc bandwidth */
10108         memset(&veb_bw, 0, sizeof(veb_bw));
10109         veb_bw.tc_valid_bits = tc_map;
10110         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10111         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10112                 if (tc_map & BIT_ULL(i))
10113                         veb_bw.tc_bw_share_credits[i] = 1;
10114         }
10115         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10116                                                    &veb_bw, NULL);
10117         if (ret) {
10118                 PMD_INIT_LOG(ERR,
10119                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10120                         hw->aq.asq_last_status);
10121                 return ret;
10122         }
10123
10124         memset(&ets_query, 0, sizeof(ets_query));
10125         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10126                                                    &ets_query, NULL);
10127         if (ret != I40E_SUCCESS) {
10128                 PMD_DRV_LOG(ERR,
10129                         "Failed to get switch_comp ETS configuration %u",
10130                         hw->aq.asq_last_status);
10131                 return ret;
10132         }
10133         memset(&bw_query, 0, sizeof(bw_query));
10134         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10135                                                   &bw_query, NULL);
10136         if (ret != I40E_SUCCESS) {
10137                 PMD_DRV_LOG(ERR,
10138                         "Failed to get switch_comp bandwidth configuration %u",
10139                         hw->aq.asq_last_status);
10140                 return ret;
10141         }
10142
10143         /* store and print out BW info */
10144         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10145         veb->bw_info.bw_max = ets_query.tc_bw_max;
10146         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10147         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10148         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10149                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10150                      I40E_16_BIT_WIDTH);
10151         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10152                 veb->bw_info.bw_ets_share_credits[i] =
10153                                 bw_query.tc_bw_share_credits[i];
10154                 veb->bw_info.bw_ets_credits[i] =
10155                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10156                 /* 4 bits per TC, 4th bit is reserved */
10157                 veb->bw_info.bw_ets_max[i] =
10158                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10159                                   RTE_LEN2MASK(3, uint8_t));
10160                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10161                             veb->bw_info.bw_ets_share_credits[i]);
10162                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10163                             veb->bw_info.bw_ets_credits[i]);
10164                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10165                             veb->bw_info.bw_ets_max[i]);
10166         }
10167
10168         veb->enabled_tc = tc_map;
10169
10170         return ret;
10171 }
10172
10173
10174 /*
10175  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10176  * @vsi: VSI to be configured
10177  * @tc_map: enabled TC bitmap
10178  *
10179  * Returns 0 on success, negative value on failure
10180  */
10181 static enum i40e_status_code
10182 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10183 {
10184         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10185         struct i40e_vsi_context ctxt;
10186         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10187         enum i40e_status_code ret = I40E_SUCCESS;
10188         int i;
10189
10190         /* Check if enabled_tc is same as existing or new TCs */
10191         if (vsi->enabled_tc == tc_map)
10192                 return ret;
10193
10194         /* configure tc bandwidth */
10195         memset(&bw_data, 0, sizeof(bw_data));
10196         bw_data.tc_valid_bits = tc_map;
10197         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10198         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10199                 if (tc_map & BIT_ULL(i))
10200                         bw_data.tc_bw_credits[i] = 1;
10201         }
10202         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10203         if (ret) {
10204                 PMD_INIT_LOG(ERR,
10205                         "AQ command Config VSI BW allocation per TC failed = %d",
10206                         hw->aq.asq_last_status);
10207                 goto out;
10208         }
10209         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10210                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10211
10212         /* Update Queue Pairs Mapping for currently enabled UPs */
10213         ctxt.seid = vsi->seid;
10214         ctxt.pf_num = hw->pf_id;
10215         ctxt.vf_num = 0;
10216         ctxt.uplink_seid = vsi->uplink_seid;
10217         ctxt.info = vsi->info;
10218         i40e_get_cap(hw);
10219         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10220         if (ret)
10221                 goto out;
10222
10223         /* Update the VSI after updating the VSI queue-mapping information */
10224         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10225         if (ret) {
10226                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10227                         hw->aq.asq_last_status);
10228                 goto out;
10229         }
10230         /* update the local VSI info with updated queue map */
10231         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10232                                         sizeof(vsi->info.tc_mapping));
10233         (void)rte_memcpy(&vsi->info.queue_mapping,
10234                         &ctxt.info.queue_mapping,
10235                 sizeof(vsi->info.queue_mapping));
10236         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10237         vsi->info.valid_sections = 0;
10238
10239         /* query and update current VSI BW information */
10240         ret = i40e_vsi_get_bw_config(vsi);
10241         if (ret) {
10242                 PMD_INIT_LOG(ERR,
10243                          "Failed updating vsi bw info, err %s aq_err %s",
10244                          i40e_stat_str(hw, ret),
10245                          i40e_aq_str(hw, hw->aq.asq_last_status));
10246                 goto out;
10247         }
10248
10249         vsi->enabled_tc = tc_map;
10250
10251 out:
10252         return ret;
10253 }
10254
10255 /*
10256  * i40e_dcb_hw_configure - program the dcb setting to hw
10257  * @pf: pf the configuration is taken on
10258  * @new_cfg: new configuration
10259  * @tc_map: enabled TC bitmap
10260  *
10261  * Returns 0 on success, negative value on failure
10262  */
10263 static enum i40e_status_code
10264 i40e_dcb_hw_configure(struct i40e_pf *pf,
10265                       struct i40e_dcbx_config *new_cfg,
10266                       uint8_t tc_map)
10267 {
10268         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10269         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10270         struct i40e_vsi *main_vsi = pf->main_vsi;
10271         struct i40e_vsi_list *vsi_list;
10272         enum i40e_status_code ret;
10273         int i;
10274         uint32_t val;
10275
10276         /* Use the FW API if FW > v4.4*/
10277         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10278               (hw->aq.fw_maj_ver >= 5))) {
10279                 PMD_INIT_LOG(ERR,
10280                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10281                 return I40E_ERR_FIRMWARE_API_VERSION;
10282         }
10283
10284         /* Check if need reconfiguration */
10285         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10286                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10287                 return I40E_SUCCESS;
10288         }
10289
10290         /* Copy the new config to the current config */
10291         *old_cfg = *new_cfg;
10292         old_cfg->etsrec = old_cfg->etscfg;
10293         ret = i40e_set_dcb_config(hw);
10294         if (ret) {
10295                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10296                          i40e_stat_str(hw, ret),
10297                          i40e_aq_str(hw, hw->aq.asq_last_status));
10298                 return ret;
10299         }
10300         /* set receive Arbiter to RR mode and ETS scheme by default */
10301         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10302                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10303                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10304                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10305                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10306                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10307                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10308                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10309                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10310                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10311                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10312                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10313                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10314         }
10315         /* get local mib to check whether it is configured correctly */
10316         /* IEEE mode */
10317         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10318         /* Get Local DCB Config */
10319         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10320                                      &hw->local_dcbx_config);
10321
10322         /* if Veb is created, need to update TC of it at first */
10323         if (main_vsi->veb) {
10324                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10325                 if (ret)
10326                         PMD_INIT_LOG(WARNING,
10327                                  "Failed configuring TC for VEB seid=%d",
10328                                  main_vsi->veb->seid);
10329         }
10330         /* Update each VSI */
10331         i40e_vsi_config_tc(main_vsi, tc_map);
10332         if (main_vsi->veb) {
10333                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10334                         /* Beside main VSI and VMDQ VSIs, only enable default
10335                          * TC for other VSIs
10336                          */
10337                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10338                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10339                                                          tc_map);
10340                         else
10341                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10342                                                          I40E_DEFAULT_TCMAP);
10343                         if (ret)
10344                                 PMD_INIT_LOG(WARNING,
10345                                         "Failed configuring TC for VSI seid=%d",
10346                                         vsi_list->vsi->seid);
10347                         /* continue */
10348                 }
10349         }
10350         return I40E_SUCCESS;
10351 }
10352
10353 /*
10354  * i40e_dcb_init_configure - initial dcb config
10355  * @dev: device being configured
10356  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10357  *
10358  * Returns 0 on success, negative value on failure
10359  */
10360 static int
10361 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10362 {
10363         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10364         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10365         int i, ret = 0;
10366
10367         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10368                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10369                 return -ENOTSUP;
10370         }
10371
10372         /* DCB initialization:
10373          * Update DCB configuration from the Firmware and configure
10374          * LLDP MIB change event.
10375          */
10376         if (sw_dcb == TRUE) {
10377                 ret = i40e_init_dcb(hw);
10378                 /* If lldp agent is stopped, the return value from
10379                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10380                  * adminq status. Otherwise, it should return success.
10381                  */
10382                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10383                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10384                         memset(&hw->local_dcbx_config, 0,
10385                                 sizeof(struct i40e_dcbx_config));
10386                         /* set dcb default configuration */
10387                         hw->local_dcbx_config.etscfg.willing = 0;
10388                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10389                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10390                         hw->local_dcbx_config.etscfg.tsatable[0] =
10391                                                 I40E_IEEE_TSA_ETS;
10392                         /* all UPs mapping to TC0 */
10393                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10394                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10395                         hw->local_dcbx_config.etsrec =
10396                                 hw->local_dcbx_config.etscfg;
10397                         hw->local_dcbx_config.pfc.willing = 0;
10398                         hw->local_dcbx_config.pfc.pfccap =
10399                                                 I40E_MAX_TRAFFIC_CLASS;
10400                         /* FW needs one App to configure HW */
10401                         hw->local_dcbx_config.numapps = 1;
10402                         hw->local_dcbx_config.app[0].selector =
10403                                                 I40E_APP_SEL_ETHTYPE;
10404                         hw->local_dcbx_config.app[0].priority = 3;
10405                         hw->local_dcbx_config.app[0].protocolid =
10406                                                 I40E_APP_PROTOID_FCOE;
10407                         ret = i40e_set_dcb_config(hw);
10408                         if (ret) {
10409                                 PMD_INIT_LOG(ERR,
10410                                         "default dcb config fails. err = %d, aq_err = %d.",
10411                                         ret, hw->aq.asq_last_status);
10412                                 return -ENOSYS;
10413                         }
10414                 } else {
10415                         PMD_INIT_LOG(ERR,
10416                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10417                                 ret, hw->aq.asq_last_status);
10418                         return -ENOTSUP;
10419                 }
10420         } else {
10421                 ret = i40e_aq_start_lldp(hw, NULL);
10422                 if (ret != I40E_SUCCESS)
10423                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10424
10425                 ret = i40e_init_dcb(hw);
10426                 if (!ret) {
10427                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10428                                 PMD_INIT_LOG(ERR,
10429                                         "HW doesn't support DCBX offload.");
10430                                 return -ENOTSUP;
10431                         }
10432                 } else {
10433                         PMD_INIT_LOG(ERR,
10434                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10435                                 ret, hw->aq.asq_last_status);
10436                         return -ENOTSUP;
10437                 }
10438         }
10439         return 0;
10440 }
10441
10442 /*
10443  * i40e_dcb_setup - setup dcb related config
10444  * @dev: device being configured
10445  *
10446  * Returns 0 on success, negative value on failure
10447  */
10448 static int
10449 i40e_dcb_setup(struct rte_eth_dev *dev)
10450 {
10451         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10452         struct i40e_dcbx_config dcb_cfg;
10453         uint8_t tc_map = 0;
10454         int ret = 0;
10455
10456         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10457                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10458                 return -ENOTSUP;
10459         }
10460
10461         if (pf->vf_num != 0)
10462                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10463
10464         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10465         if (ret) {
10466                 PMD_INIT_LOG(ERR, "invalid dcb config");
10467                 return -EINVAL;
10468         }
10469         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10470         if (ret) {
10471                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10472                 return -ENOSYS;
10473         }
10474
10475         return 0;
10476 }
10477
10478 static int
10479 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10480                       struct rte_eth_dcb_info *dcb_info)
10481 {
10482         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10483         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10484         struct i40e_vsi *vsi = pf->main_vsi;
10485         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10486         uint16_t bsf, tc_mapping;
10487         int i, j = 0;
10488
10489         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10490                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10491         else
10492                 dcb_info->nb_tcs = 1;
10493         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10494                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10495         for (i = 0; i < dcb_info->nb_tcs; i++)
10496                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10497
10498         /* get queue mapping if vmdq is disabled */
10499         if (!pf->nb_cfg_vmdq_vsi) {
10500                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10501                         if (!(vsi->enabled_tc & (1 << i)))
10502                                 continue;
10503                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10504                         dcb_info->tc_queue.tc_rxq[j][i].base =
10505                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10506                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10507                         dcb_info->tc_queue.tc_txq[j][i].base =
10508                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10509                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10510                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10511                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10512                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10513                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10514                 }
10515                 return 0;
10516         }
10517
10518         /* get queue mapping if vmdq is enabled */
10519         do {
10520                 vsi = pf->vmdq[j].vsi;
10521                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10522                         if (!(vsi->enabled_tc & (1 << i)))
10523                                 continue;
10524                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10525                         dcb_info->tc_queue.tc_rxq[j][i].base =
10526                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10527                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10528                         dcb_info->tc_queue.tc_txq[j][i].base =
10529                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10530                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10531                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10532                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10533                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10534                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10535                 }
10536                 j++;
10537         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10538         return 0;
10539 }
10540
10541 static int
10542 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10543 {
10544         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10545         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10546         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10547         uint16_t interval =
10548                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10549         uint16_t msix_intr;
10550
10551         msix_intr = intr_handle->intr_vec[queue_id];
10552         if (msix_intr == I40E_MISC_VEC_ID)
10553                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10554                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10555                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10556                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10557                                (interval <<
10558                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10559         else
10560                 I40E_WRITE_REG(hw,
10561                                I40E_PFINT_DYN_CTLN(msix_intr -
10562                                                    I40E_RX_VEC_START),
10563                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10564                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10565                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10566                                (interval <<
10567                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10568
10569         I40E_WRITE_FLUSH(hw);
10570         rte_intr_enable(&pci_dev->intr_handle);
10571
10572         return 0;
10573 }
10574
10575 static int
10576 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10577 {
10578         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10579         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10580         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10581         uint16_t msix_intr;
10582
10583         msix_intr = intr_handle->intr_vec[queue_id];
10584         if (msix_intr == I40E_MISC_VEC_ID)
10585                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10586         else
10587                 I40E_WRITE_REG(hw,
10588                                I40E_PFINT_DYN_CTLN(msix_intr -
10589                                                    I40E_RX_VEC_START),
10590                                0);
10591         I40E_WRITE_FLUSH(hw);
10592
10593         return 0;
10594 }
10595
10596 static int i40e_get_regs(struct rte_eth_dev *dev,
10597                          struct rte_dev_reg_info *regs)
10598 {
10599         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10600         uint32_t *ptr_data = regs->data;
10601         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10602         const struct i40e_reg_info *reg_info;
10603
10604         if (ptr_data == NULL) {
10605                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10606                 regs->width = sizeof(uint32_t);
10607                 return 0;
10608         }
10609
10610         /* The first few registers have to be read using AQ operations */
10611         reg_idx = 0;
10612         while (i40e_regs_adminq[reg_idx].name) {
10613                 reg_info = &i40e_regs_adminq[reg_idx++];
10614                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10615                         for (arr_idx2 = 0;
10616                                         arr_idx2 <= reg_info->count2;
10617                                         arr_idx2++) {
10618                                 reg_offset = arr_idx * reg_info->stride1 +
10619                                         arr_idx2 * reg_info->stride2;
10620                                 reg_offset += reg_info->base_addr;
10621                                 ptr_data[reg_offset >> 2] =
10622                                         i40e_read_rx_ctl(hw, reg_offset);
10623                         }
10624         }
10625
10626         /* The remaining registers can be read using primitives */
10627         reg_idx = 0;
10628         while (i40e_regs_others[reg_idx].name) {
10629                 reg_info = &i40e_regs_others[reg_idx++];
10630                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10631                         for (arr_idx2 = 0;
10632                                         arr_idx2 <= reg_info->count2;
10633                                         arr_idx2++) {
10634                                 reg_offset = arr_idx * reg_info->stride1 +
10635                                         arr_idx2 * reg_info->stride2;
10636                                 reg_offset += reg_info->base_addr;
10637                                 ptr_data[reg_offset >> 2] =
10638                                         I40E_READ_REG(hw, reg_offset);
10639                         }
10640         }
10641
10642         return 0;
10643 }
10644
10645 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10646 {
10647         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10648
10649         /* Convert word count to byte count */
10650         return hw->nvm.sr_size << 1;
10651 }
10652
10653 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10654                            struct rte_dev_eeprom_info *eeprom)
10655 {
10656         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10657         uint16_t *data = eeprom->data;
10658         uint16_t offset, length, cnt_words;
10659         int ret_code;
10660
10661         offset = eeprom->offset >> 1;
10662         length = eeprom->length >> 1;
10663         cnt_words = length;
10664
10665         if (offset > hw->nvm.sr_size ||
10666                 offset + length > hw->nvm.sr_size) {
10667                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10668                 return -EINVAL;
10669         }
10670
10671         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10672
10673         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10674         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10675                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10676                 return -EIO;
10677         }
10678
10679         return 0;
10680 }
10681
10682 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10683                                       struct ether_addr *mac_addr)
10684 {
10685         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10686
10687         if (!is_valid_assigned_ether_addr(mac_addr)) {
10688                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10689                 return;
10690         }
10691
10692         /* Flags: 0x3 updates port address */
10693         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10694 }
10695
10696 static int
10697 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10698 {
10699         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10700         struct rte_eth_dev_data *dev_data = pf->dev_data;
10701         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10702         int ret = 0;
10703
10704         /* check if mtu is within the allowed range */
10705         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10706                 return -EINVAL;
10707
10708         /* mtu setting is forbidden if port is start */
10709         if (dev_data->dev_started) {
10710                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10711                             dev_data->port_id);
10712                 return -EBUSY;
10713         }
10714
10715         if (frame_size > ETHER_MAX_LEN)
10716                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10717         else
10718                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10719
10720         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10721
10722         return ret;
10723 }
10724
10725 /* Restore ethertype filter */
10726 static void
10727 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10728 {
10729         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10730         struct i40e_ethertype_filter_list
10731                 *ethertype_list = &pf->ethertype.ethertype_list;
10732         struct i40e_ethertype_filter *f;
10733         struct i40e_control_filter_stats stats;
10734         uint16_t flags;
10735
10736         TAILQ_FOREACH(f, ethertype_list, rules) {
10737                 flags = 0;
10738                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10739                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10740                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10741                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10742                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10743
10744                 memset(&stats, 0, sizeof(stats));
10745                 i40e_aq_add_rem_control_packet_filter(hw,
10746                                             f->input.mac_addr.addr_bytes,
10747                                             f->input.ether_type,
10748                                             flags, pf->main_vsi->seid,
10749                                             f->queue, 1, &stats, NULL);
10750         }
10751         PMD_DRV_LOG(INFO, "Ethertype filter:"
10752                     " mac_etype_used = %u, etype_used = %u,"
10753                     " mac_etype_free = %u, etype_free = %u",
10754                     stats.mac_etype_used, stats.etype_used,
10755                     stats.mac_etype_free, stats.etype_free);
10756 }
10757
10758 /* Restore tunnel filter */
10759 static void
10760 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10761 {
10762         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10763         struct i40e_vsi *vsi;
10764         struct i40e_pf_vf *vf;
10765         struct i40e_tunnel_filter_list
10766                 *tunnel_list = &pf->tunnel.tunnel_list;
10767         struct i40e_tunnel_filter *f;
10768         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10769         bool big_buffer = 0;
10770
10771         TAILQ_FOREACH(f, tunnel_list, rules) {
10772                 if (!f->is_to_vf)
10773                         vsi = pf->main_vsi;
10774                 else {
10775                         vf = &pf->vfs[f->vf_id];
10776                         vsi = vf->vsi;
10777                 }
10778                 memset(&cld_filter, 0, sizeof(cld_filter));
10779                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10780                         (struct ether_addr *)&cld_filter.element.outer_mac);
10781                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10782                         (struct ether_addr *)&cld_filter.element.inner_mac);
10783                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10784                 cld_filter.element.flags = f->input.flags;
10785                 cld_filter.element.tenant_id = f->input.tenant_id;
10786                 cld_filter.element.queue_number = f->queue;
10787                 rte_memcpy(cld_filter.general_fields,
10788                            f->input.general_fields,
10789                            sizeof(f->input.general_fields));
10790
10791                 if (((f->input.flags &
10792                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10793                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10794                     ((f->input.flags &
10795                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10796                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10797                     ((f->input.flags &
10798                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10799                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10800                         big_buffer = 1;
10801
10802                 if (big_buffer)
10803                         i40e_aq_add_cloud_filters_big_buffer(hw,
10804                                              vsi->seid, &cld_filter, 1);
10805                 else
10806                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10807                                                   &cld_filter.element, 1);
10808         }
10809 }
10810
10811 static void
10812 i40e_filter_restore(struct i40e_pf *pf)
10813 {
10814         i40e_ethertype_filter_restore(pf);
10815         i40e_tunnel_filter_restore(pf);
10816         i40e_fdir_filter_restore(pf);
10817 }
10818
10819 static bool
10820 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10821 {
10822         if (strcmp(dev->device->driver->name, drv->driver.name))
10823                 return false;
10824
10825         return true;
10826 }
10827
10828 bool
10829 is_i40e_supported(struct rte_eth_dev *dev)
10830 {
10831         return is_device_supported(dev, &rte_i40e_pmd);
10832 }
10833
10834 /* Create a QinQ cloud filter
10835  *
10836  * The Fortville NIC has limited resources for tunnel filters,
10837  * so we can only reuse existing filters.
10838  *
10839  * In step 1 we define which Field Vector fields can be used for
10840  * filter types.
10841  * As we do not have the inner tag defined as a field,
10842  * we have to define it first, by reusing one of L1 entries.
10843  *
10844  * In step 2 we are replacing one of existing filter types with
10845  * a new one for QinQ.
10846  * As we reusing L1 and replacing L2, some of the default filter
10847  * types will disappear,which depends on L1 and L2 entries we reuse.
10848  *
10849  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
10850  *
10851  * 1.   Create L1 filter of outer vlan (12b) which will be in use
10852  *              later when we define the cloud filter.
10853  *      a.      Valid_flags.replace_cloud = 0
10854  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
10855  *      c.      New_filter = 0x10
10856  *      d.      TR bit = 0xff (optional, not used here)
10857  *      e.      Buffer – 2 entries:
10858  *              i.      Byte 0 = 8 (outer vlan FV index).
10859  *                      Byte 1 = 0 (rsv)
10860  *                      Byte 2-3 = 0x0fff
10861  *              ii.     Byte 0 = 37 (inner vlan FV index).
10862  *                      Byte 1 =0 (rsv)
10863  *                      Byte 2-3 = 0x0fff
10864  *
10865  * Step 2:
10866  * 2.   Create cloud filter using two L1 filters entries: stag and
10867  *              new filter(outer vlan+ inner vlan)
10868  *      a.      Valid_flags.replace_cloud = 1
10869  *      b.      Old_filter = 1 (instead of outer IP)
10870  *      c.      New_filter = 0x10
10871  *      d.      Buffer – 2 entries:
10872  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
10873  *                      Byte 1-3 = 0 (rsv)
10874  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
10875  *                      Byte 9-11 = 0 (rsv)
10876  */
10877 static int
10878 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
10879 {
10880         int ret = -ENOTSUP;
10881         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
10882         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
10883         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10884
10885         /* Init */
10886         memset(&filter_replace, 0,
10887                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10888         memset(&filter_replace_buf, 0,
10889                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10890
10891         /* create L1 filter */
10892         filter_replace.old_filter_type =
10893                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
10894         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10895         filter_replace.tr_bit = 0;
10896
10897         /* Prepare the buffer, 2 entries */
10898         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
10899         filter_replace_buf.data[0] |=
10900                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10901         /* Field Vector 12b mask */
10902         filter_replace_buf.data[2] = 0xff;
10903         filter_replace_buf.data[3] = 0x0f;
10904         filter_replace_buf.data[4] =
10905                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
10906         filter_replace_buf.data[4] |=
10907                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10908         /* Field Vector 12b mask */
10909         filter_replace_buf.data[6] = 0xff;
10910         filter_replace_buf.data[7] = 0x0f;
10911         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10912                         &filter_replace_buf);
10913         if (ret != I40E_SUCCESS)
10914                 return ret;
10915
10916         /* Apply the second L2 cloud filter */
10917         memset(&filter_replace, 0,
10918                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10919         memset(&filter_replace_buf, 0,
10920                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10921
10922         /* create L2 filter, input for L2 filter will be L1 filter  */
10923         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
10924         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
10925         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10926
10927         /* Prepare the buffer, 2 entries */
10928         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
10929         filter_replace_buf.data[0] |=
10930                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10931         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10932         filter_replace_buf.data[4] |=
10933                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10934         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10935                         &filter_replace_buf);
10936         return ret;
10937 }
10938
10939 RTE_INIT(i40e_init_log);
10940 static void
10941 i40e_init_log(void)
10942 {
10943         i40e_logtype_init = rte_log_register("pmd.i40e.init");
10944         if (i40e_logtype_init >= 0)
10945                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
10946         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
10947         if (i40e_logtype_driver >= 0)
10948                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
10949 }