1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include <mlx5_glue.h>
33 #include <mlx5_devx_cmds.h>
36 #include "mlx5_defs.h"
38 #include "mlx5_flow.h"
39 #include "mlx5_rxtx.h"
41 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
43 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
44 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
47 #ifndef HAVE_MLX5DV_DR_ESWITCH
48 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
49 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
53 #ifndef HAVE_MLX5DV_DR
54 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
57 /* VLAN header definitions */
58 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
59 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
60 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
61 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
62 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
77 * Initialize flow attributes structure according to flow items' types.
79 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
80 * mode. For tunnel mode, the items to be modified are the outermost ones.
83 * Pointer to item specification.
85 * Pointer to flow attributes structure.
87 * Pointer to the sub flow.
88 * @param[in] tunnel_decap
89 * Whether action is after tunnel decapsulation.
92 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
93 struct mlx5_flow *dev_flow, bool tunnel_decap)
96 * If layers is already initialized, it means this dev_flow is the
97 * suffix flow, the layers flags is set by the prefix flow. Need to
98 * use the layer flags from prefix flow as the suffix flow may not
99 * have the user defined items as the flow is split.
101 if (dev_flow->layers) {
102 if (dev_flow->layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
104 else if (dev_flow->layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
106 if (dev_flow->layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
108 else if (dev_flow->layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
113 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
114 uint8_t next_protocol = 0xff;
115 switch (item->type) {
116 case RTE_FLOW_ITEM_TYPE_GRE:
117 case RTE_FLOW_ITEM_TYPE_NVGRE:
118 case RTE_FLOW_ITEM_TYPE_VXLAN:
119 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
120 case RTE_FLOW_ITEM_TYPE_GENEVE:
121 case RTE_FLOW_ITEM_TYPE_MPLS:
125 case RTE_FLOW_ITEM_TYPE_IPV4:
128 if (item->mask != NULL &&
129 ((const struct rte_flow_item_ipv4 *)
130 item->mask)->hdr.next_proto_id)
132 ((const struct rte_flow_item_ipv4 *)
133 (item->spec))->hdr.next_proto_id &
134 ((const struct rte_flow_item_ipv4 *)
135 (item->mask))->hdr.next_proto_id;
136 if ((next_protocol == IPPROTO_IPIP ||
137 next_protocol == IPPROTO_IPV6) && tunnel_decap)
140 case RTE_FLOW_ITEM_TYPE_IPV6:
143 if (item->mask != NULL &&
144 ((const struct rte_flow_item_ipv6 *)
145 item->mask)->hdr.proto)
147 ((const struct rte_flow_item_ipv6 *)
148 (item->spec))->hdr.proto &
149 ((const struct rte_flow_item_ipv6 *)
150 (item->mask))->hdr.proto;
151 if ((next_protocol == IPPROTO_IPIP ||
152 next_protocol == IPPROTO_IPV6) && tunnel_decap)
155 case RTE_FLOW_ITEM_TYPE_UDP:
159 case RTE_FLOW_ITEM_TYPE_TCP:
171 * Convert rte_mtr_color to mlx5 color.
180 rte_col_2_mlx5_col(enum rte_color rcol)
183 case RTE_COLOR_GREEN:
184 return MLX5_FLOW_COLOR_GREEN;
185 case RTE_COLOR_YELLOW:
186 return MLX5_FLOW_COLOR_YELLOW;
188 return MLX5_FLOW_COLOR_RED;
192 return MLX5_FLOW_COLOR_UNDEFINED;
195 struct field_modify_info {
196 uint32_t size; /* Size of field in protocol header, in bytes. */
197 uint32_t offset; /* Offset of field in protocol header, in bytes. */
198 enum mlx5_modification_field id;
201 struct field_modify_info modify_eth[] = {
202 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
203 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
204 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
205 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
209 struct field_modify_info modify_vlan_out_first_vid[] = {
210 /* Size in bits !!! */
211 {12, 0, MLX5_MODI_OUT_FIRST_VID},
215 struct field_modify_info modify_ipv4[] = {
216 {1, 1, MLX5_MODI_OUT_IP_DSCP},
217 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
218 {4, 12, MLX5_MODI_OUT_SIPV4},
219 {4, 16, MLX5_MODI_OUT_DIPV4},
223 struct field_modify_info modify_ipv6[] = {
224 {1, 0, MLX5_MODI_OUT_IP_DSCP},
225 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
226 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
227 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
228 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
229 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
230 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
231 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
232 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
233 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
237 struct field_modify_info modify_udp[] = {
238 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
239 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
243 struct field_modify_info modify_tcp[] = {
244 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
245 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
246 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
247 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
252 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
253 uint8_t next_protocol, uint64_t *item_flags,
256 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
257 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
258 if (next_protocol == IPPROTO_IPIP) {
259 *item_flags |= MLX5_FLOW_LAYER_IPIP;
262 if (next_protocol == IPPROTO_IPV6) {
263 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
269 * Acquire the synchronizing object to protect multithreaded access
270 * to shared dv context. Lock occurs only if context is actually
271 * shared, i.e. we have multiport IB device and representors are
275 * Pointer to the rte_eth_dev structure.
278 flow_dv_shared_lock(struct rte_eth_dev *dev)
280 struct mlx5_priv *priv = dev->data->dev_private;
281 struct mlx5_ibv_shared *sh = priv->sh;
283 if (sh->dv_refcnt > 1) {
286 ret = pthread_mutex_lock(&sh->dv_mutex);
293 flow_dv_shared_unlock(struct rte_eth_dev *dev)
295 struct mlx5_priv *priv = dev->data->dev_private;
296 struct mlx5_ibv_shared *sh = priv->sh;
298 if (sh->dv_refcnt > 1) {
301 ret = pthread_mutex_unlock(&sh->dv_mutex);
307 /* Update VLAN's VID/PCP based on input rte_flow_action.
310 * Pointer to struct rte_flow_action.
312 * Pointer to struct rte_vlan_hdr.
315 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
316 struct rte_vlan_hdr *vlan)
319 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
321 ((const struct rte_flow_action_of_set_vlan_pcp *)
322 action->conf)->vlan_pcp;
323 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
324 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
325 vlan->vlan_tci |= vlan_tci;
326 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
327 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
328 vlan->vlan_tci |= rte_be_to_cpu_16
329 (((const struct rte_flow_action_of_set_vlan_vid *)
330 action->conf)->vlan_vid);
335 * Fetch 1, 2, 3 or 4 byte field from the byte array
336 * and return as unsigned integer in host-endian format.
339 * Pointer to data array.
341 * Size of field to extract.
344 * converted field in host endian format.
346 static inline uint32_t
347 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
356 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
359 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
360 ret = (ret << 8) | *(data + sizeof(uint16_t));
363 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
374 * Convert modify-header action to DV specification.
376 * Data length of each action is determined by provided field description
377 * and the item mask. Data bit offset and width of each action is determined
378 * by provided item mask.
381 * Pointer to item specification.
383 * Pointer to field modification information.
384 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
385 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
386 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
388 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
389 * Negative offset value sets the same offset as source offset.
390 * size field is ignored, value is taken from source field.
391 * @param[in,out] resource
392 * Pointer to the modify-header resource.
394 * Type of modification.
396 * Pointer to the error structure.
399 * 0 on success, a negative errno value otherwise and rte_errno is set.
402 flow_dv_convert_modify_action(struct rte_flow_item *item,
403 struct field_modify_info *field,
404 struct field_modify_info *dcopy,
405 struct mlx5_flow_dv_modify_hdr_resource *resource,
406 uint32_t type, struct rte_flow_error *error)
408 uint32_t i = resource->actions_num;
409 struct mlx5_modification_cmd *actions = resource->actions;
412 * The item and mask are provided in big-endian format.
413 * The fields should be presented as in big-endian format either.
414 * Mask must be always present, it defines the actual field width.
416 MLX5_ASSERT(item->mask);
417 MLX5_ASSERT(field->size);
424 if (i >= MLX5_MAX_MODIFY_NUM)
425 return rte_flow_error_set(error, EINVAL,
426 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
427 "too many items to modify");
428 /* Fetch variable byte size mask from the array. */
429 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
430 field->offset, field->size);
435 /* Deduce actual data width in bits from mask value. */
436 off_b = rte_bsf32(mask);
437 size_b = sizeof(uint32_t) * CHAR_BIT -
438 off_b - __builtin_clz(mask);
440 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
441 actions[i] = (struct mlx5_modification_cmd) {
447 /* Convert entire record to expected big-endian format. */
448 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
449 if (type == MLX5_MODIFICATION_TYPE_COPY) {
451 actions[i].dst_field = dcopy->id;
452 actions[i].dst_offset =
453 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
454 /* Convert entire record to big-endian format. */
455 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
457 MLX5_ASSERT(item->spec);
458 data = flow_dv_fetch_field((const uint8_t *)item->spec +
459 field->offset, field->size);
460 /* Shift out the trailing masked bits from data. */
461 data = (data & mask) >> off_b;
462 actions[i].data1 = rte_cpu_to_be_32(data);
466 } while (field->size);
467 if (resource->actions_num == i)
468 return rte_flow_error_set(error, EINVAL,
469 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
470 "invalid modification flow item");
471 resource->actions_num = i;
476 * Convert modify-header set IPv4 address action to DV specification.
478 * @param[in,out] resource
479 * Pointer to the modify-header resource.
481 * Pointer to action specification.
483 * Pointer to the error structure.
486 * 0 on success, a negative errno value otherwise and rte_errno is set.
489 flow_dv_convert_action_modify_ipv4
490 (struct mlx5_flow_dv_modify_hdr_resource *resource,
491 const struct rte_flow_action *action,
492 struct rte_flow_error *error)
494 const struct rte_flow_action_set_ipv4 *conf =
495 (const struct rte_flow_action_set_ipv4 *)(action->conf);
496 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
497 struct rte_flow_item_ipv4 ipv4;
498 struct rte_flow_item_ipv4 ipv4_mask;
500 memset(&ipv4, 0, sizeof(ipv4));
501 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
502 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
503 ipv4.hdr.src_addr = conf->ipv4_addr;
504 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
506 ipv4.hdr.dst_addr = conf->ipv4_addr;
507 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
510 item.mask = &ipv4_mask;
511 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
512 MLX5_MODIFICATION_TYPE_SET, error);
516 * Convert modify-header set IPv6 address action to DV specification.
518 * @param[in,out] resource
519 * Pointer to the modify-header resource.
521 * Pointer to action specification.
523 * Pointer to the error structure.
526 * 0 on success, a negative errno value otherwise and rte_errno is set.
529 flow_dv_convert_action_modify_ipv6
530 (struct mlx5_flow_dv_modify_hdr_resource *resource,
531 const struct rte_flow_action *action,
532 struct rte_flow_error *error)
534 const struct rte_flow_action_set_ipv6 *conf =
535 (const struct rte_flow_action_set_ipv6 *)(action->conf);
536 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
537 struct rte_flow_item_ipv6 ipv6;
538 struct rte_flow_item_ipv6 ipv6_mask;
540 memset(&ipv6, 0, sizeof(ipv6));
541 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
542 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
543 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
544 sizeof(ipv6.hdr.src_addr));
545 memcpy(&ipv6_mask.hdr.src_addr,
546 &rte_flow_item_ipv6_mask.hdr.src_addr,
547 sizeof(ipv6.hdr.src_addr));
549 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
550 sizeof(ipv6.hdr.dst_addr));
551 memcpy(&ipv6_mask.hdr.dst_addr,
552 &rte_flow_item_ipv6_mask.hdr.dst_addr,
553 sizeof(ipv6.hdr.dst_addr));
556 item.mask = &ipv6_mask;
557 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
558 MLX5_MODIFICATION_TYPE_SET, error);
562 * Convert modify-header set MAC address action to DV specification.
564 * @param[in,out] resource
565 * Pointer to the modify-header resource.
567 * Pointer to action specification.
569 * Pointer to the error structure.
572 * 0 on success, a negative errno value otherwise and rte_errno is set.
575 flow_dv_convert_action_modify_mac
576 (struct mlx5_flow_dv_modify_hdr_resource *resource,
577 const struct rte_flow_action *action,
578 struct rte_flow_error *error)
580 const struct rte_flow_action_set_mac *conf =
581 (const struct rte_flow_action_set_mac *)(action->conf);
582 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
583 struct rte_flow_item_eth eth;
584 struct rte_flow_item_eth eth_mask;
586 memset(ð, 0, sizeof(eth));
587 memset(ð_mask, 0, sizeof(eth_mask));
588 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
589 memcpy(ð.src.addr_bytes, &conf->mac_addr,
590 sizeof(eth.src.addr_bytes));
591 memcpy(ð_mask.src.addr_bytes,
592 &rte_flow_item_eth_mask.src.addr_bytes,
593 sizeof(eth_mask.src.addr_bytes));
595 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
596 sizeof(eth.dst.addr_bytes));
597 memcpy(ð_mask.dst.addr_bytes,
598 &rte_flow_item_eth_mask.dst.addr_bytes,
599 sizeof(eth_mask.dst.addr_bytes));
602 item.mask = ð_mask;
603 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
604 MLX5_MODIFICATION_TYPE_SET, error);
608 * Convert modify-header set VLAN VID action to DV specification.
610 * @param[in,out] resource
611 * Pointer to the modify-header resource.
613 * Pointer to action specification.
615 * Pointer to the error structure.
618 * 0 on success, a negative errno value otherwise and rte_errno is set.
621 flow_dv_convert_action_modify_vlan_vid
622 (struct mlx5_flow_dv_modify_hdr_resource *resource,
623 const struct rte_flow_action *action,
624 struct rte_flow_error *error)
626 const struct rte_flow_action_of_set_vlan_vid *conf =
627 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
628 int i = resource->actions_num;
629 struct mlx5_modification_cmd *actions = resource->actions;
630 struct field_modify_info *field = modify_vlan_out_first_vid;
632 if (i >= MLX5_MAX_MODIFY_NUM)
633 return rte_flow_error_set(error, EINVAL,
634 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
635 "too many items to modify");
636 actions[i] = (struct mlx5_modification_cmd) {
637 .action_type = MLX5_MODIFICATION_TYPE_SET,
639 .length = field->size,
640 .offset = field->offset,
642 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
643 actions[i].data1 = conf->vlan_vid;
644 actions[i].data1 = actions[i].data1 << 16;
645 resource->actions_num = ++i;
650 * Convert modify-header set TP action to DV specification.
652 * @param[in,out] resource
653 * Pointer to the modify-header resource.
655 * Pointer to action specification.
657 * Pointer to rte_flow_item objects list.
659 * Pointer to flow attributes structure.
660 * @param[in] dev_flow
661 * Pointer to the sub flow.
662 * @param[in] tunnel_decap
663 * Whether action is after tunnel decapsulation.
665 * Pointer to the error structure.
668 * 0 on success, a negative errno value otherwise and rte_errno is set.
671 flow_dv_convert_action_modify_tp
672 (struct mlx5_flow_dv_modify_hdr_resource *resource,
673 const struct rte_flow_action *action,
674 const struct rte_flow_item *items,
675 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
676 bool tunnel_decap, struct rte_flow_error *error)
678 const struct rte_flow_action_set_tp *conf =
679 (const struct rte_flow_action_set_tp *)(action->conf);
680 struct rte_flow_item item;
681 struct rte_flow_item_udp udp;
682 struct rte_flow_item_udp udp_mask;
683 struct rte_flow_item_tcp tcp;
684 struct rte_flow_item_tcp tcp_mask;
685 struct field_modify_info *field;
688 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
690 memset(&udp, 0, sizeof(udp));
691 memset(&udp_mask, 0, sizeof(udp_mask));
692 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
693 udp.hdr.src_port = conf->port;
694 udp_mask.hdr.src_port =
695 rte_flow_item_udp_mask.hdr.src_port;
697 udp.hdr.dst_port = conf->port;
698 udp_mask.hdr.dst_port =
699 rte_flow_item_udp_mask.hdr.dst_port;
701 item.type = RTE_FLOW_ITEM_TYPE_UDP;
703 item.mask = &udp_mask;
706 MLX5_ASSERT(attr->tcp);
707 memset(&tcp, 0, sizeof(tcp));
708 memset(&tcp_mask, 0, sizeof(tcp_mask));
709 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
710 tcp.hdr.src_port = conf->port;
711 tcp_mask.hdr.src_port =
712 rte_flow_item_tcp_mask.hdr.src_port;
714 tcp.hdr.dst_port = conf->port;
715 tcp_mask.hdr.dst_port =
716 rte_flow_item_tcp_mask.hdr.dst_port;
718 item.type = RTE_FLOW_ITEM_TYPE_TCP;
720 item.mask = &tcp_mask;
723 return flow_dv_convert_modify_action(&item, field, NULL, resource,
724 MLX5_MODIFICATION_TYPE_SET, error);
728 * Convert modify-header set TTL action to DV specification.
730 * @param[in,out] resource
731 * Pointer to the modify-header resource.
733 * Pointer to action specification.
735 * Pointer to rte_flow_item objects list.
737 * Pointer to flow attributes structure.
738 * @param[in] dev_flow
739 * Pointer to the sub flow.
740 * @param[in] tunnel_decap
741 * Whether action is after tunnel decapsulation.
743 * Pointer to the error structure.
746 * 0 on success, a negative errno value otherwise and rte_errno is set.
749 flow_dv_convert_action_modify_ttl
750 (struct mlx5_flow_dv_modify_hdr_resource *resource,
751 const struct rte_flow_action *action,
752 const struct rte_flow_item *items,
753 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
754 bool tunnel_decap, struct rte_flow_error *error)
756 const struct rte_flow_action_set_ttl *conf =
757 (const struct rte_flow_action_set_ttl *)(action->conf);
758 struct rte_flow_item item;
759 struct rte_flow_item_ipv4 ipv4;
760 struct rte_flow_item_ipv4 ipv4_mask;
761 struct rte_flow_item_ipv6 ipv6;
762 struct rte_flow_item_ipv6 ipv6_mask;
763 struct field_modify_info *field;
766 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
768 memset(&ipv4, 0, sizeof(ipv4));
769 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
770 ipv4.hdr.time_to_live = conf->ttl_value;
771 ipv4_mask.hdr.time_to_live = 0xFF;
772 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
774 item.mask = &ipv4_mask;
777 MLX5_ASSERT(attr->ipv6);
778 memset(&ipv6, 0, sizeof(ipv6));
779 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
780 ipv6.hdr.hop_limits = conf->ttl_value;
781 ipv6_mask.hdr.hop_limits = 0xFF;
782 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
784 item.mask = &ipv6_mask;
787 return flow_dv_convert_modify_action(&item, field, NULL, resource,
788 MLX5_MODIFICATION_TYPE_SET, error);
792 * Convert modify-header decrement TTL action to DV specification.
794 * @param[in,out] resource
795 * Pointer to the modify-header resource.
797 * Pointer to action specification.
799 * Pointer to rte_flow_item objects list.
801 * Pointer to flow attributes structure.
802 * @param[in] dev_flow
803 * Pointer to the sub flow.
804 * @param[in] tunnel_decap
805 * Whether action is after tunnel decapsulation.
807 * Pointer to the error structure.
810 * 0 on success, a negative errno value otherwise and rte_errno is set.
813 flow_dv_convert_action_modify_dec_ttl
814 (struct mlx5_flow_dv_modify_hdr_resource *resource,
815 const struct rte_flow_item *items,
816 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
817 bool tunnel_decap, struct rte_flow_error *error)
819 struct rte_flow_item item;
820 struct rte_flow_item_ipv4 ipv4;
821 struct rte_flow_item_ipv4 ipv4_mask;
822 struct rte_flow_item_ipv6 ipv6;
823 struct rte_flow_item_ipv6 ipv6_mask;
824 struct field_modify_info *field;
827 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
829 memset(&ipv4, 0, sizeof(ipv4));
830 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
831 ipv4.hdr.time_to_live = 0xFF;
832 ipv4_mask.hdr.time_to_live = 0xFF;
833 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
835 item.mask = &ipv4_mask;
838 MLX5_ASSERT(attr->ipv6);
839 memset(&ipv6, 0, sizeof(ipv6));
840 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
841 ipv6.hdr.hop_limits = 0xFF;
842 ipv6_mask.hdr.hop_limits = 0xFF;
843 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
845 item.mask = &ipv6_mask;
848 return flow_dv_convert_modify_action(&item, field, NULL, resource,
849 MLX5_MODIFICATION_TYPE_ADD, error);
853 * Convert modify-header increment/decrement TCP Sequence number
854 * to DV specification.
856 * @param[in,out] resource
857 * Pointer to the modify-header resource.
859 * Pointer to action specification.
861 * Pointer to the error structure.
864 * 0 on success, a negative errno value otherwise and rte_errno is set.
867 flow_dv_convert_action_modify_tcp_seq
868 (struct mlx5_flow_dv_modify_hdr_resource *resource,
869 const struct rte_flow_action *action,
870 struct rte_flow_error *error)
872 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
873 uint64_t value = rte_be_to_cpu_32(*conf);
874 struct rte_flow_item item;
875 struct rte_flow_item_tcp tcp;
876 struct rte_flow_item_tcp tcp_mask;
878 memset(&tcp, 0, sizeof(tcp));
879 memset(&tcp_mask, 0, sizeof(tcp_mask));
880 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
882 * The HW has no decrement operation, only increment operation.
883 * To simulate decrement X from Y using increment operation
884 * we need to add UINT32_MAX X times to Y.
885 * Each adding of UINT32_MAX decrements Y by 1.
888 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
889 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
890 item.type = RTE_FLOW_ITEM_TYPE_TCP;
892 item.mask = &tcp_mask;
893 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
894 MLX5_MODIFICATION_TYPE_ADD, error);
898 * Convert modify-header increment/decrement TCP Acknowledgment number
899 * to DV specification.
901 * @param[in,out] resource
902 * Pointer to the modify-header resource.
904 * Pointer to action specification.
906 * Pointer to the error structure.
909 * 0 on success, a negative errno value otherwise and rte_errno is set.
912 flow_dv_convert_action_modify_tcp_ack
913 (struct mlx5_flow_dv_modify_hdr_resource *resource,
914 const struct rte_flow_action *action,
915 struct rte_flow_error *error)
917 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
918 uint64_t value = rte_be_to_cpu_32(*conf);
919 struct rte_flow_item item;
920 struct rte_flow_item_tcp tcp;
921 struct rte_flow_item_tcp tcp_mask;
923 memset(&tcp, 0, sizeof(tcp));
924 memset(&tcp_mask, 0, sizeof(tcp_mask));
925 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
927 * The HW has no decrement operation, only increment operation.
928 * To simulate decrement X from Y using increment operation
929 * we need to add UINT32_MAX X times to Y.
930 * Each adding of UINT32_MAX decrements Y by 1.
933 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
934 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
935 item.type = RTE_FLOW_ITEM_TYPE_TCP;
937 item.mask = &tcp_mask;
938 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
939 MLX5_MODIFICATION_TYPE_ADD, error);
942 static enum mlx5_modification_field reg_to_field[] = {
943 [REG_NONE] = MLX5_MODI_OUT_NONE,
944 [REG_A] = MLX5_MODI_META_DATA_REG_A,
945 [REG_B] = MLX5_MODI_META_DATA_REG_B,
946 [REG_C_0] = MLX5_MODI_META_REG_C_0,
947 [REG_C_1] = MLX5_MODI_META_REG_C_1,
948 [REG_C_2] = MLX5_MODI_META_REG_C_2,
949 [REG_C_3] = MLX5_MODI_META_REG_C_3,
950 [REG_C_4] = MLX5_MODI_META_REG_C_4,
951 [REG_C_5] = MLX5_MODI_META_REG_C_5,
952 [REG_C_6] = MLX5_MODI_META_REG_C_6,
953 [REG_C_7] = MLX5_MODI_META_REG_C_7,
957 * Convert register set to DV specification.
959 * @param[in,out] resource
960 * Pointer to the modify-header resource.
962 * Pointer to action specification.
964 * Pointer to the error structure.
967 * 0 on success, a negative errno value otherwise and rte_errno is set.
970 flow_dv_convert_action_set_reg
971 (struct mlx5_flow_dv_modify_hdr_resource *resource,
972 const struct rte_flow_action *action,
973 struct rte_flow_error *error)
975 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
976 struct mlx5_modification_cmd *actions = resource->actions;
977 uint32_t i = resource->actions_num;
979 if (i >= MLX5_MAX_MODIFY_NUM)
980 return rte_flow_error_set(error, EINVAL,
981 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
982 "too many items to modify");
983 MLX5_ASSERT(conf->id != REG_NONE);
984 MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
985 actions[i] = (struct mlx5_modification_cmd) {
986 .action_type = MLX5_MODIFICATION_TYPE_SET,
987 .field = reg_to_field[conf->id],
989 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
990 actions[i].data1 = rte_cpu_to_be_32(conf->data);
992 resource->actions_num = i;
997 * Convert SET_TAG action to DV specification.
1000 * Pointer to the rte_eth_dev structure.
1001 * @param[in,out] resource
1002 * Pointer to the modify-header resource.
1004 * Pointer to action specification.
1006 * Pointer to the error structure.
1009 * 0 on success, a negative errno value otherwise and rte_errno is set.
1012 flow_dv_convert_action_set_tag
1013 (struct rte_eth_dev *dev,
1014 struct mlx5_flow_dv_modify_hdr_resource *resource,
1015 const struct rte_flow_action_set_tag *conf,
1016 struct rte_flow_error *error)
1018 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1019 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1020 struct rte_flow_item item = {
1024 struct field_modify_info reg_c_x[] = {
1027 enum mlx5_modification_field reg_type;
1030 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1033 MLX5_ASSERT(ret != REG_NONE);
1034 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1035 reg_type = reg_to_field[ret];
1036 MLX5_ASSERT(reg_type > 0);
1037 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1038 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1039 MLX5_MODIFICATION_TYPE_SET, error);
1043 * Convert internal COPY_REG action to DV specification.
1046 * Pointer to the rte_eth_dev structure.
1047 * @param[in,out] res
1048 * Pointer to the modify-header resource.
1050 * Pointer to action specification.
1052 * Pointer to the error structure.
1055 * 0 on success, a negative errno value otherwise and rte_errno is set.
1058 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1059 struct mlx5_flow_dv_modify_hdr_resource *res,
1060 const struct rte_flow_action *action,
1061 struct rte_flow_error *error)
1063 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1064 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1065 struct rte_flow_item item = {
1069 struct field_modify_info reg_src[] = {
1070 {4, 0, reg_to_field[conf->src]},
1073 struct field_modify_info reg_dst = {
1075 .id = reg_to_field[conf->dst],
1077 /* Adjust reg_c[0] usage according to reported mask. */
1078 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1079 struct mlx5_priv *priv = dev->data->dev_private;
1080 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1082 MLX5_ASSERT(reg_c0);
1083 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1084 if (conf->dst == REG_C_0) {
1085 /* Copy to reg_c[0], within mask only. */
1086 reg_dst.offset = rte_bsf32(reg_c0);
1088 * Mask is ignoring the enianness, because
1089 * there is no conversion in datapath.
1091 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1092 /* Copy from destination lower bits to reg_c[0]. */
1093 mask = reg_c0 >> reg_dst.offset;
1095 /* Copy from destination upper bits to reg_c[0]. */
1096 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1097 rte_fls_u32(reg_c0));
1100 mask = rte_cpu_to_be_32(reg_c0);
1101 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1102 /* Copy from reg_c[0] to destination lower bits. */
1105 /* Copy from reg_c[0] to destination upper bits. */
1106 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1107 (rte_fls_u32(reg_c0) -
1112 return flow_dv_convert_modify_action(&item,
1113 reg_src, ®_dst, res,
1114 MLX5_MODIFICATION_TYPE_COPY,
1119 * Convert MARK action to DV specification. This routine is used
1120 * in extensive metadata only and requires metadata register to be
1121 * handled. In legacy mode hardware tag resource is engaged.
1124 * Pointer to the rte_eth_dev structure.
1126 * Pointer to MARK action specification.
1127 * @param[in,out] resource
1128 * Pointer to the modify-header resource.
1130 * Pointer to the error structure.
1133 * 0 on success, a negative errno value otherwise and rte_errno is set.
1136 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1137 const struct rte_flow_action_mark *conf,
1138 struct mlx5_flow_dv_modify_hdr_resource *resource,
1139 struct rte_flow_error *error)
1141 struct mlx5_priv *priv = dev->data->dev_private;
1142 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1143 priv->sh->dv_mark_mask);
1144 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1145 struct rte_flow_item item = {
1149 struct field_modify_info reg_c_x[] = {
1150 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1156 return rte_flow_error_set(error, EINVAL,
1157 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1158 NULL, "zero mark action mask");
1159 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1162 MLX5_ASSERT(reg > 0);
1163 if (reg == REG_C_0) {
1164 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1165 uint32_t shl_c0 = rte_bsf32(msk_c0);
1167 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1168 mask = rte_cpu_to_be_32(mask) & msk_c0;
1169 mask = rte_cpu_to_be_32(mask << shl_c0);
1171 reg_c_x[0].id = reg_to_field[reg];
1172 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1173 MLX5_MODIFICATION_TYPE_SET, error);
1177 * Get metadata register index for specified steering domain.
1180 * Pointer to the rte_eth_dev structure.
1182 * Attributes of flow to determine steering domain.
1184 * Pointer to the error structure.
1187 * positive index on success, a negative errno value otherwise
1188 * and rte_errno is set.
1190 static enum modify_reg
1191 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1192 const struct rte_flow_attr *attr,
1193 struct rte_flow_error *error)
1196 mlx5_flow_get_reg_id(dev, attr->transfer ?
1200 MLX5_METADATA_RX, 0, error);
1202 return rte_flow_error_set(error,
1203 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1204 NULL, "unavailable "
1205 "metadata register");
1210 * Convert SET_META action to DV specification.
1213 * Pointer to the rte_eth_dev structure.
1214 * @param[in,out] resource
1215 * Pointer to the modify-header resource.
1217 * Attributes of flow that includes this item.
1219 * Pointer to action specification.
1221 * Pointer to the error structure.
1224 * 0 on success, a negative errno value otherwise and rte_errno is set.
1227 flow_dv_convert_action_set_meta
1228 (struct rte_eth_dev *dev,
1229 struct mlx5_flow_dv_modify_hdr_resource *resource,
1230 const struct rte_flow_attr *attr,
1231 const struct rte_flow_action_set_meta *conf,
1232 struct rte_flow_error *error)
1234 uint32_t data = conf->data;
1235 uint32_t mask = conf->mask;
1236 struct rte_flow_item item = {
1240 struct field_modify_info reg_c_x[] = {
1243 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1248 * In datapath code there is no endianness
1249 * coversions for perfromance reasons, all
1250 * pattern conversions are done in rte_flow.
1252 if (reg == REG_C_0) {
1253 struct mlx5_priv *priv = dev->data->dev_private;
1254 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1257 MLX5_ASSERT(msk_c0);
1258 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1259 shl_c0 = rte_bsf32(msk_c0);
1261 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1265 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1267 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1268 /* The routine expects parameters in memory as big-endian ones. */
1269 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1270 MLX5_MODIFICATION_TYPE_SET, error);
1274 * Convert modify-header set IPv4 DSCP action to DV specification.
1276 * @param[in,out] resource
1277 * Pointer to the modify-header resource.
1279 * Pointer to action specification.
1281 * Pointer to the error structure.
1284 * 0 on success, a negative errno value otherwise and rte_errno is set.
1287 flow_dv_convert_action_modify_ipv4_dscp
1288 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1289 const struct rte_flow_action *action,
1290 struct rte_flow_error *error)
1292 const struct rte_flow_action_set_dscp *conf =
1293 (const struct rte_flow_action_set_dscp *)(action->conf);
1294 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1295 struct rte_flow_item_ipv4 ipv4;
1296 struct rte_flow_item_ipv4 ipv4_mask;
1298 memset(&ipv4, 0, sizeof(ipv4));
1299 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1300 ipv4.hdr.type_of_service = conf->dscp;
1301 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1303 item.mask = &ipv4_mask;
1304 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1305 MLX5_MODIFICATION_TYPE_SET, error);
1309 * Convert modify-header set IPv6 DSCP action to DV specification.
1311 * @param[in,out] resource
1312 * Pointer to the modify-header resource.
1314 * Pointer to action specification.
1316 * Pointer to the error structure.
1319 * 0 on success, a negative errno value otherwise and rte_errno is set.
1322 flow_dv_convert_action_modify_ipv6_dscp
1323 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1324 const struct rte_flow_action *action,
1325 struct rte_flow_error *error)
1327 const struct rte_flow_action_set_dscp *conf =
1328 (const struct rte_flow_action_set_dscp *)(action->conf);
1329 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1330 struct rte_flow_item_ipv6 ipv6;
1331 struct rte_flow_item_ipv6 ipv6_mask;
1333 memset(&ipv6, 0, sizeof(ipv6));
1334 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1336 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1337 * rdma-core only accept the DSCP bits byte aligned start from
1338 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1339 * bits in IPv6 case as rdma-core requires byte aligned value.
1341 ipv6.hdr.vtc_flow = conf->dscp;
1342 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1344 item.mask = &ipv6_mask;
1345 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1346 MLX5_MODIFICATION_TYPE_SET, error);
1350 * Validate MARK item.
1353 * Pointer to the rte_eth_dev structure.
1355 * Item specification.
1357 * Attributes of flow that includes this item.
1359 * Pointer to error structure.
1362 * 0 on success, a negative errno value otherwise and rte_errno is set.
1365 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1366 const struct rte_flow_item *item,
1367 const struct rte_flow_attr *attr __rte_unused,
1368 struct rte_flow_error *error)
1370 struct mlx5_priv *priv = dev->data->dev_private;
1371 struct mlx5_dev_config *config = &priv->config;
1372 const struct rte_flow_item_mark *spec = item->spec;
1373 const struct rte_flow_item_mark *mask = item->mask;
1374 const struct rte_flow_item_mark nic_mask = {
1375 .id = priv->sh->dv_mark_mask,
1379 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1380 return rte_flow_error_set(error, ENOTSUP,
1381 RTE_FLOW_ERROR_TYPE_ITEM, item,
1382 "extended metadata feature"
1384 if (!mlx5_flow_ext_mreg_supported(dev))
1385 return rte_flow_error_set(error, ENOTSUP,
1386 RTE_FLOW_ERROR_TYPE_ITEM, item,
1387 "extended metadata register"
1388 " isn't supported");
1390 return rte_flow_error_set(error, ENOTSUP,
1391 RTE_FLOW_ERROR_TYPE_ITEM, item,
1392 "extended metadata register"
1393 " isn't available");
1394 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1398 return rte_flow_error_set(error, EINVAL,
1399 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1401 "data cannot be empty");
1402 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1403 return rte_flow_error_set(error, EINVAL,
1404 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1406 "mark id exceeds the limit");
1410 return rte_flow_error_set(error, EINVAL,
1411 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1412 "mask cannot be zero");
1414 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1415 (const uint8_t *)&nic_mask,
1416 sizeof(struct rte_flow_item_mark),
1424 * Validate META item.
1427 * Pointer to the rte_eth_dev structure.
1429 * Item specification.
1431 * Attributes of flow that includes this item.
1433 * Pointer to error structure.
1436 * 0 on success, a negative errno value otherwise and rte_errno is set.
1439 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1440 const struct rte_flow_item *item,
1441 const struct rte_flow_attr *attr,
1442 struct rte_flow_error *error)
1444 struct mlx5_priv *priv = dev->data->dev_private;
1445 struct mlx5_dev_config *config = &priv->config;
1446 const struct rte_flow_item_meta *spec = item->spec;
1447 const struct rte_flow_item_meta *mask = item->mask;
1448 struct rte_flow_item_meta nic_mask = {
1455 return rte_flow_error_set(error, EINVAL,
1456 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1458 "data cannot be empty");
1459 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1460 if (!mlx5_flow_ext_mreg_supported(dev))
1461 return rte_flow_error_set(error, ENOTSUP,
1462 RTE_FLOW_ERROR_TYPE_ITEM, item,
1463 "extended metadata register"
1464 " isn't supported");
1465 reg = flow_dv_get_metadata_reg(dev, attr, error);
1469 return rte_flow_error_set(error, ENOTSUP,
1470 RTE_FLOW_ERROR_TYPE_ITEM, item,
1474 nic_mask.data = priv->sh->dv_meta_mask;
1477 mask = &rte_flow_item_meta_mask;
1479 return rte_flow_error_set(error, EINVAL,
1480 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1481 "mask cannot be zero");
1483 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1484 (const uint8_t *)&nic_mask,
1485 sizeof(struct rte_flow_item_meta),
1491 * Validate TAG item.
1494 * Pointer to the rte_eth_dev structure.
1496 * Item specification.
1498 * Attributes of flow that includes this item.
1500 * Pointer to error structure.
1503 * 0 on success, a negative errno value otherwise and rte_errno is set.
1506 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1507 const struct rte_flow_item *item,
1508 const struct rte_flow_attr *attr __rte_unused,
1509 struct rte_flow_error *error)
1511 const struct rte_flow_item_tag *spec = item->spec;
1512 const struct rte_flow_item_tag *mask = item->mask;
1513 const struct rte_flow_item_tag nic_mask = {
1514 .data = RTE_BE32(UINT32_MAX),
1519 if (!mlx5_flow_ext_mreg_supported(dev))
1520 return rte_flow_error_set(error, ENOTSUP,
1521 RTE_FLOW_ERROR_TYPE_ITEM, item,
1522 "extensive metadata register"
1523 " isn't supported");
1525 return rte_flow_error_set(error, EINVAL,
1526 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1528 "data cannot be empty");
1530 mask = &rte_flow_item_tag_mask;
1532 return rte_flow_error_set(error, EINVAL,
1533 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1534 "mask cannot be zero");
1536 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1537 (const uint8_t *)&nic_mask,
1538 sizeof(struct rte_flow_item_tag),
1542 if (mask->index != 0xff)
1543 return rte_flow_error_set(error, EINVAL,
1544 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1545 "partial mask for tag index"
1546 " is not supported");
1547 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1550 MLX5_ASSERT(ret != REG_NONE);
1555 * Validate vport item.
1558 * Pointer to the rte_eth_dev structure.
1560 * Item specification.
1562 * Attributes of flow that includes this item.
1563 * @param[in] item_flags
1564 * Bit-fields that holds the items detected until now.
1566 * Pointer to error structure.
1569 * 0 on success, a negative errno value otherwise and rte_errno is set.
1572 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1573 const struct rte_flow_item *item,
1574 const struct rte_flow_attr *attr,
1575 uint64_t item_flags,
1576 struct rte_flow_error *error)
1578 const struct rte_flow_item_port_id *spec = item->spec;
1579 const struct rte_flow_item_port_id *mask = item->mask;
1580 const struct rte_flow_item_port_id switch_mask = {
1583 struct mlx5_priv *esw_priv;
1584 struct mlx5_priv *dev_priv;
1587 if (!attr->transfer)
1588 return rte_flow_error_set(error, EINVAL,
1589 RTE_FLOW_ERROR_TYPE_ITEM,
1591 "match on port id is valid only"
1592 " when transfer flag is enabled");
1593 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1594 return rte_flow_error_set(error, ENOTSUP,
1595 RTE_FLOW_ERROR_TYPE_ITEM, item,
1596 "multiple source ports are not"
1599 mask = &switch_mask;
1600 if (mask->id != 0xffffffff)
1601 return rte_flow_error_set(error, ENOTSUP,
1602 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1604 "no support for partial mask on"
1606 ret = mlx5_flow_item_acceptable
1607 (item, (const uint8_t *)mask,
1608 (const uint8_t *)&rte_flow_item_port_id_mask,
1609 sizeof(struct rte_flow_item_port_id),
1615 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1617 return rte_flow_error_set(error, rte_errno,
1618 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1619 "failed to obtain E-Switch info for"
1621 dev_priv = mlx5_dev_to_eswitch_info(dev);
1623 return rte_flow_error_set(error, rte_errno,
1624 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1626 "failed to obtain E-Switch info");
1627 if (esw_priv->domain_id != dev_priv->domain_id)
1628 return rte_flow_error_set(error, EINVAL,
1629 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1630 "cannot match on a port from a"
1631 " different E-Switch");
1636 * Validate GTP item.
1639 * Pointer to the rte_eth_dev structure.
1641 * Item specification.
1642 * @param[in] item_flags
1643 * Bit-fields that holds the items detected until now.
1645 * Pointer to error structure.
1648 * 0 on success, a negative errno value otherwise and rte_errno is set.
1651 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1652 const struct rte_flow_item *item,
1653 uint64_t item_flags,
1654 struct rte_flow_error *error)
1656 struct mlx5_priv *priv = dev->data->dev_private;
1657 const struct rte_flow_item_gtp *mask = item->mask;
1658 const struct rte_flow_item_gtp nic_mask = {
1660 .teid = RTE_BE32(0xffffffff),
1663 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1664 return rte_flow_error_set(error, ENOTSUP,
1665 RTE_FLOW_ERROR_TYPE_ITEM, item,
1666 "GTP support is not enabled");
1667 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1668 return rte_flow_error_set(error, ENOTSUP,
1669 RTE_FLOW_ERROR_TYPE_ITEM, item,
1670 "multiple tunnel layers not"
1672 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1673 return rte_flow_error_set(error, EINVAL,
1674 RTE_FLOW_ERROR_TYPE_ITEM, item,
1675 "no outer UDP layer found");
1677 mask = &rte_flow_item_gtp_mask;
1678 return mlx5_flow_item_acceptable
1679 (item, (const uint8_t *)mask,
1680 (const uint8_t *)&nic_mask,
1681 sizeof(struct rte_flow_item_gtp),
1686 * Validate the pop VLAN action.
1689 * Pointer to the rte_eth_dev structure.
1690 * @param[in] action_flags
1691 * Holds the actions detected until now.
1693 * Pointer to the pop vlan action.
1694 * @param[in] item_flags
1695 * The items found in this flow rule.
1697 * Pointer to flow attributes.
1699 * Pointer to error structure.
1702 * 0 on success, a negative errno value otherwise and rte_errno is set.
1705 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1706 uint64_t action_flags,
1707 const struct rte_flow_action *action,
1708 uint64_t item_flags,
1709 const struct rte_flow_attr *attr,
1710 struct rte_flow_error *error)
1712 const struct mlx5_priv *priv = dev->data->dev_private;
1716 if (!priv->sh->pop_vlan_action)
1717 return rte_flow_error_set(error, ENOTSUP,
1718 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1720 "pop vlan action is not supported");
1722 return rte_flow_error_set(error, ENOTSUP,
1723 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1725 "pop vlan action not supported for "
1727 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1728 return rte_flow_error_set(error, ENOTSUP,
1729 RTE_FLOW_ERROR_TYPE_ACTION, action,
1730 "no support for multiple VLAN "
1732 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1733 return rte_flow_error_set(error, ENOTSUP,
1734 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1736 "cannot pop vlan without a "
1737 "match on (outer) vlan in the flow");
1738 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1739 return rte_flow_error_set(error, EINVAL,
1740 RTE_FLOW_ERROR_TYPE_ACTION, action,
1741 "wrong action order, port_id should "
1742 "be after pop VLAN action");
1743 if (!attr->transfer && priv->representor)
1744 return rte_flow_error_set(error, ENOTSUP,
1745 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1746 "pop vlan action for VF representor "
1747 "not supported on NIC table");
1752 * Get VLAN default info from vlan match info.
1755 * the list of item specifications.
1757 * pointer VLAN info to fill to.
1760 * 0 on success, a negative errno value otherwise and rte_errno is set.
1763 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1764 struct rte_vlan_hdr *vlan)
1766 const struct rte_flow_item_vlan nic_mask = {
1767 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1768 MLX5DV_FLOW_VLAN_VID_MASK),
1769 .inner_type = RTE_BE16(0xffff),
1774 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1775 int type = items->type;
1777 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1778 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1781 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1782 const struct rte_flow_item_vlan *vlan_m = items->mask;
1783 const struct rte_flow_item_vlan *vlan_v = items->spec;
1787 /* Only full match values are accepted */
1788 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1789 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1790 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1792 rte_be_to_cpu_16(vlan_v->tci &
1793 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1795 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1796 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1797 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1799 rte_be_to_cpu_16(vlan_v->tci &
1800 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1802 if (vlan_m->inner_type == nic_mask.inner_type)
1803 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1804 vlan_m->inner_type);
1809 * Validate the push VLAN action.
1812 * Pointer to the rte_eth_dev structure.
1813 * @param[in] action_flags
1814 * Holds the actions detected until now.
1815 * @param[in] item_flags
1816 * The items found in this flow rule.
1818 * Pointer to the action structure.
1820 * Pointer to flow attributes
1822 * Pointer to error structure.
1825 * 0 on success, a negative errno value otherwise and rte_errno is set.
1828 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1829 uint64_t action_flags,
1830 uint64_t item_flags __rte_unused,
1831 const struct rte_flow_action *action,
1832 const struct rte_flow_attr *attr,
1833 struct rte_flow_error *error)
1835 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1836 const struct mlx5_priv *priv = dev->data->dev_private;
1838 if (!attr->transfer && attr->ingress)
1839 return rte_flow_error_set(error, ENOTSUP,
1840 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1842 "push VLAN action not supported for "
1844 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1845 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1846 return rte_flow_error_set(error, EINVAL,
1847 RTE_FLOW_ERROR_TYPE_ACTION, action,
1848 "invalid vlan ethertype");
1849 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1850 return rte_flow_error_set(error, ENOTSUP,
1851 RTE_FLOW_ERROR_TYPE_ACTION, action,
1852 "no support for multiple VLAN "
1854 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1855 return rte_flow_error_set(error, EINVAL,
1856 RTE_FLOW_ERROR_TYPE_ACTION, action,
1857 "wrong action order, port_id should "
1858 "be after push VLAN");
1859 if (!attr->transfer && priv->representor)
1860 return rte_flow_error_set(error, ENOTSUP,
1861 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1862 "push vlan action for VF representor "
1863 "not supported on NIC table");
1869 * Validate the set VLAN PCP.
1871 * @param[in] action_flags
1872 * Holds the actions detected until now.
1873 * @param[in] actions
1874 * Pointer to the list of actions remaining in the flow rule.
1876 * Pointer to error structure.
1879 * 0 on success, a negative errno value otherwise and rte_errno is set.
1882 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1883 const struct rte_flow_action actions[],
1884 struct rte_flow_error *error)
1886 const struct rte_flow_action *action = actions;
1887 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1889 if (conf->vlan_pcp > 7)
1890 return rte_flow_error_set(error, EINVAL,
1891 RTE_FLOW_ERROR_TYPE_ACTION, action,
1892 "VLAN PCP value is too big");
1893 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1894 return rte_flow_error_set(error, ENOTSUP,
1895 RTE_FLOW_ERROR_TYPE_ACTION, action,
1896 "set VLAN PCP action must follow "
1897 "the push VLAN action");
1898 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1899 return rte_flow_error_set(error, ENOTSUP,
1900 RTE_FLOW_ERROR_TYPE_ACTION, action,
1901 "Multiple VLAN PCP modification are "
1903 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1904 return rte_flow_error_set(error, EINVAL,
1905 RTE_FLOW_ERROR_TYPE_ACTION, action,
1906 "wrong action order, port_id should "
1907 "be after set VLAN PCP");
1912 * Validate the set VLAN VID.
1914 * @param[in] item_flags
1915 * Holds the items detected in this rule.
1916 * @param[in] action_flags
1917 * Holds the actions detected until now.
1918 * @param[in] actions
1919 * Pointer to the list of actions remaining in the flow rule.
1921 * Pointer to error structure.
1924 * 0 on success, a negative errno value otherwise and rte_errno is set.
1927 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1928 uint64_t action_flags,
1929 const struct rte_flow_action actions[],
1930 struct rte_flow_error *error)
1932 const struct rte_flow_action *action = actions;
1933 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1935 if (conf->vlan_vid > RTE_BE16(0xFFE))
1936 return rte_flow_error_set(error, EINVAL,
1937 RTE_FLOW_ERROR_TYPE_ACTION, action,
1938 "VLAN VID value is too big");
1939 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
1940 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1941 return rte_flow_error_set(error, ENOTSUP,
1942 RTE_FLOW_ERROR_TYPE_ACTION, action,
1943 "set VLAN VID action must follow push"
1944 " VLAN action or match on VLAN item");
1945 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1946 return rte_flow_error_set(error, ENOTSUP,
1947 RTE_FLOW_ERROR_TYPE_ACTION, action,
1948 "Multiple VLAN VID modifications are "
1950 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1951 return rte_flow_error_set(error, EINVAL,
1952 RTE_FLOW_ERROR_TYPE_ACTION, action,
1953 "wrong action order, port_id should "
1954 "be after set VLAN VID");
1959 * Validate the FLAG action.
1962 * Pointer to the rte_eth_dev structure.
1963 * @param[in] action_flags
1964 * Holds the actions detected until now.
1966 * Pointer to flow attributes
1968 * Pointer to error structure.
1971 * 0 on success, a negative errno value otherwise and rte_errno is set.
1974 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
1975 uint64_t action_flags,
1976 const struct rte_flow_attr *attr,
1977 struct rte_flow_error *error)
1979 struct mlx5_priv *priv = dev->data->dev_private;
1980 struct mlx5_dev_config *config = &priv->config;
1983 /* Fall back if no extended metadata register support. */
1984 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1985 return mlx5_flow_validate_action_flag(action_flags, attr,
1987 /* Extensive metadata mode requires registers. */
1988 if (!mlx5_flow_ext_mreg_supported(dev))
1989 return rte_flow_error_set(error, ENOTSUP,
1990 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1991 "no metadata registers "
1992 "to support flag action");
1993 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
1994 return rte_flow_error_set(error, ENOTSUP,
1995 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1996 "extended metadata register"
1997 " isn't available");
1998 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2001 MLX5_ASSERT(ret > 0);
2002 if (action_flags & MLX5_FLOW_ACTION_MARK)
2003 return rte_flow_error_set(error, EINVAL,
2004 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2005 "can't mark and flag in same flow");
2006 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2007 return rte_flow_error_set(error, EINVAL,
2008 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2010 " actions in same flow");
2015 * Validate MARK action.
2018 * Pointer to the rte_eth_dev structure.
2020 * Pointer to action.
2021 * @param[in] action_flags
2022 * Holds the actions detected until now.
2024 * Pointer to flow attributes
2026 * Pointer to error structure.
2029 * 0 on success, a negative errno value otherwise and rte_errno is set.
2032 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2033 const struct rte_flow_action *action,
2034 uint64_t action_flags,
2035 const struct rte_flow_attr *attr,
2036 struct rte_flow_error *error)
2038 struct mlx5_priv *priv = dev->data->dev_private;
2039 struct mlx5_dev_config *config = &priv->config;
2040 const struct rte_flow_action_mark *mark = action->conf;
2043 /* Fall back if no extended metadata register support. */
2044 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2045 return mlx5_flow_validate_action_mark(action, action_flags,
2047 /* Extensive metadata mode requires registers. */
2048 if (!mlx5_flow_ext_mreg_supported(dev))
2049 return rte_flow_error_set(error, ENOTSUP,
2050 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2051 "no metadata registers "
2052 "to support mark action");
2053 if (!priv->sh->dv_mark_mask)
2054 return rte_flow_error_set(error, ENOTSUP,
2055 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2056 "extended metadata register"
2057 " isn't available");
2058 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2061 MLX5_ASSERT(ret > 0);
2063 return rte_flow_error_set(error, EINVAL,
2064 RTE_FLOW_ERROR_TYPE_ACTION, action,
2065 "configuration cannot be null");
2066 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2067 return rte_flow_error_set(error, EINVAL,
2068 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2070 "mark id exceeds the limit");
2071 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2072 return rte_flow_error_set(error, EINVAL,
2073 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2074 "can't flag and mark in same flow");
2075 if (action_flags & MLX5_FLOW_ACTION_MARK)
2076 return rte_flow_error_set(error, EINVAL,
2077 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2078 "can't have 2 mark actions in same"
2084 * Validate SET_META action.
2087 * Pointer to the rte_eth_dev structure.
2089 * Pointer to the action structure.
2090 * @param[in] action_flags
2091 * Holds the actions detected until now.
2093 * Pointer to flow attributes
2095 * Pointer to error structure.
2098 * 0 on success, a negative errno value otherwise and rte_errno is set.
2101 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2102 const struct rte_flow_action *action,
2103 uint64_t action_flags __rte_unused,
2104 const struct rte_flow_attr *attr,
2105 struct rte_flow_error *error)
2107 const struct rte_flow_action_set_meta *conf;
2108 uint32_t nic_mask = UINT32_MAX;
2111 if (!mlx5_flow_ext_mreg_supported(dev))
2112 return rte_flow_error_set(error, ENOTSUP,
2113 RTE_FLOW_ERROR_TYPE_ACTION, action,
2114 "extended metadata register"
2115 " isn't supported");
2116 reg = flow_dv_get_metadata_reg(dev, attr, error);
2119 if (reg != REG_A && reg != REG_B) {
2120 struct mlx5_priv *priv = dev->data->dev_private;
2122 nic_mask = priv->sh->dv_meta_mask;
2124 if (!(action->conf))
2125 return rte_flow_error_set(error, EINVAL,
2126 RTE_FLOW_ERROR_TYPE_ACTION, action,
2127 "configuration cannot be null");
2128 conf = (const struct rte_flow_action_set_meta *)action->conf;
2130 return rte_flow_error_set(error, EINVAL,
2131 RTE_FLOW_ERROR_TYPE_ACTION, action,
2132 "zero mask doesn't have any effect");
2133 if (conf->mask & ~nic_mask)
2134 return rte_flow_error_set(error, EINVAL,
2135 RTE_FLOW_ERROR_TYPE_ACTION, action,
2136 "meta data must be within reg C0");
2141 * Validate SET_TAG action.
2144 * Pointer to the rte_eth_dev structure.
2146 * Pointer to the action structure.
2147 * @param[in] action_flags
2148 * Holds the actions detected until now.
2150 * Pointer to flow attributes
2152 * Pointer to error structure.
2155 * 0 on success, a negative errno value otherwise and rte_errno is set.
2158 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2159 const struct rte_flow_action *action,
2160 uint64_t action_flags,
2161 const struct rte_flow_attr *attr,
2162 struct rte_flow_error *error)
2164 const struct rte_flow_action_set_tag *conf;
2165 const uint64_t terminal_action_flags =
2166 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2167 MLX5_FLOW_ACTION_RSS;
2170 if (!mlx5_flow_ext_mreg_supported(dev))
2171 return rte_flow_error_set(error, ENOTSUP,
2172 RTE_FLOW_ERROR_TYPE_ACTION, action,
2173 "extensive metadata register"
2174 " isn't supported");
2175 if (!(action->conf))
2176 return rte_flow_error_set(error, EINVAL,
2177 RTE_FLOW_ERROR_TYPE_ACTION, action,
2178 "configuration cannot be null");
2179 conf = (const struct rte_flow_action_set_tag *)action->conf;
2181 return rte_flow_error_set(error, EINVAL,
2182 RTE_FLOW_ERROR_TYPE_ACTION, action,
2183 "zero mask doesn't have any effect");
2184 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2187 if (!attr->transfer && attr->ingress &&
2188 (action_flags & terminal_action_flags))
2189 return rte_flow_error_set(error, EINVAL,
2190 RTE_FLOW_ERROR_TYPE_ACTION, action,
2191 "set_tag has no effect"
2192 " with terminal actions");
2197 * Validate count action.
2200 * Pointer to rte_eth_dev structure.
2202 * Pointer to error structure.
2205 * 0 on success, a negative errno value otherwise and rte_errno is set.
2208 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2209 struct rte_flow_error *error)
2211 struct mlx5_priv *priv = dev->data->dev_private;
2213 if (!priv->config.devx)
2215 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2219 return rte_flow_error_set
2221 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2223 "count action not supported");
2227 * Validate the L2 encap action.
2230 * Pointer to the rte_eth_dev structure.
2231 * @param[in] action_flags
2232 * Holds the actions detected until now.
2234 * Pointer to the action structure.
2236 * Pointer to flow attributes.
2238 * Pointer to error structure.
2241 * 0 on success, a negative errno value otherwise and rte_errno is set.
2244 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2245 uint64_t action_flags,
2246 const struct rte_flow_action *action,
2247 const struct rte_flow_attr *attr,
2248 struct rte_flow_error *error)
2250 const struct mlx5_priv *priv = dev->data->dev_private;
2252 if (!(action->conf))
2253 return rte_flow_error_set(error, EINVAL,
2254 RTE_FLOW_ERROR_TYPE_ACTION, action,
2255 "configuration cannot be null");
2256 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2257 return rte_flow_error_set(error, EINVAL,
2258 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2259 "can only have a single encap action "
2261 if (!attr->transfer && priv->representor)
2262 return rte_flow_error_set(error, ENOTSUP,
2263 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2264 "encap action for VF representor "
2265 "not supported on NIC table");
2270 * Validate a decap action.
2273 * Pointer to the rte_eth_dev structure.
2274 * @param[in] action_flags
2275 * Holds the actions detected until now.
2277 * Pointer to flow attributes
2279 * Pointer to error structure.
2282 * 0 on success, a negative errno value otherwise and rte_errno is set.
2285 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2286 uint64_t action_flags,
2287 const struct rte_flow_attr *attr,
2288 struct rte_flow_error *error)
2290 const struct mlx5_priv *priv = dev->data->dev_private;
2292 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2293 return rte_flow_error_set(error, ENOTSUP,
2294 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2296 MLX5_FLOW_ACTION_DECAP ? "can only "
2297 "have a single decap action" : "decap "
2298 "after encap is not supported");
2299 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2300 return rte_flow_error_set(error, EINVAL,
2301 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2302 "can't have decap action after"
2305 return rte_flow_error_set(error, ENOTSUP,
2306 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2308 "decap action not supported for "
2310 if (!attr->transfer && priv->representor)
2311 return rte_flow_error_set(error, ENOTSUP,
2312 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2313 "decap action for VF representor "
2314 "not supported on NIC table");
2318 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2321 * Validate the raw encap and decap actions.
2324 * Pointer to the rte_eth_dev structure.
2326 * Pointer to the decap action.
2328 * Pointer to the encap action.
2330 * Pointer to flow attributes
2331 * @param[in/out] action_flags
2332 * Holds the actions detected until now.
2333 * @param[out] actions_n
2334 * pointer to the number of actions counter.
2336 * Pointer to error structure.
2339 * 0 on success, a negative errno value otherwise and rte_errno is set.
2342 flow_dv_validate_action_raw_encap_decap
2343 (struct rte_eth_dev *dev,
2344 const struct rte_flow_action_raw_decap *decap,
2345 const struct rte_flow_action_raw_encap *encap,
2346 const struct rte_flow_attr *attr, uint64_t *action_flags,
2347 int *actions_n, struct rte_flow_error *error)
2349 const struct mlx5_priv *priv = dev->data->dev_private;
2352 if (encap && (!encap->size || !encap->data))
2353 return rte_flow_error_set(error, EINVAL,
2354 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2355 "raw encap data cannot be empty");
2356 if (decap && encap) {
2357 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2358 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2361 else if (encap->size <=
2362 MLX5_ENCAPSULATION_DECISION_SIZE &&
2364 MLX5_ENCAPSULATION_DECISION_SIZE)
2367 else if (encap->size >
2368 MLX5_ENCAPSULATION_DECISION_SIZE &&
2370 MLX5_ENCAPSULATION_DECISION_SIZE)
2371 /* 2 L2 actions: encap and decap. */
2374 return rte_flow_error_set(error,
2376 RTE_FLOW_ERROR_TYPE_ACTION,
2377 NULL, "unsupported too small "
2378 "raw decap and too small raw "
2379 "encap combination");
2382 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2386 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2390 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2391 return rte_flow_error_set(error, ENOTSUP,
2392 RTE_FLOW_ERROR_TYPE_ACTION,
2394 "small raw encap size");
2395 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2396 return rte_flow_error_set(error, EINVAL,
2397 RTE_FLOW_ERROR_TYPE_ACTION,
2399 "more than one encap action");
2400 if (!attr->transfer && priv->representor)
2401 return rte_flow_error_set
2403 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2404 "encap action for VF representor "
2405 "not supported on NIC table");
2406 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2413 * Find existing encap/decap resource or create and register a new one.
2415 * @param[in, out] dev
2416 * Pointer to rte_eth_dev structure.
2417 * @param[in, out] resource
2418 * Pointer to encap/decap resource.
2419 * @parm[in, out] dev_flow
2420 * Pointer to the dev_flow.
2422 * pointer to error structure.
2425 * 0 on success otherwise -errno and errno is set.
2428 flow_dv_encap_decap_resource_register
2429 (struct rte_eth_dev *dev,
2430 struct mlx5_flow_dv_encap_decap_resource *resource,
2431 struct mlx5_flow *dev_flow,
2432 struct rte_flow_error *error)
2434 struct mlx5_priv *priv = dev->data->dev_private;
2435 struct mlx5_ibv_shared *sh = priv->sh;
2436 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2437 struct mlx5dv_dr_domain *domain;
2439 resource->flags = dev_flow->group ? 0 : 1;
2440 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2441 domain = sh->fdb_domain;
2442 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2443 domain = sh->rx_domain;
2445 domain = sh->tx_domain;
2446 /* Lookup a matching resource from cache. */
2447 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
2448 if (resource->reformat_type == cache_resource->reformat_type &&
2449 resource->ft_type == cache_resource->ft_type &&
2450 resource->flags == cache_resource->flags &&
2451 resource->size == cache_resource->size &&
2452 !memcmp((const void *)resource->buf,
2453 (const void *)cache_resource->buf,
2455 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2456 (void *)cache_resource,
2457 rte_atomic32_read(&cache_resource->refcnt));
2458 rte_atomic32_inc(&cache_resource->refcnt);
2459 dev_flow->dv.encap_decap = cache_resource;
2463 /* Register new encap/decap resource. */
2464 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2465 if (!cache_resource)
2466 return rte_flow_error_set(error, ENOMEM,
2467 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2468 "cannot allocate resource memory");
2469 *cache_resource = *resource;
2470 cache_resource->verbs_action =
2471 mlx5_glue->dv_create_flow_action_packet_reformat
2472 (sh->ctx, cache_resource->reformat_type,
2473 cache_resource->ft_type, domain, cache_resource->flags,
2474 cache_resource->size,
2475 (cache_resource->size ? cache_resource->buf : NULL));
2476 if (!cache_resource->verbs_action) {
2477 rte_free(cache_resource);
2478 return rte_flow_error_set(error, ENOMEM,
2479 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2480 NULL, "cannot create action");
2482 rte_atomic32_init(&cache_resource->refcnt);
2483 rte_atomic32_inc(&cache_resource->refcnt);
2484 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
2485 dev_flow->dv.encap_decap = cache_resource;
2486 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2487 (void *)cache_resource,
2488 rte_atomic32_read(&cache_resource->refcnt));
2493 * Find existing table jump resource or create and register a new one.
2495 * @param[in, out] dev
2496 * Pointer to rte_eth_dev structure.
2497 * @param[in, out] tbl
2498 * Pointer to flow table resource.
2499 * @parm[in, out] dev_flow
2500 * Pointer to the dev_flow.
2502 * pointer to error structure.
2505 * 0 on success otherwise -errno and errno is set.
2508 flow_dv_jump_tbl_resource_register
2509 (struct rte_eth_dev *dev __rte_unused,
2510 struct mlx5_flow_tbl_resource *tbl,
2511 struct mlx5_flow *dev_flow,
2512 struct rte_flow_error *error)
2514 struct mlx5_flow_tbl_data_entry *tbl_data =
2515 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2519 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2521 tbl_data->jump.action =
2522 mlx5_glue->dr_create_flow_action_dest_flow_tbl
2524 if (!tbl_data->jump.action)
2525 return rte_flow_error_set(error, ENOMEM,
2526 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2527 NULL, "cannot create jump action");
2528 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2529 (void *)&tbl_data->jump, cnt);
2531 MLX5_ASSERT(tbl_data->jump.action);
2532 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2533 (void *)&tbl_data->jump, cnt);
2535 rte_atomic32_inc(&tbl_data->jump.refcnt);
2536 dev_flow->dv.jump = &tbl_data->jump;
2541 * Find existing table port ID resource or create and register a new one.
2543 * @param[in, out] dev
2544 * Pointer to rte_eth_dev structure.
2545 * @param[in, out] resource
2546 * Pointer to port ID action resource.
2547 * @parm[in, out] dev_flow
2548 * Pointer to the dev_flow.
2550 * pointer to error structure.
2553 * 0 on success otherwise -errno and errno is set.
2556 flow_dv_port_id_action_resource_register
2557 (struct rte_eth_dev *dev,
2558 struct mlx5_flow_dv_port_id_action_resource *resource,
2559 struct mlx5_flow *dev_flow,
2560 struct rte_flow_error *error)
2562 struct mlx5_priv *priv = dev->data->dev_private;
2563 struct mlx5_ibv_shared *sh = priv->sh;
2564 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2566 /* Lookup a matching resource from cache. */
2567 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
2568 if (resource->port_id == cache_resource->port_id) {
2569 DRV_LOG(DEBUG, "port id action resource resource %p: "
2571 (void *)cache_resource,
2572 rte_atomic32_read(&cache_resource->refcnt));
2573 rte_atomic32_inc(&cache_resource->refcnt);
2574 dev_flow->dv.port_id_action = cache_resource;
2578 /* Register new port id action resource. */
2579 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2580 if (!cache_resource)
2581 return rte_flow_error_set(error, ENOMEM,
2582 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2583 "cannot allocate resource memory");
2584 *cache_resource = *resource;
2586 * Depending on rdma_core version the glue routine calls
2587 * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2588 * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2590 cache_resource->action =
2591 mlx5_glue->dr_create_flow_action_dest_port
2592 (priv->sh->fdb_domain, resource->port_id);
2593 if (!cache_resource->action) {
2594 rte_free(cache_resource);
2595 return rte_flow_error_set(error, ENOMEM,
2596 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2597 NULL, "cannot create action");
2599 rte_atomic32_init(&cache_resource->refcnt);
2600 rte_atomic32_inc(&cache_resource->refcnt);
2601 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
2602 dev_flow->dv.port_id_action = cache_resource;
2603 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2604 (void *)cache_resource,
2605 rte_atomic32_read(&cache_resource->refcnt));
2610 * Find existing push vlan resource or create and register a new one.
2612 * @param [in, out] dev
2613 * Pointer to rte_eth_dev structure.
2614 * @param[in, out] resource
2615 * Pointer to port ID action resource.
2616 * @parm[in, out] dev_flow
2617 * Pointer to the dev_flow.
2619 * pointer to error structure.
2622 * 0 on success otherwise -errno and errno is set.
2625 flow_dv_push_vlan_action_resource_register
2626 (struct rte_eth_dev *dev,
2627 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2628 struct mlx5_flow *dev_flow,
2629 struct rte_flow_error *error)
2631 struct mlx5_priv *priv = dev->data->dev_private;
2632 struct mlx5_ibv_shared *sh = priv->sh;
2633 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2634 struct mlx5dv_dr_domain *domain;
2636 /* Lookup a matching resource from cache. */
2637 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
2638 if (resource->vlan_tag == cache_resource->vlan_tag &&
2639 resource->ft_type == cache_resource->ft_type) {
2640 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2642 (void *)cache_resource,
2643 rte_atomic32_read(&cache_resource->refcnt));
2644 rte_atomic32_inc(&cache_resource->refcnt);
2645 dev_flow->dv.push_vlan_res = cache_resource;
2649 /* Register new push_vlan action resource. */
2650 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2651 if (!cache_resource)
2652 return rte_flow_error_set(error, ENOMEM,
2653 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2654 "cannot allocate resource memory");
2655 *cache_resource = *resource;
2656 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2657 domain = sh->fdb_domain;
2658 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2659 domain = sh->rx_domain;
2661 domain = sh->tx_domain;
2662 cache_resource->action =
2663 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2664 resource->vlan_tag);
2665 if (!cache_resource->action) {
2666 rte_free(cache_resource);
2667 return rte_flow_error_set(error, ENOMEM,
2668 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2669 NULL, "cannot create action");
2671 rte_atomic32_init(&cache_resource->refcnt);
2672 rte_atomic32_inc(&cache_resource->refcnt);
2673 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
2674 dev_flow->dv.push_vlan_res = cache_resource;
2675 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2676 (void *)cache_resource,
2677 rte_atomic32_read(&cache_resource->refcnt));
2681 * Get the size of specific rte_flow_item_type
2683 * @param[in] item_type
2684 * Tested rte_flow_item_type.
2687 * sizeof struct item_type, 0 if void or irrelevant.
2690 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2694 switch (item_type) {
2695 case RTE_FLOW_ITEM_TYPE_ETH:
2696 retval = sizeof(struct rte_flow_item_eth);
2698 case RTE_FLOW_ITEM_TYPE_VLAN:
2699 retval = sizeof(struct rte_flow_item_vlan);
2701 case RTE_FLOW_ITEM_TYPE_IPV4:
2702 retval = sizeof(struct rte_flow_item_ipv4);
2704 case RTE_FLOW_ITEM_TYPE_IPV6:
2705 retval = sizeof(struct rte_flow_item_ipv6);
2707 case RTE_FLOW_ITEM_TYPE_UDP:
2708 retval = sizeof(struct rte_flow_item_udp);
2710 case RTE_FLOW_ITEM_TYPE_TCP:
2711 retval = sizeof(struct rte_flow_item_tcp);
2713 case RTE_FLOW_ITEM_TYPE_VXLAN:
2714 retval = sizeof(struct rte_flow_item_vxlan);
2716 case RTE_FLOW_ITEM_TYPE_GRE:
2717 retval = sizeof(struct rte_flow_item_gre);
2719 case RTE_FLOW_ITEM_TYPE_NVGRE:
2720 retval = sizeof(struct rte_flow_item_nvgre);
2722 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2723 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2725 case RTE_FLOW_ITEM_TYPE_MPLS:
2726 retval = sizeof(struct rte_flow_item_mpls);
2728 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2736 #define MLX5_ENCAP_IPV4_VERSION 0x40
2737 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2738 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2739 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2740 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2741 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2742 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2745 * Convert the encap action data from list of rte_flow_item to raw buffer
2748 * Pointer to rte_flow_item objects list.
2750 * Pointer to the output buffer.
2752 * Pointer to the output buffer size.
2754 * Pointer to the error structure.
2757 * 0 on success, a negative errno value otherwise and rte_errno is set.
2760 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2761 size_t *size, struct rte_flow_error *error)
2763 struct rte_ether_hdr *eth = NULL;
2764 struct rte_vlan_hdr *vlan = NULL;
2765 struct rte_ipv4_hdr *ipv4 = NULL;
2766 struct rte_ipv6_hdr *ipv6 = NULL;
2767 struct rte_udp_hdr *udp = NULL;
2768 struct rte_vxlan_hdr *vxlan = NULL;
2769 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2770 struct rte_gre_hdr *gre = NULL;
2772 size_t temp_size = 0;
2775 return rte_flow_error_set(error, EINVAL,
2776 RTE_FLOW_ERROR_TYPE_ACTION,
2777 NULL, "invalid empty data");
2778 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2779 len = flow_dv_get_item_len(items->type);
2780 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2781 return rte_flow_error_set(error, EINVAL,
2782 RTE_FLOW_ERROR_TYPE_ACTION,
2783 (void *)items->type,
2784 "items total size is too big"
2785 " for encap action");
2786 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2787 switch (items->type) {
2788 case RTE_FLOW_ITEM_TYPE_ETH:
2789 eth = (struct rte_ether_hdr *)&buf[temp_size];
2791 case RTE_FLOW_ITEM_TYPE_VLAN:
2792 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2794 return rte_flow_error_set(error, EINVAL,
2795 RTE_FLOW_ERROR_TYPE_ACTION,
2796 (void *)items->type,
2797 "eth header not found");
2798 if (!eth->ether_type)
2799 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2801 case RTE_FLOW_ITEM_TYPE_IPV4:
2802 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2804 return rte_flow_error_set(error, EINVAL,
2805 RTE_FLOW_ERROR_TYPE_ACTION,
2806 (void *)items->type,
2807 "neither eth nor vlan"
2809 if (vlan && !vlan->eth_proto)
2810 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2811 else if (eth && !eth->ether_type)
2812 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2813 if (!ipv4->version_ihl)
2814 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2815 MLX5_ENCAP_IPV4_IHL_MIN;
2816 if (!ipv4->time_to_live)
2817 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2819 case RTE_FLOW_ITEM_TYPE_IPV6:
2820 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2822 return rte_flow_error_set(error, EINVAL,
2823 RTE_FLOW_ERROR_TYPE_ACTION,
2824 (void *)items->type,
2825 "neither eth nor vlan"
2827 if (vlan && !vlan->eth_proto)
2828 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2829 else if (eth && !eth->ether_type)
2830 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2831 if (!ipv6->vtc_flow)
2833 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2834 if (!ipv6->hop_limits)
2835 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2837 case RTE_FLOW_ITEM_TYPE_UDP:
2838 udp = (struct rte_udp_hdr *)&buf[temp_size];
2840 return rte_flow_error_set(error, EINVAL,
2841 RTE_FLOW_ERROR_TYPE_ACTION,
2842 (void *)items->type,
2843 "ip header not found");
2844 if (ipv4 && !ipv4->next_proto_id)
2845 ipv4->next_proto_id = IPPROTO_UDP;
2846 else if (ipv6 && !ipv6->proto)
2847 ipv6->proto = IPPROTO_UDP;
2849 case RTE_FLOW_ITEM_TYPE_VXLAN:
2850 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2852 return rte_flow_error_set(error, EINVAL,
2853 RTE_FLOW_ERROR_TYPE_ACTION,
2854 (void *)items->type,
2855 "udp header not found");
2857 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2858 if (!vxlan->vx_flags)
2860 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2862 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2863 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2865 return rte_flow_error_set(error, EINVAL,
2866 RTE_FLOW_ERROR_TYPE_ACTION,
2867 (void *)items->type,
2868 "udp header not found");
2869 if (!vxlan_gpe->proto)
2870 return rte_flow_error_set(error, EINVAL,
2871 RTE_FLOW_ERROR_TYPE_ACTION,
2872 (void *)items->type,
2873 "next protocol not found");
2876 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2877 if (!vxlan_gpe->vx_flags)
2878 vxlan_gpe->vx_flags =
2879 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2881 case RTE_FLOW_ITEM_TYPE_GRE:
2882 case RTE_FLOW_ITEM_TYPE_NVGRE:
2883 gre = (struct rte_gre_hdr *)&buf[temp_size];
2885 return rte_flow_error_set(error, EINVAL,
2886 RTE_FLOW_ERROR_TYPE_ACTION,
2887 (void *)items->type,
2888 "next protocol not found");
2890 return rte_flow_error_set(error, EINVAL,
2891 RTE_FLOW_ERROR_TYPE_ACTION,
2892 (void *)items->type,
2893 "ip header not found");
2894 if (ipv4 && !ipv4->next_proto_id)
2895 ipv4->next_proto_id = IPPROTO_GRE;
2896 else if (ipv6 && !ipv6->proto)
2897 ipv6->proto = IPPROTO_GRE;
2899 case RTE_FLOW_ITEM_TYPE_VOID:
2902 return rte_flow_error_set(error, EINVAL,
2903 RTE_FLOW_ERROR_TYPE_ACTION,
2904 (void *)items->type,
2905 "unsupported item type");
2915 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2917 struct rte_ether_hdr *eth = NULL;
2918 struct rte_vlan_hdr *vlan = NULL;
2919 struct rte_ipv6_hdr *ipv6 = NULL;
2920 struct rte_udp_hdr *udp = NULL;
2924 eth = (struct rte_ether_hdr *)data;
2925 next_hdr = (char *)(eth + 1);
2926 proto = RTE_BE16(eth->ether_type);
2929 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2930 vlan = (struct rte_vlan_hdr *)next_hdr;
2931 proto = RTE_BE16(vlan->eth_proto);
2932 next_hdr += sizeof(struct rte_vlan_hdr);
2935 /* HW calculates IPv4 csum. no need to proceed */
2936 if (proto == RTE_ETHER_TYPE_IPV4)
2939 /* non IPv4/IPv6 header. not supported */
2940 if (proto != RTE_ETHER_TYPE_IPV6) {
2941 return rte_flow_error_set(error, ENOTSUP,
2942 RTE_FLOW_ERROR_TYPE_ACTION,
2943 NULL, "Cannot offload non IPv4/IPv6");
2946 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2948 /* ignore non UDP */
2949 if (ipv6->proto != IPPROTO_UDP)
2952 udp = (struct rte_udp_hdr *)(ipv6 + 1);
2953 udp->dgram_cksum = 0;
2959 * Convert L2 encap action to DV specification.
2962 * Pointer to rte_eth_dev structure.
2964 * Pointer to action structure.
2965 * @param[in, out] dev_flow
2966 * Pointer to the mlx5_flow.
2967 * @param[in] transfer
2968 * Mark if the flow is E-Switch flow.
2970 * Pointer to the error structure.
2973 * 0 on success, a negative errno value otherwise and rte_errno is set.
2976 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2977 const struct rte_flow_action *action,
2978 struct mlx5_flow *dev_flow,
2980 struct rte_flow_error *error)
2982 const struct rte_flow_item *encap_data;
2983 const struct rte_flow_action_raw_encap *raw_encap_data;
2984 struct mlx5_flow_dv_encap_decap_resource res = {
2986 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2987 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2988 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2991 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2993 (const struct rte_flow_action_raw_encap *)action->conf;
2994 res.size = raw_encap_data->size;
2995 memcpy(res.buf, raw_encap_data->data, res.size);
2997 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
2999 ((const struct rte_flow_action_vxlan_encap *)
3000 action->conf)->definition;
3003 ((const struct rte_flow_action_nvgre_encap *)
3004 action->conf)->definition;
3005 if (flow_dv_convert_encap_data(encap_data, res.buf,
3009 if (flow_dv_zero_encap_udp_csum(res.buf, error))
3011 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3012 return rte_flow_error_set(error, EINVAL,
3013 RTE_FLOW_ERROR_TYPE_ACTION,
3014 NULL, "can't create L2 encap action");
3019 * Convert L2 decap action to DV specification.
3022 * Pointer to rte_eth_dev structure.
3023 * @param[in, out] dev_flow
3024 * Pointer to the mlx5_flow.
3025 * @param[in] transfer
3026 * Mark if the flow is E-Switch flow.
3028 * Pointer to the error structure.
3031 * 0 on success, a negative errno value otherwise and rte_errno is set.
3034 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3035 struct mlx5_flow *dev_flow,
3037 struct rte_flow_error *error)
3039 struct mlx5_flow_dv_encap_decap_resource res = {
3042 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3043 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3044 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3047 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3048 return rte_flow_error_set(error, EINVAL,
3049 RTE_FLOW_ERROR_TYPE_ACTION,
3050 NULL, "can't create L2 decap action");
3055 * Convert raw decap/encap (L3 tunnel) action to DV specification.
3058 * Pointer to rte_eth_dev structure.
3060 * Pointer to action structure.
3061 * @param[in, out] dev_flow
3062 * Pointer to the mlx5_flow.
3064 * Pointer to the flow attributes.
3066 * Pointer to the error structure.
3069 * 0 on success, a negative errno value otherwise and rte_errno is set.
3072 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3073 const struct rte_flow_action *action,
3074 struct mlx5_flow *dev_flow,
3075 const struct rte_flow_attr *attr,
3076 struct rte_flow_error *error)
3078 const struct rte_flow_action_raw_encap *encap_data;
3079 struct mlx5_flow_dv_encap_decap_resource res;
3081 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3082 res.size = encap_data->size;
3083 memcpy(res.buf, encap_data->data, res.size);
3084 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3085 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3086 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3088 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3090 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3091 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3092 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3093 return rte_flow_error_set(error, EINVAL,
3094 RTE_FLOW_ERROR_TYPE_ACTION,
3095 NULL, "can't create encap action");
3100 * Create action push VLAN.
3103 * Pointer to rte_eth_dev structure.
3105 * Pointer to the flow attributes.
3107 * Pointer to the vlan to push to the Ethernet header.
3108 * @param[in, out] dev_flow
3109 * Pointer to the mlx5_flow.
3111 * Pointer to the error structure.
3114 * 0 on success, a negative errno value otherwise and rte_errno is set.
3117 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3118 const struct rte_flow_attr *attr,
3119 const struct rte_vlan_hdr *vlan,
3120 struct mlx5_flow *dev_flow,
3121 struct rte_flow_error *error)
3123 struct mlx5_flow_dv_push_vlan_action_resource res;
3126 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3129 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3131 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3132 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3133 return flow_dv_push_vlan_action_resource_register
3134 (dev, &res, dev_flow, error);
3138 * Validate the modify-header actions.
3140 * @param[in] action_flags
3141 * Holds the actions detected until now.
3143 * Pointer to the modify action.
3145 * Pointer to error structure.
3148 * 0 on success, a negative errno value otherwise and rte_errno is set.
3151 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3152 const struct rte_flow_action *action,
3153 struct rte_flow_error *error)
3155 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3156 return rte_flow_error_set(error, EINVAL,
3157 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3158 NULL, "action configuration not set");
3159 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3160 return rte_flow_error_set(error, EINVAL,
3161 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3162 "can't have encap action before"
3168 * Validate the modify-header MAC address actions.
3170 * @param[in] action_flags
3171 * Holds the actions detected until now.
3173 * Pointer to the modify action.
3174 * @param[in] item_flags
3175 * Holds the items detected.
3177 * Pointer to error structure.
3180 * 0 on success, a negative errno value otherwise and rte_errno is set.
3183 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3184 const struct rte_flow_action *action,
3185 const uint64_t item_flags,
3186 struct rte_flow_error *error)
3190 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3192 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3193 return rte_flow_error_set(error, EINVAL,
3194 RTE_FLOW_ERROR_TYPE_ACTION,
3196 "no L2 item in pattern");
3202 * Validate the modify-header IPv4 address actions.
3204 * @param[in] action_flags
3205 * Holds the actions detected until now.
3207 * Pointer to the modify action.
3208 * @param[in] item_flags
3209 * Holds the items detected.
3211 * Pointer to error structure.
3214 * 0 on success, a negative errno value otherwise and rte_errno is set.
3217 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3218 const struct rte_flow_action *action,
3219 const uint64_t item_flags,
3220 struct rte_flow_error *error)
3225 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3227 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3228 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3229 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3230 if (!(item_flags & layer))
3231 return rte_flow_error_set(error, EINVAL,
3232 RTE_FLOW_ERROR_TYPE_ACTION,
3234 "no ipv4 item in pattern");
3240 * Validate the modify-header IPv6 address actions.
3242 * @param[in] action_flags
3243 * Holds the actions detected until now.
3245 * Pointer to the modify action.
3246 * @param[in] item_flags
3247 * Holds the items detected.
3249 * Pointer to error structure.
3252 * 0 on success, a negative errno value otherwise and rte_errno is set.
3255 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3256 const struct rte_flow_action *action,
3257 const uint64_t item_flags,
3258 struct rte_flow_error *error)
3263 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3265 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3266 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3267 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3268 if (!(item_flags & layer))
3269 return rte_flow_error_set(error, EINVAL,
3270 RTE_FLOW_ERROR_TYPE_ACTION,
3272 "no ipv6 item in pattern");
3278 * Validate the modify-header TP actions.
3280 * @param[in] action_flags
3281 * Holds the actions detected until now.
3283 * Pointer to the modify action.
3284 * @param[in] item_flags
3285 * Holds the items detected.
3287 * Pointer to error structure.
3290 * 0 on success, a negative errno value otherwise and rte_errno is set.
3293 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3294 const struct rte_flow_action *action,
3295 const uint64_t item_flags,
3296 struct rte_flow_error *error)
3301 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3303 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3304 MLX5_FLOW_LAYER_INNER_L4 :
3305 MLX5_FLOW_LAYER_OUTER_L4;
3306 if (!(item_flags & layer))
3307 return rte_flow_error_set(error, EINVAL,
3308 RTE_FLOW_ERROR_TYPE_ACTION,
3309 NULL, "no transport layer "
3316 * Validate the modify-header actions of increment/decrement
3317 * TCP Sequence-number.
3319 * @param[in] action_flags
3320 * Holds the actions detected until now.
3322 * Pointer to the modify action.
3323 * @param[in] item_flags
3324 * Holds the items detected.
3326 * Pointer to error structure.
3329 * 0 on success, a negative errno value otherwise and rte_errno is set.
3332 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3333 const struct rte_flow_action *action,
3334 const uint64_t item_flags,
3335 struct rte_flow_error *error)
3340 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3342 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3343 MLX5_FLOW_LAYER_INNER_L4_TCP :
3344 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3345 if (!(item_flags & layer))
3346 return rte_flow_error_set(error, EINVAL,
3347 RTE_FLOW_ERROR_TYPE_ACTION,
3348 NULL, "no TCP item in"
3350 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3351 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3352 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3353 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3354 return rte_flow_error_set(error, EINVAL,
3355 RTE_FLOW_ERROR_TYPE_ACTION,
3357 "cannot decrease and increase"
3358 " TCP sequence number"
3359 " at the same time");
3365 * Validate the modify-header actions of increment/decrement
3366 * TCP Acknowledgment number.
3368 * @param[in] action_flags
3369 * Holds the actions detected until now.
3371 * Pointer to the modify action.
3372 * @param[in] item_flags
3373 * Holds the items detected.
3375 * Pointer to error structure.
3378 * 0 on success, a negative errno value otherwise and rte_errno is set.
3381 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3382 const struct rte_flow_action *action,
3383 const uint64_t item_flags,
3384 struct rte_flow_error *error)
3389 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3391 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3392 MLX5_FLOW_LAYER_INNER_L4_TCP :
3393 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3394 if (!(item_flags & layer))
3395 return rte_flow_error_set(error, EINVAL,
3396 RTE_FLOW_ERROR_TYPE_ACTION,
3397 NULL, "no TCP item in"
3399 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3400 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3401 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3402 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3403 return rte_flow_error_set(error, EINVAL,
3404 RTE_FLOW_ERROR_TYPE_ACTION,
3406 "cannot decrease and increase"
3407 " TCP acknowledgment number"
3408 " at the same time");
3414 * Validate the modify-header TTL actions.
3416 * @param[in] action_flags
3417 * Holds the actions detected until now.
3419 * Pointer to the modify action.
3420 * @param[in] item_flags
3421 * Holds the items detected.
3423 * Pointer to error structure.
3426 * 0 on success, a negative errno value otherwise and rte_errno is set.
3429 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3430 const struct rte_flow_action *action,
3431 const uint64_t item_flags,
3432 struct rte_flow_error *error)
3437 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3439 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3440 MLX5_FLOW_LAYER_INNER_L3 :
3441 MLX5_FLOW_LAYER_OUTER_L3;
3442 if (!(item_flags & layer))
3443 return rte_flow_error_set(error, EINVAL,
3444 RTE_FLOW_ERROR_TYPE_ACTION,
3446 "no IP protocol in pattern");
3452 * Validate jump action.
3455 * Pointer to the jump action.
3456 * @param[in] action_flags
3457 * Holds the actions detected until now.
3458 * @param[in] attributes
3459 * Pointer to flow attributes
3460 * @param[in] external
3461 * Action belongs to flow rule created by request external to PMD.
3463 * Pointer to error structure.
3466 * 0 on success, a negative errno value otherwise and rte_errno is set.
3469 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3470 uint64_t action_flags,
3471 const struct rte_flow_attr *attributes,
3472 bool external, struct rte_flow_error *error)
3474 uint32_t target_group, table;
3477 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3478 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3479 return rte_flow_error_set(error, EINVAL,
3480 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3481 "can't have 2 fate actions in"
3483 if (action_flags & MLX5_FLOW_ACTION_METER)
3484 return rte_flow_error_set(error, ENOTSUP,
3485 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3486 "jump with meter not support");
3488 return rte_flow_error_set(error, EINVAL,
3489 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3490 NULL, "action configuration not set");
3492 ((const struct rte_flow_action_jump *)action->conf)->group;
3493 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3494 true, &table, error);
3497 if (attributes->group == target_group)
3498 return rte_flow_error_set(error, EINVAL,
3499 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3500 "target group must be other than"
3501 " the current flow group");
3506 * Validate the port_id action.
3509 * Pointer to rte_eth_dev structure.
3510 * @param[in] action_flags
3511 * Bit-fields that holds the actions detected until now.
3513 * Port_id RTE action structure.
3515 * Attributes of flow that includes this action.
3517 * Pointer to error structure.
3520 * 0 on success, a negative errno value otherwise and rte_errno is set.
3523 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3524 uint64_t action_flags,
3525 const struct rte_flow_action *action,
3526 const struct rte_flow_attr *attr,
3527 struct rte_flow_error *error)
3529 const struct rte_flow_action_port_id *port_id;
3530 struct mlx5_priv *act_priv;
3531 struct mlx5_priv *dev_priv;
3534 if (!attr->transfer)
3535 return rte_flow_error_set(error, ENOTSUP,
3536 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3538 "port id action is valid in transfer"
3540 if (!action || !action->conf)
3541 return rte_flow_error_set(error, ENOTSUP,
3542 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3544 "port id action parameters must be"
3546 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3547 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3548 return rte_flow_error_set(error, EINVAL,
3549 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3550 "can have only one fate actions in"
3552 dev_priv = mlx5_dev_to_eswitch_info(dev);
3554 return rte_flow_error_set(error, rte_errno,
3555 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3557 "failed to obtain E-Switch info");
3558 port_id = action->conf;
3559 port = port_id->original ? dev->data->port_id : port_id->id;
3560 act_priv = mlx5_port_to_eswitch_info(port, false);
3562 return rte_flow_error_set
3564 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3565 "failed to obtain E-Switch port id for port");
3566 if (act_priv->domain_id != dev_priv->domain_id)
3567 return rte_flow_error_set
3569 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3570 "port does not belong to"
3571 " E-Switch being configured");
3576 * Get the maximum number of modify header actions.
3579 * Pointer to rte_eth_dev structure.
3581 * Flags bits to check if root level.
3584 * Max number of modify header actions device can support.
3587 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev, uint64_t flags)
3590 * There's no way to directly query the max cap. Although it has to be
3591 * acquried by iterative trial, it is a safe assumption that more
3592 * actions are supported by FW if extensive metadata register is
3593 * supported. (Only in the root table)
3595 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3596 return MLX5_MAX_MODIFY_NUM;
3598 return mlx5_flow_ext_mreg_supported(dev) ?
3599 MLX5_ROOT_TBL_MODIFY_NUM :
3600 MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG;
3604 * Validate the meter action.
3607 * Pointer to rte_eth_dev structure.
3608 * @param[in] action_flags
3609 * Bit-fields that holds the actions detected until now.
3611 * Pointer to the meter action.
3613 * Attributes of flow that includes this action.
3615 * Pointer to error structure.
3618 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3621 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3622 uint64_t action_flags,
3623 const struct rte_flow_action *action,
3624 const struct rte_flow_attr *attr,
3625 struct rte_flow_error *error)
3627 struct mlx5_priv *priv = dev->data->dev_private;
3628 const struct rte_flow_action_meter *am = action->conf;
3629 struct mlx5_flow_meter *fm;
3632 return rte_flow_error_set(error, EINVAL,
3633 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3634 "meter action conf is NULL");
3636 if (action_flags & MLX5_FLOW_ACTION_METER)
3637 return rte_flow_error_set(error, ENOTSUP,
3638 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3639 "meter chaining not support");
3640 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3641 return rte_flow_error_set(error, ENOTSUP,
3642 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3643 "meter with jump not support");
3645 return rte_flow_error_set(error, ENOTSUP,
3646 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3648 "meter action not supported");
3649 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3651 return rte_flow_error_set(error, EINVAL,
3652 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3654 if (fm->ref_cnt && (!(fm->attr.transfer == attr->transfer ||
3655 (!fm->attr.ingress && !attr->ingress && attr->egress) ||
3656 (!fm->attr.egress && !attr->egress && attr->ingress))))
3657 return rte_flow_error_set(error, EINVAL,
3658 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3659 "Flow attributes are either invalid "
3660 "or have a conflict with current "
3661 "meter attributes");
3666 * Validate the modify-header IPv4 DSCP actions.
3668 * @param[in] action_flags
3669 * Holds the actions detected until now.
3671 * Pointer to the modify action.
3672 * @param[in] item_flags
3673 * Holds the items detected.
3675 * Pointer to error structure.
3678 * 0 on success, a negative errno value otherwise and rte_errno is set.
3681 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3682 const struct rte_flow_action *action,
3683 const uint64_t item_flags,
3684 struct rte_flow_error *error)
3688 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3690 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3691 return rte_flow_error_set(error, EINVAL,
3692 RTE_FLOW_ERROR_TYPE_ACTION,
3694 "no ipv4 item in pattern");
3700 * Validate the modify-header IPv6 DSCP actions.
3702 * @param[in] action_flags
3703 * Holds the actions detected until now.
3705 * Pointer to the modify action.
3706 * @param[in] item_flags
3707 * Holds the items detected.
3709 * Pointer to error structure.
3712 * 0 on success, a negative errno value otherwise and rte_errno is set.
3715 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3716 const struct rte_flow_action *action,
3717 const uint64_t item_flags,
3718 struct rte_flow_error *error)
3722 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3724 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3725 return rte_flow_error_set(error, EINVAL,
3726 RTE_FLOW_ERROR_TYPE_ACTION,
3728 "no ipv6 item in pattern");
3734 * Find existing modify-header resource or create and register a new one.
3736 * @param dev[in, out]
3737 * Pointer to rte_eth_dev structure.
3738 * @param[in, out] resource
3739 * Pointer to modify-header resource.
3740 * @parm[in, out] dev_flow
3741 * Pointer to the dev_flow.
3743 * pointer to error structure.
3746 * 0 on success otherwise -errno and errno is set.
3749 flow_dv_modify_hdr_resource_register
3750 (struct rte_eth_dev *dev,
3751 struct mlx5_flow_dv_modify_hdr_resource *resource,
3752 struct mlx5_flow *dev_flow,
3753 struct rte_flow_error *error)
3755 struct mlx5_priv *priv = dev->data->dev_private;
3756 struct mlx5_ibv_shared *sh = priv->sh;
3757 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3758 struct mlx5dv_dr_domain *ns;
3759 uint32_t actions_len;
3762 dev_flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3763 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3765 return rte_flow_error_set(error, EOVERFLOW,
3766 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3767 "too many modify header items");
3768 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3769 ns = sh->fdb_domain;
3770 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3774 /* Lookup a matching resource from cache. */
3775 actions_len = resource->actions_num * sizeof(resource->actions[0]);
3776 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3777 if (resource->ft_type == cache_resource->ft_type &&
3778 resource->actions_num == cache_resource->actions_num &&
3779 resource->flags == cache_resource->flags &&
3780 !memcmp((const void *)resource->actions,
3781 (const void *)cache_resource->actions,
3783 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3784 (void *)cache_resource,
3785 rte_atomic32_read(&cache_resource->refcnt));
3786 rte_atomic32_inc(&cache_resource->refcnt);
3787 dev_flow->dv.modify_hdr = cache_resource;
3791 /* Register new modify-header resource. */
3792 cache_resource = rte_calloc(__func__, 1,
3793 sizeof(*cache_resource) + actions_len, 0);
3794 if (!cache_resource)
3795 return rte_flow_error_set(error, ENOMEM,
3796 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3797 "cannot allocate resource memory");
3798 *cache_resource = *resource;
3799 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3800 cache_resource->verbs_action =
3801 mlx5_glue->dv_create_flow_action_modify_header
3802 (sh->ctx, cache_resource->ft_type, ns,
3803 cache_resource->flags, actions_len,
3804 (uint64_t *)cache_resource->actions);
3805 if (!cache_resource->verbs_action) {
3806 rte_free(cache_resource);
3807 return rte_flow_error_set(error, ENOMEM,
3808 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3809 NULL, "cannot create action");
3811 rte_atomic32_init(&cache_resource->refcnt);
3812 rte_atomic32_inc(&cache_resource->refcnt);
3813 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3814 dev_flow->dv.modify_hdr = cache_resource;
3815 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3816 (void *)cache_resource,
3817 rte_atomic32_read(&cache_resource->refcnt));
3821 #define MLX5_CNT_CONTAINER_RESIZE 64
3824 * Get or create a flow counter.
3827 * Pointer to the Ethernet device structure.
3829 * Indicate if this counter is shared with other flows.
3831 * Counter identifier.
3834 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3836 static struct mlx5_flow_counter *
3837 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
3840 struct mlx5_priv *priv = dev->data->dev_private;
3841 struct mlx5_flow_counter *cnt = NULL;
3842 struct mlx5_devx_obj *dcs = NULL;
3844 if (!priv->config.devx) {
3845 rte_errno = ENOTSUP;
3849 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
3850 if (cnt->shared && cnt->id == id) {
3856 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3859 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
3861 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3865 struct mlx5_flow_counter tmpl = {
3871 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
3873 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3879 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
3884 * Release a flow counter.
3887 * Pointer to the Ethernet device structure.
3888 * @param[in] counter
3889 * Pointer to the counter handler.
3892 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
3893 struct mlx5_flow_counter *counter)
3895 struct mlx5_priv *priv = dev->data->dev_private;
3899 if (--counter->ref_cnt == 0) {
3900 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
3901 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
3907 * Query a devx flow counter.
3910 * Pointer to the Ethernet device structure.
3912 * Pointer to the flow counter.
3914 * The statistics value of packets.
3916 * The statistics value of bytes.
3919 * 0 on success, otherwise a negative errno value and rte_errno is set.
3922 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
3923 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3926 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
3931 * Get a pool by a counter.
3934 * Pointer to the counter.
3939 static struct mlx5_flow_counter_pool *
3940 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
3943 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
3944 return (struct mlx5_flow_counter_pool *)cnt - 1;
3950 * Get a pool by devx counter ID.
3953 * Pointer to the counter container.
3955 * The counter devx ID.
3958 * The counter pool pointer if exists, NULL otherwise,
3960 static struct mlx5_flow_counter_pool *
3961 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3963 struct mlx5_flow_counter_pool *pool;
3965 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3966 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3967 MLX5_COUNTERS_PER_POOL;
3969 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
3976 * Allocate a new memory for the counter values wrapped by all the needed
3980 * Pointer to the Ethernet device structure.
3982 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3985 * The new memory management pointer on success, otherwise NULL and rte_errno
3988 static struct mlx5_counter_stats_mem_mng *
3989 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3991 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3992 (dev->data->dev_private))->sh;
3993 struct mlx5_devx_mkey_attr mkey_attr;
3994 struct mlx5_counter_stats_mem_mng *mem_mng;
3995 volatile struct flow_counter_stats *raw_data;
3996 int size = (sizeof(struct flow_counter_stats) *
3997 MLX5_COUNTERS_PER_POOL +
3998 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3999 sizeof(struct mlx5_counter_stats_mem_mng);
4000 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
4007 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4008 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4009 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4010 IBV_ACCESS_LOCAL_WRITE);
4011 if (!mem_mng->umem) {
4016 mkey_attr.addr = (uintptr_t)mem;
4017 mkey_attr.size = size;
4018 mkey_attr.umem_id = mem_mng->umem->umem_id;
4019 mkey_attr.pd = sh->pdn;
4020 mkey_attr.log_entity_size = 0;
4021 mkey_attr.pg_access = 0;
4022 mkey_attr.klm_array = NULL;
4023 mkey_attr.klm_num = 0;
4024 mkey_attr.relaxed_ordering = 1;
4025 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4027 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4032 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4033 raw_data = (volatile struct flow_counter_stats *)mem;
4034 for (i = 0; i < raws_n; ++i) {
4035 mem_mng->raws[i].mem_mng = mem_mng;
4036 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4038 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4043 * Resize a counter container.
4046 * Pointer to the Ethernet device structure.
4048 * Whether the pool is for counter that was allocated by batch command.
4051 * The new container pointer on success, otherwise NULL and rte_errno is set.
4053 static struct mlx5_pools_container *
4054 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
4056 struct mlx5_priv *priv = dev->data->dev_private;
4057 struct mlx5_pools_container *cont =
4058 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4059 struct mlx5_pools_container *new_cont =
4060 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
4061 struct mlx5_counter_stats_mem_mng *mem_mng;
4062 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4063 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4066 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
4067 /* The last resize still hasn't detected by the host thread. */
4071 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
4072 if (!new_cont->pools) {
4077 memcpy(new_cont->pools, cont->pools, cont->n *
4078 sizeof(struct mlx5_flow_counter_pool *));
4079 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4080 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4082 rte_free(new_cont->pools);
4085 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4086 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4087 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
4089 new_cont->n = resize;
4090 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
4091 TAILQ_INIT(&new_cont->pool_list);
4092 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
4093 new_cont->init_mem_mng = mem_mng;
4095 /* Flip the master container. */
4096 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
4101 * Query a devx flow counter.
4104 * Pointer to the Ethernet device structure.
4106 * Pointer to the flow counter.
4108 * The statistics value of packets.
4110 * The statistics value of bytes.
4113 * 0 on success, otherwise a negative errno value and rte_errno is set.
4116 _flow_dv_query_count(struct rte_eth_dev *dev,
4117 struct mlx5_flow_counter *cnt, uint64_t *pkts,
4120 struct mlx5_priv *priv = dev->data->dev_private;
4121 struct mlx5_flow_counter_pool *pool =
4122 flow_dv_counter_pool_get(cnt);
4123 int offset = cnt - &pool->counters_raw[0];
4125 if (priv->counter_fallback)
4126 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
4128 rte_spinlock_lock(&pool->sl);
4130 * The single counters allocation may allocate smaller ID than the
4131 * current allocated in parallel to the host reading.
4132 * In this case the new counter values must be reported as 0.
4134 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
4138 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4139 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4141 rte_spinlock_unlock(&pool->sl);
4146 * Create and initialize a new counter pool.
4149 * Pointer to the Ethernet device structure.
4151 * The devX counter handle.
4153 * Whether the pool is for counter that was allocated by batch command.
4156 * A new pool pointer on success, NULL otherwise and rte_errno is set.
4158 static struct mlx5_flow_counter_pool *
4159 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4162 struct mlx5_priv *priv = dev->data->dev_private;
4163 struct mlx5_flow_counter_pool *pool;
4164 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4166 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4169 if (cont->n == n_valid) {
4170 cont = flow_dv_container_resize(dev, batch);
4174 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
4175 sizeof(struct mlx5_flow_counter);
4176 pool = rte_calloc(__func__, 1, size, 0);
4181 pool->min_dcs = dcs;
4182 pool->raw = cont->init_mem_mng->raws + n_valid %
4183 MLX5_CNT_CONTAINER_RESIZE;
4184 pool->raw_hw = NULL;
4185 rte_spinlock_init(&pool->sl);
4187 * The generation of the new allocated counters in this pool is 0, 2 in
4188 * the pool generation makes all the counters valid for allocation.
4190 rte_atomic64_set(&pool->query_gen, 0x2);
4191 TAILQ_INIT(&pool->counters);
4192 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4193 cont->pools[n_valid] = pool;
4194 /* Pool initialization must be updated before host thread access. */
4196 rte_atomic16_add(&cont->n_valid, 1);
4201 * Prepare a new counter and/or a new counter pool.
4204 * Pointer to the Ethernet device structure.
4205 * @param[out] cnt_free
4206 * Where to put the pointer of a new counter.
4208 * Whether the pool is for counter that was allocated by batch command.
4211 * The free counter pool pointer and @p cnt_free is set on success,
4212 * NULL otherwise and rte_errno is set.
4214 static struct mlx5_flow_counter_pool *
4215 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4216 struct mlx5_flow_counter **cnt_free,
4219 struct mlx5_priv *priv = dev->data->dev_private;
4220 struct mlx5_flow_counter_pool *pool;
4221 struct mlx5_devx_obj *dcs = NULL;
4222 struct mlx5_flow_counter *cnt;
4226 /* bulk_bitmap must be 0 for single counter allocation. */
4227 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4230 pool = flow_dv_find_pool_by_id
4231 (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
4233 pool = flow_dv_pool_create(dev, dcs, batch);
4235 mlx5_devx_cmd_destroy(dcs);
4238 } else if (dcs->id < pool->min_dcs->id) {
4239 rte_atomic64_set(&pool->a64_dcs,
4240 (int64_t)(uintptr_t)dcs);
4242 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
4243 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4248 /* bulk_bitmap is in 128 counters units. */
4249 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4250 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4252 rte_errno = ENODATA;
4255 pool = flow_dv_pool_create(dev, dcs, batch);
4257 mlx5_devx_cmd_destroy(dcs);
4260 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4261 cnt = &pool->counters_raw[i];
4263 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4265 *cnt_free = &pool->counters_raw[0];
4270 * Search for existed shared counter.
4273 * Pointer to the relevant counter pool container.
4275 * The shared counter ID to search.
4278 * NULL if not existed, otherwise pointer to the shared counter.
4280 static struct mlx5_flow_counter *
4281 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
4284 static struct mlx5_flow_counter *cnt;
4285 struct mlx5_flow_counter_pool *pool;
4288 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4289 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4290 cnt = &pool->counters_raw[i];
4291 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
4299 * Allocate a flow counter.
4302 * Pointer to the Ethernet device structure.
4304 * Indicate if this counter is shared with other flows.
4306 * Counter identifier.
4308 * Counter flow group.
4311 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
4313 static struct mlx5_flow_counter *
4314 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4317 struct mlx5_priv *priv = dev->data->dev_private;
4318 struct mlx5_flow_counter_pool *pool = NULL;
4319 struct mlx5_flow_counter *cnt_free = NULL;
4321 * Currently group 0 flow counter cannot be assigned to a flow if it is
4322 * not the first one in the batch counter allocation, so it is better
4323 * to allocate counters one by one for these flows in a separate
4325 * A counter can be shared between different groups so need to take
4326 * shared counters from the single container.
4328 uint32_t batch = (group && !shared) ? 1 : 0;
4329 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4332 if (priv->counter_fallback)
4333 return flow_dv_counter_alloc_fallback(dev, shared, id);
4334 if (!priv->config.devx) {
4335 rte_errno = ENOTSUP;
4339 cnt_free = flow_dv_counter_shared_search(cont, id);
4341 if (cnt_free->ref_cnt + 1 == 0) {
4345 cnt_free->ref_cnt++;
4349 /* Pools which has a free counters are in the start. */
4350 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4352 * The free counter reset values must be updated between the
4353 * counter release to the counter allocation, so, at least one
4354 * query must be done in this time. ensure it by saving the
4355 * query generation in the release time.
4356 * The free list is sorted according to the generation - so if
4357 * the first one is not updated, all the others are not
4360 cnt_free = TAILQ_FIRST(&pool->counters);
4361 if (cnt_free && cnt_free->query_gen + 1 <
4362 rte_atomic64_read(&pool->query_gen))
4367 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4371 cnt_free->batch = batch;
4372 /* Create a DV counter action only in the first time usage. */
4373 if (!cnt_free->action) {
4375 struct mlx5_devx_obj *dcs;
4378 offset = cnt_free - &pool->counters_raw[0];
4379 dcs = pool->min_dcs;
4382 dcs = cnt_free->dcs;
4384 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4386 if (!cnt_free->action) {
4391 /* Update the counter reset values. */
4392 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
4395 cnt_free->shared = shared;
4396 cnt_free->ref_cnt = 1;
4398 if (!priv->sh->cmng.query_thread_on)
4399 /* Start the asynchronous batch query by the host thread. */
4400 mlx5_set_query_alarm(priv->sh);
4401 TAILQ_REMOVE(&pool->counters, cnt_free, next);
4402 if (TAILQ_EMPTY(&pool->counters)) {
4403 /* Move the pool to the end of the container pool list. */
4404 TAILQ_REMOVE(&cont->pool_list, pool, next);
4405 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4411 * Release a flow counter.
4414 * Pointer to the Ethernet device structure.
4415 * @param[in] counter
4416 * Pointer to the counter handler.
4419 flow_dv_counter_release(struct rte_eth_dev *dev,
4420 struct mlx5_flow_counter *counter)
4422 struct mlx5_priv *priv = dev->data->dev_private;
4426 if (priv->counter_fallback) {
4427 flow_dv_counter_release_fallback(dev, counter);
4430 if (--counter->ref_cnt == 0) {
4431 struct mlx5_flow_counter_pool *pool =
4432 flow_dv_counter_pool_get(counter);
4434 /* Put the counter in the end - the last updated one. */
4435 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
4436 counter->query_gen = rte_atomic64_read(&pool->query_gen);
4441 * Verify the @p attributes will be correctly understood by the NIC and store
4442 * them in the @p flow if everything is correct.
4445 * Pointer to dev struct.
4446 * @param[in] attributes
4447 * Pointer to flow attributes
4448 * @param[in] external
4449 * This flow rule is created by request external to PMD.
4451 * Pointer to error structure.
4454 * 0 on success, a negative errno value otherwise and rte_errno is set.
4457 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4458 const struct rte_flow_attr *attributes,
4459 bool external __rte_unused,
4460 struct rte_flow_error *error)
4462 struct mlx5_priv *priv = dev->data->dev_private;
4463 uint32_t priority_max = priv->config.flow_prio - 1;
4465 #ifndef HAVE_MLX5DV_DR
4466 if (attributes->group)
4467 return rte_flow_error_set(error, ENOTSUP,
4468 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4470 "groups are not supported");
4475 ret = mlx5_flow_group_to_table(attributes, external,
4476 attributes->group, !!priv->fdb_def_rule,
4481 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4482 attributes->priority >= priority_max)
4483 return rte_flow_error_set(error, ENOTSUP,
4484 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4486 "priority out of range");
4487 if (attributes->transfer) {
4488 if (!priv->config.dv_esw_en)
4489 return rte_flow_error_set
4491 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4492 "E-Switch dr is not supported");
4493 if (!(priv->representor || priv->master))
4494 return rte_flow_error_set
4495 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4496 NULL, "E-Switch configuration can only be"
4497 " done by a master or a representor device");
4498 if (attributes->egress)
4499 return rte_flow_error_set
4501 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4502 "egress is not supported");
4504 if (!(attributes->egress ^ attributes->ingress))
4505 return rte_flow_error_set(error, ENOTSUP,
4506 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4507 "must specify exactly one of "
4508 "ingress or egress");
4513 * Internal validation function. For validating both actions and items.
4516 * Pointer to the rte_eth_dev structure.
4518 * Pointer to the flow attributes.
4520 * Pointer to the list of items.
4521 * @param[in] actions
4522 * Pointer to the list of actions.
4523 * @param[in] external
4524 * This flow rule is created by request external to PMD.
4526 * Pointer to the error structure.
4529 * 0 on success, a negative errno value otherwise and rte_errno is set.
4532 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4533 const struct rte_flow_item items[],
4534 const struct rte_flow_action actions[],
4535 bool external, struct rte_flow_error *error)
4538 uint64_t action_flags = 0;
4539 uint64_t item_flags = 0;
4540 uint64_t last_item = 0;
4541 uint8_t next_protocol = 0xff;
4542 uint16_t ether_type = 0;
4544 uint8_t item_ipv6_proto = 0;
4545 const struct rte_flow_item *gre_item = NULL;
4546 const struct rte_flow_action_raw_decap *decap;
4547 const struct rte_flow_action_raw_encap *encap;
4548 const struct rte_flow_action_rss *rss;
4549 const struct rte_flow_item_tcp nic_tcp_mask = {
4552 .src_port = RTE_BE16(UINT16_MAX),
4553 .dst_port = RTE_BE16(UINT16_MAX),
4556 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4558 .src_addr = RTE_BE32(0xffffffff),
4559 .dst_addr = RTE_BE32(0xffffffff),
4560 .type_of_service = 0xff,
4561 .next_proto_id = 0xff,
4562 .time_to_live = 0xff,
4565 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4568 "\xff\xff\xff\xff\xff\xff\xff\xff"
4569 "\xff\xff\xff\xff\xff\xff\xff\xff",
4571 "\xff\xff\xff\xff\xff\xff\xff\xff"
4572 "\xff\xff\xff\xff\xff\xff\xff\xff",
4573 .vtc_flow = RTE_BE32(0xffffffff),
4578 struct mlx5_priv *priv = dev->data->dev_private;
4579 struct mlx5_dev_config *dev_conf = &priv->config;
4580 uint16_t queue_index = 0xFFFF;
4584 ret = flow_dv_validate_attributes(dev, attr, external, error);
4587 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4588 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4589 int type = items->type;
4592 case RTE_FLOW_ITEM_TYPE_VOID:
4594 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4595 ret = flow_dv_validate_item_port_id
4596 (dev, items, attr, item_flags, error);
4599 last_item = MLX5_FLOW_ITEM_PORT_ID;
4601 case RTE_FLOW_ITEM_TYPE_ETH:
4602 ret = mlx5_flow_validate_item_eth(items, item_flags,
4606 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4607 MLX5_FLOW_LAYER_OUTER_L2;
4608 if (items->mask != NULL && items->spec != NULL) {
4610 ((const struct rte_flow_item_eth *)
4613 ((const struct rte_flow_item_eth *)
4615 ether_type = rte_be_to_cpu_16(ether_type);
4620 case RTE_FLOW_ITEM_TYPE_VLAN:
4621 ret = mlx5_flow_validate_item_vlan(items, item_flags,
4625 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4626 MLX5_FLOW_LAYER_OUTER_VLAN;
4627 if (items->mask != NULL && items->spec != NULL) {
4629 ((const struct rte_flow_item_vlan *)
4630 items->spec)->inner_type;
4632 ((const struct rte_flow_item_vlan *)
4633 items->mask)->inner_type;
4634 ether_type = rte_be_to_cpu_16(ether_type);
4639 case RTE_FLOW_ITEM_TYPE_IPV4:
4640 mlx5_flow_tunnel_ip_check(items, next_protocol,
4641 &item_flags, &tunnel);
4642 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4649 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4650 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4651 if (items->mask != NULL &&
4652 ((const struct rte_flow_item_ipv4 *)
4653 items->mask)->hdr.next_proto_id) {
4655 ((const struct rte_flow_item_ipv4 *)
4656 (items->spec))->hdr.next_proto_id;
4658 ((const struct rte_flow_item_ipv4 *)
4659 (items->mask))->hdr.next_proto_id;
4661 /* Reset for inner layer. */
4662 next_protocol = 0xff;
4665 case RTE_FLOW_ITEM_TYPE_IPV6:
4666 mlx5_flow_tunnel_ip_check(items, next_protocol,
4667 &item_flags, &tunnel);
4668 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4675 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4676 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4677 if (items->mask != NULL &&
4678 ((const struct rte_flow_item_ipv6 *)
4679 items->mask)->hdr.proto) {
4681 ((const struct rte_flow_item_ipv6 *)
4682 items->spec)->hdr.proto;
4684 ((const struct rte_flow_item_ipv6 *)
4685 items->spec)->hdr.proto;
4687 ((const struct rte_flow_item_ipv6 *)
4688 items->mask)->hdr.proto;
4690 /* Reset for inner layer. */
4691 next_protocol = 0xff;
4694 case RTE_FLOW_ITEM_TYPE_TCP:
4695 ret = mlx5_flow_validate_item_tcp
4702 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4703 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4705 case RTE_FLOW_ITEM_TYPE_UDP:
4706 ret = mlx5_flow_validate_item_udp(items, item_flags,
4711 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4712 MLX5_FLOW_LAYER_OUTER_L4_UDP;
4714 case RTE_FLOW_ITEM_TYPE_GRE:
4715 ret = mlx5_flow_validate_item_gre(items, item_flags,
4716 next_protocol, error);
4720 last_item = MLX5_FLOW_LAYER_GRE;
4722 case RTE_FLOW_ITEM_TYPE_NVGRE:
4723 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4728 last_item = MLX5_FLOW_LAYER_NVGRE;
4730 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4731 ret = mlx5_flow_validate_item_gre_key
4732 (items, item_flags, gre_item, error);
4735 last_item = MLX5_FLOW_LAYER_GRE_KEY;
4737 case RTE_FLOW_ITEM_TYPE_VXLAN:
4738 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4742 last_item = MLX5_FLOW_LAYER_VXLAN;
4744 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4745 ret = mlx5_flow_validate_item_vxlan_gpe(items,
4750 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4752 case RTE_FLOW_ITEM_TYPE_GENEVE:
4753 ret = mlx5_flow_validate_item_geneve(items,
4758 last_item = MLX5_FLOW_LAYER_GENEVE;
4760 case RTE_FLOW_ITEM_TYPE_MPLS:
4761 ret = mlx5_flow_validate_item_mpls(dev, items,
4766 last_item = MLX5_FLOW_LAYER_MPLS;
4769 case RTE_FLOW_ITEM_TYPE_MARK:
4770 ret = flow_dv_validate_item_mark(dev, items, attr,
4774 last_item = MLX5_FLOW_ITEM_MARK;
4776 case RTE_FLOW_ITEM_TYPE_META:
4777 ret = flow_dv_validate_item_meta(dev, items, attr,
4781 last_item = MLX5_FLOW_ITEM_METADATA;
4783 case RTE_FLOW_ITEM_TYPE_ICMP:
4784 ret = mlx5_flow_validate_item_icmp(items, item_flags,
4789 last_item = MLX5_FLOW_LAYER_ICMP;
4791 case RTE_FLOW_ITEM_TYPE_ICMP6:
4792 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4797 item_ipv6_proto = IPPROTO_ICMPV6;
4798 last_item = MLX5_FLOW_LAYER_ICMP6;
4800 case RTE_FLOW_ITEM_TYPE_TAG:
4801 ret = flow_dv_validate_item_tag(dev, items,
4805 last_item = MLX5_FLOW_ITEM_TAG;
4807 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4808 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4810 case RTE_FLOW_ITEM_TYPE_GTP:
4811 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
4815 last_item = MLX5_FLOW_LAYER_GTP;
4818 return rte_flow_error_set(error, ENOTSUP,
4819 RTE_FLOW_ERROR_TYPE_ITEM,
4820 NULL, "item not supported");
4822 item_flags |= last_item;
4824 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4825 int type = actions->type;
4826 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4827 return rte_flow_error_set(error, ENOTSUP,
4828 RTE_FLOW_ERROR_TYPE_ACTION,
4829 actions, "too many actions");
4831 case RTE_FLOW_ACTION_TYPE_VOID:
4833 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4834 ret = flow_dv_validate_action_port_id(dev,
4841 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4844 case RTE_FLOW_ACTION_TYPE_FLAG:
4845 ret = flow_dv_validate_action_flag(dev, action_flags,
4849 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4850 /* Count all modify-header actions as one. */
4851 if (!(action_flags &
4852 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4854 action_flags |= MLX5_FLOW_ACTION_FLAG |
4855 MLX5_FLOW_ACTION_MARK_EXT;
4857 action_flags |= MLX5_FLOW_ACTION_FLAG;
4861 case RTE_FLOW_ACTION_TYPE_MARK:
4862 ret = flow_dv_validate_action_mark(dev, actions,
4867 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4868 /* Count all modify-header actions as one. */
4869 if (!(action_flags &
4870 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4872 action_flags |= MLX5_FLOW_ACTION_MARK |
4873 MLX5_FLOW_ACTION_MARK_EXT;
4875 action_flags |= MLX5_FLOW_ACTION_MARK;
4879 case RTE_FLOW_ACTION_TYPE_SET_META:
4880 ret = flow_dv_validate_action_set_meta(dev, actions,
4885 /* Count all modify-header actions as one action. */
4886 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4888 action_flags |= MLX5_FLOW_ACTION_SET_META;
4890 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4891 ret = flow_dv_validate_action_set_tag(dev, actions,
4896 /* Count all modify-header actions as one action. */
4897 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4899 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4901 case RTE_FLOW_ACTION_TYPE_DROP:
4902 ret = mlx5_flow_validate_action_drop(action_flags,
4906 action_flags |= MLX5_FLOW_ACTION_DROP;
4909 case RTE_FLOW_ACTION_TYPE_QUEUE:
4910 ret = mlx5_flow_validate_action_queue(actions,
4915 queue_index = ((const struct rte_flow_action_queue *)
4916 (actions->conf))->index;
4917 action_flags |= MLX5_FLOW_ACTION_QUEUE;
4920 case RTE_FLOW_ACTION_TYPE_RSS:
4921 rss = actions->conf;
4922 ret = mlx5_flow_validate_action_rss(actions,
4928 if (rss != NULL && rss->queue_num)
4929 queue_index = rss->queue[0];
4930 action_flags |= MLX5_FLOW_ACTION_RSS;
4933 case RTE_FLOW_ACTION_TYPE_COUNT:
4934 ret = flow_dv_validate_action_count(dev, error);
4937 action_flags |= MLX5_FLOW_ACTION_COUNT;
4940 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4941 if (flow_dv_validate_action_pop_vlan(dev,
4947 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
4950 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
4951 ret = flow_dv_validate_action_push_vlan(dev,
4958 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
4961 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
4962 ret = flow_dv_validate_action_set_vlan_pcp
4963 (action_flags, actions, error);
4966 /* Count PCP with push_vlan command. */
4967 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
4969 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
4970 ret = flow_dv_validate_action_set_vlan_vid
4971 (item_flags, action_flags,
4975 /* Count VID with push_vlan command. */
4976 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
4978 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
4979 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
4980 ret = flow_dv_validate_action_l2_encap(dev,
4986 action_flags |= MLX5_FLOW_ACTION_ENCAP;
4989 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
4990 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
4991 ret = flow_dv_validate_action_decap(dev, action_flags,
4995 action_flags |= MLX5_FLOW_ACTION_DECAP;
4998 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4999 ret = flow_dv_validate_action_raw_encap_decap
5000 (dev, NULL, actions->conf, attr, &action_flags,
5005 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5006 decap = actions->conf;
5007 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5009 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5013 encap = actions->conf;
5015 ret = flow_dv_validate_action_raw_encap_decap
5017 decap ? decap : &empty_decap, encap,
5018 attr, &action_flags, &actions_n,
5023 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5024 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5025 ret = flow_dv_validate_action_modify_mac(action_flags,
5031 /* Count all modify-header actions as one action. */
5032 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5034 action_flags |= actions->type ==
5035 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5036 MLX5_FLOW_ACTION_SET_MAC_SRC :
5037 MLX5_FLOW_ACTION_SET_MAC_DST;
5040 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5041 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5042 ret = flow_dv_validate_action_modify_ipv4(action_flags,
5048 /* Count all modify-header actions as one action. */
5049 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5051 action_flags |= actions->type ==
5052 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5053 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5054 MLX5_FLOW_ACTION_SET_IPV4_DST;
5056 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5057 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5058 ret = flow_dv_validate_action_modify_ipv6(action_flags,
5064 if (item_ipv6_proto == IPPROTO_ICMPV6)
5065 return rte_flow_error_set(error, ENOTSUP,
5066 RTE_FLOW_ERROR_TYPE_ACTION,
5068 "Can't change header "
5069 "with ICMPv6 proto");
5070 /* Count all modify-header actions as one action. */
5071 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5073 action_flags |= actions->type ==
5074 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5075 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5076 MLX5_FLOW_ACTION_SET_IPV6_DST;
5078 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5079 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5080 ret = flow_dv_validate_action_modify_tp(action_flags,
5086 /* Count all modify-header actions as one action. */
5087 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5089 action_flags |= actions->type ==
5090 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5091 MLX5_FLOW_ACTION_SET_TP_SRC :
5092 MLX5_FLOW_ACTION_SET_TP_DST;
5094 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5095 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5096 ret = flow_dv_validate_action_modify_ttl(action_flags,
5102 /* Count all modify-header actions as one action. */
5103 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5105 action_flags |= actions->type ==
5106 RTE_FLOW_ACTION_TYPE_SET_TTL ?
5107 MLX5_FLOW_ACTION_SET_TTL :
5108 MLX5_FLOW_ACTION_DEC_TTL;
5110 case RTE_FLOW_ACTION_TYPE_JUMP:
5111 ret = flow_dv_validate_action_jump(actions,
5118 action_flags |= MLX5_FLOW_ACTION_JUMP;
5120 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5121 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5122 ret = flow_dv_validate_action_modify_tcp_seq
5129 /* Count all modify-header actions as one action. */
5130 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5132 action_flags |= actions->type ==
5133 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5134 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5135 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5137 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5138 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5139 ret = flow_dv_validate_action_modify_tcp_ack
5146 /* Count all modify-header actions as one action. */
5147 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5149 action_flags |= actions->type ==
5150 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5151 MLX5_FLOW_ACTION_INC_TCP_ACK :
5152 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5154 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5155 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5156 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5158 case RTE_FLOW_ACTION_TYPE_METER:
5159 ret = mlx5_flow_validate_action_meter(dev,
5165 action_flags |= MLX5_FLOW_ACTION_METER;
5168 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5169 ret = flow_dv_validate_action_modify_ipv4_dscp
5176 /* Count all modify-header actions as one action. */
5177 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5179 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5181 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5182 ret = flow_dv_validate_action_modify_ipv6_dscp
5189 /* Count all modify-header actions as one action. */
5190 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5192 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5195 return rte_flow_error_set(error, ENOTSUP,
5196 RTE_FLOW_ERROR_TYPE_ACTION,
5198 "action not supported");
5202 * Validate the drop action mutual exclusion with other actions.
5203 * Drop action is mutually-exclusive with any other action, except for
5206 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5207 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5208 return rte_flow_error_set(error, EINVAL,
5209 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5210 "Drop action is mutually-exclusive "
5211 "with any other action, except for "
5213 /* Eswitch has few restrictions on using items and actions */
5214 if (attr->transfer) {
5215 if (!mlx5_flow_ext_mreg_supported(dev) &&
5216 action_flags & MLX5_FLOW_ACTION_FLAG)
5217 return rte_flow_error_set(error, ENOTSUP,
5218 RTE_FLOW_ERROR_TYPE_ACTION,
5220 "unsupported action FLAG");
5221 if (!mlx5_flow_ext_mreg_supported(dev) &&
5222 action_flags & MLX5_FLOW_ACTION_MARK)
5223 return rte_flow_error_set(error, ENOTSUP,
5224 RTE_FLOW_ERROR_TYPE_ACTION,
5226 "unsupported action MARK");
5227 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5228 return rte_flow_error_set(error, ENOTSUP,
5229 RTE_FLOW_ERROR_TYPE_ACTION,
5231 "unsupported action QUEUE");
5232 if (action_flags & MLX5_FLOW_ACTION_RSS)
5233 return rte_flow_error_set(error, ENOTSUP,
5234 RTE_FLOW_ERROR_TYPE_ACTION,
5236 "unsupported action RSS");
5237 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5238 return rte_flow_error_set(error, EINVAL,
5239 RTE_FLOW_ERROR_TYPE_ACTION,
5241 "no fate action is found");
5243 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5244 return rte_flow_error_set(error, EINVAL,
5245 RTE_FLOW_ERROR_TYPE_ACTION,
5247 "no fate action is found");
5249 /* Continue validation for Xcap actions.*/
5250 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5251 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5252 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5253 MLX5_FLOW_XCAP_ACTIONS)
5254 return rte_flow_error_set(error, ENOTSUP,
5255 RTE_FLOW_ERROR_TYPE_ACTION,
5256 NULL, "encap and decap "
5257 "combination aren't supported");
5258 if (!attr->transfer && attr->ingress && (action_flags &
5259 MLX5_FLOW_ACTION_ENCAP))
5260 return rte_flow_error_set(error, ENOTSUP,
5261 RTE_FLOW_ERROR_TYPE_ACTION,
5262 NULL, "encap is not supported"
5263 " for ingress traffic");
5269 * Internal preparation function. Allocates the DV flow size,
5270 * this size is constant.
5273 * Pointer to the flow attributes.
5275 * Pointer to the list of items.
5276 * @param[in] actions
5277 * Pointer to the list of actions.
5279 * Pointer to the error structure.
5282 * Pointer to mlx5_flow object on success,
5283 * otherwise NULL and rte_errno is set.
5285 static struct mlx5_flow *
5286 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
5287 const struct rte_flow_item items[] __rte_unused,
5288 const struct rte_flow_action actions[] __rte_unused,
5289 struct rte_flow_error *error)
5291 size_t size = sizeof(struct mlx5_flow);
5292 struct mlx5_flow *dev_flow;
5294 dev_flow = rte_calloc(__func__, 1, size, 0);
5296 rte_flow_error_set(error, ENOMEM,
5297 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5298 "not enough memory to create flow");
5301 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5302 dev_flow->ingress = attr->ingress;
5303 dev_flow->transfer = attr->transfer;
5307 #ifdef RTE_LIBRTE_MLX5_DEBUG
5309 * Sanity check for match mask and value. Similar to check_valid_spec() in
5310 * kernel driver. If unmasked bit is present in value, it returns failure.
5313 * pointer to match mask buffer.
5314 * @param match_value
5315 * pointer to match value buffer.
5318 * 0 if valid, -EINVAL otherwise.
5321 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5323 uint8_t *m = match_mask;
5324 uint8_t *v = match_value;
5327 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5330 "match_value differs from match_criteria"
5331 " %p[%u] != %p[%u]",
5332 match_value, i, match_mask, i);
5341 * Add Ethernet item to matcher and to the value.
5343 * @param[in, out] matcher
5345 * @param[in, out] key
5346 * Flow matcher value.
5348 * Flow pattern to translate.
5350 * Item is inner pattern.
5353 flow_dv_translate_item_eth(void *matcher, void *key,
5354 const struct rte_flow_item *item, int inner)
5356 const struct rte_flow_item_eth *eth_m = item->mask;
5357 const struct rte_flow_item_eth *eth_v = item->spec;
5358 const struct rte_flow_item_eth nic_mask = {
5359 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5360 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5361 .type = RTE_BE16(0xffff),
5373 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5375 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5377 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5379 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5381 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5382 ð_m->dst, sizeof(eth_m->dst));
5383 /* The value must be in the range of the mask. */
5384 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5385 for (i = 0; i < sizeof(eth_m->dst); ++i)
5386 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5387 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5388 ð_m->src, sizeof(eth_m->src));
5389 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5390 /* The value must be in the range of the mask. */
5391 for (i = 0; i < sizeof(eth_m->dst); ++i)
5392 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5394 /* When ethertype is present set mask for tagged VLAN. */
5395 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5396 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5397 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5398 eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5399 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5401 /* Return here to avoid setting match on ethertype. */
5406 * HW supports match on one Ethertype, the Ethertype following the last
5407 * VLAN tag of the packet (see PRM).
5408 * Set match on ethertype only if ETH header is not followed by VLAN.
5410 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5411 rte_be_to_cpu_16(eth_m->type));
5412 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5413 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5417 * Add VLAN item to matcher and to the value.
5419 * @param[in, out] dev_flow
5421 * @param[in, out] matcher
5423 * @param[in, out] key
5424 * Flow matcher value.
5426 * Flow pattern to translate.
5428 * Item is inner pattern.
5431 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5432 void *matcher, void *key,
5433 const struct rte_flow_item *item,
5436 const struct rte_flow_item_vlan *vlan_m = item->mask;
5437 const struct rte_flow_item_vlan *vlan_v = item->spec;
5446 vlan_m = &rte_flow_item_vlan_mask;
5448 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5450 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5452 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5454 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5456 * This is workaround, masks are not supported,
5457 * and pre-validated.
5459 dev_flow->dv.vf_vlan.tag =
5460 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5462 tci_m = rte_be_to_cpu_16(vlan_m->tci);
5463 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5464 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5465 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5466 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5467 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5468 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5469 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5470 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5471 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5472 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5473 rte_be_to_cpu_16(vlan_m->inner_type));
5474 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5475 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5479 * Add IPV4 item to matcher and to the value.
5481 * @param[in, out] matcher
5483 * @param[in, out] key
5484 * Flow matcher value.
5486 * Flow pattern to translate.
5487 * @param[in] item_flags
5488 * Bit-fields that holds the items detected until now.
5490 * Item is inner pattern.
5492 * The group to insert the rule.
5495 flow_dv_translate_item_ipv4(void *matcher, void *key,
5496 const struct rte_flow_item *item,
5497 const uint64_t item_flags,
5498 int inner, uint32_t group)
5500 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5501 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5502 const struct rte_flow_item_ipv4 nic_mask = {
5504 .src_addr = RTE_BE32(0xffffffff),
5505 .dst_addr = RTE_BE32(0xffffffff),
5506 .type_of_service = 0xff,
5507 .next_proto_id = 0xff,
5508 .time_to_live = 0xff,
5518 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5520 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5522 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5524 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5527 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5529 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5530 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5532 * On outer header (which must contains L2), or inner header with L2,
5533 * set cvlan_tag mask bit to mark this packet as untagged.
5534 * This should be done even if item->spec is empty.
5536 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5537 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5542 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5543 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5544 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5545 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5546 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5547 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5548 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5549 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5550 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5551 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5552 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5553 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5554 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5555 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5556 ipv4_m->hdr.type_of_service);
5557 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5558 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5559 ipv4_m->hdr.type_of_service >> 2);
5560 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5561 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5562 ipv4_m->hdr.next_proto_id);
5563 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5564 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5565 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5566 ipv4_m->hdr.time_to_live);
5567 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5568 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5572 * Add IPV6 item to matcher and to the value.
5574 * @param[in, out] matcher
5576 * @param[in, out] key
5577 * Flow matcher value.
5579 * Flow pattern to translate.
5580 * @param[in] item_flags
5581 * Bit-fields that holds the items detected until now.
5583 * Item is inner pattern.
5585 * The group to insert the rule.
5588 flow_dv_translate_item_ipv6(void *matcher, void *key,
5589 const struct rte_flow_item *item,
5590 const uint64_t item_flags,
5591 int inner, uint32_t group)
5593 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5594 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5595 const struct rte_flow_item_ipv6 nic_mask = {
5598 "\xff\xff\xff\xff\xff\xff\xff\xff"
5599 "\xff\xff\xff\xff\xff\xff\xff\xff",
5601 "\xff\xff\xff\xff\xff\xff\xff\xff"
5602 "\xff\xff\xff\xff\xff\xff\xff\xff",
5603 .vtc_flow = RTE_BE32(0xffffffff),
5610 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5611 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5620 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5622 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5624 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5626 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5629 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5631 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5632 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5634 * On outer header (which must contains L2), or inner header with L2,
5635 * set cvlan_tag mask bit to mark this packet as untagged.
5636 * This should be done even if item->spec is empty.
5638 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5639 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5644 size = sizeof(ipv6_m->hdr.dst_addr);
5645 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5646 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5647 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5648 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5649 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5650 for (i = 0; i < size; ++i)
5651 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5652 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5653 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5654 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5655 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5656 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5657 for (i = 0; i < size; ++i)
5658 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5660 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5661 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5662 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5663 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5664 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5665 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5668 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5670 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5673 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5675 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5679 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5681 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5682 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5684 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5685 ipv6_m->hdr.hop_limits);
5686 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5687 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
5691 * Add TCP item to matcher and to the value.
5693 * @param[in, out] matcher
5695 * @param[in, out] key
5696 * Flow matcher value.
5698 * Flow pattern to translate.
5700 * Item is inner pattern.
5703 flow_dv_translate_item_tcp(void *matcher, void *key,
5704 const struct rte_flow_item *item,
5707 const struct rte_flow_item_tcp *tcp_m = item->mask;
5708 const struct rte_flow_item_tcp *tcp_v = item->spec;
5713 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5715 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5717 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5719 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5721 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5722 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5726 tcp_m = &rte_flow_item_tcp_mask;
5727 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5728 rte_be_to_cpu_16(tcp_m->hdr.src_port));
5729 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5730 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5731 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5732 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5733 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5734 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5735 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5736 tcp_m->hdr.tcp_flags);
5737 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5738 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5742 * Add UDP item to matcher and to the value.
5744 * @param[in, out] matcher
5746 * @param[in, out] key
5747 * Flow matcher value.
5749 * Flow pattern to translate.
5751 * Item is inner pattern.
5754 flow_dv_translate_item_udp(void *matcher, void *key,
5755 const struct rte_flow_item *item,
5758 const struct rte_flow_item_udp *udp_m = item->mask;
5759 const struct rte_flow_item_udp *udp_v = item->spec;
5764 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5766 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5768 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5770 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5772 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5773 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5777 udp_m = &rte_flow_item_udp_mask;
5778 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5779 rte_be_to_cpu_16(udp_m->hdr.src_port));
5780 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5781 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5782 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5783 rte_be_to_cpu_16(udp_m->hdr.dst_port));
5784 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5785 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5789 * Add GRE optional Key item to matcher and to the value.
5791 * @param[in, out] matcher
5793 * @param[in, out] key
5794 * Flow matcher value.
5796 * Flow pattern to translate.
5798 * Item is inner pattern.
5801 flow_dv_translate_item_gre_key(void *matcher, void *key,
5802 const struct rte_flow_item *item)
5804 const rte_be32_t *key_m = item->mask;
5805 const rte_be32_t *key_v = item->spec;
5806 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5807 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5808 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5810 /* GRE K bit must be on and should already be validated */
5811 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5812 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5816 key_m = &gre_key_default_mask;
5817 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5818 rte_be_to_cpu_32(*key_m) >> 8);
5819 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5820 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5821 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5822 rte_be_to_cpu_32(*key_m) & 0xFF);
5823 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5824 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5828 * Add GRE item to matcher and to the value.
5830 * @param[in, out] matcher
5832 * @param[in, out] key
5833 * Flow matcher value.
5835 * Flow pattern to translate.
5837 * Item is inner pattern.
5840 flow_dv_translate_item_gre(void *matcher, void *key,
5841 const struct rte_flow_item *item,
5844 const struct rte_flow_item_gre *gre_m = item->mask;
5845 const struct rte_flow_item_gre *gre_v = item->spec;
5848 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5849 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5856 uint16_t s_present:1;
5857 uint16_t k_present:1;
5858 uint16_t rsvd_bit1:1;
5859 uint16_t c_present:1;
5863 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5866 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5868 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5870 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5872 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5874 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5875 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5879 gre_m = &rte_flow_item_gre_mask;
5880 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5881 rte_be_to_cpu_16(gre_m->protocol));
5882 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5883 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5884 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5885 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5886 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5887 gre_crks_rsvd0_ver_m.c_present);
5888 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
5889 gre_crks_rsvd0_ver_v.c_present &
5890 gre_crks_rsvd0_ver_m.c_present);
5891 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
5892 gre_crks_rsvd0_ver_m.k_present);
5893 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
5894 gre_crks_rsvd0_ver_v.k_present &
5895 gre_crks_rsvd0_ver_m.k_present);
5896 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
5897 gre_crks_rsvd0_ver_m.s_present);
5898 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
5899 gre_crks_rsvd0_ver_v.s_present &
5900 gre_crks_rsvd0_ver_m.s_present);
5904 * Add NVGRE item to matcher and to the value.
5906 * @param[in, out] matcher
5908 * @param[in, out] key
5909 * Flow matcher value.
5911 * Flow pattern to translate.
5913 * Item is inner pattern.
5916 flow_dv_translate_item_nvgre(void *matcher, void *key,
5917 const struct rte_flow_item *item,
5920 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
5921 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
5922 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5923 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5924 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
5925 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
5931 /* For NVGRE, GRE header fields must be set with defined values. */
5932 const struct rte_flow_item_gre gre_spec = {
5933 .c_rsvd0_ver = RTE_BE16(0x2000),
5934 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
5936 const struct rte_flow_item_gre gre_mask = {
5937 .c_rsvd0_ver = RTE_BE16(0xB000),
5938 .protocol = RTE_BE16(UINT16_MAX),
5940 const struct rte_flow_item gre_item = {
5945 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
5949 nvgre_m = &rte_flow_item_nvgre_mask;
5950 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
5951 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
5952 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
5953 memcpy(gre_key_m, tni_flow_id_m, size);
5954 for (i = 0; i < size; ++i)
5955 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
5959 * Add VXLAN item to matcher and to the value.
5961 * @param[in, out] matcher
5963 * @param[in, out] key
5964 * Flow matcher value.
5966 * Flow pattern to translate.
5968 * Item is inner pattern.
5971 flow_dv_translate_item_vxlan(void *matcher, void *key,
5972 const struct rte_flow_item *item,
5975 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
5976 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
5979 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5980 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5988 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5990 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5992 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5994 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5996 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
5997 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
5998 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5999 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6000 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6005 vxlan_m = &rte_flow_item_vxlan_mask;
6006 size = sizeof(vxlan_m->vni);
6007 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6008 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6009 memcpy(vni_m, vxlan_m->vni, size);
6010 for (i = 0; i < size; ++i)
6011 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6015 * Add VXLAN-GPE item to matcher and to the value.
6017 * @param[in, out] matcher
6019 * @param[in, out] key
6020 * Flow matcher value.
6022 * Flow pattern to translate.
6024 * Item is inner pattern.
6028 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6029 const struct rte_flow_item *item, int inner)
6031 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6032 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6036 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6038 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6044 uint8_t flags_m = 0xff;
6045 uint8_t flags_v = 0xc;
6048 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6050 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6052 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6054 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6056 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6057 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6058 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6059 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6060 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6065 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6066 size = sizeof(vxlan_m->vni);
6067 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6068 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6069 memcpy(vni_m, vxlan_m->vni, size);
6070 for (i = 0; i < size; ++i)
6071 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6072 if (vxlan_m->flags) {
6073 flags_m = vxlan_m->flags;
6074 flags_v = vxlan_v->flags;
6076 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6077 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6078 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6080 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6085 * Add Geneve item to matcher and to the value.
6087 * @param[in, out] matcher
6089 * @param[in, out] key
6090 * Flow matcher value.
6092 * Flow pattern to translate.
6094 * Item is inner pattern.
6098 flow_dv_translate_item_geneve(void *matcher, void *key,
6099 const struct rte_flow_item *item, int inner)
6101 const struct rte_flow_item_geneve *geneve_m = item->mask;
6102 const struct rte_flow_item_geneve *geneve_v = item->spec;
6105 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6106 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6115 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6117 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6119 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6121 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6123 dport = MLX5_UDP_PORT_GENEVE;
6124 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6125 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6126 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6131 geneve_m = &rte_flow_item_geneve_mask;
6132 size = sizeof(geneve_m->vni);
6133 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6134 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6135 memcpy(vni_m, geneve_m->vni, size);
6136 for (i = 0; i < size; ++i)
6137 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6138 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6139 rte_be_to_cpu_16(geneve_m->protocol));
6140 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6141 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6142 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6143 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6144 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6145 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6146 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6147 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6148 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6149 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6150 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6151 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6152 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6156 * Add MPLS item to matcher and to the value.
6158 * @param[in, out] matcher
6160 * @param[in, out] key
6161 * Flow matcher value.
6163 * Flow pattern to translate.
6164 * @param[in] prev_layer
6165 * The protocol layer indicated in previous item.
6167 * Item is inner pattern.
6170 flow_dv_translate_item_mpls(void *matcher, void *key,
6171 const struct rte_flow_item *item,
6172 uint64_t prev_layer,
6175 const uint32_t *in_mpls_m = item->mask;
6176 const uint32_t *in_mpls_v = item->spec;
6177 uint32_t *out_mpls_m = 0;
6178 uint32_t *out_mpls_v = 0;
6179 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6180 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6181 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6183 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6184 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6185 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6187 switch (prev_layer) {
6188 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6189 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6190 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6191 MLX5_UDP_PORT_MPLS);
6193 case MLX5_FLOW_LAYER_GRE:
6194 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6195 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6196 RTE_ETHER_TYPE_MPLS);
6199 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6200 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6207 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6208 switch (prev_layer) {
6209 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6211 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6212 outer_first_mpls_over_udp);
6214 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6215 outer_first_mpls_over_udp);
6217 case MLX5_FLOW_LAYER_GRE:
6219 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6220 outer_first_mpls_over_gre);
6222 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6223 outer_first_mpls_over_gre);
6226 /* Inner MPLS not over GRE is not supported. */
6229 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6233 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6239 if (out_mpls_m && out_mpls_v) {
6240 *out_mpls_m = *in_mpls_m;
6241 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6246 * Add metadata register item to matcher
6248 * @param[in, out] matcher
6250 * @param[in, out] key
6251 * Flow matcher value.
6252 * @param[in] reg_type
6253 * Type of device metadata register
6260 flow_dv_match_meta_reg(void *matcher, void *key,
6261 enum modify_reg reg_type,
6262 uint32_t data, uint32_t mask)
6265 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6267 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6273 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6274 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6277 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6278 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6282 * The metadata register C0 field might be divided into
6283 * source vport index and META item value, we should set
6284 * this field according to specified mask, not as whole one.
6286 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6288 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6289 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6292 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6295 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6296 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6299 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6300 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6303 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6304 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6307 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6308 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6311 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6312 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6315 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6316 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6319 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6320 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6329 * Add MARK item to matcher
6332 * The device to configure through.
6333 * @param[in, out] matcher
6335 * @param[in, out] key
6336 * Flow matcher value.
6338 * Flow pattern to translate.
6341 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6342 void *matcher, void *key,
6343 const struct rte_flow_item *item)
6345 struct mlx5_priv *priv = dev->data->dev_private;
6346 const struct rte_flow_item_mark *mark;
6350 mark = item->mask ? (const void *)item->mask :
6351 &rte_flow_item_mark_mask;
6352 mask = mark->id & priv->sh->dv_mark_mask;
6353 mark = (const void *)item->spec;
6355 value = mark->id & priv->sh->dv_mark_mask & mask;
6357 enum modify_reg reg;
6359 /* Get the metadata register index for the mark. */
6360 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6361 MLX5_ASSERT(reg > 0);
6362 if (reg == REG_C_0) {
6363 struct mlx5_priv *priv = dev->data->dev_private;
6364 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6365 uint32_t shl_c0 = rte_bsf32(msk_c0);
6371 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6376 * Add META item to matcher
6379 * The devich to configure through.
6380 * @param[in, out] matcher
6382 * @param[in, out] key
6383 * Flow matcher value.
6385 * Attributes of flow that includes this item.
6387 * Flow pattern to translate.
6390 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6391 void *matcher, void *key,
6392 const struct rte_flow_attr *attr,
6393 const struct rte_flow_item *item)
6395 const struct rte_flow_item_meta *meta_m;
6396 const struct rte_flow_item_meta *meta_v;
6398 meta_m = (const void *)item->mask;
6400 meta_m = &rte_flow_item_meta_mask;
6401 meta_v = (const void *)item->spec;
6404 uint32_t value = meta_v->data;
6405 uint32_t mask = meta_m->data;
6407 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6411 * In datapath code there is no endianness
6412 * coversions for perfromance reasons, all
6413 * pattern conversions are done in rte_flow.
6415 value = rte_cpu_to_be_32(value);
6416 mask = rte_cpu_to_be_32(mask);
6417 if (reg == REG_C_0) {
6418 struct mlx5_priv *priv = dev->data->dev_private;
6419 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6420 uint32_t shl_c0 = rte_bsf32(msk_c0);
6421 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6422 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6429 MLX5_ASSERT(msk_c0);
6430 MLX5_ASSERT(!(~msk_c0 & mask));
6432 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6437 * Add vport metadata Reg C0 item to matcher
6439 * @param[in, out] matcher
6441 * @param[in, out] key
6442 * Flow matcher value.
6444 * Flow pattern to translate.
6447 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6448 uint32_t value, uint32_t mask)
6450 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6454 * Add tag item to matcher
6457 * The devich to configure through.
6458 * @param[in, out] matcher
6460 * @param[in, out] key
6461 * Flow matcher value.
6463 * Flow pattern to translate.
6466 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6467 void *matcher, void *key,
6468 const struct rte_flow_item *item)
6470 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6471 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6472 uint32_t mask, value;
6475 value = tag_v->data;
6476 mask = tag_m ? tag_m->data : UINT32_MAX;
6477 if (tag_v->id == REG_C_0) {
6478 struct mlx5_priv *priv = dev->data->dev_private;
6479 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6480 uint32_t shl_c0 = rte_bsf32(msk_c0);
6486 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6490 * Add TAG item to matcher
6493 * The devich to configure through.
6494 * @param[in, out] matcher
6496 * @param[in, out] key
6497 * Flow matcher value.
6499 * Flow pattern to translate.
6502 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6503 void *matcher, void *key,
6504 const struct rte_flow_item *item)
6506 const struct rte_flow_item_tag *tag_v = item->spec;
6507 const struct rte_flow_item_tag *tag_m = item->mask;
6508 enum modify_reg reg;
6511 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6512 /* Get the metadata register index for the tag. */
6513 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6514 MLX5_ASSERT(reg > 0);
6515 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6519 * Add source vport match to the specified matcher.
6521 * @param[in, out] matcher
6523 * @param[in, out] key
6524 * Flow matcher value.
6526 * Source vport value to match
6531 flow_dv_translate_item_source_vport(void *matcher, void *key,
6532 int16_t port, uint16_t mask)
6534 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6535 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6537 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6538 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6542 * Translate port-id item to eswitch match on port-id.
6545 * The devich to configure through.
6546 * @param[in, out] matcher
6548 * @param[in, out] key
6549 * Flow matcher value.
6551 * Flow pattern to translate.
6554 * 0 on success, a negative errno value otherwise.
6557 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6558 void *key, const struct rte_flow_item *item)
6560 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6561 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6562 struct mlx5_priv *priv;
6565 mask = pid_m ? pid_m->id : 0xffff;
6566 id = pid_v ? pid_v->id : dev->data->port_id;
6567 priv = mlx5_port_to_eswitch_info(id, item == NULL);
6570 /* Translate to vport field or to metadata, depending on mode. */
6571 if (priv->vport_meta_mask)
6572 flow_dv_translate_item_meta_vport(matcher, key,
6573 priv->vport_meta_tag,
6574 priv->vport_meta_mask);
6576 flow_dv_translate_item_source_vport(matcher, key,
6577 priv->vport_id, mask);
6582 * Add ICMP6 item to matcher and to the value.
6584 * @param[in, out] matcher
6586 * @param[in, out] key
6587 * Flow matcher value.
6589 * Flow pattern to translate.
6591 * Item is inner pattern.
6594 flow_dv_translate_item_icmp6(void *matcher, void *key,
6595 const struct rte_flow_item *item,
6598 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6599 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6602 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6604 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6606 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6608 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6610 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6612 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6614 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6615 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6619 icmp6_m = &rte_flow_item_icmp6_mask;
6621 * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
6622 * If only the protocol is specified, no need to match the frag.
6624 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6625 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6626 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6627 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6628 icmp6_v->type & icmp6_m->type);
6629 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6630 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6631 icmp6_v->code & icmp6_m->code);
6635 * Add ICMP item to matcher and to the value.
6637 * @param[in, out] matcher
6639 * @param[in, out] key
6640 * Flow matcher value.
6642 * Flow pattern to translate.
6644 * Item is inner pattern.
6647 flow_dv_translate_item_icmp(void *matcher, void *key,
6648 const struct rte_flow_item *item,
6651 const struct rte_flow_item_icmp *icmp_m = item->mask;
6652 const struct rte_flow_item_icmp *icmp_v = item->spec;
6655 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6657 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6659 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6661 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6663 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6665 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6667 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6668 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6672 icmp_m = &rte_flow_item_icmp_mask;
6674 * Force flow only to match the non-fragmented IPv4 ICMP packets.
6675 * If only the protocol is specified, no need to match the frag.
6677 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6678 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6679 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6680 icmp_m->hdr.icmp_type);
6681 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6682 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6683 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6684 icmp_m->hdr.icmp_code);
6685 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6686 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6690 * Add GTP item to matcher and to the value.
6692 * @param[in, out] matcher
6694 * @param[in, out] key
6695 * Flow matcher value.
6697 * Flow pattern to translate.
6699 * Item is inner pattern.
6702 flow_dv_translate_item_gtp(void *matcher, void *key,
6703 const struct rte_flow_item *item, int inner)
6705 const struct rte_flow_item_gtp *gtp_m = item->mask;
6706 const struct rte_flow_item_gtp *gtp_v = item->spec;
6709 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6711 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6712 uint16_t dport = RTE_GTPU_UDP_PORT;
6715 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6717 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6719 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6721 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6723 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6724 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6725 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6730 gtp_m = &rte_flow_item_gtp_mask;
6731 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
6732 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
6733 gtp_v->msg_type & gtp_m->msg_type);
6734 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
6735 rte_be_to_cpu_32(gtp_m->teid));
6736 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
6737 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
6740 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6742 #define HEADER_IS_ZERO(match_criteria, headers) \
6743 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
6744 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6747 * Calculate flow matcher enable bitmap.
6749 * @param match_criteria
6750 * Pointer to flow matcher criteria.
6753 * Bitmap of enabled fields.
6756 flow_dv_matcher_enable(uint32_t *match_criteria)
6758 uint8_t match_criteria_enable;
6760 match_criteria_enable =
6761 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6762 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6763 match_criteria_enable |=
6764 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6765 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6766 match_criteria_enable |=
6767 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6768 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6769 match_criteria_enable |=
6770 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6771 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6772 match_criteria_enable |=
6773 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6774 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6775 return match_criteria_enable;
6782 * @param[in, out] dev
6783 * Pointer to rte_eth_dev structure.
6784 * @param[in] table_id
6787 * Direction of the table.
6788 * @param[in] transfer
6789 * E-Switch or NIC flow.
6791 * pointer to error structure.
6794 * Returns tables resource based on the index, NULL in case of failed.
6796 static struct mlx5_flow_tbl_resource *
6797 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6798 uint32_t table_id, uint8_t egress,
6800 struct rte_flow_error *error)
6802 struct mlx5_priv *priv = dev->data->dev_private;
6803 struct mlx5_ibv_shared *sh = priv->sh;
6804 struct mlx5_flow_tbl_resource *tbl;
6805 union mlx5_flow_tbl_key table_key = {
6807 .table_id = table_id,
6809 .domain = !!transfer,
6810 .direction = !!egress,
6813 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6815 struct mlx5_flow_tbl_data_entry *tbl_data;
6820 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6822 tbl = &tbl_data->tbl;
6823 rte_atomic32_inc(&tbl->refcnt);
6826 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
6828 rte_flow_error_set(error, ENOMEM,
6829 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6831 "cannot allocate flow table data entry");
6834 tbl = &tbl_data->tbl;
6835 pos = &tbl_data->entry;
6837 domain = sh->fdb_domain;
6839 domain = sh->tx_domain;
6841 domain = sh->rx_domain;
6842 tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6844 rte_flow_error_set(error, ENOMEM,
6845 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6846 NULL, "cannot create flow table object");
6851 * No multi-threads now, but still better to initialize the reference
6852 * count before insert it into the hash list.
6854 rte_atomic32_init(&tbl->refcnt);
6855 /* Jump action reference count is initialized here. */
6856 rte_atomic32_init(&tbl_data->jump.refcnt);
6857 pos->key = table_key.v64;
6858 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6860 rte_flow_error_set(error, -ret,
6861 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6862 "cannot insert flow table data entry");
6863 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6866 rte_atomic32_inc(&tbl->refcnt);
6871 * Release a flow table.
6874 * Pointer to rte_eth_dev structure.
6876 * Table resource to be released.
6879 * Returns 0 if table was released, else return 1;
6882 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
6883 struct mlx5_flow_tbl_resource *tbl)
6885 struct mlx5_priv *priv = dev->data->dev_private;
6886 struct mlx5_ibv_shared *sh = priv->sh;
6887 struct mlx5_flow_tbl_data_entry *tbl_data =
6888 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6892 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
6893 struct mlx5_hlist_entry *pos = &tbl_data->entry;
6895 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6897 /* remove the entry from the hash list and free memory. */
6898 mlx5_hlist_remove(sh->flow_tbls, pos);
6906 * Register the flow matcher.
6908 * @param[in, out] dev
6909 * Pointer to rte_eth_dev structure.
6910 * @param[in, out] matcher
6911 * Pointer to flow matcher.
6912 * @param[in, out] key
6913 * Pointer to flow table key.
6914 * @parm[in, out] dev_flow
6915 * Pointer to the dev_flow.
6917 * pointer to error structure.
6920 * 0 on success otherwise -errno and errno is set.
6923 flow_dv_matcher_register(struct rte_eth_dev *dev,
6924 struct mlx5_flow_dv_matcher *matcher,
6925 union mlx5_flow_tbl_key *key,
6926 struct mlx5_flow *dev_flow,
6927 struct rte_flow_error *error)
6929 struct mlx5_priv *priv = dev->data->dev_private;
6930 struct mlx5_ibv_shared *sh = priv->sh;
6931 struct mlx5_flow_dv_matcher *cache_matcher;
6932 struct mlx5dv_flow_matcher_attr dv_attr = {
6933 .type = IBV_FLOW_ATTR_NORMAL,
6934 .match_mask = (void *)&matcher->mask,
6936 struct mlx5_flow_tbl_resource *tbl;
6937 struct mlx5_flow_tbl_data_entry *tbl_data;
6939 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
6940 key->domain, error);
6942 return -rte_errno; /* No need to refill the error info */
6943 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6944 /* Lookup from cache. */
6945 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
6946 if (matcher->crc == cache_matcher->crc &&
6947 matcher->priority == cache_matcher->priority &&
6948 !memcmp((const void *)matcher->mask.buf,
6949 (const void *)cache_matcher->mask.buf,
6950 cache_matcher->mask.size)) {
6952 "%s group %u priority %hd use %s "
6953 "matcher %p: refcnt %d++",
6954 key->domain ? "FDB" : "NIC", key->table_id,
6955 cache_matcher->priority,
6956 key->direction ? "tx" : "rx",
6957 (void *)cache_matcher,
6958 rte_atomic32_read(&cache_matcher->refcnt));
6959 rte_atomic32_inc(&cache_matcher->refcnt);
6960 dev_flow->dv.matcher = cache_matcher;
6961 /* old matcher should not make the table ref++. */
6962 flow_dv_tbl_resource_release(dev, tbl);
6966 /* Register new matcher. */
6967 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
6968 if (!cache_matcher) {
6969 flow_dv_tbl_resource_release(dev, tbl);
6970 return rte_flow_error_set(error, ENOMEM,
6971 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6972 "cannot allocate matcher memory");
6974 *cache_matcher = *matcher;
6975 dv_attr.match_criteria_enable =
6976 flow_dv_matcher_enable(cache_matcher->mask.buf);
6977 dv_attr.priority = matcher->priority;
6979 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
6980 cache_matcher->matcher_object =
6981 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
6982 if (!cache_matcher->matcher_object) {
6983 rte_free(cache_matcher);
6984 #ifdef HAVE_MLX5DV_DR
6985 flow_dv_tbl_resource_release(dev, tbl);
6987 return rte_flow_error_set(error, ENOMEM,
6988 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6989 NULL, "cannot create matcher");
6991 /* Save the table information */
6992 cache_matcher->tbl = tbl;
6993 rte_atomic32_init(&cache_matcher->refcnt);
6994 /* only matcher ref++, table ref++ already done above in get API. */
6995 rte_atomic32_inc(&cache_matcher->refcnt);
6996 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
6997 dev_flow->dv.matcher = cache_matcher;
6998 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
6999 key->domain ? "FDB" : "NIC", key->table_id,
7000 cache_matcher->priority,
7001 key->direction ? "tx" : "rx", (void *)cache_matcher,
7002 rte_atomic32_read(&cache_matcher->refcnt));
7007 * Find existing tag resource or create and register a new one.
7009 * @param dev[in, out]
7010 * Pointer to rte_eth_dev structure.
7011 * @param[in, out] tag_be24
7012 * Tag value in big endian then R-shift 8.
7013 * @parm[in, out] dev_flow
7014 * Pointer to the dev_flow.
7016 * pointer to error structure.
7019 * 0 on success otherwise -errno and errno is set.
7022 flow_dv_tag_resource_register
7023 (struct rte_eth_dev *dev,
7025 struct mlx5_flow *dev_flow,
7026 struct rte_flow_error *error)
7028 struct mlx5_priv *priv = dev->data->dev_private;
7029 struct mlx5_ibv_shared *sh = priv->sh;
7030 struct mlx5_flow_dv_tag_resource *cache_resource;
7031 struct mlx5_hlist_entry *entry;
7033 /* Lookup a matching resource from cache. */
7034 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7036 cache_resource = container_of
7037 (entry, struct mlx5_flow_dv_tag_resource, entry);
7038 rte_atomic32_inc(&cache_resource->refcnt);
7039 dev_flow->dv.tag_resource = cache_resource;
7040 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7041 (void *)cache_resource,
7042 rte_atomic32_read(&cache_resource->refcnt));
7045 /* Register new resource. */
7046 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
7047 if (!cache_resource)
7048 return rte_flow_error_set(error, ENOMEM,
7049 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7050 "cannot allocate resource memory");
7051 cache_resource->entry.key = (uint64_t)tag_be24;
7052 cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7053 if (!cache_resource->action) {
7054 rte_free(cache_resource);
7055 return rte_flow_error_set(error, ENOMEM,
7056 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7057 NULL, "cannot create action");
7059 rte_atomic32_init(&cache_resource->refcnt);
7060 rte_atomic32_inc(&cache_resource->refcnt);
7061 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7062 mlx5_glue->destroy_flow_action(cache_resource->action);
7063 rte_free(cache_resource);
7064 return rte_flow_error_set(error, EEXIST,
7065 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7066 NULL, "cannot insert tag");
7068 dev_flow->dv.tag_resource = cache_resource;
7069 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7070 (void *)cache_resource,
7071 rte_atomic32_read(&cache_resource->refcnt));
7079 * Pointer to Ethernet device.
7081 * Pointer to mlx5_flow.
7084 * 1 while a reference on it exists, 0 when freed.
7087 flow_dv_tag_release(struct rte_eth_dev *dev,
7088 struct mlx5_flow_dv_tag_resource *tag)
7090 struct mlx5_priv *priv = dev->data->dev_private;
7091 struct mlx5_ibv_shared *sh = priv->sh;
7094 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7095 dev->data->port_id, (void *)tag,
7096 rte_atomic32_read(&tag->refcnt));
7097 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7098 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7099 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7100 DRV_LOG(DEBUG, "port %u tag %p: removed",
7101 dev->data->port_id, (void *)tag);
7109 * Translate port ID action to vport.
7112 * Pointer to rte_eth_dev structure.
7114 * Pointer to the port ID action.
7115 * @param[out] dst_port_id
7116 * The target port ID.
7118 * Pointer to the error structure.
7121 * 0 on success, a negative errno value otherwise and rte_errno is set.
7124 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7125 const struct rte_flow_action *action,
7126 uint32_t *dst_port_id,
7127 struct rte_flow_error *error)
7130 struct mlx5_priv *priv;
7131 const struct rte_flow_action_port_id *conf =
7132 (const struct rte_flow_action_port_id *)action->conf;
7134 port = conf->original ? dev->data->port_id : conf->id;
7135 priv = mlx5_port_to_eswitch_info(port, false);
7137 return rte_flow_error_set(error, -rte_errno,
7138 RTE_FLOW_ERROR_TYPE_ACTION,
7140 "No eswitch info was found for port");
7141 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7143 * This parameter is transferred to
7144 * mlx5dv_dr_action_create_dest_ib_port().
7146 *dst_port_id = priv->ibv_port;
7149 * Legacy mode, no LAG configurations is supported.
7150 * This parameter is transferred to
7151 * mlx5dv_dr_action_create_dest_vport().
7153 *dst_port_id = priv->vport_id;
7159 * Add Tx queue matcher
7162 * Pointer to the dev struct.
7163 * @param[in, out] matcher
7165 * @param[in, out] key
7166 * Flow matcher value.
7168 * Flow pattern to translate.
7170 * Item is inner pattern.
7173 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7174 void *matcher, void *key,
7175 const struct rte_flow_item *item)
7177 const struct mlx5_rte_flow_item_tx_queue *queue_m;
7178 const struct mlx5_rte_flow_item_tx_queue *queue_v;
7180 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7182 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7183 struct mlx5_txq_ctrl *txq;
7187 queue_m = (const void *)item->mask;
7190 queue_v = (const void *)item->spec;
7193 txq = mlx5_txq_get(dev, queue_v->queue);
7196 queue = txq->obj->sq->id;
7197 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7198 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7199 queue & queue_m->queue);
7200 mlx5_txq_release(dev, queue_v->queue);
7204 * Set the hash fields according to the @p flow information.
7206 * @param[in] dev_flow
7207 * Pointer to the mlx5_flow.
7210 flow_dv_hashfields_set(struct mlx5_flow *dev_flow)
7212 struct rte_flow *flow = dev_flow->flow;
7213 uint64_t items = dev_flow->layers;
7215 uint64_t rss_types = rte_eth_rss_hf_refine(flow->rss.types);
7217 dev_flow->hash_fields = 0;
7218 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7219 if (flow->rss.level >= 2) {
7220 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7224 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7225 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7226 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7227 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7228 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7229 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7230 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7232 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7234 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7235 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7236 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7237 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7238 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7239 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7240 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7242 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7245 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7246 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7247 if (rss_types & ETH_RSS_UDP) {
7248 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7249 dev_flow->hash_fields |=
7250 IBV_RX_HASH_SRC_PORT_UDP;
7251 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7252 dev_flow->hash_fields |=
7253 IBV_RX_HASH_DST_PORT_UDP;
7255 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7257 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7258 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7259 if (rss_types & ETH_RSS_TCP) {
7260 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7261 dev_flow->hash_fields |=
7262 IBV_RX_HASH_SRC_PORT_TCP;
7263 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7264 dev_flow->hash_fields |=
7265 IBV_RX_HASH_DST_PORT_TCP;
7267 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7273 * Fill the flow with DV spec, lock free
7274 * (mutex should be acquired by caller).
7277 * Pointer to rte_eth_dev structure.
7278 * @param[in, out] dev_flow
7279 * Pointer to the sub flow.
7281 * Pointer to the flow attributes.
7283 * Pointer to the list of items.
7284 * @param[in] actions
7285 * Pointer to the list of actions.
7287 * Pointer to the error structure.
7290 * 0 on success, a negative errno value otherwise and rte_errno is set.
7293 __flow_dv_translate(struct rte_eth_dev *dev,
7294 struct mlx5_flow *dev_flow,
7295 const struct rte_flow_attr *attr,
7296 const struct rte_flow_item items[],
7297 const struct rte_flow_action actions[],
7298 struct rte_flow_error *error)
7300 struct mlx5_priv *priv = dev->data->dev_private;
7301 struct mlx5_dev_config *dev_conf = &priv->config;
7302 struct rte_flow *flow = dev_flow->flow;
7303 uint64_t item_flags = 0;
7304 uint64_t last_item = 0;
7305 uint64_t action_flags = 0;
7306 uint64_t priority = attr->priority;
7307 struct mlx5_flow_dv_matcher matcher = {
7309 .size = sizeof(matcher.mask.buf),
7313 bool actions_end = false;
7315 struct mlx5_flow_dv_modify_hdr_resource res;
7316 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7317 sizeof(struct mlx5_modification_cmd) *
7318 (MLX5_MAX_MODIFY_NUM + 1)];
7320 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7321 union flow_dv_attr flow_attr = { .attr = 0 };
7323 union mlx5_flow_tbl_key tbl_key;
7324 uint32_t modify_action_position = UINT32_MAX;
7325 void *match_mask = matcher.mask.buf;
7326 void *match_value = dev_flow->dv.value.buf;
7327 uint8_t next_protocol = 0xff;
7328 struct rte_vlan_hdr vlan = { 0 };
7332 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7333 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7334 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7335 !!priv->fdb_def_rule, &table, error);
7338 dev_flow->group = table;
7340 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7341 if (priority == MLX5_FLOW_PRIO_RSVD)
7342 priority = dev_conf->flow_prio - 1;
7343 /* number of actions must be set to 0 in case of dirty stack. */
7344 mhdr_res->actions_num = 0;
7345 for (; !actions_end ; actions++) {
7346 const struct rte_flow_action_queue *queue;
7347 const struct rte_flow_action_rss *rss;
7348 const struct rte_flow_action *action = actions;
7349 const struct rte_flow_action_count *count = action->conf;
7350 const uint8_t *rss_key;
7351 const struct rte_flow_action_jump *jump_data;
7352 const struct rte_flow_action_meter *mtr;
7353 struct mlx5_flow_tbl_resource *tbl;
7354 uint32_t port_id = 0;
7355 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7356 int action_type = actions->type;
7357 const struct rte_flow_action *found_action = NULL;
7359 switch (action_type) {
7360 case RTE_FLOW_ACTION_TYPE_VOID:
7362 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7363 if (flow_dv_translate_action_port_id(dev, action,
7366 port_id_resource.port_id = port_id;
7367 if (flow_dv_port_id_action_resource_register
7368 (dev, &port_id_resource, dev_flow, error))
7370 dev_flow->dv.actions[actions_n++] =
7371 dev_flow->dv.port_id_action->action;
7372 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7374 case RTE_FLOW_ACTION_TYPE_FLAG:
7375 action_flags |= MLX5_FLOW_ACTION_FLAG;
7376 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7377 struct rte_flow_action_mark mark = {
7378 .id = MLX5_FLOW_MARK_DEFAULT,
7381 if (flow_dv_convert_action_mark(dev, &mark,
7385 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7388 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7389 if (!dev_flow->dv.tag_resource)
7390 if (flow_dv_tag_resource_register
7391 (dev, tag_be, dev_flow, error))
7393 dev_flow->dv.actions[actions_n++] =
7394 dev_flow->dv.tag_resource->action;
7396 case RTE_FLOW_ACTION_TYPE_MARK:
7397 action_flags |= MLX5_FLOW_ACTION_MARK;
7398 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7399 const struct rte_flow_action_mark *mark =
7400 (const struct rte_flow_action_mark *)
7403 if (flow_dv_convert_action_mark(dev, mark,
7407 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7411 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7412 /* Legacy (non-extensive) MARK action. */
7413 tag_be = mlx5_flow_mark_set
7414 (((const struct rte_flow_action_mark *)
7415 (actions->conf))->id);
7416 if (!dev_flow->dv.tag_resource)
7417 if (flow_dv_tag_resource_register
7418 (dev, tag_be, dev_flow, error))
7420 dev_flow->dv.actions[actions_n++] =
7421 dev_flow->dv.tag_resource->action;
7423 case RTE_FLOW_ACTION_TYPE_SET_META:
7424 if (flow_dv_convert_action_set_meta
7425 (dev, mhdr_res, attr,
7426 (const struct rte_flow_action_set_meta *)
7427 actions->conf, error))
7429 action_flags |= MLX5_FLOW_ACTION_SET_META;
7431 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7432 if (flow_dv_convert_action_set_tag
7434 (const struct rte_flow_action_set_tag *)
7435 actions->conf, error))
7437 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7439 case RTE_FLOW_ACTION_TYPE_DROP:
7440 action_flags |= MLX5_FLOW_ACTION_DROP;
7442 case RTE_FLOW_ACTION_TYPE_QUEUE:
7443 MLX5_ASSERT(flow->rss.queue);
7444 queue = actions->conf;
7445 flow->rss.queue_num = 1;
7446 (*flow->rss.queue)[0] = queue->index;
7447 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7449 case RTE_FLOW_ACTION_TYPE_RSS:
7450 MLX5_ASSERT(flow->rss.queue);
7451 rss = actions->conf;
7452 if (flow->rss.queue)
7453 memcpy((*flow->rss.queue), rss->queue,
7454 rss->queue_num * sizeof(uint16_t));
7455 flow->rss.queue_num = rss->queue_num;
7456 /* NULL RSS key indicates default RSS key. */
7457 rss_key = !rss->key ? rss_hash_default_key : rss->key;
7458 memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7460 * rss->level and rss.types should be set in advance
7461 * when expanding items for RSS.
7463 action_flags |= MLX5_FLOW_ACTION_RSS;
7465 case RTE_FLOW_ACTION_TYPE_COUNT:
7466 if (!dev_conf->devx) {
7467 rte_errno = ENOTSUP;
7470 flow->counter = flow_dv_counter_alloc(dev,
7474 if (flow->counter == NULL)
7476 dev_flow->dv.actions[actions_n++] =
7477 flow->counter->action;
7478 action_flags |= MLX5_FLOW_ACTION_COUNT;
7481 if (rte_errno == ENOTSUP)
7482 return rte_flow_error_set
7484 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7486 "count action not supported");
7488 return rte_flow_error_set
7490 RTE_FLOW_ERROR_TYPE_ACTION,
7492 "cannot create counter"
7495 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7496 dev_flow->dv.actions[actions_n++] =
7497 priv->sh->pop_vlan_action;
7498 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7500 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7501 flow_dev_get_vlan_info_from_items(items, &vlan);
7502 vlan.eth_proto = rte_be_to_cpu_16
7503 ((((const struct rte_flow_action_of_push_vlan *)
7504 actions->conf)->ethertype));
7505 found_action = mlx5_flow_find_action
7507 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7509 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7510 found_action = mlx5_flow_find_action
7512 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7514 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7515 if (flow_dv_create_action_push_vlan
7516 (dev, attr, &vlan, dev_flow, error))
7518 dev_flow->dv.actions[actions_n++] =
7519 dev_flow->dv.push_vlan_res->action;
7520 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7522 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7523 /* of_vlan_push action handled this action */
7524 MLX5_ASSERT(action_flags &
7525 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7527 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7528 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7530 flow_dev_get_vlan_info_from_items(items, &vlan);
7531 mlx5_update_vlan_vid_pcp(actions, &vlan);
7532 /* If no VLAN push - this is a modify header action */
7533 if (flow_dv_convert_action_modify_vlan_vid
7534 (mhdr_res, actions, error))
7536 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7538 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7539 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7540 if (flow_dv_create_action_l2_encap(dev, actions,
7545 dev_flow->dv.actions[actions_n++] =
7546 dev_flow->dv.encap_decap->verbs_action;
7547 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7549 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7550 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7551 if (flow_dv_create_action_l2_decap(dev, dev_flow,
7555 dev_flow->dv.actions[actions_n++] =
7556 dev_flow->dv.encap_decap->verbs_action;
7557 action_flags |= MLX5_FLOW_ACTION_DECAP;
7559 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7560 /* Handle encap with preceding decap. */
7561 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
7562 if (flow_dv_create_action_raw_encap
7563 (dev, actions, dev_flow, attr, error))
7565 dev_flow->dv.actions[actions_n++] =
7566 dev_flow->dv.encap_decap->verbs_action;
7568 /* Handle encap without preceding decap. */
7569 if (flow_dv_create_action_l2_encap
7570 (dev, actions, dev_flow, attr->transfer,
7573 dev_flow->dv.actions[actions_n++] =
7574 dev_flow->dv.encap_decap->verbs_action;
7576 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7578 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7579 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
7581 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7582 if (flow_dv_create_action_l2_decap
7583 (dev, dev_flow, attr->transfer, error))
7585 dev_flow->dv.actions[actions_n++] =
7586 dev_flow->dv.encap_decap->verbs_action;
7588 /* If decap is followed by encap, handle it at encap. */
7589 action_flags |= MLX5_FLOW_ACTION_DECAP;
7591 case RTE_FLOW_ACTION_TYPE_JUMP:
7592 jump_data = action->conf;
7593 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7595 !!priv->fdb_def_rule,
7599 tbl = flow_dv_tbl_resource_get(dev, table,
7601 attr->transfer, error);
7603 return rte_flow_error_set
7605 RTE_FLOW_ERROR_TYPE_ACTION,
7607 "cannot create jump action.");
7608 if (flow_dv_jump_tbl_resource_register
7609 (dev, tbl, dev_flow, error)) {
7610 flow_dv_tbl_resource_release(dev, tbl);
7611 return rte_flow_error_set
7613 RTE_FLOW_ERROR_TYPE_ACTION,
7615 "cannot create jump action.");
7617 dev_flow->dv.actions[actions_n++] =
7618 dev_flow->dv.jump->action;
7619 action_flags |= MLX5_FLOW_ACTION_JUMP;
7621 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7622 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7623 if (flow_dv_convert_action_modify_mac
7624 (mhdr_res, actions, error))
7626 action_flags |= actions->type ==
7627 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7628 MLX5_FLOW_ACTION_SET_MAC_SRC :
7629 MLX5_FLOW_ACTION_SET_MAC_DST;
7631 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7632 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7633 if (flow_dv_convert_action_modify_ipv4
7634 (mhdr_res, actions, error))
7636 action_flags |= actions->type ==
7637 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7638 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7639 MLX5_FLOW_ACTION_SET_IPV4_DST;
7641 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7642 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7643 if (flow_dv_convert_action_modify_ipv6
7644 (mhdr_res, actions, error))
7646 action_flags |= actions->type ==
7647 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7648 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7649 MLX5_FLOW_ACTION_SET_IPV6_DST;
7651 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7652 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7653 if (flow_dv_convert_action_modify_tp
7654 (mhdr_res, actions, items,
7655 &flow_attr, dev_flow, !!(action_flags &
7656 MLX5_FLOW_ACTION_DECAP), error))
7658 action_flags |= actions->type ==
7659 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7660 MLX5_FLOW_ACTION_SET_TP_SRC :
7661 MLX5_FLOW_ACTION_SET_TP_DST;
7663 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7664 if (flow_dv_convert_action_modify_dec_ttl
7665 (mhdr_res, items, &flow_attr, dev_flow,
7667 MLX5_FLOW_ACTION_DECAP), error))
7669 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
7671 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7672 if (flow_dv_convert_action_modify_ttl
7673 (mhdr_res, actions, items, &flow_attr,
7674 dev_flow, !!(action_flags &
7675 MLX5_FLOW_ACTION_DECAP), error))
7677 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
7679 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7680 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7681 if (flow_dv_convert_action_modify_tcp_seq
7682 (mhdr_res, actions, error))
7684 action_flags |= actions->type ==
7685 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7686 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7687 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7690 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7691 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7692 if (flow_dv_convert_action_modify_tcp_ack
7693 (mhdr_res, actions, error))
7695 action_flags |= actions->type ==
7696 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7697 MLX5_FLOW_ACTION_INC_TCP_ACK :
7698 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7700 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7701 if (flow_dv_convert_action_set_reg
7702 (mhdr_res, actions, error))
7704 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7706 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7707 if (flow_dv_convert_action_copy_mreg
7708 (dev, mhdr_res, actions, error))
7710 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7712 case RTE_FLOW_ACTION_TYPE_METER:
7713 mtr = actions->conf;
7715 flow->meter = mlx5_flow_meter_attach(priv,
7719 return rte_flow_error_set(error,
7721 RTE_FLOW_ERROR_TYPE_ACTION,
7724 "or invalid parameters");
7726 /* Set the meter action. */
7727 dev_flow->dv.actions[actions_n++] =
7728 flow->meter->mfts->meter_action;
7729 action_flags |= MLX5_FLOW_ACTION_METER;
7731 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7732 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
7735 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7737 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7738 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
7741 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7743 case RTE_FLOW_ACTION_TYPE_END:
7745 if (mhdr_res->actions_num) {
7746 /* create modify action if needed. */
7747 if (flow_dv_modify_hdr_resource_register
7748 (dev, mhdr_res, dev_flow, error))
7750 dev_flow->dv.actions[modify_action_position] =
7751 dev_flow->dv.modify_hdr->verbs_action;
7757 if (mhdr_res->actions_num &&
7758 modify_action_position == UINT32_MAX)
7759 modify_action_position = actions_n++;
7761 dev_flow->dv.actions_n = actions_n;
7762 dev_flow->actions = action_flags;
7763 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7764 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7765 int item_type = items->type;
7767 switch (item_type) {
7768 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7769 flow_dv_translate_item_port_id(dev, match_mask,
7770 match_value, items);
7771 last_item = MLX5_FLOW_ITEM_PORT_ID;
7773 case RTE_FLOW_ITEM_TYPE_ETH:
7774 flow_dv_translate_item_eth(match_mask, match_value,
7776 matcher.priority = MLX5_PRIORITY_MAP_L2;
7777 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7778 MLX5_FLOW_LAYER_OUTER_L2;
7780 case RTE_FLOW_ITEM_TYPE_VLAN:
7781 flow_dv_translate_item_vlan(dev_flow,
7782 match_mask, match_value,
7784 matcher.priority = MLX5_PRIORITY_MAP_L2;
7785 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7786 MLX5_FLOW_LAYER_INNER_VLAN) :
7787 (MLX5_FLOW_LAYER_OUTER_L2 |
7788 MLX5_FLOW_LAYER_OUTER_VLAN);
7790 case RTE_FLOW_ITEM_TYPE_IPV4:
7791 mlx5_flow_tunnel_ip_check(items, next_protocol,
7792 &item_flags, &tunnel);
7793 flow_dv_translate_item_ipv4(match_mask, match_value,
7794 items, item_flags, tunnel,
7796 matcher.priority = MLX5_PRIORITY_MAP_L3;
7797 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7798 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7799 if (items->mask != NULL &&
7800 ((const struct rte_flow_item_ipv4 *)
7801 items->mask)->hdr.next_proto_id) {
7803 ((const struct rte_flow_item_ipv4 *)
7804 (items->spec))->hdr.next_proto_id;
7806 ((const struct rte_flow_item_ipv4 *)
7807 (items->mask))->hdr.next_proto_id;
7809 /* Reset for inner layer. */
7810 next_protocol = 0xff;
7813 case RTE_FLOW_ITEM_TYPE_IPV6:
7814 mlx5_flow_tunnel_ip_check(items, next_protocol,
7815 &item_flags, &tunnel);
7816 flow_dv_translate_item_ipv6(match_mask, match_value,
7817 items, item_flags, tunnel,
7819 matcher.priority = MLX5_PRIORITY_MAP_L3;
7820 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7821 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7822 if (items->mask != NULL &&
7823 ((const struct rte_flow_item_ipv6 *)
7824 items->mask)->hdr.proto) {
7826 ((const struct rte_flow_item_ipv6 *)
7827 items->spec)->hdr.proto;
7829 ((const struct rte_flow_item_ipv6 *)
7830 items->mask)->hdr.proto;
7832 /* Reset for inner layer. */
7833 next_protocol = 0xff;
7836 case RTE_FLOW_ITEM_TYPE_TCP:
7837 flow_dv_translate_item_tcp(match_mask, match_value,
7839 matcher.priority = MLX5_PRIORITY_MAP_L4;
7840 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7841 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7843 case RTE_FLOW_ITEM_TYPE_UDP:
7844 flow_dv_translate_item_udp(match_mask, match_value,
7846 matcher.priority = MLX5_PRIORITY_MAP_L4;
7847 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7848 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7850 case RTE_FLOW_ITEM_TYPE_GRE:
7851 flow_dv_translate_item_gre(match_mask, match_value,
7853 matcher.priority = flow->rss.level >= 2 ?
7854 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7855 last_item = MLX5_FLOW_LAYER_GRE;
7857 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7858 flow_dv_translate_item_gre_key(match_mask,
7859 match_value, items);
7860 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7862 case RTE_FLOW_ITEM_TYPE_NVGRE:
7863 flow_dv_translate_item_nvgre(match_mask, match_value,
7865 matcher.priority = flow->rss.level >= 2 ?
7866 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7867 last_item = MLX5_FLOW_LAYER_GRE;
7869 case RTE_FLOW_ITEM_TYPE_VXLAN:
7870 flow_dv_translate_item_vxlan(match_mask, match_value,
7872 matcher.priority = flow->rss.level >= 2 ?
7873 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7874 last_item = MLX5_FLOW_LAYER_VXLAN;
7876 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7877 flow_dv_translate_item_vxlan_gpe(match_mask,
7880 matcher.priority = flow->rss.level >= 2 ?
7881 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7882 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7884 case RTE_FLOW_ITEM_TYPE_GENEVE:
7885 flow_dv_translate_item_geneve(match_mask, match_value,
7887 matcher.priority = flow->rss.level >= 2 ?
7888 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7889 last_item = MLX5_FLOW_LAYER_GENEVE;
7891 case RTE_FLOW_ITEM_TYPE_MPLS:
7892 flow_dv_translate_item_mpls(match_mask, match_value,
7893 items, last_item, tunnel);
7894 matcher.priority = flow->rss.level >= 2 ?
7895 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7896 last_item = MLX5_FLOW_LAYER_MPLS;
7898 case RTE_FLOW_ITEM_TYPE_MARK:
7899 flow_dv_translate_item_mark(dev, match_mask,
7900 match_value, items);
7901 last_item = MLX5_FLOW_ITEM_MARK;
7903 case RTE_FLOW_ITEM_TYPE_META:
7904 flow_dv_translate_item_meta(dev, match_mask,
7905 match_value, attr, items);
7906 last_item = MLX5_FLOW_ITEM_METADATA;
7908 case RTE_FLOW_ITEM_TYPE_ICMP:
7909 flow_dv_translate_item_icmp(match_mask, match_value,
7911 last_item = MLX5_FLOW_LAYER_ICMP;
7913 case RTE_FLOW_ITEM_TYPE_ICMP6:
7914 flow_dv_translate_item_icmp6(match_mask, match_value,
7916 last_item = MLX5_FLOW_LAYER_ICMP6;
7918 case RTE_FLOW_ITEM_TYPE_TAG:
7919 flow_dv_translate_item_tag(dev, match_mask,
7920 match_value, items);
7921 last_item = MLX5_FLOW_ITEM_TAG;
7923 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7924 flow_dv_translate_mlx5_item_tag(dev, match_mask,
7925 match_value, items);
7926 last_item = MLX5_FLOW_ITEM_TAG;
7928 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7929 flow_dv_translate_item_tx_queue(dev, match_mask,
7932 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
7934 case RTE_FLOW_ITEM_TYPE_GTP:
7935 flow_dv_translate_item_gtp(match_mask, match_value,
7937 matcher.priority = flow->rss.level >= 2 ?
7938 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7939 last_item = MLX5_FLOW_LAYER_GTP;
7944 item_flags |= last_item;
7947 * When E-Switch mode is enabled, we have two cases where we need to
7948 * set the source port manually.
7949 * The first one, is in case of Nic steering rule, and the second is
7950 * E-Switch rule where no port_id item was found. In both cases
7951 * the source port is set according the current port in use.
7953 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
7954 (priv->representor || priv->master)) {
7955 if (flow_dv_translate_item_port_id(dev, match_mask,
7959 #ifdef RTE_LIBRTE_MLX5_DEBUG
7960 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
7961 dev_flow->dv.value.buf));
7964 * Layers may be already initialized from prefix flow if this dev_flow
7965 * is the suffix flow.
7967 dev_flow->layers |= item_flags;
7968 if (action_flags & MLX5_FLOW_ACTION_RSS)
7969 flow_dv_hashfields_set(dev_flow);
7970 /* Register matcher. */
7971 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
7973 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
7975 /* reserved field no needs to be set to 0 here. */
7976 tbl_key.domain = attr->transfer;
7977 tbl_key.direction = attr->egress;
7978 tbl_key.table_id = dev_flow->group;
7979 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
7985 * Apply the flow to the NIC, lock free,
7986 * (mutex should be acquired by caller).
7989 * Pointer to the Ethernet device structure.
7990 * @param[in, out] flow
7991 * Pointer to flow structure.
7993 * Pointer to error structure.
7996 * 0 on success, a negative errno value otherwise and rte_errno is set.
7999 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8000 struct rte_flow_error *error)
8002 struct mlx5_flow_dv *dv;
8003 struct mlx5_flow *dev_flow;
8004 struct mlx5_priv *priv = dev->data->dev_private;
8008 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
8011 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP) {
8012 if (dev_flow->transfer) {
8013 dv->actions[n++] = priv->sh->esw_drop_action;
8015 dv->hrxq = mlx5_hrxq_drop_new(dev);
8019 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8021 "cannot get drop hash queue");
8024 dv->actions[n++] = dv->hrxq->action;
8026 } else if (dev_flow->actions &
8027 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
8028 struct mlx5_hrxq *hrxq;
8030 MLX5_ASSERT(flow->rss.queue);
8031 hrxq = mlx5_hrxq_get(dev, flow->rss.key,
8032 MLX5_RSS_HASH_KEY_LEN,
8033 dev_flow->hash_fields,
8035 flow->rss.queue_num);
8037 hrxq = mlx5_hrxq_new
8038 (dev, flow->rss.key,
8039 MLX5_RSS_HASH_KEY_LEN,
8040 dev_flow->hash_fields,
8042 flow->rss.queue_num,
8043 !!(dev_flow->layers &
8044 MLX5_FLOW_LAYER_TUNNEL));
8049 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8050 "cannot get hash queue");
8054 dv->actions[n++] = dv->hrxq->action;
8057 mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
8058 (void *)&dv->value, n,
8061 rte_flow_error_set(error, errno,
8062 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8064 "hardware refuses to create flow");
8067 if (priv->vmwa_context &&
8068 dev_flow->dv.vf_vlan.tag &&
8069 !dev_flow->dv.vf_vlan.created) {
8071 * The rule contains the VLAN pattern.
8072 * For VF we are going to create VLAN
8073 * interface to make hypervisor set correct
8074 * e-Switch vport context.
8076 mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
8081 err = rte_errno; /* Save rte_errno before cleanup. */
8082 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
8083 struct mlx5_flow_dv *dv = &dev_flow->dv;
8085 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
8086 mlx5_hrxq_drop_release(dev);
8088 mlx5_hrxq_release(dev, dv->hrxq);
8091 if (dev_flow->dv.vf_vlan.tag &&
8092 dev_flow->dv.vf_vlan.created)
8093 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
8095 rte_errno = err; /* Restore rte_errno. */
8100 * Release the flow matcher.
8103 * Pointer to Ethernet device.
8105 * Pointer to mlx5_flow.
8108 * 1 while a reference on it exists, 0 when freed.
8111 flow_dv_matcher_release(struct rte_eth_dev *dev,
8112 struct mlx5_flow *flow)
8114 struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
8116 MLX5_ASSERT(matcher->matcher_object);
8117 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8118 dev->data->port_id, (void *)matcher,
8119 rte_atomic32_read(&matcher->refcnt));
8120 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8121 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8122 (matcher->matcher_object));
8123 LIST_REMOVE(matcher, next);
8124 /* table ref-- in release interface. */
8125 flow_dv_tbl_resource_release(dev, matcher->tbl);
8127 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8128 dev->data->port_id, (void *)matcher);
8135 * Release an encap/decap resource.
8138 * Pointer to mlx5_flow.
8141 * 1 while a reference on it exists, 0 when freed.
8144 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
8146 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
8147 flow->dv.encap_decap;
8149 MLX5_ASSERT(cache_resource->verbs_action);
8150 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8151 (void *)cache_resource,
8152 rte_atomic32_read(&cache_resource->refcnt));
8153 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8154 claim_zero(mlx5_glue->destroy_flow_action
8155 (cache_resource->verbs_action));
8156 LIST_REMOVE(cache_resource, next);
8157 rte_free(cache_resource);
8158 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8159 (void *)cache_resource);
8166 * Release an jump to table action resource.
8169 * Pointer to Ethernet device.
8171 * Pointer to mlx5_flow.
8174 * 1 while a reference on it exists, 0 when freed.
8177 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8178 struct mlx5_flow *flow)
8180 struct mlx5_flow_dv_jump_tbl_resource *cache_resource = flow->dv.jump;
8181 struct mlx5_flow_tbl_data_entry *tbl_data =
8182 container_of(cache_resource,
8183 struct mlx5_flow_tbl_data_entry, jump);
8185 MLX5_ASSERT(cache_resource->action);
8186 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8187 (void *)cache_resource,
8188 rte_atomic32_read(&cache_resource->refcnt));
8189 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8190 claim_zero(mlx5_glue->destroy_flow_action
8191 (cache_resource->action));
8192 /* jump action memory free is inside the table release. */
8193 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8194 DRV_LOG(DEBUG, "jump table resource %p: removed",
8195 (void *)cache_resource);
8202 * Release a modify-header resource.
8205 * Pointer to mlx5_flow.
8208 * 1 while a reference on it exists, 0 when freed.
8211 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
8213 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8214 flow->dv.modify_hdr;
8216 MLX5_ASSERT(cache_resource->verbs_action);
8217 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8218 (void *)cache_resource,
8219 rte_atomic32_read(&cache_resource->refcnt));
8220 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8221 claim_zero(mlx5_glue->destroy_flow_action
8222 (cache_resource->verbs_action));
8223 LIST_REMOVE(cache_resource, next);
8224 rte_free(cache_resource);
8225 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8226 (void *)cache_resource);
8233 * Release port ID action resource.
8236 * Pointer to mlx5_flow.
8239 * 1 while a reference on it exists, 0 when freed.
8242 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
8244 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
8245 flow->dv.port_id_action;
8247 MLX5_ASSERT(cache_resource->action);
8248 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8249 (void *)cache_resource,
8250 rte_atomic32_read(&cache_resource->refcnt));
8251 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8252 claim_zero(mlx5_glue->destroy_flow_action
8253 (cache_resource->action));
8254 LIST_REMOVE(cache_resource, next);
8255 rte_free(cache_resource);
8256 DRV_LOG(DEBUG, "port id action resource %p: removed",
8257 (void *)cache_resource);
8264 * Release push vlan action resource.
8267 * Pointer to mlx5_flow.
8270 * 1 while a reference on it exists, 0 when freed.
8273 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
8275 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
8276 flow->dv.push_vlan_res;
8278 MLX5_ASSERT(cache_resource->action);
8279 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8280 (void *)cache_resource,
8281 rte_atomic32_read(&cache_resource->refcnt));
8282 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8283 claim_zero(mlx5_glue->destroy_flow_action
8284 (cache_resource->action));
8285 LIST_REMOVE(cache_resource, next);
8286 rte_free(cache_resource);
8287 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8288 (void *)cache_resource);
8295 * Remove the flow from the NIC but keeps it in memory.
8296 * Lock free, (mutex should be acquired by caller).
8299 * Pointer to Ethernet device.
8300 * @param[in, out] flow
8301 * Pointer to flow structure.
8304 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8306 struct mlx5_flow_dv *dv;
8307 struct mlx5_flow *dev_flow;
8311 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
8314 claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
8318 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
8319 mlx5_hrxq_drop_release(dev);
8321 mlx5_hrxq_release(dev, dv->hrxq);
8324 if (dev_flow->dv.vf_vlan.tag &&
8325 dev_flow->dv.vf_vlan.created)
8326 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
8331 * Remove the flow from the NIC and the memory.
8332 * Lock free, (mutex should be acquired by caller).
8335 * Pointer to the Ethernet device structure.
8336 * @param[in, out] flow
8337 * Pointer to flow structure.
8340 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8342 struct mlx5_flow *dev_flow;
8346 __flow_dv_remove(dev, flow);
8347 if (flow->counter) {
8348 flow_dv_counter_release(dev, flow->counter);
8349 flow->counter = NULL;
8352 mlx5_flow_meter_detach(flow->meter);
8355 while (!LIST_EMPTY(&flow->dev_flows)) {
8356 dev_flow = LIST_FIRST(&flow->dev_flows);
8357 LIST_REMOVE(dev_flow, next);
8358 if (dev_flow->dv.matcher)
8359 flow_dv_matcher_release(dev, dev_flow);
8360 if (dev_flow->dv.encap_decap)
8361 flow_dv_encap_decap_resource_release(dev_flow);
8362 if (dev_flow->dv.modify_hdr)
8363 flow_dv_modify_hdr_resource_release(dev_flow);
8364 if (dev_flow->dv.jump)
8365 flow_dv_jump_tbl_resource_release(dev, dev_flow);
8366 if (dev_flow->dv.port_id_action)
8367 flow_dv_port_id_action_resource_release(dev_flow);
8368 if (dev_flow->dv.push_vlan_res)
8369 flow_dv_push_vlan_action_resource_release(dev_flow);
8370 if (dev_flow->dv.tag_resource)
8371 flow_dv_tag_release(dev, dev_flow->dv.tag_resource);
8377 * Query a dv flow rule for its statistics via devx.
8380 * Pointer to Ethernet device.
8382 * Pointer to the sub flow.
8384 * data retrieved by the query.
8386 * Perform verbose error reporting if not NULL.
8389 * 0 on success, a negative errno value otherwise and rte_errno is set.
8392 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8393 void *data, struct rte_flow_error *error)
8395 struct mlx5_priv *priv = dev->data->dev_private;
8396 struct rte_flow_query_count *qc = data;
8398 if (!priv->config.devx)
8399 return rte_flow_error_set(error, ENOTSUP,
8400 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8402 "counters are not supported");
8403 if (flow->counter) {
8404 uint64_t pkts, bytes;
8405 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8409 return rte_flow_error_set(error, -err,
8410 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8411 NULL, "cannot read counters");
8414 qc->hits = pkts - flow->counter->hits;
8415 qc->bytes = bytes - flow->counter->bytes;
8417 flow->counter->hits = pkts;
8418 flow->counter->bytes = bytes;
8422 return rte_flow_error_set(error, EINVAL,
8423 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8425 "counters are not available");
8431 * @see rte_flow_query()
8435 flow_dv_query(struct rte_eth_dev *dev,
8436 struct rte_flow *flow __rte_unused,
8437 const struct rte_flow_action *actions __rte_unused,
8438 void *data __rte_unused,
8439 struct rte_flow_error *error __rte_unused)
8443 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8444 switch (actions->type) {
8445 case RTE_FLOW_ACTION_TYPE_VOID:
8447 case RTE_FLOW_ACTION_TYPE_COUNT:
8448 ret = flow_dv_query_count(dev, flow, data, error);
8451 return rte_flow_error_set(error, ENOTSUP,
8452 RTE_FLOW_ERROR_TYPE_ACTION,
8454 "action not supported");
8461 * Destroy the meter table set.
8462 * Lock free, (mutex should be acquired by caller).
8465 * Pointer to Ethernet device.
8467 * Pointer to the meter table set.
8473 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8474 struct mlx5_meter_domains_infos *tbl)
8476 struct mlx5_priv *priv = dev->data->dev_private;
8477 struct mlx5_meter_domains_infos *mtd =
8478 (struct mlx5_meter_domains_infos *)tbl;
8480 if (!mtd || !priv->config.dv_flow_en)
8482 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8483 claim_zero(mlx5_glue->dv_destroy_flow
8484 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8485 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8486 claim_zero(mlx5_glue->dv_destroy_flow
8487 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8488 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8489 claim_zero(mlx5_glue->dv_destroy_flow
8490 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8491 if (mtd->egress.color_matcher)
8492 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8493 (mtd->egress.color_matcher));
8494 if (mtd->egress.any_matcher)
8495 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8496 (mtd->egress.any_matcher));
8497 if (mtd->egress.tbl)
8498 claim_zero(flow_dv_tbl_resource_release(dev,
8500 if (mtd->ingress.color_matcher)
8501 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8502 (mtd->ingress.color_matcher));
8503 if (mtd->ingress.any_matcher)
8504 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8505 (mtd->ingress.any_matcher));
8506 if (mtd->ingress.tbl)
8507 claim_zero(flow_dv_tbl_resource_release(dev,
8509 if (mtd->transfer.color_matcher)
8510 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8511 (mtd->transfer.color_matcher));
8512 if (mtd->transfer.any_matcher)
8513 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8514 (mtd->transfer.any_matcher));
8515 if (mtd->transfer.tbl)
8516 claim_zero(flow_dv_tbl_resource_release(dev,
8517 mtd->transfer.tbl));
8519 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8524 /* Number of meter flow actions, count and jump or count and drop. */
8525 #define METER_ACTIONS 2
8528 * Create specify domain meter table and suffix table.
8531 * Pointer to Ethernet device.
8532 * @param[in,out] mtb
8533 * Pointer to DV meter table set.
8536 * @param[in] transfer
8538 * @param[in] color_reg_c_idx
8539 * Reg C index for color match.
8542 * 0 on success, -1 otherwise and rte_errno is set.
8545 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
8546 struct mlx5_meter_domains_infos *mtb,
8547 uint8_t egress, uint8_t transfer,
8548 uint32_t color_reg_c_idx)
8550 struct mlx5_priv *priv = dev->data->dev_private;
8551 struct mlx5_ibv_shared *sh = priv->sh;
8552 struct mlx5_flow_dv_match_params mask = {
8553 .size = sizeof(mask.buf),
8555 struct mlx5_flow_dv_match_params value = {
8556 .size = sizeof(value.buf),
8558 struct mlx5dv_flow_matcher_attr dv_attr = {
8559 .type = IBV_FLOW_ATTR_NORMAL,
8561 .match_criteria_enable = 0,
8562 .match_mask = (void *)&mask,
8564 void *actions[METER_ACTIONS];
8565 struct mlx5_flow_tbl_resource **sfx_tbl;
8566 struct mlx5_meter_domain_info *dtb;
8567 struct rte_flow_error error;
8571 sfx_tbl = &sh->fdb_mtr_sfx_tbl;
8572 dtb = &mtb->transfer;
8573 } else if (egress) {
8574 sfx_tbl = &sh->tx_mtr_sfx_tbl;
8577 sfx_tbl = &sh->rx_mtr_sfx_tbl;
8578 dtb = &mtb->ingress;
8580 /* If the suffix table in missing, create it. */
8582 *sfx_tbl = flow_dv_tbl_resource_get(dev,
8583 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
8584 egress, transfer, &error);
8586 DRV_LOG(ERR, "Failed to create meter suffix table.");
8590 /* Create the meter table with METER level. */
8591 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
8592 egress, transfer, &error);
8594 DRV_LOG(ERR, "Failed to create meter policer table.");
8597 /* Create matchers, Any and Color. */
8598 dv_attr.priority = 3;
8599 dv_attr.match_criteria_enable = 0;
8600 dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8603 if (!dtb->any_matcher) {
8604 DRV_LOG(ERR, "Failed to create meter"
8605 " policer default matcher.");
8608 dv_attr.priority = 0;
8609 dv_attr.match_criteria_enable =
8610 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8611 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
8612 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
8613 dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8616 if (!dtb->color_matcher) {
8617 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
8620 if (mtb->count_actns[RTE_MTR_DROPPED])
8621 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
8622 actions[i++] = mtb->drop_actn;
8623 /* Default rule: lowest priority, match any, actions: drop. */
8624 dtb->policer_rules[RTE_MTR_DROPPED] =
8625 mlx5_glue->dv_create_flow(dtb->any_matcher,
8626 (void *)&value, i, actions);
8627 if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
8628 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
8637 * Create the needed meter and suffix tables.
8638 * Lock free, (mutex should be acquired by caller).
8641 * Pointer to Ethernet device.
8643 * Pointer to the flow meter.
8646 * Pointer to table set on success, NULL otherwise and rte_errno is set.
8648 static struct mlx5_meter_domains_infos *
8649 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
8650 const struct mlx5_flow_meter *fm)
8652 struct mlx5_priv *priv = dev->data->dev_private;
8653 struct mlx5_meter_domains_infos *mtb;
8657 if (!priv->mtr_en) {
8658 rte_errno = ENOTSUP;
8661 mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
8663 DRV_LOG(ERR, "Failed to allocate memory for meter.");
8666 /* Create meter count actions */
8667 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
8668 if (!fm->policer_stats.cnt[i])
8670 mtb->count_actns[i] = fm->policer_stats.cnt[i]->action;
8672 /* Create drop action. */
8673 mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
8674 if (!mtb->drop_actn) {
8675 DRV_LOG(ERR, "Failed to create drop action.");
8678 /* Egress meter table. */
8679 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
8681 DRV_LOG(ERR, "Failed to prepare egress meter table.");
8684 /* Ingress meter table. */
8685 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
8687 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
8690 /* FDB meter table. */
8691 if (priv->config.dv_esw_en) {
8692 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
8693 priv->mtr_color_reg);
8695 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
8701 flow_dv_destroy_mtr_tbl(dev, mtb);
8706 * Destroy domain policer rule.
8709 * Pointer to domain table.
8712 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8716 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8717 if (dt->policer_rules[i]) {
8718 claim_zero(mlx5_glue->dv_destroy_flow
8719 (dt->policer_rules[i]));
8720 dt->policer_rules[i] = NULL;
8723 if (dt->jump_actn) {
8724 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8725 dt->jump_actn = NULL;
8730 * Destroy policer rules.
8733 * Pointer to Ethernet device.
8735 * Pointer to flow meter structure.
8737 * Pointer to flow attributes.
8743 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8744 const struct mlx5_flow_meter *fm,
8745 const struct rte_flow_attr *attr)
8747 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
8752 flow_dv_destroy_domain_policer_rule(&mtb->egress);
8754 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
8756 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
8761 * Create specify domain meter policer rule.
8764 * Pointer to flow meter structure.
8766 * Pointer to DV meter table set.
8768 * Pointer to suffix table.
8769 * @param[in] mtr_reg_c
8770 * Color match REG_C.
8773 * 0 on success, -1 otherwise.
8776 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
8777 struct mlx5_meter_domain_info *dtb,
8778 struct mlx5_flow_tbl_resource *sfx_tb,
8781 struct mlx5_flow_dv_match_params matcher = {
8782 .size = sizeof(matcher.buf),
8784 struct mlx5_flow_dv_match_params value = {
8785 .size = sizeof(value.buf),
8787 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8788 void *actions[METER_ACTIONS];
8791 /* Create jump action. */
8794 if (!dtb->jump_actn)
8796 mlx5_glue->dr_create_flow_action_dest_flow_tbl
8798 if (!dtb->jump_actn) {
8799 DRV_LOG(ERR, "Failed to create policer jump action.");
8802 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8805 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
8806 rte_col_2_mlx5_col(i), UINT8_MAX);
8807 if (mtb->count_actns[i])
8808 actions[j++] = mtb->count_actns[i];
8809 if (fm->params.action[i] == MTR_POLICER_ACTION_DROP)
8810 actions[j++] = mtb->drop_actn;
8812 actions[j++] = dtb->jump_actn;
8813 dtb->policer_rules[i] =
8814 mlx5_glue->dv_create_flow(dtb->color_matcher,
8817 if (!dtb->policer_rules[i]) {
8818 DRV_LOG(ERR, "Failed to create policer rule.");
8829 * Create policer rules.
8832 * Pointer to Ethernet device.
8834 * Pointer to flow meter structure.
8836 * Pointer to flow attributes.
8839 * 0 on success, -1 otherwise.
8842 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
8843 struct mlx5_flow_meter *fm,
8844 const struct rte_flow_attr *attr)
8846 struct mlx5_priv *priv = dev->data->dev_private;
8847 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8851 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
8852 priv->sh->tx_mtr_sfx_tbl,
8853 priv->mtr_color_reg);
8855 DRV_LOG(ERR, "Failed to create egress policer.");
8859 if (attr->ingress) {
8860 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
8861 priv->sh->rx_mtr_sfx_tbl,
8862 priv->mtr_color_reg);
8864 DRV_LOG(ERR, "Failed to create ingress policer.");
8868 if (attr->transfer) {
8869 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
8870 priv->sh->fdb_mtr_sfx_tbl,
8871 priv->mtr_color_reg);
8873 DRV_LOG(ERR, "Failed to create transfer policer.");
8879 flow_dv_destroy_policer_rules(dev, fm, attr);
8884 * Query a devx counter.
8887 * Pointer to the Ethernet device structure.
8889 * Pointer to the flow counter.
8891 * Set to clear the counter statistics.
8893 * The statistics value of packets.
8895 * The statistics value of bytes.
8898 * 0 on success, otherwise return -1.
8901 flow_dv_counter_query(struct rte_eth_dev *dev,
8902 struct mlx5_flow_counter *cnt, bool clear,
8903 uint64_t *pkts, uint64_t *bytes)
8905 struct mlx5_priv *priv = dev->data->dev_private;
8906 uint64_t inn_pkts, inn_bytes;
8909 if (!priv->config.devx)
8911 ret = _flow_dv_query_count(dev, cnt, &inn_pkts, &inn_bytes);
8914 *pkts = inn_pkts - cnt->hits;
8915 *bytes = inn_bytes - cnt->bytes;
8917 cnt->hits = inn_pkts;
8918 cnt->bytes = inn_bytes;
8924 * Mutex-protected thunk to lock-free __flow_dv_translate().
8927 flow_dv_translate(struct rte_eth_dev *dev,
8928 struct mlx5_flow *dev_flow,
8929 const struct rte_flow_attr *attr,
8930 const struct rte_flow_item items[],
8931 const struct rte_flow_action actions[],
8932 struct rte_flow_error *error)
8936 flow_dv_shared_lock(dev);
8937 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
8938 flow_dv_shared_unlock(dev);
8943 * Mutex-protected thunk to lock-free __flow_dv_apply().
8946 flow_dv_apply(struct rte_eth_dev *dev,
8947 struct rte_flow *flow,
8948 struct rte_flow_error *error)
8952 flow_dv_shared_lock(dev);
8953 ret = __flow_dv_apply(dev, flow, error);
8954 flow_dv_shared_unlock(dev);
8959 * Mutex-protected thunk to lock-free __flow_dv_remove().
8962 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8964 flow_dv_shared_lock(dev);
8965 __flow_dv_remove(dev, flow);
8966 flow_dv_shared_unlock(dev);
8970 * Mutex-protected thunk to lock-free __flow_dv_destroy().
8973 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8975 flow_dv_shared_lock(dev);
8976 __flow_dv_destroy(dev, flow);
8977 flow_dv_shared_unlock(dev);
8981 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
8983 static struct mlx5_flow_counter *
8984 flow_dv_counter_allocate(struct rte_eth_dev *dev)
8986 struct mlx5_flow_counter *cnt;
8988 flow_dv_shared_lock(dev);
8989 cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
8990 flow_dv_shared_unlock(dev);
8995 * Mutex-protected thunk to lock-free flow_dv_counter_release().
8998 flow_dv_counter_free(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt)
9000 flow_dv_shared_lock(dev);
9001 flow_dv_counter_release(dev, cnt);
9002 flow_dv_shared_unlock(dev);
9005 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9006 .validate = flow_dv_validate,
9007 .prepare = flow_dv_prepare,
9008 .translate = flow_dv_translate,
9009 .apply = flow_dv_apply,
9010 .remove = flow_dv_remove,
9011 .destroy = flow_dv_destroy,
9012 .query = flow_dv_query,
9013 .create_mtr_tbls = flow_dv_create_mtr_tbl,
9014 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9015 .create_policer_rules = flow_dv_create_policer_rules,
9016 .destroy_policer_rules = flow_dv_destroy_policer_rules,
9017 .counter_alloc = flow_dv_counter_allocate,
9018 .counter_free = flow_dv_counter_free,
9019 .counter_query = flow_dv_counter_query,
9022 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */