1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015-2019 Mellanox Technologies, Ltd
11 #include <rte_mempool.h>
12 #include <rte_prefetch.h>
13 #include <rte_common.h>
14 #include <rte_branch_prediction.h>
15 #include <rte_ether.h>
16 #include <rte_cycles.h>
20 #include <mlx5_common.h>
22 #include "mlx5_autoconf.h"
23 #include "mlx5_defs.h"
26 #include "mlx5_utils.h"
27 #include "mlx5_rxtx.h"
29 /* TX burst subroutines return codes. */
30 enum mlx5_txcmp_code {
31 MLX5_TXCMP_CODE_EXIT = 0,
32 MLX5_TXCMP_CODE_ERROR,
33 MLX5_TXCMP_CODE_SINGLE,
34 MLX5_TXCMP_CODE_MULTI,
40 * These defines are used to configure Tx burst routine option set
41 * supported at compile time. The not specified options are optimized out
42 * out due to if conditions can be explicitly calculated at compile time.
43 * The offloads with bigger runtime check (require more CPU cycles to
44 * skip) overhead should have the bigger index - this is needed to
45 * select the better matching routine function if no exact match and
46 * some offloads are not actually requested.
48 #define MLX5_TXOFF_CONFIG_MULTI (1u << 0) /* Multi-segment packets.*/
49 #define MLX5_TXOFF_CONFIG_TSO (1u << 1) /* TCP send offload supported.*/
50 #define MLX5_TXOFF_CONFIG_SWP (1u << 2) /* Tunnels/SW Parser offloads.*/
51 #define MLX5_TXOFF_CONFIG_CSUM (1u << 3) /* Check Sums offloaded. */
52 #define MLX5_TXOFF_CONFIG_INLINE (1u << 4) /* Data inlining supported. */
53 #define MLX5_TXOFF_CONFIG_VLAN (1u << 5) /* VLAN insertion supported.*/
54 #define MLX5_TXOFF_CONFIG_METADATA (1u << 6) /* Flow metadata. */
55 #define MLX5_TXOFF_CONFIG_EMPW (1u << 8) /* Enhanced MPW supported.*/
56 #define MLX5_TXOFF_CONFIG_MPW (1u << 9) /* Legacy MPW supported.*/
57 #define MLX5_TXOFF_CONFIG_TXPP (1u << 10) /* Scheduling on timestamp.*/
59 /* The most common offloads groups. */
60 #define MLX5_TXOFF_CONFIG_NONE 0
61 #define MLX5_TXOFF_CONFIG_FULL (MLX5_TXOFF_CONFIG_MULTI | \
62 MLX5_TXOFF_CONFIG_TSO | \
63 MLX5_TXOFF_CONFIG_SWP | \
64 MLX5_TXOFF_CONFIG_CSUM | \
65 MLX5_TXOFF_CONFIG_INLINE | \
66 MLX5_TXOFF_CONFIG_VLAN | \
67 MLX5_TXOFF_CONFIG_METADATA)
69 #define MLX5_TXOFF_CONFIG(mask) (olx & MLX5_TXOFF_CONFIG_##mask)
71 #define MLX5_TXOFF_DECL(func, olx) \
72 static uint16_t mlx5_tx_burst_##func(void *txq, \
73 struct rte_mbuf **pkts, \
76 return mlx5_tx_burst_tmpl((struct mlx5_txq_data *)txq, \
77 pkts, pkts_n, (olx)); \
80 #define MLX5_TXOFF_INFO(func, olx) {mlx5_tx_burst_##func, olx},
82 static __rte_always_inline uint32_t
83 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
84 volatile struct mlx5_mini_cqe8 *mcqe);
86 static __rte_always_inline int
87 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
88 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
90 static __rte_always_inline uint32_t
91 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
93 static __rte_always_inline void
94 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
95 volatile struct mlx5_cqe *cqe,
96 volatile struct mlx5_mini_cqe8 *mcqe);
99 mlx5_queue_state_modify(struct rte_eth_dev *dev,
100 struct mlx5_mp_arg_queue_state_modify *sm);
103 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *__rte_restrict tcp,
104 volatile struct mlx5_cqe *__rte_restrict cqe,
105 uint32_t phcsum, uint8_t l4_type);
108 mlx5_lro_update_hdr(uint8_t *__rte_restrict padd,
109 volatile struct mlx5_cqe *__rte_restrict cqe,
110 volatile struct mlx5_mini_cqe8 *mcqe,
111 struct mlx5_rxq_data *rxq, uint32_t len);
113 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
114 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
117 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
118 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
120 uint64_t rte_net_mlx5_dynf_inline_mask;
121 #define PKT_TX_DYNF_NOINLINE rte_net_mlx5_dynf_inline_mask
124 * Build a table to translate Rx completion flags to packet type.
126 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
129 mlx5_set_ptype_table(void)
132 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
134 /* Last entry must not be overwritten, reserved for errored packet. */
135 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
136 (*p)[i] = RTE_PTYPE_UNKNOWN;
138 * The index to the array should have:
139 * bit[1:0] = l3_hdr_type
140 * bit[4:2] = l4_hdr_type
143 * bit[7] = outer_l3_type
146 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
148 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
149 RTE_PTYPE_L4_NONFRAG;
150 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
151 RTE_PTYPE_L4_NONFRAG;
153 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
155 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
158 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
160 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
162 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
164 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
166 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
168 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
171 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
173 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
175 /* Repeat with outer_l3_type being set. Just in case. */
176 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
177 RTE_PTYPE_L4_NONFRAG;
178 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
179 RTE_PTYPE_L4_NONFRAG;
180 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
182 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
184 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
186 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
188 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
190 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
192 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
194 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
196 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
198 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
201 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
202 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
203 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
204 RTE_PTYPE_INNER_L4_NONFRAG;
205 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
206 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
207 RTE_PTYPE_INNER_L4_NONFRAG;
208 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
209 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
210 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
211 RTE_PTYPE_INNER_L4_NONFRAG;
212 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
213 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
214 RTE_PTYPE_INNER_L4_NONFRAG;
215 /* Tunneled - Fragmented */
216 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
217 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
218 RTE_PTYPE_INNER_L4_FRAG;
219 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
220 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
221 RTE_PTYPE_INNER_L4_FRAG;
222 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
223 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
224 RTE_PTYPE_INNER_L4_FRAG;
225 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
226 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
227 RTE_PTYPE_INNER_L4_FRAG;
229 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
230 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
231 RTE_PTYPE_INNER_L4_TCP;
232 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
233 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
234 RTE_PTYPE_INNER_L4_TCP;
235 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
236 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
237 RTE_PTYPE_INNER_L4_TCP;
238 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
239 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
240 RTE_PTYPE_INNER_L4_TCP;
241 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
242 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
243 RTE_PTYPE_INNER_L4_TCP;
244 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
245 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
246 RTE_PTYPE_INNER_L4_TCP;
247 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
248 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
249 RTE_PTYPE_INNER_L4_TCP;
250 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
251 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
252 RTE_PTYPE_INNER_L4_TCP;
253 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
254 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
255 RTE_PTYPE_INNER_L4_TCP;
256 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
257 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
258 RTE_PTYPE_INNER_L4_TCP;
259 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
260 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
261 RTE_PTYPE_INNER_L4_TCP;
262 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
263 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
264 RTE_PTYPE_INNER_L4_TCP;
266 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
267 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
268 RTE_PTYPE_INNER_L4_UDP;
269 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
270 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
271 RTE_PTYPE_INNER_L4_UDP;
272 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
273 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
274 RTE_PTYPE_INNER_L4_UDP;
275 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
276 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
277 RTE_PTYPE_INNER_L4_UDP;
281 * Build a table to translate packet to checksum type of Verbs.
284 mlx5_set_cksum_table(void)
290 * The index should have:
291 * bit[0] = PKT_TX_TCP_SEG
292 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
293 * bit[4] = PKT_TX_IP_CKSUM
294 * bit[8] = PKT_TX_OUTER_IP_CKSUM
297 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
300 /* Tunneled packet. */
301 if (i & (1 << 8)) /* Outer IP. */
302 v |= MLX5_ETH_WQE_L3_CSUM;
303 if (i & (1 << 4)) /* Inner IP. */
304 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
305 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
306 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
309 if (i & (1 << 4)) /* IP. */
310 v |= MLX5_ETH_WQE_L3_CSUM;
311 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
312 v |= MLX5_ETH_WQE_L4_CSUM;
314 mlx5_cksum_table[i] = v;
319 * Build a table to translate packet type of mbuf to SWP type of Verbs.
322 mlx5_set_swp_types_table(void)
328 * The index should have:
329 * bit[0:1] = PKT_TX_L4_MASK
330 * bit[4] = PKT_TX_IPV6
331 * bit[8] = PKT_TX_OUTER_IPV6
332 * bit[9] = PKT_TX_OUTER_UDP
334 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
337 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
339 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
341 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
342 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
343 v |= MLX5_ETH_WQE_L4_INNER_UDP;
344 mlx5_swp_types_table[i] = v;
349 * Set Software Parser flags and offsets in Ethernet Segment of WQE.
350 * Flags must be preliminary initialized to zero.
353 * Pointer to burst routine local context.
355 * Pointer to store Software Parser flags
357 * Configured Tx offloads mask. It is fully defined at
358 * compile time and may be used for optimization.
361 * Software Parser offsets packed in dword.
362 * Software Parser flags are set by pointer.
364 static __rte_always_inline uint32_t
365 txq_mbuf_to_swp(struct mlx5_txq_local *__rte_restrict loc,
370 unsigned int idx, off;
373 if (!MLX5_TXOFF_CONFIG(SWP))
375 ol = loc->mbuf->ol_flags;
376 tunnel = ol & PKT_TX_TUNNEL_MASK;
378 * Check whether Software Parser is required.
379 * Only customized tunnels may ask for.
381 if (likely(tunnel != PKT_TX_TUNNEL_UDP && tunnel != PKT_TX_TUNNEL_IP))
384 * The index should have:
385 * bit[0:1] = PKT_TX_L4_MASK
386 * bit[4] = PKT_TX_IPV6
387 * bit[8] = PKT_TX_OUTER_IPV6
388 * bit[9] = PKT_TX_OUTER_UDP
390 idx = (ol & (PKT_TX_L4_MASK | PKT_TX_IPV6 | PKT_TX_OUTER_IPV6)) >> 52;
391 idx |= (tunnel == PKT_TX_TUNNEL_UDP) ? (1 << 9) : 0;
392 *swp_flags = mlx5_swp_types_table[idx];
394 * Set offsets for SW parser. Since ConnectX-5, SW parser just
395 * complements HW parser. SW parser starts to engage only if HW parser
396 * can't reach a header. For the older devices, HW parser will not kick
397 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
398 * should be set regardless of HW offload.
400 off = loc->mbuf->outer_l2_len;
401 if (MLX5_TXOFF_CONFIG(VLAN) && ol & PKT_TX_VLAN_PKT)
402 off += sizeof(struct rte_vlan_hdr);
403 set = (off >> 1) << 8; /* Outer L3 offset. */
404 off += loc->mbuf->outer_l3_len;
405 if (tunnel == PKT_TX_TUNNEL_UDP)
406 set |= off >> 1; /* Outer L4 offset. */
407 if (ol & (PKT_TX_IPV4 | PKT_TX_IPV6)) { /* Inner IP. */
408 const uint64_t csum = ol & PKT_TX_L4_MASK;
409 off += loc->mbuf->l2_len;
410 set |= (off >> 1) << 24; /* Inner L3 offset. */
411 if (csum == PKT_TX_TCP_CKSUM ||
412 csum == PKT_TX_UDP_CKSUM ||
413 (MLX5_TXOFF_CONFIG(TSO) && ol & PKT_TX_TCP_SEG)) {
414 off += loc->mbuf->l3_len;
415 set |= (off >> 1) << 16; /* Inner L4 offset. */
418 set = rte_cpu_to_le_32(set);
423 * Convert the Checksum offloads to Verbs.
426 * Pointer to the mbuf.
429 * Converted checksum flags.
431 static __rte_always_inline uint8_t
432 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
435 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
436 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
437 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
440 * The index should have:
441 * bit[0] = PKT_TX_TCP_SEG
442 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
443 * bit[4] = PKT_TX_IP_CKSUM
444 * bit[8] = PKT_TX_OUTER_IP_CKSUM
447 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
448 return mlx5_cksum_table[idx];
452 * Internal function to compute the number of used descriptors in an RX queue
458 * The number of used rx descriptor.
461 rx_queue_count(struct mlx5_rxq_data *rxq)
463 struct rxq_zip *zip = &rxq->zip;
464 volatile struct mlx5_cqe *cqe;
465 const unsigned int cqe_n = (1 << rxq->cqe_n);
466 const unsigned int sges_n = (1 << rxq->sges_n);
467 const unsigned int elts_n = (1 << rxq->elts_n);
468 const unsigned int strd_n = (1 << rxq->strd_num_n);
469 const unsigned int cqe_cnt = cqe_n - 1;
470 unsigned int cq_ci, used;
472 /* if we are processing a compressed cqe */
474 used = zip->cqe_cnt - zip->ai;
480 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
481 while (check_cqe(cqe, cqe_n, cq_ci) != MLX5_CQE_STATUS_HW_OWN) {
485 op_own = cqe->op_own;
486 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
487 n = rte_be_to_cpu_32(cqe->byte_cnt);
492 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
494 used = RTE_MIN(used * sges_n, elts_n * strd_n);
499 * DPDK callback to check the status of a rx descriptor.
504 * The index of the descriptor in the ring.
507 * The status of the tx descriptor.
510 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
512 struct mlx5_rxq_data *rxq = rx_queue;
513 struct mlx5_rxq_ctrl *rxq_ctrl =
514 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
515 struct rte_eth_dev *dev = ETH_DEV(rxq_ctrl->priv);
517 if (dev->rx_pkt_burst == NULL ||
518 dev->rx_pkt_burst == removed_rx_burst) {
522 if (offset >= (1 << rxq->cqe_n)) {
526 if (offset < rx_queue_count(rxq))
527 return RTE_ETH_RX_DESC_DONE;
528 return RTE_ETH_RX_DESC_AVAIL;
532 * DPDK callback to get the RX queue information
535 * Pointer to the device structure.
538 * Rx queue identificator.
541 * Pointer to the RX queue information structure.
548 mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
549 struct rte_eth_rxq_info *qinfo)
551 struct mlx5_priv *priv = dev->data->dev_private;
552 struct mlx5_rxq_data *rxq = (*priv->rxqs)[rx_queue_id];
553 struct mlx5_rxq_ctrl *rxq_ctrl =
554 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
558 qinfo->mp = mlx5_rxq_mprq_enabled(rxq) ?
559 rxq->mprq_mp : rxq->mp;
560 qinfo->conf.rx_thresh.pthresh = 0;
561 qinfo->conf.rx_thresh.hthresh = 0;
562 qinfo->conf.rx_thresh.wthresh = 0;
563 qinfo->conf.rx_free_thresh = rxq->rq_repl_thresh;
564 qinfo->conf.rx_drop_en = 1;
565 qinfo->conf.rx_deferred_start = rxq_ctrl ? 0 : 1;
566 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
567 qinfo->scattered_rx = dev->data->scattered_rx;
568 qinfo->nb_desc = mlx5_rxq_mprq_enabled(rxq) ?
569 (1 << rxq->elts_n) * (1 << rxq->strd_num_n) :
574 * DPDK callback to get the RX packet burst mode information
577 * Pointer to the device structure.
580 * Rx queue identificatior.
583 * Pointer to the burts mode information.
586 * 0 as success, -EINVAL as failure.
590 mlx5_rx_burst_mode_get(struct rte_eth_dev *dev,
591 uint16_t rx_queue_id __rte_unused,
592 struct rte_eth_burst_mode *mode)
594 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
595 struct mlx5_priv *priv = dev->data->dev_private;
596 struct mlx5_rxq_data *rxq;
598 rxq = (*priv->rxqs)[rx_queue_id];
603 if (pkt_burst == mlx5_rx_burst) {
604 snprintf(mode->info, sizeof(mode->info), "%s", "Scalar");
605 } else if (pkt_burst == mlx5_rx_burst_mprq) {
606 snprintf(mode->info, sizeof(mode->info), "%s", "Multi-Packet RQ");
607 } else if (pkt_burst == mlx5_rx_burst_vec) {
608 #if defined RTE_ARCH_X86_64
609 snprintf(mode->info, sizeof(mode->info), "%s", "Vector SSE");
610 #elif defined RTE_ARCH_ARM64
611 snprintf(mode->info, sizeof(mode->info), "%s", "Vector Neon");
612 #elif defined RTE_ARCH_PPC_64
613 snprintf(mode->info, sizeof(mode->info), "%s", "Vector AltiVec");
617 } else if (pkt_burst == mlx5_rx_burst_mprq_vec) {
618 #if defined RTE_ARCH_X86_64
619 snprintf(mode->info, sizeof(mode->info), "%s", "MPRQ Vector SSE");
620 #elif defined RTE_ARCH_ARM64
621 snprintf(mode->info, sizeof(mode->info), "%s", "MPRQ Vector Neon");
622 #elif defined RTE_ARCH_PPC_64
623 snprintf(mode->info, sizeof(mode->info), "%s", "MPRQ Vector AltiVec");
634 * DPDK callback to get the number of used descriptors in a RX queue
637 * Pointer to the device structure.
643 * The number of used rx descriptor.
644 * -EINVAL if the queue is invalid
647 mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
649 struct mlx5_priv *priv = dev->data->dev_private;
650 struct mlx5_rxq_data *rxq;
652 if (dev->rx_pkt_burst == NULL ||
653 dev->rx_pkt_burst == removed_rx_burst) {
657 rxq = (*priv->rxqs)[rx_queue_id];
662 return rx_queue_count(rxq);
665 #define MLX5_SYSTEM_LOG_DIR "/var/log"
667 * Dump debug information to log file.
672 * If not NULL this string is printed as a header to the output
673 * and the output will be in hexadecimal view.
675 * This is the buffer address to print out.
677 * The number of bytes to dump out.
680 mlx5_dump_debug_information(const char *fname, const char *hex_title,
681 const void *buf, unsigned int hex_len)
685 MKSTR(path, "%s/%s", MLX5_SYSTEM_LOG_DIR, fname);
686 fd = fopen(path, "a+");
688 DRV_LOG(WARNING, "cannot open %s for debug dump", path);
689 MKSTR(path2, "./%s", fname);
690 fd = fopen(path2, "a+");
692 DRV_LOG(ERR, "cannot open %s for debug dump", path2);
695 DRV_LOG(INFO, "New debug dump in file %s", path2);
697 DRV_LOG(INFO, "New debug dump in file %s", path);
700 rte_hexdump(fd, hex_title, buf, hex_len);
702 fprintf(fd, "%s", (const char *)buf);
703 fprintf(fd, "\n\n\n");
708 * Move QP from error state to running state and initialize indexes.
711 * Pointer to TX queue control structure.
714 * 0 on success, else -1.
717 tx_recover_qp(struct mlx5_txq_ctrl *txq_ctrl)
719 struct mlx5_mp_arg_queue_state_modify sm = {
721 .queue_id = txq_ctrl->txq.idx,
724 if (mlx5_queue_state_modify(ETH_DEV(txq_ctrl->priv), &sm))
726 txq_ctrl->txq.wqe_ci = 0;
727 txq_ctrl->txq.wqe_pi = 0;
728 txq_ctrl->txq.elts_comp = 0;
732 /* Return 1 if the error CQE is signed otherwise, sign it and return 0. */
734 check_err_cqe_seen(volatile struct mlx5_err_cqe *err_cqe)
736 static const uint8_t magic[] = "seen";
740 for (i = 0; i < sizeof(magic); ++i)
741 if (!ret || err_cqe->rsvd1[i] != magic[i]) {
743 err_cqe->rsvd1[i] = magic[i];
752 * Pointer to TX queue structure.
754 * Pointer to the error CQE.
757 * Negative value if queue recovery failed, otherwise
758 * the error completion entry is handled successfully.
761 mlx5_tx_error_cqe_handle(struct mlx5_txq_data *__rte_restrict txq,
762 volatile struct mlx5_err_cqe *err_cqe)
764 if (err_cqe->syndrome != MLX5_CQE_SYNDROME_WR_FLUSH_ERR) {
765 const uint16_t wqe_m = ((1 << txq->wqe_n) - 1);
766 struct mlx5_txq_ctrl *txq_ctrl =
767 container_of(txq, struct mlx5_txq_ctrl, txq);
768 uint16_t new_wqe_pi = rte_be_to_cpu_16(err_cqe->wqe_counter);
769 int seen = check_err_cqe_seen(err_cqe);
771 if (!seen && txq_ctrl->dump_file_n <
772 txq_ctrl->priv->config.max_dump_files_num) {
773 MKSTR(err_str, "Unexpected CQE error syndrome "
774 "0x%02x CQN = %u SQN = %u wqe_counter = %u "
775 "wq_ci = %u cq_ci = %u", err_cqe->syndrome,
776 txq->cqe_s, txq->qp_num_8s >> 8,
777 rte_be_to_cpu_16(err_cqe->wqe_counter),
778 txq->wqe_ci, txq->cq_ci);
779 MKSTR(name, "dpdk_mlx5_port_%u_txq_%u_index_%u_%u",
780 PORT_ID(txq_ctrl->priv), txq->idx,
781 txq_ctrl->dump_file_n, (uint32_t)rte_rdtsc());
782 mlx5_dump_debug_information(name, NULL, err_str, 0);
783 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
784 (const void *)((uintptr_t)
788 mlx5_dump_debug_information(name, "MLX5 Error SQ:",
789 (const void *)((uintptr_t)
793 txq_ctrl->dump_file_n++;
797 * Count errors in WQEs units.
798 * Later it can be improved to count error packets,
799 * for example, by SQ parsing to find how much packets
800 * should be counted for each WQE.
802 txq->stats.oerrors += ((txq->wqe_ci & wqe_m) -
804 if (tx_recover_qp(txq_ctrl)) {
805 /* Recovering failed - retry later on the same WQE. */
808 /* Release all the remaining buffers. */
809 txq_free_elts(txq_ctrl);
815 * Translate RX completion flags to packet type.
818 * Pointer to RX queue structure.
822 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
825 * Packet type for struct rte_mbuf.
827 static inline uint32_t
828 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
829 volatile struct mlx5_mini_cqe8 *mcqe)
833 uint8_t pinfo = (cqe->pkt_info & 0x3) << 6;
835 /* Get l3/l4 header from mini-CQE in case L3/L4 format*/
837 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_L34H_STRIDX)
838 ptype = (cqe->hdr_type_etc & 0xfc00) >> 10;
840 ptype = mcqe->hdr_type >> 2;
842 * The index to the array should have:
843 * bit[1:0] = l3_hdr_type
844 * bit[4:2] = l4_hdr_type
847 * bit[7] = outer_l3_type
850 return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
854 * Initialize Rx WQ and indexes.
857 * Pointer to RX queue structure.
860 mlx5_rxq_initialize(struct mlx5_rxq_data *rxq)
862 const unsigned int wqe_n = 1 << rxq->elts_n;
865 for (i = 0; (i != wqe_n); ++i) {
866 volatile struct mlx5_wqe_data_seg *scat;
870 if (mlx5_rxq_mprq_enabled(rxq)) {
871 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[i];
873 scat = &((volatile struct mlx5_wqe_mprq *)
875 addr = (uintptr_t)mlx5_mprq_buf_addr(buf,
876 1 << rxq->strd_num_n);
877 byte_count = (1 << rxq->strd_sz_n) *
878 (1 << rxq->strd_num_n);
880 struct rte_mbuf *buf = (*rxq->elts)[i];
882 scat = &((volatile struct mlx5_wqe_data_seg *)
884 addr = rte_pktmbuf_mtod(buf, uintptr_t);
885 byte_count = DATA_LEN(buf);
887 /* scat->addr must be able to store a pointer. */
888 MLX5_ASSERT(sizeof(scat->addr) >= sizeof(uintptr_t));
889 *scat = (struct mlx5_wqe_data_seg){
890 .addr = rte_cpu_to_be_64(addr),
891 .byte_count = rte_cpu_to_be_32(byte_count),
892 .lkey = mlx5_rx_addr2mr(rxq, addr),
895 rxq->consumed_strd = 0;
896 rxq->decompressed = 0;
898 rxq->zip = (struct rxq_zip){
901 rxq->elts_ci = mlx5_rxq_mprq_enabled(rxq) ?
902 (wqe_n >> rxq->sges_n) * (1 << rxq->strd_num_n) : 0;
903 /* Update doorbell counter. */
904 rxq->rq_ci = wqe_n >> rxq->sges_n;
906 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
910 * Modify a Verbs/DevX queue state.
911 * This must be called from the primary process.
914 * Pointer to Ethernet device.
916 * State modify request parameters.
919 * 0 in case of success else non-zero value and rte_errno is set.
922 mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
923 const struct mlx5_mp_arg_queue_state_modify *sm)
926 struct mlx5_priv *priv = dev->data->dev_private;
929 struct mlx5_rxq_data *rxq = (*priv->rxqs)[sm->queue_id];
930 struct mlx5_rxq_ctrl *rxq_ctrl =
931 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
933 ret = priv->obj_ops.rxq_obj_modify(rxq_ctrl->obj, sm->state);
935 DRV_LOG(ERR, "Cannot change Rx WQ state to %u - %s",
936 sm->state, strerror(errno));
941 struct mlx5_txq_data *txq = (*priv->txqs)[sm->queue_id];
942 struct mlx5_txq_ctrl *txq_ctrl =
943 container_of(txq, struct mlx5_txq_ctrl, txq);
945 ret = priv->obj_ops.txq_obj_modify(txq_ctrl->obj,
946 MLX5_TXQ_MOD_ERR2RDY,
947 (uint8_t)priv->dev_port);
955 * Modify a Verbs queue state.
958 * Pointer to Ethernet device.
960 * State modify request parameters.
963 * 0 in case of success else non-zero value.
966 mlx5_queue_state_modify(struct rte_eth_dev *dev,
967 struct mlx5_mp_arg_queue_state_modify *sm)
969 struct mlx5_priv *priv = dev->data->dev_private;
972 switch (rte_eal_process_type()) {
973 case RTE_PROC_PRIMARY:
974 ret = mlx5_queue_state_modify_primary(dev, sm);
976 case RTE_PROC_SECONDARY:
977 ret = mlx5_mp_req_queue_state_modify(&priv->mp_id, sm);
987 * The function inserts the RQ state to reset when the first error CQE is
988 * shown, then drains the CQ by the caller function loop. When the CQ is empty,
989 * it moves the RQ state to ready and initializes the RQ.
990 * Next CQE identification and error counting are in the caller responsibility.
993 * Pointer to RX queue structure.
995 * 1 when called from vectorized Rx burst, need to prepare mbufs for the RQ.
996 * 0 when called from non-vectorized Rx burst.
999 * -1 in case of recovery error, otherwise the CQE status.
1002 mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec)
1004 const uint16_t cqe_n = 1 << rxq->cqe_n;
1005 const uint16_t cqe_mask = cqe_n - 1;
1006 const uint16_t wqe_n = 1 << rxq->elts_n;
1007 const uint16_t strd_n = 1 << rxq->strd_num_n;
1008 struct mlx5_rxq_ctrl *rxq_ctrl =
1009 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
1011 volatile struct mlx5_cqe *cqe;
1012 volatile struct mlx5_err_cqe *err_cqe;
1014 .cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask],
1016 struct mlx5_mp_arg_queue_state_modify sm;
1019 switch (rxq->err_state) {
1020 case MLX5_RXQ_ERR_STATE_NO_ERROR:
1021 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_RESET;
1023 case MLX5_RXQ_ERR_STATE_NEED_RESET:
1025 sm.queue_id = rxq->idx;
1026 sm.state = IBV_WQS_RESET;
1027 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv), &sm))
1029 if (rxq_ctrl->dump_file_n <
1030 rxq_ctrl->priv->config.max_dump_files_num) {
1031 MKSTR(err_str, "Unexpected CQE error syndrome "
1032 "0x%02x CQN = %u RQN = %u wqe_counter = %u"
1033 " rq_ci = %u cq_ci = %u", u.err_cqe->syndrome,
1034 rxq->cqn, rxq_ctrl->wqn,
1035 rte_be_to_cpu_16(u.err_cqe->wqe_counter),
1036 rxq->rq_ci << rxq->sges_n, rxq->cq_ci);
1037 MKSTR(name, "dpdk_mlx5_port_%u_rxq_%u_%u",
1038 rxq->port_id, rxq->idx, (uint32_t)rte_rdtsc());
1039 mlx5_dump_debug_information(name, NULL, err_str, 0);
1040 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
1041 (const void *)((uintptr_t)
1043 sizeof(*u.cqe) * cqe_n);
1044 mlx5_dump_debug_information(name, "MLX5 Error RQ:",
1045 (const void *)((uintptr_t)
1048 rxq_ctrl->dump_file_n++;
1050 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_READY;
1052 case MLX5_RXQ_ERR_STATE_NEED_READY:
1053 ret = check_cqe(u.cqe, cqe_n, rxq->cq_ci);
1054 if (ret == MLX5_CQE_STATUS_HW_OWN) {
1056 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1059 * The RQ consumer index must be zeroed while moving
1060 * from RESET state to RDY state.
1062 *rxq->rq_db = rte_cpu_to_be_32(0);
1065 sm.queue_id = rxq->idx;
1066 sm.state = IBV_WQS_RDY;
1067 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv),
1071 const uint32_t elts_n =
1072 mlx5_rxq_mprq_enabled(rxq) ?
1073 wqe_n * strd_n : wqe_n;
1074 const uint32_t e_mask = elts_n - 1;
1076 mlx5_rxq_mprq_enabled(rxq) ?
1077 rxq->elts_ci : rxq->rq_ci;
1079 struct rte_mbuf **elt;
1081 unsigned int n = elts_n - (elts_ci -
1084 for (i = 0; i < (int)n; ++i) {
1085 elt_idx = (elts_ci + i) & e_mask;
1086 elt = &(*rxq->elts)[elt_idx];
1087 *elt = rte_mbuf_raw_alloc(rxq->mp);
1089 for (i--; i >= 0; --i) {
1090 elt_idx = (elts_ci +
1094 rte_pktmbuf_free_seg
1100 for (i = 0; i < (int)elts_n; ++i) {
1101 elt = &(*rxq->elts)[i];
1103 (uint16_t)((*elt)->buf_len -
1104 rte_pktmbuf_headroom(*elt));
1106 /* Padding with a fake mbuf for vec Rx. */
1107 for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i)
1108 (*rxq->elts)[elts_n + i] =
1111 mlx5_rxq_initialize(rxq);
1112 rxq->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
1121 * Get size of the next packet for a given CQE. For compressed CQEs, the
1122 * consumer index is updated only once all packets of the current one have
1126 * Pointer to RX queue.
1130 * Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
1134 * 0 in case of empty CQE, otherwise the packet size in bytes.
1137 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1138 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
1140 struct rxq_zip *zip = &rxq->zip;
1141 uint16_t cqe_n = cqe_cnt + 1;
1147 /* Process compressed data in the CQE and mini arrays. */
1149 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1150 (volatile struct mlx5_mini_cqe8 (*)[8])
1151 (uintptr_t)(&(*rxq->cqes)[zip->ca &
1153 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt &
1155 *mcqe = &(*mc)[zip->ai & 7];
1156 if ((++zip->ai & 7) == 0) {
1157 /* Invalidate consumed CQEs */
1160 while (idx != end) {
1161 (*rxq->cqes)[idx & cqe_cnt].op_own =
1162 MLX5_CQE_INVALIDATE;
1166 * Increment consumer index to skip the number
1167 * of CQEs consumed. Hardware leaves holes in
1168 * the CQ ring for software use.
1173 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1174 /* Invalidate the rest */
1178 while (idx != end) {
1179 (*rxq->cqes)[idx & cqe_cnt].op_own =
1180 MLX5_CQE_INVALIDATE;
1183 rxq->cq_ci = zip->cq_ci;
1187 * No compressed data, get next CQE and verify if it is
1195 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1196 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
1197 if (unlikely(ret == MLX5_CQE_STATUS_ERR ||
1199 ret = mlx5_rx_err_handle(rxq, 0);
1200 if (ret == MLX5_CQE_STATUS_HW_OWN ||
1208 * Introduce the local variable to have queue cq_ci
1209 * index in queue structure always consistent with
1210 * actual CQE boundary (not pointing to the middle
1211 * of compressed CQE session).
1213 cq_ci = rxq->cq_ci + 1;
1214 op_own = cqe->op_own;
1215 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1216 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1217 (volatile struct mlx5_mini_cqe8 (*)[8])
1218 (uintptr_t)(&(*rxq->cqes)
1219 [cq_ci & cqe_cnt].pkt_info);
1221 /* Fix endianness. */
1222 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1224 * Current mini array position is the one
1225 * returned by check_cqe64().
1227 * If completion comprises several mini arrays,
1228 * as a special case the second one is located
1229 * 7 CQEs after the initial CQE instead of 8
1230 * for subsequent ones.
1233 zip->na = zip->ca + 7;
1234 /* Compute the next non compressed CQE. */
1235 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1236 /* Get packet size to return. */
1237 len = rte_be_to_cpu_32((*mc)[0].byte_cnt &
1241 /* Prefetch all to be invalidated */
1244 while (idx != end) {
1245 rte_prefetch0(&(*rxq->cqes)[(idx) &
1251 len = rte_be_to_cpu_32(cqe->byte_cnt);
1254 if (unlikely(rxq->err_state)) {
1255 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1256 ++rxq->stats.idropped;
1264 * Translate RX completion flags to offload flags.
1270 * Offload flags (ol_flags) for struct rte_mbuf.
1272 static inline uint32_t
1273 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1275 uint32_t ol_flags = 0;
1276 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1280 MLX5_CQE_RX_L3_HDR_VALID,
1281 PKT_RX_IP_CKSUM_GOOD) |
1283 MLX5_CQE_RX_L4_HDR_VALID,
1284 PKT_RX_L4_CKSUM_GOOD);
1289 * Fill in mbuf fields from RX completion flags.
1290 * Note that pkt->ol_flags should be initialized outside of this function.
1293 * Pointer to RX queue.
1298 * @param rss_hash_res
1299 * Packet RSS Hash result.
1302 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1303 volatile struct mlx5_cqe *cqe,
1304 volatile struct mlx5_mini_cqe8 *mcqe)
1306 /* Update packet information. */
1307 pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe, mcqe);
1309 if (rxq->rss_hash) {
1310 uint32_t rss_hash_res = 0;
1312 /* If compressed, take hash result from mini-CQE. */
1314 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_HASH)
1315 rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
1317 rss_hash_res = rte_be_to_cpu_32(mcqe->rx_hash_result);
1319 pkt->hash.rss = rss_hash_res;
1320 pkt->ol_flags |= PKT_RX_RSS_HASH;
1326 /* If compressed, take flow tag from mini-CQE. */
1328 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_FTAG_STRIDX)
1329 mark = cqe->sop_drop_qpn;
1331 mark = ((mcqe->byte_cnt_flow & 0xff) << 8) |
1332 (mcqe->flow_tag_high << 16);
1333 if (MLX5_FLOW_MARK_IS_VALID(mark)) {
1334 pkt->ol_flags |= PKT_RX_FDIR;
1335 if (mark != RTE_BE32(MLX5_FLOW_MARK_DEFAULT)) {
1336 pkt->ol_flags |= PKT_RX_FDIR_ID;
1337 pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1341 if (rxq->dynf_meta && cqe->flow_table_metadata) {
1342 pkt->ol_flags |= rxq->flow_meta_mask;
1343 *RTE_MBUF_DYNFIELD(pkt, rxq->flow_meta_offset, uint32_t *) =
1344 cqe->flow_table_metadata;
1347 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1348 if (rxq->vlan_strip) {
1352 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_L34H_STRIDX)
1353 vlan_strip = cqe->hdr_type_etc &
1354 RTE_BE16(MLX5_CQE_VLAN_STRIPPED);
1356 vlan_strip = mcqe->hdr_type &
1357 RTE_BE16(MLX5_CQE_VLAN_STRIPPED);
1359 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1360 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1363 if (rxq->hw_timestamp) {
1364 uint64_t ts = rte_be_to_cpu_64(cqe->timestamp);
1366 if (rxq->rt_timestamp)
1367 ts = mlx5_txpp_convert_rx_ts(rxq->sh, ts);
1368 mlx5_timestamp_set(pkt, rxq->timestamp_offset, ts);
1369 pkt->ol_flags |= rxq->timestamp_rx_flag;
1374 * DPDK callback for RX.
1377 * Generic pointer to RX queue structure.
1379 * Array to store received packets.
1381 * Maximum number of packets in array.
1384 * Number of packets successfully received (<= pkts_n).
1387 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1389 struct mlx5_rxq_data *rxq = dpdk_rxq;
1390 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1391 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1392 const unsigned int sges_n = rxq->sges_n;
1393 struct rte_mbuf *pkt = NULL;
1394 struct rte_mbuf *seg = NULL;
1395 volatile struct mlx5_cqe *cqe =
1396 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1398 unsigned int rq_ci = rxq->rq_ci << sges_n;
1399 int len = 0; /* keep its value across iterations. */
1402 unsigned int idx = rq_ci & wqe_cnt;
1403 volatile struct mlx5_wqe_data_seg *wqe =
1404 &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
1405 struct rte_mbuf *rep = (*rxq->elts)[idx];
1406 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1414 /* Allocate the buf from the same pool. */
1415 rep = rte_mbuf_raw_alloc(seg->pool);
1416 if (unlikely(rep == NULL)) {
1417 ++rxq->stats.rx_nombuf;
1420 * no buffers before we even started,
1421 * bail out silently.
1425 while (pkt != seg) {
1426 MLX5_ASSERT(pkt != (*rxq->elts)[idx]);
1430 rte_mbuf_raw_free(pkt);
1436 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1437 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
1439 rte_mbuf_raw_free(rep);
1443 MLX5_ASSERT(len >= (rxq->crc_present << 2));
1444 pkt->ol_flags &= EXT_ATTACHED_MBUF;
1445 rxq_cq_to_mbuf(rxq, pkt, cqe, mcqe);
1446 if (rxq->crc_present)
1447 len -= RTE_ETHER_CRC_LEN;
1449 if (cqe->lro_num_seg > 1) {
1451 (rte_pktmbuf_mtod(pkt, uint8_t *), cqe,
1453 pkt->ol_flags |= PKT_RX_LRO;
1454 pkt->tso_segsz = len / cqe->lro_num_seg;
1457 DATA_LEN(rep) = DATA_LEN(seg);
1458 PKT_LEN(rep) = PKT_LEN(seg);
1459 SET_DATA_OFF(rep, DATA_OFF(seg));
1460 PORT(rep) = PORT(seg);
1461 (*rxq->elts)[idx] = rep;
1463 * Fill NIC descriptor with the new buffer. The lkey and size
1464 * of the buffers are already known, only the buffer address
1467 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1468 /* If there's only one MR, no need to replace LKey in WQE. */
1469 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1470 wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
1471 if (len > DATA_LEN(seg)) {
1472 len -= DATA_LEN(seg);
1477 DATA_LEN(seg) = len;
1478 #ifdef MLX5_PMD_SOFT_COUNTERS
1479 /* Increment bytes counter. */
1480 rxq->stats.ibytes += PKT_LEN(pkt);
1482 /* Return packet. */
1487 /* Align consumer index to the next stride. */
1492 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1494 /* Update the consumer index. */
1495 rxq->rq_ci = rq_ci >> sges_n;
1497 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1499 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1500 #ifdef MLX5_PMD_SOFT_COUNTERS
1501 /* Increment packets counter. */
1502 rxq->stats.ipackets += i;
1508 * Update LRO packet TCP header.
1509 * The HW LRO feature doesn't update the TCP header after coalescing the
1510 * TCP segments but supplies information in CQE to fill it by SW.
1513 * Pointer to the TCP header.
1515 * Pointer to the completion entry..
1517 * The L3 pseudo-header checksum.
1520 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *__rte_restrict tcp,
1521 volatile struct mlx5_cqe *__rte_restrict cqe,
1522 uint32_t phcsum, uint8_t l4_type)
1525 * The HW calculates only the TCP payload checksum, need to complete
1526 * the TCP header checksum and the L3 pseudo-header checksum.
1528 uint32_t csum = phcsum + cqe->csum;
1530 if (l4_type == MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK ||
1531 l4_type == MLX5_L4_HDR_TYPE_TCP_WITH_ACL) {
1532 tcp->tcp_flags |= RTE_TCP_ACK_FLAG;
1533 tcp->recv_ack = cqe->lro_ack_seq_num;
1534 tcp->rx_win = cqe->lro_tcp_win;
1536 if (cqe->lro_tcppsh_abort_dupack & MLX5_CQE_LRO_PUSH_MASK)
1537 tcp->tcp_flags |= RTE_TCP_PSH_FLAG;
1539 csum += rte_raw_cksum(tcp, (tcp->data_off >> 4) * 4);
1540 csum = ((csum & 0xffff0000) >> 16) + (csum & 0xffff);
1541 csum = (~csum) & 0xffff;
1548 * Update LRO packet headers.
1549 * The HW LRO feature doesn't update the L3/TCP headers after coalescing the
1550 * TCP segments but supply information in CQE to fill it by SW.
1553 * The packet address.
1555 * Pointer to the completion entry..
1557 * The packet length.
1560 mlx5_lro_update_hdr(uint8_t *__rte_restrict padd,
1561 volatile struct mlx5_cqe *__rte_restrict cqe,
1562 volatile struct mlx5_mini_cqe8 *mcqe,
1563 struct mlx5_rxq_data *rxq, uint32_t len)
1566 struct rte_ether_hdr *eth;
1567 struct rte_vlan_hdr *vlan;
1568 struct rte_ipv4_hdr *ipv4;
1569 struct rte_ipv6_hdr *ipv6;
1570 struct rte_tcp_hdr *tcp;
1575 uint16_t proto = h.eth->ether_type;
1580 while (proto == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
1581 proto == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
1582 proto = h.vlan->eth_proto;
1585 if (proto == RTE_BE16(RTE_ETHER_TYPE_IPV4)) {
1586 h.ipv4->time_to_live = cqe->lro_min_ttl;
1587 h.ipv4->total_length = rte_cpu_to_be_16(len - (h.hdr - padd));
1588 h.ipv4->hdr_checksum = 0;
1589 h.ipv4->hdr_checksum = rte_ipv4_cksum(h.ipv4);
1590 phcsum = rte_ipv4_phdr_cksum(h.ipv4, 0);
1593 h.ipv6->hop_limits = cqe->lro_min_ttl;
1594 h.ipv6->payload_len = rte_cpu_to_be_16(len - (h.hdr - padd) -
1596 phcsum = rte_ipv6_phdr_cksum(h.ipv6, 0);
1600 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_L34H_STRIDX)
1601 l4_type = (rte_be_to_cpu_16(cqe->hdr_type_etc) &
1602 MLX5_CQE_L4_TYPE_MASK) >> MLX5_CQE_L4_TYPE_SHIFT;
1604 l4_type = (rte_be_to_cpu_16(mcqe->hdr_type) &
1605 MLX5_CQE_L4_TYPE_MASK) >> MLX5_CQE_L4_TYPE_SHIFT;
1606 mlx5_lro_update_tcp_hdr(h.tcp, cqe, phcsum, l4_type);
1610 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
1612 struct mlx5_mprq_buf *buf = opaque;
1614 if (__atomic_load_n(&buf->refcnt, __ATOMIC_RELAXED) == 1) {
1615 rte_mempool_put(buf->mp, buf);
1616 } else if (unlikely(__atomic_sub_fetch(&buf->refcnt, 1,
1617 __ATOMIC_RELAXED) == 0)) {
1618 __atomic_store_n(&buf->refcnt, 1, __ATOMIC_RELAXED);
1619 rte_mempool_put(buf->mp, buf);
1624 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
1626 mlx5_mprq_buf_free_cb(NULL, buf);
1630 * DPDK callback for RX with Multi-Packet RQ support.
1633 * Generic pointer to RX queue structure.
1635 * Array to store received packets.
1637 * Maximum number of packets in array.
1640 * Number of packets successfully received (<= pkts_n).
1643 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1645 struct mlx5_rxq_data *rxq = dpdk_rxq;
1646 const uint32_t strd_n = 1 << rxq->strd_num_n;
1647 const uint32_t strd_sz = 1 << rxq->strd_sz_n;
1648 const uint32_t cq_mask = (1 << rxq->cqe_n) - 1;
1649 const uint32_t wq_mask = (1 << rxq->elts_n) - 1;
1650 volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1652 uint32_t rq_ci = rxq->rq_ci;
1653 uint16_t consumed_strd = rxq->consumed_strd;
1654 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1656 while (i < pkts_n) {
1657 struct rte_mbuf *pkt;
1663 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1664 enum mlx5_rqx_code rxq_code;
1666 if (consumed_strd == strd_n) {
1667 /* Replace WQE if the buffer is still in use. */
1668 mprq_buf_replace(rxq, rq_ci & wq_mask);
1669 /* Advance to the next WQE. */
1672 buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1674 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1675 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
1679 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
1680 MLX5_ASSERT((int)len >= (rxq->crc_present << 2));
1681 if (rxq->crc_present)
1682 len -= RTE_ETHER_CRC_LEN;
1684 rxq->mcqe_format == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX)
1685 strd_cnt = (len / strd_sz) + !!(len % strd_sz);
1687 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
1688 MLX5_MPRQ_STRIDE_NUM_SHIFT;
1689 MLX5_ASSERT(strd_cnt);
1690 consumed_strd += strd_cnt;
1691 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
1693 strd_idx = rte_be_to_cpu_16(mcqe == NULL ?
1696 MLX5_ASSERT(strd_idx < strd_n);
1697 MLX5_ASSERT(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) &
1699 pkt = rte_pktmbuf_alloc(rxq->mp);
1700 if (unlikely(pkt == NULL)) {
1701 ++rxq->stats.rx_nombuf;
1704 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
1705 MLX5_ASSERT((int)len >= (rxq->crc_present << 2));
1706 if (rxq->crc_present)
1707 len -= RTE_ETHER_CRC_LEN;
1708 rxq_code = mprq_buf_to_pkt(rxq, pkt, len, buf,
1709 strd_idx, strd_cnt);
1710 if (unlikely(rxq_code != MLX5_RXQ_CODE_EXIT)) {
1711 rte_pktmbuf_free_seg(pkt);
1712 if (rxq_code == MLX5_RXQ_CODE_DROPPED) {
1713 ++rxq->stats.idropped;
1716 if (rxq_code == MLX5_RXQ_CODE_NOMBUF) {
1717 ++rxq->stats.rx_nombuf;
1721 rxq_cq_to_mbuf(rxq, pkt, cqe, mcqe);
1722 if (cqe->lro_num_seg > 1) {
1723 mlx5_lro_update_hdr(rte_pktmbuf_mtod(pkt, uint8_t *),
1724 cqe, mcqe, rxq, len);
1725 pkt->ol_flags |= PKT_RX_LRO;
1726 pkt->tso_segsz = len / cqe->lro_num_seg;
1729 PORT(pkt) = rxq->port_id;
1730 #ifdef MLX5_PMD_SOFT_COUNTERS
1731 /* Increment bytes counter. */
1732 rxq->stats.ibytes += PKT_LEN(pkt);
1734 /* Return packet. */
1738 /* Update the consumer indexes. */
1739 rxq->consumed_strd = consumed_strd;
1741 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1742 if (rq_ci != rxq->rq_ci) {
1745 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1747 #ifdef MLX5_PMD_SOFT_COUNTERS
1748 /* Increment packets counter. */
1749 rxq->stats.ipackets += i;
1755 * Dummy DPDK callback for TX.
1757 * This function is used to temporarily replace the real callback during
1758 * unsafe control operations on the queue, or in case of error.
1761 * Generic pointer to TX queue structure.
1763 * Packets to transmit.
1765 * Number of packets in array.
1768 * Number of packets successfully transmitted (<= pkts_n).
1771 removed_tx_burst(void *dpdk_txq __rte_unused,
1772 struct rte_mbuf **pkts __rte_unused,
1773 uint16_t pkts_n __rte_unused)
1780 * Dummy DPDK callback for RX.
1782 * This function is used to temporarily replace the real callback during
1783 * unsafe control operations on the queue, or in case of error.
1786 * Generic pointer to RX queue structure.
1788 * Array to store received packets.
1790 * Maximum number of packets in array.
1793 * Number of packets successfully received (<= pkts_n).
1796 removed_rx_burst(void *dpdk_txq __rte_unused,
1797 struct rte_mbuf **pkts __rte_unused,
1798 uint16_t pkts_n __rte_unused)
1805 * Vectorized Rx/Tx routines are not compiled in when required vector
1806 * instructions are not supported on a target architecture. The following null
1807 * stubs are needed for linkage when those are not included outside of this file
1808 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1812 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
1813 struct rte_mbuf **pkts __rte_unused,
1814 uint16_t pkts_n __rte_unused)
1820 mlx5_rx_burst_mprq_vec(void *dpdk_txq __rte_unused,
1821 struct rte_mbuf **pkts __rte_unused,
1822 uint16_t pkts_n __rte_unused)
1828 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
1834 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
1840 * Free the mbufs from the linear array of pointers.
1843 * Pointer to array of packets to be free.
1845 * Number of packets to be freed.
1847 * Configured Tx offloads mask. It is fully defined at
1848 * compile time and may be used for optimization.
1850 static __rte_always_inline void
1851 mlx5_tx_free_mbuf(struct rte_mbuf **__rte_restrict pkts,
1852 unsigned int pkts_n,
1853 unsigned int olx __rte_unused)
1855 struct rte_mempool *pool = NULL;
1856 struct rte_mbuf **p_free = NULL;
1857 struct rte_mbuf *mbuf;
1858 unsigned int n_free = 0;
1861 * The implemented algorithm eliminates
1862 * copying pointers to temporary array
1863 * for rte_mempool_put_bulk() calls.
1866 MLX5_ASSERT(pkts_n);
1870 * Decrement mbuf reference counter, detach
1871 * indirect and external buffers if needed.
1873 mbuf = rte_pktmbuf_prefree_seg(*pkts);
1874 if (likely(mbuf != NULL)) {
1875 MLX5_ASSERT(mbuf == *pkts);
1876 if (likely(n_free != 0)) {
1877 if (unlikely(pool != mbuf->pool))
1878 /* From different pool. */
1881 /* Start new scan array. */
1888 if (unlikely(pkts_n == 0)) {
1894 * This happens if mbuf is still referenced.
1895 * We can't put it back to the pool, skip.
1899 if (unlikely(n_free != 0))
1900 /* There is some array to free.*/
1902 if (unlikely(pkts_n == 0))
1903 /* Last mbuf, nothing to free. */
1909 * This loop is implemented to avoid multiple
1910 * inlining of rte_mempool_put_bulk().
1913 MLX5_ASSERT(p_free);
1914 MLX5_ASSERT(n_free);
1916 * Free the array of pre-freed mbufs
1917 * belonging to the same memory pool.
1919 rte_mempool_put_bulk(pool, (void *)p_free, n_free);
1920 if (unlikely(mbuf != NULL)) {
1921 /* There is the request to start new scan. */
1926 if (likely(pkts_n != 0))
1929 * This is the last mbuf to be freed.
1930 * Do one more loop iteration to complete.
1931 * This is rare case of the last unique mbuf.
1936 if (likely(pkts_n == 0))
1945 * Free the mbuf from the elts ring buffer till new tail.
1948 * Pointer to Tx queue structure.
1950 * Index in elts to free up to, becomes new elts tail.
1952 * Configured Tx offloads mask. It is fully defined at
1953 * compile time and may be used for optimization.
1955 static __rte_always_inline void
1956 mlx5_tx_free_elts(struct mlx5_txq_data *__rte_restrict txq,
1958 unsigned int olx __rte_unused)
1960 uint16_t n_elts = tail - txq->elts_tail;
1962 MLX5_ASSERT(n_elts);
1963 MLX5_ASSERT(n_elts <= txq->elts_s);
1965 * Implement a loop to support ring buffer wraparound
1966 * with single inlining of mlx5_tx_free_mbuf().
1971 part = txq->elts_s - (txq->elts_tail & txq->elts_m);
1972 part = RTE_MIN(part, n_elts);
1974 MLX5_ASSERT(part <= txq->elts_s);
1975 mlx5_tx_free_mbuf(&txq->elts[txq->elts_tail & txq->elts_m],
1977 txq->elts_tail += part;
1983 * Store the mbuf being sent into elts ring buffer.
1984 * On Tx completion these mbufs will be freed.
1987 * Pointer to Tx queue structure.
1989 * Pointer to array of packets to be stored.
1991 * Number of packets to be stored.
1993 * Configured Tx offloads mask. It is fully defined at
1994 * compile time and may be used for optimization.
1996 static __rte_always_inline void
1997 mlx5_tx_copy_elts(struct mlx5_txq_data *__rte_restrict txq,
1998 struct rte_mbuf **__rte_restrict pkts,
1999 unsigned int pkts_n,
2000 unsigned int olx __rte_unused)
2003 struct rte_mbuf **elts = (struct rte_mbuf **)txq->elts;
2006 MLX5_ASSERT(pkts_n);
2007 part = txq->elts_s - (txq->elts_head & txq->elts_m);
2009 MLX5_ASSERT(part <= txq->elts_s);
2010 /* This code is a good candidate for vectorizing with SIMD. */
2011 rte_memcpy((void *)(elts + (txq->elts_head & txq->elts_m)),
2013 RTE_MIN(part, pkts_n) * sizeof(struct rte_mbuf *));
2014 txq->elts_head += pkts_n;
2015 if (unlikely(part < pkts_n))
2016 /* The copy is wrapping around the elts array. */
2017 rte_memcpy((void *)elts, (void *)(pkts + part),
2018 (pkts_n - part) * sizeof(struct rte_mbuf *));
2022 * Update completion queue consuming index via doorbell
2023 * and flush the completed data buffers.
2026 * Pointer to TX queue structure.
2027 * @param valid CQE pointer
2028 * if not NULL update txq->wqe_pi and flush the buffers
2030 * Configured Tx offloads mask. It is fully defined at
2031 * compile time and may be used for optimization.
2033 static __rte_always_inline void
2034 mlx5_tx_comp_flush(struct mlx5_txq_data *__rte_restrict txq,
2035 volatile struct mlx5_cqe *last_cqe,
2036 unsigned int olx __rte_unused)
2038 if (likely(last_cqe != NULL)) {
2041 txq->wqe_pi = rte_be_to_cpu_16(last_cqe->wqe_counter);
2042 tail = txq->fcqs[(txq->cq_ci - 1) & txq->cqe_m];
2043 if (likely(tail != txq->elts_tail)) {
2044 mlx5_tx_free_elts(txq, tail, olx);
2045 MLX5_ASSERT(tail == txq->elts_tail);
2051 * Manage TX completions. This routine checks the CQ for
2052 * arrived CQEs, deduces the last accomplished WQE in SQ,
2053 * updates SQ producing index and frees all completed mbufs.
2056 * Pointer to TX queue structure.
2058 * Configured Tx offloads mask. It is fully defined at
2059 * compile time and may be used for optimization.
2061 * NOTE: not inlined intentionally, it makes tx_burst
2062 * routine smaller, simple and faster - from experiments.
2065 mlx5_tx_handle_completion(struct mlx5_txq_data *__rte_restrict txq,
2066 unsigned int olx __rte_unused)
2068 unsigned int count = MLX5_TX_COMP_MAX_CQE;
2069 volatile struct mlx5_cqe *last_cqe = NULL;
2070 bool ring_doorbell = false;
2073 static_assert(MLX5_CQE_STATUS_HW_OWN < 0, "Must be negative value");
2074 static_assert(MLX5_CQE_STATUS_SW_OWN < 0, "Must be negative value");
2076 volatile struct mlx5_cqe *cqe;
2078 cqe = &txq->cqes[txq->cq_ci & txq->cqe_m];
2079 ret = check_cqe(cqe, txq->cqe_s, txq->cq_ci);
2080 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
2081 if (likely(ret != MLX5_CQE_STATUS_ERR)) {
2082 /* No new CQEs in completion queue. */
2083 MLX5_ASSERT(ret == MLX5_CQE_STATUS_HW_OWN);
2087 * Some error occurred, try to restart.
2088 * We have no barrier after WQE related Doorbell
2089 * written, make sure all writes are completed
2090 * here, before we might perform SQ reset.
2093 ret = mlx5_tx_error_cqe_handle
2094 (txq, (volatile struct mlx5_err_cqe *)cqe);
2095 if (unlikely(ret < 0)) {
2097 * Some error occurred on queue error
2098 * handling, we do not advance the index
2099 * here, allowing to retry on next call.
2104 * We are going to fetch all entries with
2105 * MLX5_CQE_SYNDROME_WR_FLUSH_ERR status.
2106 * The send queue is supposed to be empty.
2108 ring_doorbell = true;
2110 txq->cq_pi = txq->cq_ci;
2114 /* Normal transmit completion. */
2115 MLX5_ASSERT(txq->cq_ci != txq->cq_pi);
2116 MLX5_ASSERT((txq->fcqs[txq->cq_ci & txq->cqe_m] >> 16) ==
2118 ring_doorbell = true;
2122 * We have to restrict the amount of processed CQEs
2123 * in one tx_burst routine call. The CQ may be large
2124 * and many CQEs may be updated by the NIC in one
2125 * transaction. Buffers freeing is time consuming,
2126 * multiple iterations may introduce significant
2129 if (likely(--count == 0))
2132 if (likely(ring_doorbell)) {
2133 /* Ring doorbell to notify hardware. */
2134 rte_compiler_barrier();
2135 *txq->cq_db = rte_cpu_to_be_32(txq->cq_ci);
2136 mlx5_tx_comp_flush(txq, last_cqe, olx);
2141 * Check if the completion request flag should be set in the last WQE.
2142 * Both pushed mbufs and WQEs are monitored and the completion request
2143 * flag is set if any of thresholds is reached.
2146 * Pointer to TX queue structure.
2148 * Pointer to burst routine local context.
2150 * Configured Tx offloads mask. It is fully defined at
2151 * compile time and may be used for optimization.
2153 static __rte_always_inline void
2154 mlx5_tx_request_completion(struct mlx5_txq_data *__rte_restrict txq,
2155 struct mlx5_txq_local *__rte_restrict loc,
2158 uint16_t head = txq->elts_head;
2161 part = MLX5_TXOFF_CONFIG(INLINE) ?
2162 0 : loc->pkts_sent - loc->pkts_copy;
2164 if ((uint16_t)(head - txq->elts_comp) >= MLX5_TX_COMP_THRESH ||
2165 (MLX5_TXOFF_CONFIG(INLINE) &&
2166 (uint16_t)(txq->wqe_ci - txq->wqe_comp) >= txq->wqe_thres)) {
2167 volatile struct mlx5_wqe *last = loc->wqe_last;
2170 txq->elts_comp = head;
2171 if (MLX5_TXOFF_CONFIG(INLINE))
2172 txq->wqe_comp = txq->wqe_ci;
2173 /* Request unconditional completion on last WQE. */
2174 last->cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
2175 MLX5_COMP_MODE_OFFSET);
2176 /* Save elts_head in dedicated free on completion queue. */
2177 #ifdef RTE_LIBRTE_MLX5_DEBUG
2178 txq->fcqs[txq->cq_pi++ & txq->cqe_m] = head |
2179 (last->cseg.opcode >> 8) << 16;
2181 txq->fcqs[txq->cq_pi++ & txq->cqe_m] = head;
2183 /* A CQE slot must always be available. */
2184 MLX5_ASSERT((txq->cq_pi - txq->cq_ci) <= txq->cqe_s);
2189 * DPDK callback to check the status of a tx descriptor.
2194 * The index of the descriptor in the ring.
2197 * The status of the tx descriptor.
2200 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
2202 struct mlx5_txq_data *__rte_restrict txq = tx_queue;
2205 mlx5_tx_handle_completion(txq, 0);
2206 used = txq->elts_head - txq->elts_tail;
2208 return RTE_ETH_TX_DESC_FULL;
2209 return RTE_ETH_TX_DESC_DONE;
2213 * Build the Control Segment with specified opcode:
2214 * - MLX5_OPCODE_SEND
2215 * - MLX5_OPCODE_ENHANCED_MPSW
2219 * Pointer to TX queue structure.
2221 * Pointer to burst routine local context.
2223 * Pointer to WQE to fill with built Control Segment.
2225 * Supposed length of WQE in segments.
2227 * SQ WQE opcode to put into Control Segment.
2229 * Configured Tx offloads mask. It is fully defined at
2230 * compile time and may be used for optimization.
2232 static __rte_always_inline void
2233 mlx5_tx_cseg_init(struct mlx5_txq_data *__rte_restrict txq,
2234 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
2235 struct mlx5_wqe *__rte_restrict wqe,
2237 unsigned int opcode,
2238 unsigned int olx __rte_unused)
2240 struct mlx5_wqe_cseg *__rte_restrict cs = &wqe->cseg;
2242 /* For legacy MPW replace the EMPW by TSO with modifier. */
2243 if (MLX5_TXOFF_CONFIG(MPW) && opcode == MLX5_OPCODE_ENHANCED_MPSW)
2244 opcode = MLX5_OPCODE_TSO | MLX5_OPC_MOD_MPW << 24;
2245 cs->opcode = rte_cpu_to_be_32((txq->wqe_ci << 8) | opcode);
2246 cs->sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
2247 cs->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
2248 MLX5_COMP_MODE_OFFSET);
2249 cs->misc = RTE_BE32(0);
2253 * Build the Synchronize Queue Segment with specified completion index.
2256 * Pointer to TX queue structure.
2258 * Pointer to burst routine local context.
2260 * Pointer to WQE to fill with built Control Segment.
2262 * Completion index in Clock Queue to wait.
2264 * Configured Tx offloads mask. It is fully defined at
2265 * compile time and may be used for optimization.
2267 static __rte_always_inline void
2268 mlx5_tx_wseg_init(struct mlx5_txq_data *restrict txq,
2269 struct mlx5_txq_local *restrict loc __rte_unused,
2270 struct mlx5_wqe *restrict wqe,
2272 unsigned int olx __rte_unused)
2274 struct mlx5_wqe_qseg *qs;
2276 qs = RTE_PTR_ADD(wqe, MLX5_WSEG_SIZE);
2277 qs->max_index = rte_cpu_to_be_32(wci);
2278 qs->qpn_cqn = rte_cpu_to_be_32(txq->sh->txpp.clock_queue.cq->id);
2279 qs->reserved0 = RTE_BE32(0);
2280 qs->reserved1 = RTE_BE32(0);
2284 * Build the Ethernet Segment without inlined data.
2285 * Supports Software Parser, Checksums and VLAN
2286 * insertion Tx offload features.
2289 * Pointer to TX queue structure.
2291 * Pointer to burst routine local context.
2293 * Pointer to WQE to fill with built Ethernet Segment.
2295 * Configured Tx offloads mask. It is fully defined at
2296 * compile time and may be used for optimization.
2298 static __rte_always_inline void
2299 mlx5_tx_eseg_none(struct mlx5_txq_data *__rte_restrict txq __rte_unused,
2300 struct mlx5_txq_local *__rte_restrict loc,
2301 struct mlx5_wqe *__rte_restrict wqe,
2304 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2308 * Calculate and set check sum flags first, dword field
2309 * in segment may be shared with Software Parser flags.
2311 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2312 es->flags = rte_cpu_to_le_32(csum);
2314 * Calculate and set Software Parser offsets and flags.
2315 * These flags a set for custom UDP and IP tunnel packets.
2317 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2318 /* Fill metadata field if needed. */
2319 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2320 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2321 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2322 /* Engage VLAN tag insertion feature if requested. */
2323 if (MLX5_TXOFF_CONFIG(VLAN) &&
2324 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
2326 * We should get here only if device support
2327 * this feature correctly.
2329 MLX5_ASSERT(txq->vlan_en);
2330 es->inline_hdr = rte_cpu_to_be_32(MLX5_ETH_WQE_VLAN_INSERT |
2331 loc->mbuf->vlan_tci);
2333 es->inline_hdr = RTE_BE32(0);
2338 * Build the Ethernet Segment with minimal inlined data
2339 * of MLX5_ESEG_MIN_INLINE_SIZE bytes length. This is
2340 * used to fill the gap in single WQEBB WQEs.
2341 * Supports Software Parser, Checksums and VLAN
2342 * insertion Tx offload features.
2345 * Pointer to TX queue structure.
2347 * Pointer to burst routine local context.
2349 * Pointer to WQE to fill with built Ethernet Segment.
2351 * Length of VLAN tag insertion if any.
2353 * Configured Tx offloads mask. It is fully defined at
2354 * compile time and may be used for optimization.
2356 static __rte_always_inline void
2357 mlx5_tx_eseg_dmin(struct mlx5_txq_data *__rte_restrict txq __rte_unused,
2358 struct mlx5_txq_local *__rte_restrict loc,
2359 struct mlx5_wqe *__rte_restrict wqe,
2363 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2365 uint8_t *psrc, *pdst;
2368 * Calculate and set check sum flags first, dword field
2369 * in segment may be shared with Software Parser flags.
2371 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2372 es->flags = rte_cpu_to_le_32(csum);
2374 * Calculate and set Software Parser offsets and flags.
2375 * These flags a set for custom UDP and IP tunnel packets.
2377 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2378 /* Fill metadata field if needed. */
2379 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2380 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2381 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2382 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2384 sizeof(rte_v128u32_t)),
2385 "invalid Ethernet Segment data size");
2386 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2388 sizeof(struct rte_vlan_hdr) +
2389 2 * RTE_ETHER_ADDR_LEN),
2390 "invalid Ethernet Segment data size");
2391 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2392 es->inline_hdr_sz = RTE_BE16(MLX5_ESEG_MIN_INLINE_SIZE);
2393 es->inline_data = *(unaligned_uint16_t *)psrc;
2394 psrc += sizeof(uint16_t);
2395 pdst = (uint8_t *)(es + 1);
2396 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2397 /* Implement VLAN tag insertion as part inline data. */
2398 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2399 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2400 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2401 /* Insert VLAN ethertype + VLAN tag. */
2402 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2403 ((RTE_ETHER_TYPE_VLAN << 16) |
2404 loc->mbuf->vlan_tci);
2405 pdst += sizeof(struct rte_vlan_hdr);
2406 /* Copy the rest two bytes from packet data. */
2407 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2408 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2410 /* Fill the gap in the title WQEBB with inline data. */
2411 rte_mov16(pdst, psrc);
2416 * Build the Ethernet Segment with entire packet
2417 * data inlining. Checks the boundary of WQEBB and
2418 * ring buffer wrapping, supports Software Parser,
2419 * Checksums and VLAN insertion Tx offload features.
2422 * Pointer to TX queue structure.
2424 * Pointer to burst routine local context.
2426 * Pointer to WQE to fill with built Ethernet Segment.
2428 * Length of VLAN tag insertion if any.
2430 * Length of data to inline (VLAN included, if any).
2432 * TSO flag, set mss field from the packet.
2434 * Configured Tx offloads mask. It is fully defined at
2435 * compile time and may be used for optimization.
2438 * Pointer to the next Data Segment (aligned and wrapped around).
2440 static __rte_always_inline struct mlx5_wqe_dseg *
2441 mlx5_tx_eseg_data(struct mlx5_txq_data *__rte_restrict txq,
2442 struct mlx5_txq_local *__rte_restrict loc,
2443 struct mlx5_wqe *__rte_restrict wqe,
2449 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2451 uint8_t *psrc, *pdst;
2455 * Calculate and set check sum flags first, dword field
2456 * in segment may be shared with Software Parser flags.
2458 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2461 csum |= loc->mbuf->tso_segsz;
2462 es->flags = rte_cpu_to_be_32(csum);
2464 es->flags = rte_cpu_to_le_32(csum);
2467 * Calculate and set Software Parser offsets and flags.
2468 * These flags a set for custom UDP and IP tunnel packets.
2470 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2471 /* Fill metadata field if needed. */
2472 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2473 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2474 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2475 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2477 sizeof(rte_v128u32_t)),
2478 "invalid Ethernet Segment data size");
2479 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2481 sizeof(struct rte_vlan_hdr) +
2482 2 * RTE_ETHER_ADDR_LEN),
2483 "invalid Ethernet Segment data size");
2484 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2485 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2486 es->inline_data = *(unaligned_uint16_t *)psrc;
2487 psrc += sizeof(uint16_t);
2488 pdst = (uint8_t *)(es + 1);
2489 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2490 /* Implement VLAN tag insertion as part inline data. */
2491 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2492 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2493 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2494 /* Insert VLAN ethertype + VLAN tag. */
2495 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2496 ((RTE_ETHER_TYPE_VLAN << 16) |
2497 loc->mbuf->vlan_tci);
2498 pdst += sizeof(struct rte_vlan_hdr);
2499 /* Copy the rest two bytes from packet data. */
2500 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2501 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2502 psrc += sizeof(uint16_t);
2504 /* Fill the gap in the title WQEBB with inline data. */
2505 rte_mov16(pdst, psrc);
2506 psrc += sizeof(rte_v128u32_t);
2508 pdst = (uint8_t *)(es + 2);
2509 MLX5_ASSERT(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2510 MLX5_ASSERT(pdst < (uint8_t *)txq->wqes_end);
2511 inlen -= MLX5_ESEG_MIN_INLINE_SIZE;
2513 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2514 return (struct mlx5_wqe_dseg *)pdst;
2517 * The WQEBB space availability is checked by caller.
2518 * Here we should be aware of WQE ring buffer wraparound only.
2520 part = (uint8_t *)txq->wqes_end - pdst;
2521 part = RTE_MIN(part, inlen);
2523 rte_memcpy(pdst, psrc, part);
2525 if (likely(!inlen)) {
2527 * If return value is not used by the caller
2528 * the code below will be optimized out.
2531 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2532 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2533 pdst = (uint8_t *)txq->wqes;
2534 return (struct mlx5_wqe_dseg *)pdst;
2536 pdst = (uint8_t *)txq->wqes;
2543 * Copy data from chain of mbuf to the specified linear buffer.
2544 * Checksums and VLAN insertion Tx offload features. If data
2545 * from some mbuf copied completely this mbuf is freed. Local
2546 * structure is used to keep the byte stream state.
2549 * Pointer to the destination linear buffer.
2551 * Pointer to burst routine local context.
2553 * Length of data to be copied.
2555 * Length of data to be copied ignoring no inline hint.
2557 * Configured Tx offloads mask. It is fully defined at
2558 * compile time and may be used for optimization.
2561 * Number of actual copied data bytes. This is always greater than or
2562 * equal to must parameter and might be lesser than len in no inline
2563 * hint flag is encountered.
2565 static __rte_always_inline unsigned int
2566 mlx5_tx_mseg_memcpy(uint8_t *pdst,
2567 struct mlx5_txq_local *__rte_restrict loc,
2570 unsigned int olx __rte_unused)
2572 struct rte_mbuf *mbuf;
2573 unsigned int part, dlen, copy = 0;
2577 MLX5_ASSERT(must <= len);
2579 /* Allow zero length packets, must check first. */
2580 dlen = rte_pktmbuf_data_len(loc->mbuf);
2581 if (dlen <= loc->mbuf_off) {
2582 /* Exhausted packet, just free. */
2584 loc->mbuf = mbuf->next;
2585 rte_pktmbuf_free_seg(mbuf);
2587 MLX5_ASSERT(loc->mbuf_nseg > 1);
2588 MLX5_ASSERT(loc->mbuf);
2590 if (loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE) {
2595 * We already copied the minimal
2596 * requested amount of data.
2601 if (diff <= rte_pktmbuf_data_len(loc->mbuf)) {
2603 * Copy only the minimal required
2604 * part of the data buffer.
2611 dlen -= loc->mbuf_off;
2612 psrc = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2614 part = RTE_MIN(len, dlen);
2615 rte_memcpy(pdst, psrc, part);
2617 loc->mbuf_off += part;
2620 if (loc->mbuf_off >= rte_pktmbuf_data_len(loc->mbuf)) {
2622 /* Exhausted packet, just free. */
2624 loc->mbuf = mbuf->next;
2625 rte_pktmbuf_free_seg(mbuf);
2627 MLX5_ASSERT(loc->mbuf_nseg >= 1);
2637 * Build the Ethernet Segment with inlined data from
2638 * multi-segment packet. Checks the boundary of WQEBB
2639 * and ring buffer wrapping, supports Software Parser,
2640 * Checksums and VLAN insertion Tx offload features.
2643 * Pointer to TX queue structure.
2645 * Pointer to burst routine local context.
2647 * Pointer to WQE to fill with built Ethernet Segment.
2649 * Length of VLAN tag insertion if any.
2651 * Length of data to inline (VLAN included, if any).
2653 * TSO flag, set mss field from the packet.
2655 * Configured Tx offloads mask. It is fully defined at
2656 * compile time and may be used for optimization.
2659 * Pointer to the next Data Segment (aligned and
2660 * possible NOT wrapped around - caller should do
2661 * wrapping check on its own).
2663 static __rte_always_inline struct mlx5_wqe_dseg *
2664 mlx5_tx_eseg_mdat(struct mlx5_txq_data *__rte_restrict txq,
2665 struct mlx5_txq_local *__rte_restrict loc,
2666 struct mlx5_wqe *__rte_restrict wqe,
2672 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2675 unsigned int part, tlen = 0;
2678 * Calculate and set check sum flags first, uint32_t field
2679 * in segment may be shared with Software Parser flags.
2681 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2684 csum |= loc->mbuf->tso_segsz;
2685 es->flags = rte_cpu_to_be_32(csum);
2687 es->flags = rte_cpu_to_le_32(csum);
2690 * Calculate and set Software Parser offsets and flags.
2691 * These flags a set for custom UDP and IP tunnel packets.
2693 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2694 /* Fill metadata field if needed. */
2695 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2696 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2697 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2698 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2700 sizeof(rte_v128u32_t)),
2701 "invalid Ethernet Segment data size");
2702 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2704 sizeof(struct rte_vlan_hdr) +
2705 2 * RTE_ETHER_ADDR_LEN),
2706 "invalid Ethernet Segment data size");
2707 MLX5_ASSERT(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2708 pdst = (uint8_t *)&es->inline_data;
2709 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2710 /* Implement VLAN tag insertion as part inline data. */
2711 mlx5_tx_mseg_memcpy(pdst, loc,
2712 2 * RTE_ETHER_ADDR_LEN,
2713 2 * RTE_ETHER_ADDR_LEN, olx);
2714 pdst += 2 * RTE_ETHER_ADDR_LEN;
2715 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2716 ((RTE_ETHER_TYPE_VLAN << 16) |
2717 loc->mbuf->vlan_tci);
2718 pdst += sizeof(struct rte_vlan_hdr);
2719 tlen += 2 * RTE_ETHER_ADDR_LEN + sizeof(struct rte_vlan_hdr);
2721 MLX5_ASSERT(pdst < (uint8_t *)txq->wqes_end);
2723 * The WQEBB space availability is checked by caller.
2724 * Here we should be aware of WQE ring buffer wraparound only.
2726 part = (uint8_t *)txq->wqes_end - pdst;
2727 part = RTE_MIN(part, inlen - tlen);
2733 * Copying may be interrupted inside the routine
2734 * if run into no inline hint flag.
2736 copy = tlen >= txq->inlen_mode ? 0 : (txq->inlen_mode - tlen);
2737 copy = mlx5_tx_mseg_memcpy(pdst, loc, part, copy, olx);
2739 if (likely(inlen <= tlen) || copy < part) {
2740 es->inline_hdr_sz = rte_cpu_to_be_16(tlen);
2742 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2743 return (struct mlx5_wqe_dseg *)pdst;
2745 pdst = (uint8_t *)txq->wqes;
2746 part = inlen - tlen;
2751 * Build the Data Segment of pointer type.
2754 * Pointer to TX queue structure.
2756 * Pointer to burst routine local context.
2758 * Pointer to WQE to fill with built Data Segment.
2760 * Data buffer to point.
2762 * Data buffer length.
2764 * Configured Tx offloads mask. It is fully defined at
2765 * compile time and may be used for optimization.
2767 static __rte_always_inline void
2768 mlx5_tx_dseg_ptr(struct mlx5_txq_data *__rte_restrict txq,
2769 struct mlx5_txq_local *__rte_restrict loc,
2770 struct mlx5_wqe_dseg *__rte_restrict dseg,
2773 unsigned int olx __rte_unused)
2777 dseg->bcount = rte_cpu_to_be_32(len);
2778 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2779 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2783 * Build the Data Segment of pointer type or inline
2784 * if data length is less than buffer in minimal
2785 * Data Segment size.
2788 * Pointer to TX queue structure.
2790 * Pointer to burst routine local context.
2792 * Pointer to WQE to fill with built Data Segment.
2794 * Data buffer to point.
2796 * Data buffer length.
2798 * Configured Tx offloads mask. It is fully defined at
2799 * compile time and may be used for optimization.
2801 static __rte_always_inline void
2802 mlx5_tx_dseg_iptr(struct mlx5_txq_data *__rte_restrict txq,
2803 struct mlx5_txq_local *__rte_restrict loc,
2804 struct mlx5_wqe_dseg *__rte_restrict dseg,
2807 unsigned int olx __rte_unused)
2813 if (len > MLX5_DSEG_MIN_INLINE_SIZE) {
2814 dseg->bcount = rte_cpu_to_be_32(len);
2815 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2816 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2820 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2821 /* Unrolled implementation of generic rte_memcpy. */
2822 dst = (uintptr_t)&dseg->inline_data[0];
2823 src = (uintptr_t)buf;
2825 #ifdef RTE_ARCH_STRICT_ALIGN
2826 MLX5_ASSERT(dst == RTE_PTR_ALIGN(dst, sizeof(uint32_t)));
2827 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2828 dst += sizeof(uint32_t);
2829 src += sizeof(uint32_t);
2830 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2831 dst += sizeof(uint32_t);
2832 src += sizeof(uint32_t);
2834 *(uint64_t *)dst = *(unaligned_uint64_t *)src;
2835 dst += sizeof(uint64_t);
2836 src += sizeof(uint64_t);
2840 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2841 dst += sizeof(uint32_t);
2842 src += sizeof(uint32_t);
2845 *(uint16_t *)dst = *(unaligned_uint16_t *)src;
2846 dst += sizeof(uint16_t);
2847 src += sizeof(uint16_t);
2850 *(uint8_t *)dst = *(uint8_t *)src;
2854 * Build the Data Segment of inlined data from single
2855 * segment packet, no VLAN insertion.
2858 * Pointer to TX queue structure.
2860 * Pointer to burst routine local context.
2862 * Pointer to WQE to fill with built Data Segment.
2864 * Data buffer to point.
2866 * Data buffer length.
2868 * Configured Tx offloads mask. It is fully defined at
2869 * compile time and may be used for optimization.
2872 * Pointer to the next Data Segment after inlined data.
2873 * Ring buffer wraparound check is needed. We do not
2874 * do it here because it may not be needed for the
2875 * last packet in the eMPW session.
2877 static __rte_always_inline struct mlx5_wqe_dseg *
2878 mlx5_tx_dseg_empw(struct mlx5_txq_data *__rte_restrict txq,
2879 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
2880 struct mlx5_wqe_dseg *__rte_restrict dseg,
2883 unsigned int olx __rte_unused)
2888 if (!MLX5_TXOFF_CONFIG(MPW)) {
2889 /* Store the descriptor byte counter for eMPW sessions. */
2890 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2891 pdst = &dseg->inline_data[0];
2893 /* The entire legacy MPW session counter is stored on close. */
2894 pdst = (uint8_t *)dseg;
2897 * The WQEBB space availability is checked by caller.
2898 * Here we should be aware of WQE ring buffer wraparound only.
2900 part = (uint8_t *)txq->wqes_end - pdst;
2901 part = RTE_MIN(part, len);
2903 rte_memcpy(pdst, buf, part);
2907 if (!MLX5_TXOFF_CONFIG(MPW))
2908 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2909 /* Note: no final wraparound check here. */
2910 return (struct mlx5_wqe_dseg *)pdst;
2912 pdst = (uint8_t *)txq->wqes;
2919 * Build the Data Segment of inlined data from single
2920 * segment packet with VLAN insertion.
2923 * Pointer to TX queue structure.
2925 * Pointer to burst routine local context.
2927 * Pointer to the dseg fill with built Data Segment.
2929 * Data buffer to point.
2931 * Data buffer length.
2933 * Configured Tx offloads mask. It is fully defined at
2934 * compile time and may be used for optimization.
2937 * Pointer to the next Data Segment after inlined data.
2938 * Ring buffer wraparound check is needed.
2940 static __rte_always_inline struct mlx5_wqe_dseg *
2941 mlx5_tx_dseg_vlan(struct mlx5_txq_data *__rte_restrict txq,
2942 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
2943 struct mlx5_wqe_dseg *__rte_restrict dseg,
2946 unsigned int olx __rte_unused)
2952 MLX5_ASSERT(len > MLX5_ESEG_MIN_INLINE_SIZE);
2953 static_assert(MLX5_DSEG_MIN_INLINE_SIZE ==
2954 (2 * RTE_ETHER_ADDR_LEN),
2955 "invalid Data Segment data size");
2956 if (!MLX5_TXOFF_CONFIG(MPW)) {
2957 /* Store the descriptor byte counter for eMPW sessions. */
2958 dseg->bcount = rte_cpu_to_be_32
2959 ((len + sizeof(struct rte_vlan_hdr)) |
2960 MLX5_ETH_WQE_DATA_INLINE);
2961 pdst = &dseg->inline_data[0];
2963 /* The entire legacy MPW session counter is stored on close. */
2964 pdst = (uint8_t *)dseg;
2966 memcpy(pdst, buf, MLX5_DSEG_MIN_INLINE_SIZE);
2967 buf += MLX5_DSEG_MIN_INLINE_SIZE;
2968 pdst += MLX5_DSEG_MIN_INLINE_SIZE;
2969 len -= MLX5_DSEG_MIN_INLINE_SIZE;
2970 /* Insert VLAN ethertype + VLAN tag. Pointer is aligned. */
2971 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2972 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2973 pdst = (uint8_t *)txq->wqes;
2974 *(uint32_t *)pdst = rte_cpu_to_be_32((RTE_ETHER_TYPE_VLAN << 16) |
2975 loc->mbuf->vlan_tci);
2976 pdst += sizeof(struct rte_vlan_hdr);
2978 * The WQEBB space availability is checked by caller.
2979 * Here we should be aware of WQE ring buffer wraparound only.
2981 part = (uint8_t *)txq->wqes_end - pdst;
2982 part = RTE_MIN(part, len);
2984 rte_memcpy(pdst, buf, part);
2988 if (!MLX5_TXOFF_CONFIG(MPW))
2989 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2990 /* Note: no final wraparound check here. */
2991 return (struct mlx5_wqe_dseg *)pdst;
2993 pdst = (uint8_t *)txq->wqes;
3000 * Build the Ethernet Segment with optionally inlined data with
3001 * VLAN insertion and following Data Segments (if any) from
3002 * multi-segment packet. Used by ordinary send and TSO.
3005 * Pointer to TX queue structure.
3007 * Pointer to burst routine local context.
3009 * Pointer to WQE to fill with built Ethernet/Data Segments.
3011 * Length of VLAN header to insert, 0 means no VLAN insertion.
3013 * Data length to inline. For TSO this parameter specifies
3014 * exact value, for ordinary send routine can be aligned by
3015 * caller to provide better WQE space saving and data buffer
3016 * start address alignment. This length includes VLAN header
3019 * Zero means ordinary send, inlined data can be extended,
3020 * otherwise this is TSO, inlined data length is fixed.
3022 * Configured Tx offloads mask. It is fully defined at
3023 * compile time and may be used for optimization.
3026 * Actual size of built WQE in segments.
3028 static __rte_always_inline unsigned int
3029 mlx5_tx_mseg_build(struct mlx5_txq_data *__rte_restrict txq,
3030 struct mlx5_txq_local *__rte_restrict loc,
3031 struct mlx5_wqe *__rte_restrict wqe,
3035 unsigned int olx __rte_unused)
3037 struct mlx5_wqe_dseg *__rte_restrict dseg;
3040 MLX5_ASSERT((rte_pktmbuf_pkt_len(loc->mbuf) + vlan) >= inlen);
3041 loc->mbuf_nseg = NB_SEGS(loc->mbuf);
3044 dseg = mlx5_tx_eseg_mdat(txq, loc, wqe, vlan, inlen, tso, olx);
3045 if (!loc->mbuf_nseg)
3048 * There are still some mbuf remaining, not inlined.
3049 * The first mbuf may be partially inlined and we
3050 * must process the possible non-zero data offset.
3052 if (loc->mbuf_off) {
3057 * Exhausted packets must be dropped before.
3058 * Non-zero offset means there are some data
3059 * remained in the packet.
3061 MLX5_ASSERT(loc->mbuf_off < rte_pktmbuf_data_len(loc->mbuf));
3062 MLX5_ASSERT(rte_pktmbuf_data_len(loc->mbuf));
3063 dptr = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
3065 dlen = rte_pktmbuf_data_len(loc->mbuf) - loc->mbuf_off;
3067 * Build the pointer/minimal data Data Segment.
3068 * Do ring buffer wrapping check in advance.
3070 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3071 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3072 mlx5_tx_dseg_iptr(txq, loc, dseg, dptr, dlen, olx);
3073 /* Store the mbuf to be freed on completion. */
3074 MLX5_ASSERT(loc->elts_free);
3075 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3078 if (--loc->mbuf_nseg == 0)
3080 loc->mbuf = loc->mbuf->next;
3084 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3085 struct rte_mbuf *mbuf;
3087 /* Zero length segment found, just skip. */
3089 loc->mbuf = loc->mbuf->next;
3090 rte_pktmbuf_free_seg(mbuf);
3091 if (--loc->mbuf_nseg == 0)
3094 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3095 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3098 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3099 rte_pktmbuf_data_len(loc->mbuf), olx);
3100 MLX5_ASSERT(loc->elts_free);
3101 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3104 if (--loc->mbuf_nseg == 0)
3106 loc->mbuf = loc->mbuf->next;
3111 /* Calculate actual segments used from the dseg pointer. */
3112 if ((uintptr_t)wqe < (uintptr_t)dseg)
3113 ds = ((uintptr_t)dseg - (uintptr_t)wqe) / MLX5_WSEG_SIZE;
3115 ds = (((uintptr_t)dseg - (uintptr_t)wqe) +
3116 txq->wqe_s * MLX5_WQE_SIZE) / MLX5_WSEG_SIZE;
3121 * The routine checks timestamp flag in the current packet,
3122 * and push WAIT WQE into the queue if scheduling is required.
3125 * Pointer to TX queue structure.
3127 * Pointer to burst routine local context.
3129 * Configured Tx offloads mask. It is fully defined at
3130 * compile time and may be used for optimization.
3133 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3134 * MLX5_TXCMP_CODE_SINGLE - continue processing with the packet.
3135 * MLX5_TXCMP_CODE_MULTI - the WAIT inserted, continue processing.
3136 * Local context variables partially updated.
3138 static __rte_always_inline enum mlx5_txcmp_code
3139 mlx5_tx_schedule_send(struct mlx5_txq_data *restrict txq,
3140 struct mlx5_txq_local *restrict loc,
3143 if (MLX5_TXOFF_CONFIG(TXPP) &&
3144 loc->mbuf->ol_flags & txq->ts_mask) {
3145 struct mlx5_wqe *wqe;
3150 * Estimate the required space quickly and roughly.
3151 * We would like to ensure the packet can be pushed
3152 * to the queue and we won't get the orphan WAIT WQE.
3154 if (loc->wqe_free <= MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE ||
3155 loc->elts_free < NB_SEGS(loc->mbuf))
3156 return MLX5_TXCMP_CODE_EXIT;
3157 /* Convert the timestamp into completion to wait. */
3158 ts = *RTE_MBUF_DYNFIELD(loc->mbuf, txq->ts_offset, uint64_t *);
3159 wci = mlx5_txpp_convert_tx_ts(txq->sh, ts);
3160 if (unlikely(wci < 0))
3161 return MLX5_TXCMP_CODE_SINGLE;
3162 /* Build the WAIT WQE with specified completion. */
3163 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3164 mlx5_tx_cseg_init(txq, loc, wqe, 2, MLX5_OPCODE_WAIT, olx);
3165 mlx5_tx_wseg_init(txq, loc, wqe, wci, olx);
3168 return MLX5_TXCMP_CODE_MULTI;
3170 return MLX5_TXCMP_CODE_SINGLE;
3174 * Tx one packet function for multi-segment TSO. Supports all
3175 * types of Tx offloads, uses MLX5_OPCODE_TSO to build WQEs,
3176 * sends one packet per WQE.
3178 * This routine is responsible for storing processed mbuf
3179 * into elts ring buffer and update elts_head.
3182 * Pointer to TX queue structure.
3184 * Pointer to burst routine local context.
3186 * Configured Tx offloads mask. It is fully defined at
3187 * compile time and may be used for optimization.
3190 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3191 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3192 * Local context variables partially updated.
3194 static __rte_always_inline enum mlx5_txcmp_code
3195 mlx5_tx_packet_multi_tso(struct mlx5_txq_data *__rte_restrict txq,
3196 struct mlx5_txq_local *__rte_restrict loc,
3199 struct mlx5_wqe *__rte_restrict wqe;
3200 unsigned int ds, dlen, inlen, ntcp, vlan = 0;
3202 if (MLX5_TXOFF_CONFIG(TXPP)) {
3203 enum mlx5_txcmp_code wret;
3205 /* Generate WAIT for scheduling if requested. */
3206 wret = mlx5_tx_schedule_send(txq, loc, olx);
3207 if (wret == MLX5_TXCMP_CODE_EXIT)
3208 return MLX5_TXCMP_CODE_EXIT;
3209 if (wret == MLX5_TXCMP_CODE_ERROR)
3210 return MLX5_TXCMP_CODE_ERROR;
3213 * Calculate data length to be inlined to estimate
3214 * the required space in WQE ring buffer.
3216 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3217 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3218 vlan = sizeof(struct rte_vlan_hdr);
3219 inlen = loc->mbuf->l2_len + vlan +
3220 loc->mbuf->l3_len + loc->mbuf->l4_len;
3221 if (unlikely((!inlen || !loc->mbuf->tso_segsz)))
3222 return MLX5_TXCMP_CODE_ERROR;
3223 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3224 inlen += loc->mbuf->outer_l2_len + loc->mbuf->outer_l3_len;
3225 /* Packet must contain all TSO headers. */
3226 if (unlikely(inlen > MLX5_MAX_TSO_HEADER ||
3227 inlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3228 inlen > (dlen + vlan)))
3229 return MLX5_TXCMP_CODE_ERROR;
3230 MLX5_ASSERT(inlen >= txq->inlen_mode);
3232 * Check whether there are enough free WQEBBs:
3234 * - Ethernet Segment
3235 * - First Segment of inlined Ethernet data
3236 * - ... data continued ...
3237 * - Data Segments of pointer/min inline type
3239 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3240 MLX5_ESEG_MIN_INLINE_SIZE +
3242 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3243 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3244 return MLX5_TXCMP_CODE_EXIT;
3245 /* Check for maximal WQE size. */
3246 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3247 return MLX5_TXCMP_CODE_ERROR;
3248 #ifdef MLX5_PMD_SOFT_COUNTERS
3249 /* Update sent data bytes/packets counters. */
3250 ntcp = (dlen - (inlen - vlan) + loc->mbuf->tso_segsz - 1) /
3251 loc->mbuf->tso_segsz;
3253 * One will be added for mbuf itself
3254 * at the end of the mlx5_tx_burst from
3255 * loc->pkts_sent field.
3258 txq->stats.opackets += ntcp;
3259 txq->stats.obytes += dlen + vlan + ntcp * inlen;
3261 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3262 loc->wqe_last = wqe;
3263 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_TSO, olx);
3264 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 1, olx);
3265 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3266 txq->wqe_ci += (ds + 3) / 4;
3267 loc->wqe_free -= (ds + 3) / 4;
3268 return MLX5_TXCMP_CODE_MULTI;
3272 * Tx one packet function for multi-segment SEND. Supports all
3273 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3274 * sends one packet per WQE, without any data inlining in
3277 * This routine is responsible for storing processed mbuf
3278 * into elts ring buffer and update elts_head.
3281 * Pointer to TX queue structure.
3283 * Pointer to burst routine local context.
3285 * Configured Tx offloads mask. It is fully defined at
3286 * compile time and may be used for optimization.
3289 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3290 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3291 * Local context variables partially updated.
3293 static __rte_always_inline enum mlx5_txcmp_code
3294 mlx5_tx_packet_multi_send(struct mlx5_txq_data *__rte_restrict txq,
3295 struct mlx5_txq_local *__rte_restrict loc,
3298 struct mlx5_wqe_dseg *__rte_restrict dseg;
3299 struct mlx5_wqe *__rte_restrict wqe;
3300 unsigned int ds, nseg;
3302 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3303 if (MLX5_TXOFF_CONFIG(TXPP)) {
3304 enum mlx5_txcmp_code wret;
3306 /* Generate WAIT for scheduling if requested. */
3307 wret = mlx5_tx_schedule_send(txq, loc, olx);
3308 if (wret == MLX5_TXCMP_CODE_EXIT)
3309 return MLX5_TXCMP_CODE_EXIT;
3310 if (wret == MLX5_TXCMP_CODE_ERROR)
3311 return MLX5_TXCMP_CODE_ERROR;
3314 * No inline at all, it means the CPU cycles saving
3315 * is prioritized at configuration, we should not
3316 * copy any packet data to WQE.
3318 nseg = NB_SEGS(loc->mbuf);
3320 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3321 return MLX5_TXCMP_CODE_EXIT;
3322 /* Check for maximal WQE size. */
3323 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3324 return MLX5_TXCMP_CODE_ERROR;
3326 * Some Tx offloads may cause an error if
3327 * packet is not long enough, check against
3328 * assumed minimal length.
3330 if (rte_pktmbuf_pkt_len(loc->mbuf) <= MLX5_ESEG_MIN_INLINE_SIZE)
3331 return MLX5_TXCMP_CODE_ERROR;
3332 #ifdef MLX5_PMD_SOFT_COUNTERS
3333 /* Update sent data bytes counter. */
3334 txq->stats.obytes += rte_pktmbuf_pkt_len(loc->mbuf);
3335 if (MLX5_TXOFF_CONFIG(VLAN) &&
3336 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3337 txq->stats.obytes += sizeof(struct rte_vlan_hdr);
3340 * SEND WQE, one WQEBB:
3341 * - Control Segment, SEND opcode
3342 * - Ethernet Segment, optional VLAN, no inline
3343 * - Data Segments, pointer only type
3345 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3346 loc->wqe_last = wqe;
3347 mlx5_tx_cseg_init(txq, loc, wqe, ds, MLX5_OPCODE_SEND, olx);
3348 mlx5_tx_eseg_none(txq, loc, wqe, olx);
3349 dseg = &wqe->dseg[0];
3351 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3352 struct rte_mbuf *mbuf;
3355 * Zero length segment found, have to
3356 * correct total size of WQE in segments.
3357 * It is supposed to be rare occasion, so
3358 * in normal case (no zero length segments)
3359 * we avoid extra writing to the Control
3363 wqe->cseg.sq_ds -= RTE_BE32(1);
3365 loc->mbuf = mbuf->next;
3366 rte_pktmbuf_free_seg(mbuf);
3372 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3373 rte_pktmbuf_data_len(loc->mbuf), olx);
3374 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3379 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3380 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3381 loc->mbuf = loc->mbuf->next;
3384 txq->wqe_ci += (ds + 3) / 4;
3385 loc->wqe_free -= (ds + 3) / 4;
3386 return MLX5_TXCMP_CODE_MULTI;
3390 * Tx one packet function for multi-segment SEND. Supports all
3391 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3392 * sends one packet per WQE, with data inlining in
3393 * Ethernet Segment and minimal Data Segments.
3395 * This routine is responsible for storing processed mbuf
3396 * into elts ring buffer and update elts_head.
3399 * Pointer to TX queue structure.
3401 * Pointer to burst routine local context.
3403 * Configured Tx offloads mask. It is fully defined at
3404 * compile time and may be used for optimization.
3407 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3408 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3409 * Local context variables partially updated.
3411 static __rte_always_inline enum mlx5_txcmp_code
3412 mlx5_tx_packet_multi_inline(struct mlx5_txq_data *__rte_restrict txq,
3413 struct mlx5_txq_local *__rte_restrict loc,
3416 struct mlx5_wqe *__rte_restrict wqe;
3417 unsigned int ds, inlen, dlen, vlan = 0;
3419 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
3420 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3421 if (MLX5_TXOFF_CONFIG(TXPP)) {
3422 enum mlx5_txcmp_code wret;
3424 /* Generate WAIT for scheduling if requested. */
3425 wret = mlx5_tx_schedule_send(txq, loc, olx);
3426 if (wret == MLX5_TXCMP_CODE_EXIT)
3427 return MLX5_TXCMP_CODE_EXIT;
3428 if (wret == MLX5_TXCMP_CODE_ERROR)
3429 return MLX5_TXCMP_CODE_ERROR;
3432 * First calculate data length to be inlined
3433 * to estimate the required space for WQE.
3435 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3436 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3437 vlan = sizeof(struct rte_vlan_hdr);
3438 inlen = dlen + vlan;
3439 /* Check against minimal length. */
3440 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
3441 return MLX5_TXCMP_CODE_ERROR;
3442 MLX5_ASSERT(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
3443 if (inlen > txq->inlen_send ||
3444 loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE) {
3445 struct rte_mbuf *mbuf;
3450 * Packet length exceeds the allowed inline
3451 * data length, check whether the minimal
3452 * inlining is required.
3454 if (txq->inlen_mode) {
3455 MLX5_ASSERT(txq->inlen_mode >=
3456 MLX5_ESEG_MIN_INLINE_SIZE);
3457 MLX5_ASSERT(txq->inlen_mode <= txq->inlen_send);
3458 inlen = txq->inlen_mode;
3460 if (loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE ||
3461 !vlan || txq->vlan_en) {
3463 * VLAN insertion will be done inside by HW.
3464 * It is not utmost effective - VLAN flag is
3465 * checked twice, but we should proceed the
3466 * inlining length correctly and take into
3467 * account the VLAN header being inserted.
3469 return mlx5_tx_packet_multi_send
3472 inlen = MLX5_ESEG_MIN_INLINE_SIZE;
3475 * Now we know the minimal amount of data is requested
3476 * to inline. Check whether we should inline the buffers
3477 * from the chain beginning to eliminate some mbufs.
3480 nxlen = rte_pktmbuf_data_len(mbuf);
3481 if (unlikely(nxlen <= txq->inlen_send)) {
3482 /* We can inline first mbuf at least. */
3483 if (nxlen < inlen) {
3486 /* Scan mbufs till inlen filled. */
3491 nxlen = rte_pktmbuf_data_len(mbuf);
3493 } while (unlikely(nxlen < inlen));
3494 if (unlikely(nxlen > txq->inlen_send)) {
3495 /* We cannot inline entire mbuf. */
3496 smlen = inlen - smlen;
3497 start = rte_pktmbuf_mtod_offset
3498 (mbuf, uintptr_t, smlen);
3505 /* There should be not end of packet. */
3507 nxlen = inlen + rte_pktmbuf_data_len(mbuf);
3508 } while (unlikely(nxlen < txq->inlen_send));
3510 start = rte_pktmbuf_mtod(mbuf, uintptr_t);
3512 * Check whether we can do inline to align start
3513 * address of data buffer to cacheline.
3516 start = (~start + 1) & (RTE_CACHE_LINE_SIZE - 1);
3517 if (unlikely(start)) {
3519 if (start <= txq->inlen_send)
3524 * Check whether there are enough free WQEBBs:
3526 * - Ethernet Segment
3527 * - First Segment of inlined Ethernet data
3528 * - ... data continued ...
3529 * - Data Segments of pointer/min inline type
3531 * Estimate the number of Data Segments conservatively,
3532 * supposing no any mbufs is being freed during inlining.
3534 MLX5_ASSERT(inlen <= txq->inlen_send);
3535 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3536 MLX5_ESEG_MIN_INLINE_SIZE +
3538 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3539 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3540 return MLX5_TXCMP_CODE_EXIT;
3541 /* Check for maximal WQE size. */
3542 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3543 return MLX5_TXCMP_CODE_ERROR;
3544 #ifdef MLX5_PMD_SOFT_COUNTERS
3545 /* Update sent data bytes/packets counters. */
3546 txq->stats.obytes += dlen + vlan;
3548 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3549 loc->wqe_last = wqe;
3550 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_SEND, olx);
3551 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 0, olx);
3552 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3553 txq->wqe_ci += (ds + 3) / 4;
3554 loc->wqe_free -= (ds + 3) / 4;
3555 return MLX5_TXCMP_CODE_MULTI;
3559 * Tx burst function for multi-segment packets. Supports all
3560 * types of Tx offloads, uses MLX5_OPCODE_SEND/TSO to build WQEs,
3561 * sends one packet per WQE. Function stops sending if it
3562 * encounters the single-segment packet.
3564 * This routine is responsible for storing processed mbuf
3565 * into elts ring buffer and update elts_head.
3568 * Pointer to TX queue structure.
3570 * Packets to transmit.
3572 * Number of packets in array.
3574 * Pointer to burst routine local context.
3576 * Configured Tx offloads mask. It is fully defined at
3577 * compile time and may be used for optimization.
3580 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3581 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3582 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3583 * MLX5_TXCMP_CODE_TSO - TSO single-segment packet encountered.
3584 * Local context variables updated.
3586 static __rte_always_inline enum mlx5_txcmp_code
3587 mlx5_tx_burst_mseg(struct mlx5_txq_data *__rte_restrict txq,
3588 struct rte_mbuf **__rte_restrict pkts,
3589 unsigned int pkts_n,
3590 struct mlx5_txq_local *__rte_restrict loc,
3593 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
3594 MLX5_ASSERT(pkts_n > loc->pkts_sent);
3595 pkts += loc->pkts_sent + 1;
3596 pkts_n -= loc->pkts_sent;
3598 enum mlx5_txcmp_code ret;
3600 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3602 * Estimate the number of free elts quickly but
3603 * conservatively. Some segment may be fully inlined
3604 * and freed, ignore this here - precise estimation
3607 if (loc->elts_free < NB_SEGS(loc->mbuf))
3608 return MLX5_TXCMP_CODE_EXIT;
3609 if (MLX5_TXOFF_CONFIG(TSO) &&
3610 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)) {
3611 /* Proceed with multi-segment TSO. */
3612 ret = mlx5_tx_packet_multi_tso(txq, loc, olx);
3613 } else if (MLX5_TXOFF_CONFIG(INLINE)) {
3614 /* Proceed with multi-segment SEND with inlining. */
3615 ret = mlx5_tx_packet_multi_inline(txq, loc, olx);
3617 /* Proceed with multi-segment SEND w/o inlining. */
3618 ret = mlx5_tx_packet_multi_send(txq, loc, olx);
3620 if (ret == MLX5_TXCMP_CODE_EXIT)
3621 return MLX5_TXCMP_CODE_EXIT;
3622 if (ret == MLX5_TXCMP_CODE_ERROR)
3623 return MLX5_TXCMP_CODE_ERROR;
3624 /* WQE is built, go to the next packet. */
3627 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3628 return MLX5_TXCMP_CODE_EXIT;
3629 loc->mbuf = *pkts++;
3631 rte_prefetch0(*pkts);
3632 if (likely(NB_SEGS(loc->mbuf) > 1))
3634 /* Here ends the series of multi-segment packets. */
3635 if (MLX5_TXOFF_CONFIG(TSO) &&
3636 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3637 return MLX5_TXCMP_CODE_TSO;
3638 return MLX5_TXCMP_CODE_SINGLE;
3644 * Tx burst function for single-segment packets with TSO.
3645 * Supports all types of Tx offloads, except multi-packets.
3646 * Uses MLX5_OPCODE_TSO to build WQEs, sends one packet per WQE.
3647 * Function stops sending if it encounters the multi-segment
3648 * packet or packet without TSO requested.
3650 * The routine is responsible for storing processed mbuf
3651 * into elts ring buffer and update elts_head if inline
3652 * offloads is requested due to possible early freeing
3653 * of the inlined mbufs (can not store pkts array in elts
3657 * Pointer to TX queue structure.
3659 * Packets to transmit.
3661 * Number of packets in array.
3663 * Pointer to burst routine local context.
3665 * Configured Tx offloads mask. It is fully defined at
3666 * compile time and may be used for optimization.
3669 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3670 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3671 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3672 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3673 * Local context variables updated.
3675 static __rte_always_inline enum mlx5_txcmp_code
3676 mlx5_tx_burst_tso(struct mlx5_txq_data *__rte_restrict txq,
3677 struct rte_mbuf **__rte_restrict pkts,
3678 unsigned int pkts_n,
3679 struct mlx5_txq_local *__rte_restrict loc,
3682 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
3683 MLX5_ASSERT(pkts_n > loc->pkts_sent);
3684 pkts += loc->pkts_sent + 1;
3685 pkts_n -= loc->pkts_sent;
3687 struct mlx5_wqe_dseg *__rte_restrict dseg;
3688 struct mlx5_wqe *__rte_restrict wqe;
3689 unsigned int ds, dlen, hlen, ntcp, vlan = 0;
3692 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
3693 if (MLX5_TXOFF_CONFIG(TXPP)) {
3694 enum mlx5_txcmp_code wret;
3696 /* Generate WAIT for scheduling if requested. */
3697 wret = mlx5_tx_schedule_send(txq, loc, olx);
3698 if (wret == MLX5_TXCMP_CODE_EXIT)
3699 return MLX5_TXCMP_CODE_EXIT;
3700 if (wret == MLX5_TXCMP_CODE_ERROR)
3701 return MLX5_TXCMP_CODE_ERROR;
3703 dlen = rte_pktmbuf_data_len(loc->mbuf);
3704 if (MLX5_TXOFF_CONFIG(VLAN) &&
3705 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
3706 vlan = sizeof(struct rte_vlan_hdr);
3709 * First calculate the WQE size to check
3710 * whether we have enough space in ring buffer.
3712 hlen = loc->mbuf->l2_len + vlan +
3713 loc->mbuf->l3_len + loc->mbuf->l4_len;
3714 if (unlikely((!hlen || !loc->mbuf->tso_segsz)))
3715 return MLX5_TXCMP_CODE_ERROR;
3716 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3717 hlen += loc->mbuf->outer_l2_len +
3718 loc->mbuf->outer_l3_len;
3719 /* Segment must contain all TSO headers. */
3720 if (unlikely(hlen > MLX5_MAX_TSO_HEADER ||
3721 hlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3722 hlen > (dlen + vlan)))
3723 return MLX5_TXCMP_CODE_ERROR;
3725 * Check whether there are enough free WQEBBs:
3727 * - Ethernet Segment
3728 * - First Segment of inlined Ethernet data
3729 * - ... data continued ...
3730 * - Finishing Data Segment of pointer type
3732 ds = 4 + (hlen - MLX5_ESEG_MIN_INLINE_SIZE +
3733 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3734 if (loc->wqe_free < ((ds + 3) / 4))
3735 return MLX5_TXCMP_CODE_EXIT;
3736 #ifdef MLX5_PMD_SOFT_COUNTERS
3737 /* Update sent data bytes/packets counters. */
3738 ntcp = (dlen + vlan - hlen +
3739 loc->mbuf->tso_segsz - 1) /
3740 loc->mbuf->tso_segsz;
3742 * One will be added for mbuf itself at the end
3743 * of the mlx5_tx_burst from loc->pkts_sent field.
3746 txq->stats.opackets += ntcp;
3747 txq->stats.obytes += dlen + vlan + ntcp * hlen;
3750 * Build the TSO WQE:
3752 * - Ethernet Segment with hlen bytes inlined
3753 * - Data Segment of pointer type
3755 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3756 loc->wqe_last = wqe;
3757 mlx5_tx_cseg_init(txq, loc, wqe, ds,
3758 MLX5_OPCODE_TSO, olx);
3759 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan, hlen, 1, olx);
3760 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) + hlen - vlan;
3761 dlen -= hlen - vlan;
3762 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
3764 * WQE is built, update the loop parameters
3765 * and go to the next packet.
3767 txq->wqe_ci += (ds + 3) / 4;
3768 loc->wqe_free -= (ds + 3) / 4;
3769 if (MLX5_TXOFF_CONFIG(INLINE))
3770 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3774 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3775 return MLX5_TXCMP_CODE_EXIT;
3776 loc->mbuf = *pkts++;
3778 rte_prefetch0(*pkts);
3779 if (MLX5_TXOFF_CONFIG(MULTI) &&
3780 unlikely(NB_SEGS(loc->mbuf) > 1))
3781 return MLX5_TXCMP_CODE_MULTI;
3782 if (likely(!(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)))
3783 return MLX5_TXCMP_CODE_SINGLE;
3784 /* Continue with the next TSO packet. */
3790 * Analyze the packet and select the best method to send.
3793 * Pointer to TX queue structure.
3795 * Pointer to burst routine local context.
3797 * Configured Tx offloads mask. It is fully defined at
3798 * compile time and may be used for optimization.
3800 * The predefined flag whether do complete check for
3801 * multi-segment packets and TSO.
3804 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3805 * MLX5_TXCMP_CODE_TSO - TSO required, use TSO/LSO.
3806 * MLX5_TXCMP_CODE_SINGLE - single-segment packet, use SEND.
3807 * MLX5_TXCMP_CODE_EMPW - single-segment packet, use MPW.
3809 static __rte_always_inline enum mlx5_txcmp_code
3810 mlx5_tx_able_to_empw(struct mlx5_txq_data *__rte_restrict txq,
3811 struct mlx5_txq_local *__rte_restrict loc,
3815 /* Check for multi-segment packet. */
3817 MLX5_TXOFF_CONFIG(MULTI) &&
3818 unlikely(NB_SEGS(loc->mbuf) > 1))
3819 return MLX5_TXCMP_CODE_MULTI;
3820 /* Check for TSO packet. */
3822 MLX5_TXOFF_CONFIG(TSO) &&
3823 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3824 return MLX5_TXCMP_CODE_TSO;
3825 /* Check if eMPW is enabled at all. */
3826 if (!MLX5_TXOFF_CONFIG(EMPW))
3827 return MLX5_TXCMP_CODE_SINGLE;
3828 /* Check if eMPW can be engaged. */
3829 if (MLX5_TXOFF_CONFIG(VLAN) &&
3830 unlikely(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) &&
3831 (!MLX5_TXOFF_CONFIG(INLINE) ||
3832 unlikely((rte_pktmbuf_data_len(loc->mbuf) +
3833 sizeof(struct rte_vlan_hdr)) > txq->inlen_empw))) {
3835 * eMPW does not support VLAN insertion offload,
3836 * we have to inline the entire packet but
3837 * packet is too long for inlining.
3839 return MLX5_TXCMP_CODE_SINGLE;
3841 return MLX5_TXCMP_CODE_EMPW;
3845 * Check the next packet attributes to match with the eMPW batch ones.
3846 * In addition, for legacy MPW the packet length is checked either.
3849 * Pointer to TX queue structure.
3851 * Pointer to Ethernet Segment of eMPW batch.
3853 * Pointer to burst routine local context.
3855 * Length of previous packet in MPW descriptor.
3857 * Configured Tx offloads mask. It is fully defined at
3858 * compile time and may be used for optimization.
3861 * true - packet match with eMPW batch attributes.
3862 * false - no match, eMPW should be restarted.
3864 static __rte_always_inline bool
3865 mlx5_tx_match_empw(struct mlx5_txq_data *__rte_restrict txq,
3866 struct mlx5_wqe_eseg *__rte_restrict es,
3867 struct mlx5_txq_local *__rte_restrict loc,
3871 uint8_t swp_flags = 0;
3873 /* Compare the checksum flags, if any. */
3874 if (MLX5_TXOFF_CONFIG(CSUM) &&
3875 txq_ol_cksum_to_cs(loc->mbuf) != es->cs_flags)
3877 /* Compare the Software Parser offsets and flags. */
3878 if (MLX5_TXOFF_CONFIG(SWP) &&
3879 (es->swp_offs != txq_mbuf_to_swp(loc, &swp_flags, olx) ||
3880 es->swp_flags != swp_flags))
3882 /* Fill metadata field if needed. */
3883 if (MLX5_TXOFF_CONFIG(METADATA) &&
3884 es->metadata != (loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
3885 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0))
3887 /* Legacy MPW can send packets with the same lengt only. */
3888 if (MLX5_TXOFF_CONFIG(MPW) &&
3889 dlen != rte_pktmbuf_data_len(loc->mbuf))
3891 /* There must be no VLAN packets in eMPW loop. */
3892 if (MLX5_TXOFF_CONFIG(VLAN))
3893 MLX5_ASSERT(!(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT));
3894 /* Check if the scheduling is requested. */
3895 if (MLX5_TXOFF_CONFIG(TXPP) &&
3896 loc->mbuf->ol_flags & txq->ts_mask)
3902 * Update send loop variables and WQE for eMPW loop
3903 * without data inlining. Number of Data Segments is
3904 * equal to the number of sent packets.
3907 * Pointer to TX queue structure.
3909 * Pointer to burst routine local context.
3911 * Number of packets/Data Segments/Packets.
3913 * Accumulated statistics, bytes sent
3915 * Configured Tx offloads mask. It is fully defined at
3916 * compile time and may be used for optimization.
3919 * true - packet match with eMPW batch attributes.
3920 * false - no match, eMPW should be restarted.
3922 static __rte_always_inline void
3923 mlx5_tx_sdone_empw(struct mlx5_txq_data *__rte_restrict txq,
3924 struct mlx5_txq_local *__rte_restrict loc,
3927 unsigned int olx __rte_unused)
3929 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
3930 #ifdef MLX5_PMD_SOFT_COUNTERS
3931 /* Update sent data bytes counter. */
3932 txq->stats.obytes += slen;
3936 loc->elts_free -= ds;
3937 loc->pkts_sent += ds;
3939 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3940 txq->wqe_ci += (ds + 3) / 4;
3941 loc->wqe_free -= (ds + 3) / 4;
3945 * Update send loop variables and WQE for eMPW loop
3946 * with data inlining. Gets the size of pushed descriptors
3947 * and data to the WQE.
3950 * Pointer to TX queue structure.
3952 * Pointer to burst routine local context.
3954 * Total size of descriptor/data in bytes.
3956 * Accumulated statistics, data bytes sent.
3958 * The base WQE for the eMPW/MPW descriptor.
3960 * Configured Tx offloads mask. It is fully defined at
3961 * compile time and may be used for optimization.
3964 * true - packet match with eMPW batch attributes.
3965 * false - no match, eMPW should be restarted.
3967 static __rte_always_inline void
3968 mlx5_tx_idone_empw(struct mlx5_txq_data *__rte_restrict txq,
3969 struct mlx5_txq_local *__rte_restrict loc,
3972 struct mlx5_wqe *__rte_restrict wqem,
3973 unsigned int olx __rte_unused)
3975 struct mlx5_wqe_dseg *dseg = &wqem->dseg[0];
3977 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
3978 #ifdef MLX5_PMD_SOFT_COUNTERS
3979 /* Update sent data bytes counter. */
3980 txq->stats.obytes += slen;
3984 if (MLX5_TXOFF_CONFIG(MPW) && dseg->bcount == RTE_BE32(0)) {
3986 * If the legacy MPW session contains the inline packets
3987 * we should set the only inline data segment length
3988 * and align the total length to the segment size.
3990 MLX5_ASSERT(len > sizeof(dseg->bcount));
3991 dseg->bcount = rte_cpu_to_be_32((len - sizeof(dseg->bcount)) |
3992 MLX5_ETH_WQE_DATA_INLINE);
3993 len = (len + MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE + 2;
3996 * The session is not legacy MPW or contains the
3997 * data buffer pointer segments.
3999 MLX5_ASSERT((len % MLX5_WSEG_SIZE) == 0);
4000 len = len / MLX5_WSEG_SIZE + 2;
4002 wqem->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | len);
4003 txq->wqe_ci += (len + 3) / 4;
4004 loc->wqe_free -= (len + 3) / 4;
4005 loc->wqe_last = wqem;
4009 * The set of Tx burst functions for single-segment packets
4010 * without TSO and with Multi-Packet Writing feature support.
4011 * Supports all types of Tx offloads, except multi-packets
4014 * Uses MLX5_OPCODE_EMPW to build WQEs if possible and sends
4015 * as many packet per WQE as it can. If eMPW is not configured
4016 * or packet can not be sent with eMPW (VLAN insertion) the
4017 * ordinary SEND opcode is used and only one packet placed
4020 * Functions stop sending if it encounters the multi-segment
4021 * packet or packet with TSO requested.
4023 * The routines are responsible for storing processed mbuf
4024 * into elts ring buffer and update elts_head if inlining
4025 * offload is requested. Otherwise the copying mbufs to elts
4026 * can be postponed and completed at the end of burst routine.
4029 * Pointer to TX queue structure.
4031 * Packets to transmit.
4033 * Number of packets in array.
4035 * Pointer to burst routine local context.
4037 * Configured Tx offloads mask. It is fully defined at
4038 * compile time and may be used for optimization.
4041 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
4042 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
4043 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
4044 * MLX5_TXCMP_CODE_TSO - TSO packet encountered.
4045 * MLX5_TXCMP_CODE_SINGLE - used inside functions set.
4046 * MLX5_TXCMP_CODE_EMPW - used inside functions set.
4048 * Local context variables updated.
4051 * The routine sends packets with MLX5_OPCODE_EMPW
4052 * without inlining, this is dedicated optimized branch.
4053 * No VLAN insertion is supported.
4055 static __rte_always_inline enum mlx5_txcmp_code
4056 mlx5_tx_burst_empw_simple(struct mlx5_txq_data *__rte_restrict txq,
4057 struct rte_mbuf **__rte_restrict pkts,
4058 unsigned int pkts_n,
4059 struct mlx5_txq_local *__rte_restrict loc,
4063 * Subroutine is the part of mlx5_tx_burst_single()
4064 * and sends single-segment packet with eMPW opcode
4065 * without data inlining.
4067 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
4068 MLX5_ASSERT(MLX5_TXOFF_CONFIG(EMPW));
4069 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4070 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4071 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
4072 pkts += loc->pkts_sent + 1;
4073 pkts_n -= loc->pkts_sent;
4075 struct mlx5_wqe_dseg *__rte_restrict dseg;
4076 struct mlx5_wqe_eseg *__rte_restrict eseg;
4077 enum mlx5_txcmp_code ret;
4078 unsigned int part, loop;
4079 unsigned int slen = 0;
4082 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4083 if (MLX5_TXOFF_CONFIG(TXPP)) {
4084 enum mlx5_txcmp_code wret;
4086 /* Generate WAIT for scheduling if requested. */
4087 wret = mlx5_tx_schedule_send(txq, loc, olx);
4088 if (wret == MLX5_TXCMP_CODE_EXIT)
4089 return MLX5_TXCMP_CODE_EXIT;
4090 if (wret == MLX5_TXCMP_CODE_ERROR)
4091 return MLX5_TXCMP_CODE_ERROR;
4093 part = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
4094 MLX5_MPW_MAX_PACKETS :
4095 MLX5_EMPW_MAX_PACKETS);
4096 if (unlikely(loc->elts_free < part)) {
4097 /* We have no enough elts to save all mbufs. */
4098 if (unlikely(loc->elts_free < MLX5_EMPW_MIN_PACKETS))
4099 return MLX5_TXCMP_CODE_EXIT;
4100 /* But we still able to send at least minimal eMPW. */
4101 part = loc->elts_free;
4103 /* Check whether we have enough WQEs */
4104 if (unlikely(loc->wqe_free < ((2 + part + 3) / 4))) {
4105 if (unlikely(loc->wqe_free <
4106 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
4107 return MLX5_TXCMP_CODE_EXIT;
4108 part = (loc->wqe_free * 4) - 2;
4110 if (likely(part > 1))
4111 rte_prefetch0(*pkts);
4112 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4114 * Build eMPW title WQEBB:
4115 * - Control Segment, eMPW opcode
4116 * - Ethernet Segment, no inline
4118 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, part + 2,
4119 MLX5_OPCODE_ENHANCED_MPSW, olx);
4120 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
4121 olx & ~MLX5_TXOFF_CONFIG_VLAN);
4122 eseg = &loc->wqe_last->eseg;
4123 dseg = &loc->wqe_last->dseg[0];
4125 /* Store the packet length for legacy MPW. */
4126 if (MLX5_TXOFF_CONFIG(MPW))
4127 eseg->mss = rte_cpu_to_be_16
4128 (rte_pktmbuf_data_len(loc->mbuf));
4130 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
4131 #ifdef MLX5_PMD_SOFT_COUNTERS
4132 /* Update sent data bytes counter. */
4137 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4139 if (unlikely(--loop == 0))
4141 loc->mbuf = *pkts++;
4142 if (likely(loop > 1))
4143 rte_prefetch0(*pkts);
4144 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4146 * Unroll the completion code to avoid
4147 * returning variable value - it results in
4148 * unoptimized sequent checking in caller.
4150 if (ret == MLX5_TXCMP_CODE_MULTI) {
4152 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4153 if (unlikely(!loc->elts_free ||
4155 return MLX5_TXCMP_CODE_EXIT;
4156 return MLX5_TXCMP_CODE_MULTI;
4158 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4159 if (ret == MLX5_TXCMP_CODE_TSO) {
4161 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4162 if (unlikely(!loc->elts_free ||
4164 return MLX5_TXCMP_CODE_EXIT;
4165 return MLX5_TXCMP_CODE_TSO;
4167 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4169 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4170 if (unlikely(!loc->elts_free ||
4172 return MLX5_TXCMP_CODE_EXIT;
4173 return MLX5_TXCMP_CODE_SINGLE;
4175 if (ret != MLX5_TXCMP_CODE_EMPW) {
4178 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4179 return MLX5_TXCMP_CODE_ERROR;
4182 * Check whether packet parameters coincide
4183 * within assumed eMPW batch:
4184 * - check sum settings
4186 * - software parser settings
4187 * - packets length (legacy MPW only)
4188 * - scheduling is not required
4190 if (!mlx5_tx_match_empw(txq, eseg, loc, dlen, olx)) {
4193 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4194 if (unlikely(!loc->elts_free ||
4196 return MLX5_TXCMP_CODE_EXIT;
4200 /* Packet attributes match, continue the same eMPW. */
4202 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4203 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4205 /* eMPW is built successfully, update loop parameters. */
4207 MLX5_ASSERT(pkts_n >= part);
4208 #ifdef MLX5_PMD_SOFT_COUNTERS
4209 /* Update sent data bytes counter. */
4210 txq->stats.obytes += slen;
4212 loc->elts_free -= part;
4213 loc->pkts_sent += part;
4214 txq->wqe_ci += (2 + part + 3) / 4;
4215 loc->wqe_free -= (2 + part + 3) / 4;
4217 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4218 return MLX5_TXCMP_CODE_EXIT;
4219 loc->mbuf = *pkts++;
4220 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4221 if (unlikely(ret != MLX5_TXCMP_CODE_EMPW))
4223 /* Continue sending eMPW batches. */
4229 * The routine sends packets with MLX5_OPCODE_EMPW
4230 * with inlining, optionally supports VLAN insertion.
4232 static __rte_always_inline enum mlx5_txcmp_code
4233 mlx5_tx_burst_empw_inline(struct mlx5_txq_data *__rte_restrict txq,
4234 struct rte_mbuf **__rte_restrict pkts,
4235 unsigned int pkts_n,
4236 struct mlx5_txq_local *__rte_restrict loc,
4240 * Subroutine is the part of mlx5_tx_burst_single()
4241 * and sends single-segment packet with eMPW opcode
4242 * with data inlining.
4244 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4245 MLX5_ASSERT(MLX5_TXOFF_CONFIG(EMPW));
4246 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4247 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4248 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
4249 pkts += loc->pkts_sent + 1;
4250 pkts_n -= loc->pkts_sent;
4252 struct mlx5_wqe_dseg *__rte_restrict dseg;
4253 struct mlx5_wqe *__rte_restrict wqem;
4254 enum mlx5_txcmp_code ret;
4255 unsigned int room, part, nlim;
4256 unsigned int slen = 0;
4258 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4259 if (MLX5_TXOFF_CONFIG(TXPP)) {
4260 enum mlx5_txcmp_code wret;
4262 /* Generate WAIT for scheduling if requested. */
4263 wret = mlx5_tx_schedule_send(txq, loc, olx);
4264 if (wret == MLX5_TXCMP_CODE_EXIT)
4265 return MLX5_TXCMP_CODE_EXIT;
4266 if (wret == MLX5_TXCMP_CODE_ERROR)
4267 return MLX5_TXCMP_CODE_ERROR;
4270 * Limits the amount of packets in one WQE
4271 * to improve CQE latency generation.
4273 nlim = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
4274 MLX5_MPW_INLINE_MAX_PACKETS :
4275 MLX5_EMPW_MAX_PACKETS);
4276 /* Check whether we have minimal amount WQEs */
4277 if (unlikely(loc->wqe_free <
4278 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
4279 return MLX5_TXCMP_CODE_EXIT;
4280 if (likely(pkts_n > 1))
4281 rte_prefetch0(*pkts);
4282 wqem = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4284 * Build eMPW title WQEBB:
4285 * - Control Segment, eMPW opcode, zero DS
4286 * - Ethernet Segment, no inline
4288 mlx5_tx_cseg_init(txq, loc, wqem, 0,
4289 MLX5_OPCODE_ENHANCED_MPSW, olx);
4290 mlx5_tx_eseg_none(txq, loc, wqem,
4291 olx & ~MLX5_TXOFF_CONFIG_VLAN);
4292 dseg = &wqem->dseg[0];
4293 /* Store the packet length for legacy MPW. */
4294 if (MLX5_TXOFF_CONFIG(MPW))
4295 wqem->eseg.mss = rte_cpu_to_be_16
4296 (rte_pktmbuf_data_len(loc->mbuf));
4297 room = RTE_MIN(MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE,
4298 loc->wqe_free) * MLX5_WQE_SIZE -
4299 MLX5_WQE_CSEG_SIZE -
4301 /* Limit the room for legacy MPW sessions for performance. */
4302 if (MLX5_TXOFF_CONFIG(MPW))
4303 room = RTE_MIN(room,
4304 RTE_MAX(txq->inlen_empw +
4305 sizeof(dseg->bcount) +
4306 (MLX5_TXOFF_CONFIG(VLAN) ?
4307 sizeof(struct rte_vlan_hdr) : 0),
4308 MLX5_MPW_INLINE_MAX_PACKETS *
4309 MLX5_WQE_DSEG_SIZE));
4310 /* Build WQE till we have space, packets and resources. */
4313 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
4314 uint8_t *dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
4317 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE);
4318 MLX5_ASSERT((room % MLX5_WQE_DSEG_SIZE) == 0);
4319 MLX5_ASSERT((uintptr_t)dseg < (uintptr_t)txq->wqes_end);
4321 * Some Tx offloads may cause an error if
4322 * packet is not long enough, check against
4323 * assumed minimal length.
4325 if (unlikely(dlen <= MLX5_ESEG_MIN_INLINE_SIZE)) {
4327 if (unlikely(!part))
4328 return MLX5_TXCMP_CODE_ERROR;
4330 * We have some successfully built
4331 * packet Data Segments to send.
4333 mlx5_tx_idone_empw(txq, loc, part,
4335 return MLX5_TXCMP_CODE_ERROR;
4337 /* Inline or not inline - that's the Question. */
4338 if (dlen > txq->inlen_empw ||
4339 loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE)
4341 if (MLX5_TXOFF_CONFIG(MPW)) {
4342 if (dlen > txq->inlen_send)
4346 /* Open new inline MPW session. */
4347 tlen += sizeof(dseg->bcount);
4348 dseg->bcount = RTE_BE32(0);
4350 (dseg, sizeof(dseg->bcount));
4353 * No pointer and inline descriptor
4354 * intermix for legacy MPW sessions.
4356 if (wqem->dseg[0].bcount)
4360 tlen = sizeof(dseg->bcount) + dlen;
4362 /* Inline entire packet, optional VLAN insertion. */
4363 if (MLX5_TXOFF_CONFIG(VLAN) &&
4364 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4366 * The packet length must be checked in
4367 * mlx5_tx_able_to_empw() and packet
4368 * fits into inline length guaranteed.
4371 sizeof(struct rte_vlan_hdr)) <=
4373 tlen += sizeof(struct rte_vlan_hdr);
4376 dseg = mlx5_tx_dseg_vlan(txq, loc, dseg,
4378 #ifdef MLX5_PMD_SOFT_COUNTERS
4379 /* Update sent data bytes counter. */
4380 slen += sizeof(struct rte_vlan_hdr);
4385 dseg = mlx5_tx_dseg_empw(txq, loc, dseg,
4388 if (!MLX5_TXOFF_CONFIG(MPW))
4389 tlen = RTE_ALIGN(tlen, MLX5_WSEG_SIZE);
4390 MLX5_ASSERT(room >= tlen);
4393 * Packet data are completely inlined,
4394 * free the packet immediately.
4396 rte_pktmbuf_free_seg(loc->mbuf);
4400 * No pointer and inline descriptor
4401 * intermix for legacy MPW sessions.
4403 if (MLX5_TXOFF_CONFIG(MPW) &&
4405 wqem->dseg[0].bcount == RTE_BE32(0))
4408 * Not inlinable VLAN packets are
4409 * proceeded outside of this routine.
4411 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE);
4412 if (MLX5_TXOFF_CONFIG(VLAN))
4413 MLX5_ASSERT(!(loc->mbuf->ol_flags &
4415 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
4416 /* We have to store mbuf in elts.*/
4417 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
4418 room -= MLX5_WQE_DSEG_SIZE;
4419 /* Ring buffer wraparound is checked at the loop end.*/
4422 #ifdef MLX5_PMD_SOFT_COUNTERS
4423 /* Update sent data bytes counter. */
4429 if (unlikely(!pkts_n || !loc->elts_free)) {
4431 * We have no resources/packets to
4432 * continue build descriptors.
4435 mlx5_tx_idone_empw(txq, loc, part,
4437 return MLX5_TXCMP_CODE_EXIT;
4439 loc->mbuf = *pkts++;
4440 if (likely(pkts_n > 1))
4441 rte_prefetch0(*pkts);
4442 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4444 * Unroll the completion code to avoid
4445 * returning variable value - it results in
4446 * unoptimized sequent checking in caller.
4448 if (ret == MLX5_TXCMP_CODE_MULTI) {
4450 mlx5_tx_idone_empw(txq, loc, part,
4452 if (unlikely(!loc->elts_free ||
4454 return MLX5_TXCMP_CODE_EXIT;
4455 return MLX5_TXCMP_CODE_MULTI;
4457 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4458 if (ret == MLX5_TXCMP_CODE_TSO) {
4460 mlx5_tx_idone_empw(txq, loc, part,
4462 if (unlikely(!loc->elts_free ||
4464 return MLX5_TXCMP_CODE_EXIT;
4465 return MLX5_TXCMP_CODE_TSO;
4467 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4469 mlx5_tx_idone_empw(txq, loc, part,
4471 if (unlikely(!loc->elts_free ||
4473 return MLX5_TXCMP_CODE_EXIT;
4474 return MLX5_TXCMP_CODE_SINGLE;
4476 if (ret != MLX5_TXCMP_CODE_EMPW) {
4479 mlx5_tx_idone_empw(txq, loc, part,
4481 return MLX5_TXCMP_CODE_ERROR;
4483 /* Check if we have minimal room left. */
4485 if (unlikely(!nlim || room < MLX5_WQE_DSEG_SIZE))
4488 * Check whether packet parameters coincide
4489 * within assumed eMPW batch:
4490 * - check sum settings
4492 * - software parser settings
4493 * - packets length (legacy MPW only)
4494 * - scheduling is not required
4496 if (!mlx5_tx_match_empw(txq, &wqem->eseg,
4499 /* Packet attributes match, continue the same eMPW. */
4500 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4501 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4504 * We get here to close an existing eMPW
4505 * session and start the new one.
4507 MLX5_ASSERT(pkts_n);
4509 if (unlikely(!part))
4510 return MLX5_TXCMP_CODE_EXIT;
4511 mlx5_tx_idone_empw(txq, loc, part, slen, wqem, olx);
4512 if (unlikely(!loc->elts_free ||
4514 return MLX5_TXCMP_CODE_EXIT;
4515 /* Continue the loop with new eMPW session. */
4521 * The routine sends packets with ordinary MLX5_OPCODE_SEND.
4522 * Data inlining and VLAN insertion are supported.
4524 static __rte_always_inline enum mlx5_txcmp_code
4525 mlx5_tx_burst_single_send(struct mlx5_txq_data *__rte_restrict txq,
4526 struct rte_mbuf **__rte_restrict pkts,
4527 unsigned int pkts_n,
4528 struct mlx5_txq_local *__rte_restrict loc,
4532 * Subroutine is the part of mlx5_tx_burst_single()
4533 * and sends single-segment packet with SEND opcode.
4535 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4536 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4537 pkts += loc->pkts_sent + 1;
4538 pkts_n -= loc->pkts_sent;
4540 struct mlx5_wqe *__rte_restrict wqe;
4541 enum mlx5_txcmp_code ret;
4543 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4544 if (MLX5_TXOFF_CONFIG(TXPP)) {
4545 enum mlx5_txcmp_code wret;
4547 /* Generate WAIT for scheduling if requested. */
4548 wret = mlx5_tx_schedule_send(txq, loc, olx);
4549 if (wret == MLX5_TXCMP_CODE_EXIT)
4550 return MLX5_TXCMP_CODE_EXIT;
4551 if (wret == MLX5_TXCMP_CODE_ERROR)
4552 return MLX5_TXCMP_CODE_ERROR;
4554 if (MLX5_TXOFF_CONFIG(INLINE)) {
4555 unsigned int inlen, vlan = 0;
4557 inlen = rte_pktmbuf_data_len(loc->mbuf);
4558 if (MLX5_TXOFF_CONFIG(VLAN) &&
4559 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4560 vlan = sizeof(struct rte_vlan_hdr);
4562 static_assert((sizeof(struct rte_vlan_hdr) +
4563 sizeof(struct rte_ether_hdr)) ==
4564 MLX5_ESEG_MIN_INLINE_SIZE,
4565 "invalid min inline data size");
4568 * If inlining is enabled at configuration time
4569 * the limit must be not less than minimal size.
4570 * Otherwise we would do extra check for data
4571 * size to avoid crashes due to length overflow.
4573 MLX5_ASSERT(txq->inlen_send >=
4574 MLX5_ESEG_MIN_INLINE_SIZE);
4575 if (inlen <= txq->inlen_send) {
4576 unsigned int seg_n, wqe_n;
4578 rte_prefetch0(rte_pktmbuf_mtod
4579 (loc->mbuf, uint8_t *));
4580 /* Check against minimal length. */
4581 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
4582 return MLX5_TXCMP_CODE_ERROR;
4583 if (loc->mbuf->ol_flags &
4584 PKT_TX_DYNF_NOINLINE) {
4586 * The hint flag not to inline packet
4587 * data is set. Check whether we can
4590 if ((!MLX5_TXOFF_CONFIG(EMPW) &&
4592 (MLX5_TXOFF_CONFIG(MPW) &&
4594 if (inlen <= txq->inlen_send)
4597 * The hardware requires the
4598 * minimal inline data header.
4600 goto single_min_inline;
4602 if (MLX5_TXOFF_CONFIG(VLAN) &&
4603 vlan && !txq->vlan_en) {
4605 * We must insert VLAN tag
4606 * by software means.
4608 goto single_part_inline;
4610 goto single_no_inline;
4614 * Completely inlined packet data WQE:
4615 * - Control Segment, SEND opcode
4616 * - Ethernet Segment, no VLAN insertion
4617 * - Data inlined, VLAN optionally inserted
4618 * - Alignment to MLX5_WSEG_SIZE
4619 * Have to estimate amount of WQEBBs
4621 seg_n = (inlen + 3 * MLX5_WSEG_SIZE -
4622 MLX5_ESEG_MIN_INLINE_SIZE +
4623 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4624 /* Check if there are enough WQEBBs. */
4625 wqe_n = (seg_n + 3) / 4;
4626 if (wqe_n > loc->wqe_free)
4627 return MLX5_TXCMP_CODE_EXIT;
4628 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4629 loc->wqe_last = wqe;
4630 mlx5_tx_cseg_init(txq, loc, wqe, seg_n,
4631 MLX5_OPCODE_SEND, olx);
4632 mlx5_tx_eseg_data(txq, loc, wqe,
4633 vlan, inlen, 0, olx);
4634 txq->wqe_ci += wqe_n;
4635 loc->wqe_free -= wqe_n;
4637 * Packet data are completely inlined,
4638 * free the packet immediately.
4640 rte_pktmbuf_free_seg(loc->mbuf);
4641 } else if ((!MLX5_TXOFF_CONFIG(EMPW) ||
4642 MLX5_TXOFF_CONFIG(MPW)) &&
4645 * If minimal inlining is requested the eMPW
4646 * feature should be disabled due to data is
4647 * inlined into Ethernet Segment, which can
4648 * not contain inlined data for eMPW due to
4649 * segment shared for all packets.
4651 struct mlx5_wqe_dseg *__rte_restrict dseg;
4656 * The inline-mode settings require
4657 * to inline the specified amount of
4658 * data bytes to the Ethernet Segment.
4659 * We should check the free space in
4660 * WQE ring buffer to inline partially.
4663 MLX5_ASSERT(txq->inlen_send >= txq->inlen_mode);
4664 MLX5_ASSERT(inlen > txq->inlen_mode);
4665 MLX5_ASSERT(txq->inlen_mode >=
4666 MLX5_ESEG_MIN_INLINE_SIZE);
4668 * Check whether there are enough free WQEBBs:
4670 * - Ethernet Segment
4671 * - First Segment of inlined Ethernet data
4672 * - ... data continued ...
4673 * - Finishing Data Segment of pointer type
4675 ds = (MLX5_WQE_CSEG_SIZE +
4676 MLX5_WQE_ESEG_SIZE +
4677 MLX5_WQE_DSEG_SIZE +
4679 MLX5_ESEG_MIN_INLINE_SIZE +
4680 MLX5_WQE_DSEG_SIZE +
4681 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4682 if (loc->wqe_free < ((ds + 3) / 4))
4683 return MLX5_TXCMP_CODE_EXIT;
4685 * Build the ordinary SEND WQE:
4687 * - Ethernet Segment, inline inlen_mode bytes
4688 * - Data Segment of pointer type
4690 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4691 loc->wqe_last = wqe;
4692 mlx5_tx_cseg_init(txq, loc, wqe, ds,
4693 MLX5_OPCODE_SEND, olx);
4694 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan,
4697 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4698 txq->inlen_mode - vlan;
4699 inlen -= txq->inlen_mode;
4700 mlx5_tx_dseg_ptr(txq, loc, dseg,
4703 * WQE is built, update the loop parameters
4704 * and got to the next packet.
4706 txq->wqe_ci += (ds + 3) / 4;
4707 loc->wqe_free -= (ds + 3) / 4;
4708 /* We have to store mbuf in elts.*/
4709 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4710 txq->elts[txq->elts_head++ & txq->elts_m] =
4718 * Partially inlined packet data WQE, we have
4719 * some space in title WQEBB, we can fill it
4720 * with some packet data. It takes one WQEBB,
4721 * it is available, no extra space check:
4722 * - Control Segment, SEND opcode
4723 * - Ethernet Segment, no VLAN insertion
4724 * - MLX5_ESEG_MIN_INLINE_SIZE bytes of Data
4725 * - Data Segment, pointer type
4727 * We also get here if VLAN insertion is not
4728 * supported by HW, the inline is enabled.
4731 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4732 loc->wqe_last = wqe;
4733 mlx5_tx_cseg_init(txq, loc, wqe, 4,
4734 MLX5_OPCODE_SEND, olx);
4735 mlx5_tx_eseg_dmin(txq, loc, wqe, vlan, olx);
4736 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4737 MLX5_ESEG_MIN_INLINE_SIZE - vlan;
4739 * The length check is performed above, by
4740 * comparing with txq->inlen_send. We should
4741 * not get overflow here.
4743 MLX5_ASSERT(inlen > MLX5_ESEG_MIN_INLINE_SIZE);
4744 dlen = inlen - MLX5_ESEG_MIN_INLINE_SIZE;
4745 mlx5_tx_dseg_ptr(txq, loc, &wqe->dseg[1],
4749 /* We have to store mbuf in elts.*/
4750 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4751 txq->elts[txq->elts_head++ & txq->elts_m] =
4755 #ifdef MLX5_PMD_SOFT_COUNTERS
4756 /* Update sent data bytes counter. */
4757 txq->stats.obytes += vlan +
4758 rte_pktmbuf_data_len(loc->mbuf);
4762 * No inline at all, it means the CPU cycles saving
4763 * is prioritized at configuration, we should not
4764 * copy any packet data to WQE.
4766 * SEND WQE, one WQEBB:
4767 * - Control Segment, SEND opcode
4768 * - Ethernet Segment, optional VLAN, no inline
4769 * - Data Segment, pointer type
4772 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4773 loc->wqe_last = wqe;
4774 mlx5_tx_cseg_init(txq, loc, wqe, 3,
4775 MLX5_OPCODE_SEND, olx);
4776 mlx5_tx_eseg_none(txq, loc, wqe, olx);
4778 (txq, loc, &wqe->dseg[0],
4779 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4780 rte_pktmbuf_data_len(loc->mbuf), olx);
4784 * We should not store mbuf pointer in elts
4785 * if no inlining is configured, this is done
4786 * by calling routine in a batch copy.
4788 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
4790 #ifdef MLX5_PMD_SOFT_COUNTERS
4791 /* Update sent data bytes counter. */
4792 txq->stats.obytes += rte_pktmbuf_data_len(loc->mbuf);
4793 if (MLX5_TXOFF_CONFIG(VLAN) &&
4794 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
4795 txq->stats.obytes +=
4796 sizeof(struct rte_vlan_hdr);
4801 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4802 return MLX5_TXCMP_CODE_EXIT;
4803 loc->mbuf = *pkts++;
4805 rte_prefetch0(*pkts);
4806 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4807 if (unlikely(ret != MLX5_TXCMP_CODE_SINGLE))
4813 static __rte_always_inline enum mlx5_txcmp_code
4814 mlx5_tx_burst_single(struct mlx5_txq_data *__rte_restrict txq,
4815 struct rte_mbuf **__rte_restrict pkts,
4816 unsigned int pkts_n,
4817 struct mlx5_txq_local *__rte_restrict loc,
4820 enum mlx5_txcmp_code ret;
4822 ret = mlx5_tx_able_to_empw(txq, loc, olx, false);
4823 if (ret == MLX5_TXCMP_CODE_SINGLE)
4825 MLX5_ASSERT(ret == MLX5_TXCMP_CODE_EMPW);
4827 /* Optimize for inline/no inline eMPW send. */
4828 ret = (MLX5_TXOFF_CONFIG(INLINE)) ?
4829 mlx5_tx_burst_empw_inline
4830 (txq, pkts, pkts_n, loc, olx) :
4831 mlx5_tx_burst_empw_simple
4832 (txq, pkts, pkts_n, loc, olx);
4833 if (ret != MLX5_TXCMP_CODE_SINGLE)
4835 /* The resources to send one packet should remain. */
4836 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4838 ret = mlx5_tx_burst_single_send(txq, pkts, pkts_n, loc, olx);
4839 MLX5_ASSERT(ret != MLX5_TXCMP_CODE_SINGLE);
4840 if (ret != MLX5_TXCMP_CODE_EMPW)
4842 /* The resources to send one packet should remain. */
4843 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4848 * DPDK Tx callback template. This is configured template
4849 * used to generate routines optimized for specified offload setup.
4850 * One of this generated functions is chosen at SQ configuration
4854 * Generic pointer to TX queue structure.
4856 * Packets to transmit.
4858 * Number of packets in array.
4860 * Configured offloads mask, presents the bits of MLX5_TXOFF_CONFIG_xxx
4861 * values. Should be static to take compile time static configuration
4865 * Number of packets successfully transmitted (<= pkts_n).
4867 static __rte_always_inline uint16_t
4868 mlx5_tx_burst_tmpl(struct mlx5_txq_data *__rte_restrict txq,
4869 struct rte_mbuf **__rte_restrict pkts,
4873 struct mlx5_txq_local loc;
4874 enum mlx5_txcmp_code ret;
4877 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4878 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4879 if (unlikely(!pkts_n))
4883 loc.wqe_last = NULL;
4886 loc.pkts_loop = loc.pkts_sent;
4888 * Check if there are some CQEs, if any:
4889 * - process an encountered errors
4890 * - process the completed WQEs
4891 * - free related mbufs
4892 * - doorbell the NIC about processed CQEs
4894 rte_prefetch0(*(pkts + loc.pkts_sent));
4895 mlx5_tx_handle_completion(txq, olx);
4897 * Calculate the number of available resources - elts and WQEs.
4898 * There are two possible different scenarios:
4899 * - no data inlining into WQEs, one WQEBB may contains up to
4900 * four packets, in this case elts become scarce resource
4901 * - data inlining into WQEs, one packet may require multiple
4902 * WQEBBs, the WQEs become the limiting factor.
4904 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4905 loc.elts_free = txq->elts_s -
4906 (uint16_t)(txq->elts_head - txq->elts_tail);
4907 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4908 loc.wqe_free = txq->wqe_s -
4909 (uint16_t)(txq->wqe_ci - txq->wqe_pi);
4910 if (unlikely(!loc.elts_free || !loc.wqe_free))
4914 * Fetch the packet from array. Usually this is
4915 * the first packet in series of multi/single
4918 loc.mbuf = *(pkts + loc.pkts_sent);
4919 /* Dedicated branch for multi-segment packets. */
4920 if (MLX5_TXOFF_CONFIG(MULTI) &&
4921 unlikely(NB_SEGS(loc.mbuf) > 1)) {
4923 * Multi-segment packet encountered.
4924 * Hardware is able to process it only
4925 * with SEND/TSO opcodes, one packet
4926 * per WQE, do it in dedicated routine.
4929 MLX5_ASSERT(loc.pkts_sent >= loc.pkts_copy);
4930 part = loc.pkts_sent - loc.pkts_copy;
4931 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4933 * There are some single-segment mbufs not
4934 * stored in elts. The mbufs must be in the
4935 * same order as WQEs, so we must copy the
4936 * mbufs to elts here, before the coming
4937 * multi-segment packet mbufs is appended.
4939 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy,
4941 loc.pkts_copy = loc.pkts_sent;
4943 MLX5_ASSERT(pkts_n > loc.pkts_sent);
4944 ret = mlx5_tx_burst_mseg(txq, pkts, pkts_n, &loc, olx);
4945 if (!MLX5_TXOFF_CONFIG(INLINE))
4946 loc.pkts_copy = loc.pkts_sent;
4948 * These returned code checks are supposed
4949 * to be optimized out due to routine inlining.
4951 if (ret == MLX5_TXCMP_CODE_EXIT) {
4953 * The routine returns this code when
4954 * all packets are sent or there is no
4955 * enough resources to complete request.
4959 if (ret == MLX5_TXCMP_CODE_ERROR) {
4961 * The routine returns this code when
4962 * some error in the incoming packets
4965 txq->stats.oerrors++;
4968 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4970 * The single-segment packet was encountered
4971 * in the array, try to send it with the
4972 * best optimized way, possible engaging eMPW.
4974 goto enter_send_single;
4976 if (MLX5_TXOFF_CONFIG(TSO) &&
4977 ret == MLX5_TXCMP_CODE_TSO) {
4979 * The single-segment TSO packet was
4980 * encountered in the array.
4982 goto enter_send_tso;
4984 /* We must not get here. Something is going wrong. */
4986 txq->stats.oerrors++;
4989 /* Dedicated branch for single-segment TSO packets. */
4990 if (MLX5_TXOFF_CONFIG(TSO) &&
4991 unlikely(loc.mbuf->ol_flags & PKT_TX_TCP_SEG)) {
4993 * TSO might require special way for inlining
4994 * (dedicated parameters) and is sent with
4995 * MLX5_OPCODE_TSO opcode only, provide this
4996 * in dedicated branch.
4999 MLX5_ASSERT(NB_SEGS(loc.mbuf) == 1);
5000 MLX5_ASSERT(pkts_n > loc.pkts_sent);
5001 ret = mlx5_tx_burst_tso(txq, pkts, pkts_n, &loc, olx);
5003 * These returned code checks are supposed
5004 * to be optimized out due to routine inlining.
5006 if (ret == MLX5_TXCMP_CODE_EXIT)
5008 if (ret == MLX5_TXCMP_CODE_ERROR) {
5009 txq->stats.oerrors++;
5012 if (ret == MLX5_TXCMP_CODE_SINGLE)
5013 goto enter_send_single;
5014 if (MLX5_TXOFF_CONFIG(MULTI) &&
5015 ret == MLX5_TXCMP_CODE_MULTI) {
5017 * The multi-segment packet was
5018 * encountered in the array.
5020 goto enter_send_multi;
5022 /* We must not get here. Something is going wrong. */
5024 txq->stats.oerrors++;
5028 * The dedicated branch for the single-segment packets
5029 * without TSO. Often these ones can be sent using
5030 * MLX5_OPCODE_EMPW with multiple packets in one WQE.
5031 * The routine builds the WQEs till it encounters
5032 * the TSO or multi-segment packet (in case if these
5033 * offloads are requested at SQ configuration time).
5036 MLX5_ASSERT(pkts_n > loc.pkts_sent);
5037 ret = mlx5_tx_burst_single(txq, pkts, pkts_n, &loc, olx);
5039 * These returned code checks are supposed
5040 * to be optimized out due to routine inlining.
5042 if (ret == MLX5_TXCMP_CODE_EXIT)
5044 if (ret == MLX5_TXCMP_CODE_ERROR) {
5045 txq->stats.oerrors++;
5048 if (MLX5_TXOFF_CONFIG(MULTI) &&
5049 ret == MLX5_TXCMP_CODE_MULTI) {
5051 * The multi-segment packet was
5052 * encountered in the array.
5054 goto enter_send_multi;
5056 if (MLX5_TXOFF_CONFIG(TSO) &&
5057 ret == MLX5_TXCMP_CODE_TSO) {
5059 * The single-segment TSO packet was
5060 * encountered in the array.
5062 goto enter_send_tso;
5064 /* We must not get here. Something is going wrong. */
5066 txq->stats.oerrors++;
5070 * Main Tx loop is completed, do the rest:
5071 * - set completion request if thresholds are reached
5072 * - doorbell the hardware
5073 * - copy the rest of mbufs to elts (if any)
5075 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE) ||
5076 loc.pkts_sent >= loc.pkts_copy);
5077 /* Take a shortcut if nothing is sent. */
5078 if (unlikely(loc.pkts_sent == loc.pkts_loop))
5080 /* Request CQE generation if limits are reached. */
5081 mlx5_tx_request_completion(txq, &loc, olx);
5083 * Ring QP doorbell immediately after WQE building completion
5084 * to improve latencies. The pure software related data treatment
5085 * can be completed after doorbell. Tx CQEs for this SQ are
5086 * processed in this thread only by the polling.
5088 * The rdma core library can map doorbell register in two ways,
5089 * depending on the environment variable "MLX5_SHUT_UP_BF":
5091 * - as regular cached memory, the variable is either missing or
5092 * set to zero. This type of mapping may cause the significant
5093 * doorbell register writing latency and requires explicit
5094 * memory write barrier to mitigate this issue and prevent
5097 * - as non-cached memory, the variable is present and set to
5098 * not "0" value. This type of mapping may cause performance
5099 * impact under heavy loading conditions but the explicit write
5100 * memory barrier is not required and it may improve core
5103 * - the legacy behaviour (prior 19.08 release) was to use some
5104 * heuristics to decide whether write memory barrier should
5105 * be performed. This behavior is supported with specifying
5106 * tx_db_nc=2, write barrier is skipped if application
5107 * provides the full recommended burst of packets, it
5108 * supposes the next packets are coming and the write barrier
5109 * will be issued on the next burst (after descriptor writing,
5112 mlx5_tx_dbrec_cond_wmb(txq, loc.wqe_last, !txq->db_nc &&
5113 (!txq->db_heu || pkts_n % MLX5_TX_DEFAULT_BURST));
5114 /* Not all of the mbufs may be stored into elts yet. */
5115 part = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc.pkts_sent - loc.pkts_copy;
5116 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
5118 * There are some single-segment mbufs not stored in elts.
5119 * It can be only if the last packet was single-segment.
5120 * The copying is gathered into one place due to it is
5121 * a good opportunity to optimize that with SIMD.
5122 * Unfortunately if inlining is enabled the gaps in
5123 * pointer array may happen due to early freeing of the
5126 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy, part, olx);
5127 loc.pkts_copy = loc.pkts_sent;
5129 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
5130 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
5131 if (pkts_n > loc.pkts_sent) {
5133 * If burst size is large there might be no enough CQE
5134 * fetched from completion queue and no enough resources
5135 * freed to send all the packets.
5140 #ifdef MLX5_PMD_SOFT_COUNTERS
5141 /* Increment sent packets counter. */
5142 txq->stats.opackets += loc.pkts_sent;
5144 return loc.pkts_sent;
5147 /* Generate routines with Enhanced Multi-Packet Write support. */
5148 MLX5_TXOFF_DECL(full_empw,
5149 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_EMPW)
5151 MLX5_TXOFF_DECL(none_empw,
5152 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
5154 MLX5_TXOFF_DECL(md_empw,
5155 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5157 MLX5_TXOFF_DECL(mt_empw,
5158 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5159 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5161 MLX5_TXOFF_DECL(mtsc_empw,
5162 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5163 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5164 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5166 MLX5_TXOFF_DECL(mti_empw,
5167 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5168 MLX5_TXOFF_CONFIG_INLINE |
5169 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5171 MLX5_TXOFF_DECL(mtv_empw,
5172 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5173 MLX5_TXOFF_CONFIG_VLAN |
5174 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5176 MLX5_TXOFF_DECL(mtiv_empw,
5177 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5178 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5179 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5181 MLX5_TXOFF_DECL(sc_empw,
5182 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5183 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5185 MLX5_TXOFF_DECL(sci_empw,
5186 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5187 MLX5_TXOFF_CONFIG_INLINE |
5188 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5190 MLX5_TXOFF_DECL(scv_empw,
5191 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5192 MLX5_TXOFF_CONFIG_VLAN |
5193 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5195 MLX5_TXOFF_DECL(sciv_empw,
5196 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5197 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5198 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5200 MLX5_TXOFF_DECL(i_empw,
5201 MLX5_TXOFF_CONFIG_INLINE |
5202 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5204 MLX5_TXOFF_DECL(v_empw,
5205 MLX5_TXOFF_CONFIG_VLAN |
5206 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5208 MLX5_TXOFF_DECL(iv_empw,
5209 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5210 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5212 /* Generate routines without Enhanced Multi-Packet Write support. */
5213 MLX5_TXOFF_DECL(full,
5214 MLX5_TXOFF_CONFIG_FULL)
5216 MLX5_TXOFF_DECL(none,
5217 MLX5_TXOFF_CONFIG_NONE)
5220 MLX5_TXOFF_CONFIG_METADATA)
5223 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5224 MLX5_TXOFF_CONFIG_METADATA)
5226 MLX5_TXOFF_DECL(mtsc,
5227 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5228 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5229 MLX5_TXOFF_CONFIG_METADATA)
5231 MLX5_TXOFF_DECL(mti,
5232 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5233 MLX5_TXOFF_CONFIG_INLINE |
5234 MLX5_TXOFF_CONFIG_METADATA)
5237 MLX5_TXOFF_DECL(mtv,
5238 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5239 MLX5_TXOFF_CONFIG_VLAN |
5240 MLX5_TXOFF_CONFIG_METADATA)
5243 MLX5_TXOFF_DECL(mtiv,
5244 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5245 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5246 MLX5_TXOFF_CONFIG_METADATA)
5249 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5250 MLX5_TXOFF_CONFIG_METADATA)
5252 MLX5_TXOFF_DECL(sci,
5253 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5254 MLX5_TXOFF_CONFIG_INLINE |
5255 MLX5_TXOFF_CONFIG_METADATA)
5258 MLX5_TXOFF_DECL(scv,
5259 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5260 MLX5_TXOFF_CONFIG_VLAN |
5261 MLX5_TXOFF_CONFIG_METADATA)
5264 MLX5_TXOFF_DECL(sciv,
5265 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5266 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5267 MLX5_TXOFF_CONFIG_METADATA)
5270 MLX5_TXOFF_CONFIG_INLINE |
5271 MLX5_TXOFF_CONFIG_METADATA)
5274 MLX5_TXOFF_CONFIG_VLAN |
5275 MLX5_TXOFF_CONFIG_METADATA)
5278 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5279 MLX5_TXOFF_CONFIG_METADATA)
5281 /* Generate routines with timestamp scheduling. */
5282 MLX5_TXOFF_DECL(full_ts_nompw,
5283 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP)
5285 MLX5_TXOFF_DECL(full_ts_nompwi,
5286 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5287 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5288 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5289 MLX5_TXOFF_CONFIG_TXPP)
5291 MLX5_TXOFF_DECL(full_ts,
5292 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP |
5293 MLX5_TXOFF_CONFIG_EMPW)
5295 MLX5_TXOFF_DECL(full_ts_noi,
5296 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5297 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5298 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5299 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5301 MLX5_TXOFF_DECL(none_ts,
5302 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_TXPP |
5303 MLX5_TXOFF_CONFIG_EMPW)
5305 MLX5_TXOFF_DECL(mdi_ts,
5306 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5307 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5309 MLX5_TXOFF_DECL(mti_ts,
5310 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5311 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5312 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5314 MLX5_TXOFF_DECL(mtiv_ts,
5315 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5316 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5317 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_TXPP |
5318 MLX5_TXOFF_CONFIG_EMPW)
5321 * Generate routines with Legacy Multi-Packet Write support.
5322 * This mode is supported by ConnectX-4 Lx only and imposes
5323 * offload limitations, not supported:
5324 * - ACL/Flows (metadata are becoming meaningless)
5325 * - WQE Inline headers
5326 * - SRIOV (E-Switch offloads)
5328 * - tunnel encapsulation/decapsulation
5331 MLX5_TXOFF_DECL(none_mpw,
5332 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW |
5333 MLX5_TXOFF_CONFIG_MPW)
5335 MLX5_TXOFF_DECL(mci_mpw,
5336 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5337 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5338 MLX5_TXOFF_CONFIG_MPW)
5340 MLX5_TXOFF_DECL(mc_mpw,
5341 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5342 MLX5_TXOFF_CONFIG_EMPW | MLX5_TXOFF_CONFIG_MPW)
5344 MLX5_TXOFF_DECL(i_mpw,
5345 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5346 MLX5_TXOFF_CONFIG_MPW)
5349 * Array of declared and compiled Tx burst function and corresponding
5350 * supported offloads set. The array is used to select the Tx burst
5351 * function for specified offloads set at Tx queue configuration time.
5354 eth_tx_burst_t func;
5357 MLX5_TXOFF_INFO(full_empw,
5358 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5359 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5360 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5361 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5363 MLX5_TXOFF_INFO(none_empw,
5364 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
5366 MLX5_TXOFF_INFO(md_empw,
5367 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5369 MLX5_TXOFF_INFO(mt_empw,
5370 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5371 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5373 MLX5_TXOFF_INFO(mtsc_empw,
5374 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5375 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5376 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5378 MLX5_TXOFF_INFO(mti_empw,
5379 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5380 MLX5_TXOFF_CONFIG_INLINE |
5381 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5383 MLX5_TXOFF_INFO(mtv_empw,
5384 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5385 MLX5_TXOFF_CONFIG_VLAN |
5386 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5388 MLX5_TXOFF_INFO(mtiv_empw,
5389 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5390 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5391 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5393 MLX5_TXOFF_INFO(sc_empw,
5394 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5395 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5397 MLX5_TXOFF_INFO(sci_empw,
5398 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5399 MLX5_TXOFF_CONFIG_INLINE |
5400 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5402 MLX5_TXOFF_INFO(scv_empw,
5403 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5404 MLX5_TXOFF_CONFIG_VLAN |
5405 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5407 MLX5_TXOFF_INFO(sciv_empw,
5408 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5409 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5410 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5412 MLX5_TXOFF_INFO(i_empw,
5413 MLX5_TXOFF_CONFIG_INLINE |
5414 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5416 MLX5_TXOFF_INFO(v_empw,
5417 MLX5_TXOFF_CONFIG_VLAN |
5418 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5420 MLX5_TXOFF_INFO(iv_empw,
5421 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5422 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5424 MLX5_TXOFF_INFO(full_ts_nompw,
5425 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP)
5427 MLX5_TXOFF_INFO(full_ts_nompwi,
5428 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5429 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5430 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5431 MLX5_TXOFF_CONFIG_TXPP)
5433 MLX5_TXOFF_INFO(full_ts,
5434 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP |
5435 MLX5_TXOFF_CONFIG_EMPW)
5437 MLX5_TXOFF_INFO(full_ts_noi,
5438 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5439 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5440 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5441 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5443 MLX5_TXOFF_INFO(none_ts,
5444 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_TXPP |
5445 MLX5_TXOFF_CONFIG_EMPW)
5447 MLX5_TXOFF_INFO(mdi_ts,
5448 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5449 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5451 MLX5_TXOFF_INFO(mti_ts,
5452 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5453 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5454 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5456 MLX5_TXOFF_INFO(mtiv_ts,
5457 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5458 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5459 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_TXPP |
5460 MLX5_TXOFF_CONFIG_EMPW)
5462 MLX5_TXOFF_INFO(full,
5463 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5464 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5465 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5466 MLX5_TXOFF_CONFIG_METADATA)
5468 MLX5_TXOFF_INFO(none,
5469 MLX5_TXOFF_CONFIG_NONE)
5472 MLX5_TXOFF_CONFIG_METADATA)
5475 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5476 MLX5_TXOFF_CONFIG_METADATA)
5478 MLX5_TXOFF_INFO(mtsc,
5479 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5480 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5481 MLX5_TXOFF_CONFIG_METADATA)
5483 MLX5_TXOFF_INFO(mti,
5484 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5485 MLX5_TXOFF_CONFIG_INLINE |
5486 MLX5_TXOFF_CONFIG_METADATA)
5488 MLX5_TXOFF_INFO(mtv,
5489 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5490 MLX5_TXOFF_CONFIG_VLAN |
5491 MLX5_TXOFF_CONFIG_METADATA)
5493 MLX5_TXOFF_INFO(mtiv,
5494 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5495 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5496 MLX5_TXOFF_CONFIG_METADATA)
5499 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5500 MLX5_TXOFF_CONFIG_METADATA)
5502 MLX5_TXOFF_INFO(sci,
5503 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5504 MLX5_TXOFF_CONFIG_INLINE |
5505 MLX5_TXOFF_CONFIG_METADATA)
5507 MLX5_TXOFF_INFO(scv,
5508 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5509 MLX5_TXOFF_CONFIG_VLAN |
5510 MLX5_TXOFF_CONFIG_METADATA)
5512 MLX5_TXOFF_INFO(sciv,
5513 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5514 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5515 MLX5_TXOFF_CONFIG_METADATA)
5518 MLX5_TXOFF_CONFIG_INLINE |
5519 MLX5_TXOFF_CONFIG_METADATA)
5522 MLX5_TXOFF_CONFIG_VLAN |
5523 MLX5_TXOFF_CONFIG_METADATA)
5526 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5527 MLX5_TXOFF_CONFIG_METADATA)
5529 MLX5_TXOFF_INFO(none_mpw,
5530 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW |
5531 MLX5_TXOFF_CONFIG_MPW)
5533 MLX5_TXOFF_INFO(mci_mpw,
5534 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5535 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5536 MLX5_TXOFF_CONFIG_MPW)
5538 MLX5_TXOFF_INFO(mc_mpw,
5539 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5540 MLX5_TXOFF_CONFIG_EMPW | MLX5_TXOFF_CONFIG_MPW)
5542 MLX5_TXOFF_INFO(i_mpw,
5543 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5544 MLX5_TXOFF_CONFIG_MPW)
5548 * Configure the Tx function to use. The routine checks configured
5549 * Tx offloads for the device and selects appropriate Tx burst
5550 * routine. There are multiple Tx burst routines compiled from
5551 * the same template in the most optimal way for the dedicated
5555 * Pointer to private data structure.
5558 * Pointer to selected Tx burst function.
5561 mlx5_select_tx_function(struct rte_eth_dev *dev)
5563 struct mlx5_priv *priv = dev->data->dev_private;
5564 struct mlx5_dev_config *config = &priv->config;
5565 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
5566 unsigned int diff = 0, olx = 0, i, m;
5568 static_assert(MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE <=
5569 MLX5_DSEG_MAX, "invalid WQE max size");
5570 static_assert(MLX5_WQE_CSEG_SIZE == MLX5_WSEG_SIZE,
5571 "invalid WQE Control Segment size");
5572 static_assert(MLX5_WQE_ESEG_SIZE == MLX5_WSEG_SIZE,
5573 "invalid WQE Ethernet Segment size");
5574 static_assert(MLX5_WQE_DSEG_SIZE == MLX5_WSEG_SIZE,
5575 "invalid WQE Data Segment size");
5576 static_assert(MLX5_WQE_SIZE == 4 * MLX5_WSEG_SIZE,
5577 "invalid WQE size");
5579 if (tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS) {
5580 /* We should support Multi-Segment Packets. */
5581 olx |= MLX5_TXOFF_CONFIG_MULTI;
5583 if (tx_offloads & (DEV_TX_OFFLOAD_TCP_TSO |
5584 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
5585 DEV_TX_OFFLOAD_GRE_TNL_TSO |
5586 DEV_TX_OFFLOAD_IP_TNL_TSO |
5587 DEV_TX_OFFLOAD_UDP_TNL_TSO)) {
5588 /* We should support TCP Send Offload. */
5589 olx |= MLX5_TXOFF_CONFIG_TSO;
5591 if (tx_offloads & (DEV_TX_OFFLOAD_IP_TNL_TSO |
5592 DEV_TX_OFFLOAD_UDP_TNL_TSO |
5593 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5594 /* We should support Software Parser for Tunnels. */
5595 olx |= MLX5_TXOFF_CONFIG_SWP;
5597 if (tx_offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
5598 DEV_TX_OFFLOAD_UDP_CKSUM |
5599 DEV_TX_OFFLOAD_TCP_CKSUM |
5600 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5601 /* We should support IP/TCP/UDP Checksums. */
5602 olx |= MLX5_TXOFF_CONFIG_CSUM;
5604 if (tx_offloads & DEV_TX_OFFLOAD_VLAN_INSERT) {
5605 /* We should support VLAN insertion. */
5606 olx |= MLX5_TXOFF_CONFIG_VLAN;
5608 if (tx_offloads & DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP &&
5609 rte_mbuf_dynflag_lookup
5610 (RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL) >= 0 &&
5611 rte_mbuf_dynfield_lookup
5612 (RTE_MBUF_DYNFIELD_TIMESTAMP_NAME, NULL) >= 0) {
5613 /* Offload configured, dynamic entities registered. */
5614 olx |= MLX5_TXOFF_CONFIG_TXPP;
5616 if (priv->txqs_n && (*priv->txqs)[0]) {
5617 struct mlx5_txq_data *txd = (*priv->txqs)[0];
5619 if (txd->inlen_send) {
5621 * Check the data inline requirements. Data inline
5622 * is enabled on per device basis, we can check
5623 * the first Tx queue only.
5625 * If device does not support VLAN insertion in WQE
5626 * and some queues are requested to perform VLAN
5627 * insertion offload than inline must be enabled.
5629 olx |= MLX5_TXOFF_CONFIG_INLINE;
5632 if (config->mps == MLX5_MPW_ENHANCED &&
5633 config->txq_inline_min <= 0) {
5635 * The NIC supports Enhanced Multi-Packet Write
5636 * and does not require minimal inline data.
5638 olx |= MLX5_TXOFF_CONFIG_EMPW;
5640 if (rte_flow_dynf_metadata_avail()) {
5641 /* We should support Flow metadata. */
5642 olx |= MLX5_TXOFF_CONFIG_METADATA;
5644 if (config->mps == MLX5_MPW) {
5646 * The NIC supports Legacy Multi-Packet Write.
5647 * The MLX5_TXOFF_CONFIG_MPW controls the
5648 * descriptor building method in combination
5649 * with MLX5_TXOFF_CONFIG_EMPW.
5651 if (!(olx & (MLX5_TXOFF_CONFIG_TSO |
5652 MLX5_TXOFF_CONFIG_SWP |
5653 MLX5_TXOFF_CONFIG_VLAN |
5654 MLX5_TXOFF_CONFIG_METADATA)))
5655 olx |= MLX5_TXOFF_CONFIG_EMPW |
5656 MLX5_TXOFF_CONFIG_MPW;
5659 * Scan the routines table to find the minimal
5660 * satisfying routine with requested offloads.
5662 m = RTE_DIM(txoff_func);
5663 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5666 tmp = txoff_func[i].olx;
5668 /* Meets requested offloads exactly.*/
5672 if ((tmp & olx) != olx) {
5673 /* Does not meet requested offloads at all. */
5676 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_MPW)
5677 /* Do not enable legacy MPW if not configured. */
5679 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_EMPW)
5680 /* Do not enable eMPW if not configured. */
5682 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_INLINE)
5683 /* Do not enable inlining if not configured. */
5685 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_TXPP)
5686 /* Do not enable scheduling if not configured. */
5689 * Some routine meets the requirements.
5690 * Check whether it has minimal amount
5691 * of not requested offloads.
5693 tmp = __builtin_popcountl(tmp & ~olx);
5694 if (m >= RTE_DIM(txoff_func) || tmp < diff) {
5695 /* First or better match, save and continue. */
5701 tmp = txoff_func[i].olx ^ txoff_func[m].olx;
5702 if (__builtin_ffsl(txoff_func[i].olx & ~tmp) <
5703 __builtin_ffsl(txoff_func[m].olx & ~tmp)) {
5704 /* Lighter not requested offload. */
5709 if (m >= RTE_DIM(txoff_func)) {
5710 DRV_LOG(DEBUG, "port %u has no selected Tx function"
5711 " for requested offloads %04X",
5712 dev->data->port_id, olx);
5715 DRV_LOG(DEBUG, "port %u has selected Tx function"
5716 " supporting offloads %04X/%04X",
5717 dev->data->port_id, olx, txoff_func[m].olx);
5718 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MULTI)
5719 DRV_LOG(DEBUG, "\tMULTI (multi segment)");
5720 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TSO)
5721 DRV_LOG(DEBUG, "\tTSO (TCP send offload)");
5722 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_SWP)
5723 DRV_LOG(DEBUG, "\tSWP (software parser)");
5724 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_CSUM)
5725 DRV_LOG(DEBUG, "\tCSUM (checksum offload)");
5726 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_INLINE)
5727 DRV_LOG(DEBUG, "\tINLIN (inline data)");
5728 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_VLAN)
5729 DRV_LOG(DEBUG, "\tVLANI (VLAN insertion)");
5730 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_METADATA)
5731 DRV_LOG(DEBUG, "\tMETAD (tx Flow metadata)");
5732 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TXPP)
5733 DRV_LOG(DEBUG, "\tMETAD (tx Scheduling)");
5734 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_EMPW) {
5735 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MPW)
5736 DRV_LOG(DEBUG, "\tMPW (Legacy MPW)");
5738 DRV_LOG(DEBUG, "\tEMPW (Enhanced MPW)");
5740 return txoff_func[m].func;
5744 * DPDK callback to get the TX queue information
5747 * Pointer to the device structure.
5749 * @param tx_queue_id
5750 * Tx queue identificator.
5753 * Pointer to the TX queue information structure.
5760 mlx5_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
5761 struct rte_eth_txq_info *qinfo)
5763 struct mlx5_priv *priv = dev->data->dev_private;
5764 struct mlx5_txq_data *txq = (*priv->txqs)[tx_queue_id];
5765 struct mlx5_txq_ctrl *txq_ctrl =
5766 container_of(txq, struct mlx5_txq_ctrl, txq);
5770 qinfo->nb_desc = txq->elts_s;
5771 qinfo->conf.tx_thresh.pthresh = 0;
5772 qinfo->conf.tx_thresh.hthresh = 0;
5773 qinfo->conf.tx_thresh.wthresh = 0;
5774 qinfo->conf.tx_rs_thresh = 0;
5775 qinfo->conf.tx_free_thresh = 0;
5776 qinfo->conf.tx_deferred_start = txq_ctrl ? 0 : 1;
5777 qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
5781 * DPDK callback to get the TX packet burst mode information
5784 * Pointer to the device structure.
5786 * @param tx_queue_id
5787 * Tx queue identificatior.
5790 * Pointer to the burts mode information.
5793 * 0 as success, -EINVAL as failure.
5797 mlx5_tx_burst_mode_get(struct rte_eth_dev *dev,
5798 uint16_t tx_queue_id __rte_unused,
5799 struct rte_eth_burst_mode *mode)
5801 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
5802 unsigned int i, olx;
5804 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5805 if (pkt_burst == txoff_func[i].func) {
5806 olx = txoff_func[i].olx;
5807 snprintf(mode->info, sizeof(mode->info),
5808 "%s%s%s%s%s%s%s%s%s",
5809 (olx & MLX5_TXOFF_CONFIG_EMPW) ?
5810 ((olx & MLX5_TXOFF_CONFIG_MPW) ?
5811 "Legacy MPW" : "Enhanced MPW") : "No MPW",
5812 (olx & MLX5_TXOFF_CONFIG_MULTI) ?
5814 (olx & MLX5_TXOFF_CONFIG_TSO) ?
5816 (olx & MLX5_TXOFF_CONFIG_SWP) ?
5818 (olx & MLX5_TXOFF_CONFIG_CSUM) ?
5820 (olx & MLX5_TXOFF_CONFIG_INLINE) ?
5822 (olx & MLX5_TXOFF_CONFIG_VLAN) ?
5824 (olx & MLX5_TXOFF_CONFIG_METADATA) ?
5826 (olx & MLX5_TXOFF_CONFIG_TXPP) ?