drivers/net/qede/base/ecore_mcp.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include "bcm_osal.h"
   8 #include "ecore.h"
   9 #include "ecore_status.h"
  10 #include "nvm_cfg.h"
  11 #include "ecore_mcp.h"
  12 #include "mcp_public.h"
  13 #include "reg_addr.h"
  14 #include "ecore_hw.h"
  15 #include "ecore_init_fw_funcs.h"
  16 #include "ecore_sriov.h"
  17 #include "ecore_vf.h"
  18 #include "ecore_iov_api.h"
  19 #include "ecore_gtt_reg_addr.h"
  20 #include "ecore_iro.h"
  21 #include "ecore_dcbx.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_cxt.h"
  24
  25 #define CHIP_MCP_RESP_ITER_US 10
  26 #define EMUL_MCP_RESP_ITER_US (1000 * 1000)
  27
  28 #define ECORE_DRV_MB_MAX_RETRIES (500 * 1000)   /* Account for 5 sec */
  29 #define ECORE_MCP_RESET_RETRIES (50 * 1000)     /* Account for 500 msec */
  30
  31 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
  32         ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
  33                  _val)
  34
  35 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
  36         ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
  37
  38 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
  39         DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
  40                      OFFSETOF(struct public_drv_mb, _field), _val)
  41
  42 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
  43         DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
  44                      OFFSETOF(struct public_drv_mb, _field))
  45
  46 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
  47         DRV_ID_PDA_COMP_VER_OFFSET)
  48
  49 #define MCP_BYTES_PER_MBIT_OFFSET 17
  50
  51 #ifndef ASIC_ONLY
  52 static int loaded;
  53 static int loaded_port[MAX_NUM_PORTS] = { 0 };
  54 #endif
  55
  56 bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn)
  57 {
  58         if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
  59                 return false;
  60         return true;
  61 }
  62
  63 void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  64 {
  65         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
  66                                         PUBLIC_PORT);
  67         u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
  68
  69         p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
  70                                                    MFW_PORT(p_hwfn));
  71         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
  72                    "port_addr = 0x%x, port_id 0x%02x\n",
  73                    p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
  74 }
  75
  76 void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  77 {
  78         u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
  79         OSAL_BE32 tmp;
  80         u32 i;
  81
  82 #ifndef ASIC_ONLY
  83         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
  84                 return;
  85 #endif
  86
  87         if (!p_hwfn->mcp_info->public_base)
  88                 return;
  89
  90         for (i = 0; i < length; i++) {
  91                 tmp = ecore_rd(p_hwfn, p_ptt,
  92                                p_hwfn->mcp_info->mfw_mb_addr +
  93                                (i << 2) + sizeof(u32));
  94
  95                 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
  96                     OSAL_BE32_TO_CPU(tmp);
  97         }
  98 }
  99
 100 struct ecore_mcp_cmd_elem {
 101         osal_list_entry_t list;
 102         struct ecore_mcp_mb_params *p_mb_params;
 103         u16 expected_seq_num;
 104         bool b_is_completed;
 105 };
 106
 107 /* Must be called while cmd_lock is acquired */
 108 static struct ecore_mcp_cmd_elem *
 109 ecore_mcp_cmd_add_elem(struct ecore_hwfn *p_hwfn,
 110                        struct ecore_mcp_mb_params *p_mb_params,
 111                        u16 expected_seq_num)
 112 {
 113         struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
 114
 115         p_cmd_elem = OSAL_ZALLOC(p_hwfn->p_dev, GFP_ATOMIC,
 116                                  sizeof(*p_cmd_elem));
 117         if (!p_cmd_elem) {
 118                 DP_NOTICE(p_hwfn, false,
 119                           "Failed to allocate `struct ecore_mcp_cmd_elem'\n");
 120                 goto out;
 121         }
 122
 123         p_cmd_elem->p_mb_params = p_mb_params;
 124         p_cmd_elem->expected_seq_num = expected_seq_num;
 125         OSAL_LIST_PUSH_HEAD(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
 126 out:
 127         return p_cmd_elem;
 128 }
 129
 130 /* Must be called while cmd_lock is acquired */
 131 static void ecore_mcp_cmd_del_elem(struct ecore_hwfn *p_hwfn,
 132                                    struct ecore_mcp_cmd_elem *p_cmd_elem)
 133 {
 134         OSAL_LIST_REMOVE_ENTRY(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
 135         OSAL_FREE(p_hwfn->p_dev, p_cmd_elem);
 136 }
 137
 138 /* Must be called while cmd_lock is acquired */
 139 static struct ecore_mcp_cmd_elem *
 140 ecore_mcp_cmd_get_elem(struct ecore_hwfn *p_hwfn, u16 seq_num)
 141 {
 142         struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
 143
 144         OSAL_LIST_FOR_EACH_ENTRY(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list,
 145                                  struct ecore_mcp_cmd_elem) {
 146                 if (p_cmd_elem->expected_seq_num == seq_num)
 147                         return p_cmd_elem;
 148         }
 149
 150         return OSAL_NULL;
 151 }
 152
 153 enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn)
 154 {
 155         if (p_hwfn->mcp_info) {
 156                 struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL, *p_tmp;
 157
 158                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_cur);
 159                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_shadow);
 160
 161                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 162                 OSAL_LIST_FOR_EACH_ENTRY_SAFE(p_cmd_elem, p_tmp,
 163                                               &p_hwfn->mcp_info->cmd_list, list,
 164                                               struct ecore_mcp_cmd_elem) {
 165                         ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 166                 }
 167                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 168
 169 #ifdef CONFIG_ECORE_LOCK_ALLOC
 170                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->cmd_lock);
 171                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->link_lock);
 172 #endif
 173         }
 174
 175         OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
 176
 177         return ECORE_SUCCESS;
 178 }
 179
 180 static enum _ecore_status_t ecore_load_mcp_offsets(struct ecore_hwfn *p_hwfn,
 181                                                    struct ecore_ptt *p_ptt)
 182 {
 183         struct ecore_mcp_info *p_info = p_hwfn->mcp_info;
 184         u32 drv_mb_offsize, mfw_mb_offsize;
 185         u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
 186
 187 #ifndef ASIC_ONLY
 188         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 189                 DP_NOTICE(p_hwfn, false, "Emulation - assume no MFW\n");
 190                 p_info->public_base = 0;
 191                 return ECORE_INVAL;
 192         }
 193 #endif
 194
 195         p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
 196         if (!p_info->public_base)
 197                 return ECORE_INVAL;
 198
 199         p_info->public_base |= GRCBASE_MCP;
 200
 201         /* Calculate the driver and MFW mailbox address */
 202         drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 203                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 204                                                        PUBLIC_DRV_MB));
 205         p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
 206         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 207                    "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x"
 208                    " mcp_pf_id = 0x%x\n",
 209                    drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
 210
 211         /* Set the MFW MB address */
 212         mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 213                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 214                                                        PUBLIC_MFW_MB));
 215         p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
 216         p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
 217                                                p_info->mfw_mb_addr);
 218
 219         /* Get the current driver mailbox sequence before sending
 220          * the first command
 221          */
 222         p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 223             DRV_MSG_SEQ_NUMBER_MASK;
 224
 225         /* Get current FW pulse sequence */
 226         p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
 227             DRV_PULSE_SEQ_MASK;
 228
 229         p_info->mcp_hist = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 230
 231         return ECORE_SUCCESS;
 232 }
 233
 234 enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
 235                                         struct ecore_ptt *p_ptt)
 236 {
 237         struct ecore_mcp_info *p_info;
 238         u32 size;
 239
 240         /* Allocate mcp_info structure */
 241         p_hwfn->mcp_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 242                         sizeof(*p_hwfn->mcp_info));
 243         if (!p_hwfn->mcp_info) {
 244                 DP_NOTICE(p_hwfn, false, "Failed to allocate mcp_info\n");
 245                 return ECORE_NOMEM;
 246         }
 247         p_info = p_hwfn->mcp_info;
 248
 249         /* Initialize the MFW spinlocks */
 250 #ifdef CONFIG_ECORE_LOCK_ALLOC
 251         if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->cmd_lock)) {
 252                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
 253                 return ECORE_NOMEM;
 254         }
 255         if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->link_lock)) {
 256                 OSAL_SPIN_LOCK_DEALLOC(&p_info->cmd_lock);
 257                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
 258                 return ECORE_NOMEM;
 259         }
 260 #endif
 261         OSAL_SPIN_LOCK_INIT(&p_info->cmd_lock);
 262         OSAL_SPIN_LOCK_INIT(&p_info->link_lock);
 263
 264         OSAL_LIST_INIT(&p_info->cmd_list);
 265
 266         if (ecore_load_mcp_offsets(p_hwfn, p_ptt) != ECORE_SUCCESS) {
 267                 DP_NOTICE(p_hwfn, false, "MCP is not initialized\n");
 268                 /* Do not free mcp_info here, since public_base indicate that
 269                  * the MCP is not initialized
 270                  */
 271                 return ECORE_SUCCESS;
 272         }
 273
 274         size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
 275         p_info->mfw_mb_cur = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 276         p_info->mfw_mb_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 277         if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
 278                 goto err;
 279
 280         return ECORE_SUCCESS;
 281
 282 err:
 283         DP_NOTICE(p_hwfn, false, "Failed to allocate mcp memory\n");
 284         ecore_mcp_free(p_hwfn);
 285         return ECORE_NOMEM;
 286 }
 287
 288 static void ecore_mcp_reread_offsets(struct ecore_hwfn *p_hwfn,
 289                                      struct ecore_ptt *p_ptt)
 290 {
 291         u32 generic_por_0 = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 292
 293         /* Use MCP history register to check if MCP reset occurred between init
 294          * time and now.
 295          */
 296         if (p_hwfn->mcp_info->mcp_hist != generic_por_0) {
 297                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 298                            "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n",
 299                            p_hwfn->mcp_info->mcp_hist, generic_por_0);
 300
 301                 ecore_load_mcp_offsets(p_hwfn, p_ptt);
 302                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
 303         }
 304 }
 305
 306 enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
 307                                      struct ecore_ptt *p_ptt)
 308 {
 309         u32 org_mcp_reset_seq, seq, delay = CHIP_MCP_RESP_ITER_US, cnt = 0;
 310         enum _ecore_status_t rc = ECORE_SUCCESS;
 311
 312 #ifndef ASIC_ONLY
 313         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 314                 delay = EMUL_MCP_RESP_ITER_US;
 315 #endif
 316
 317         if (p_hwfn->mcp_info->b_block_cmd) {
 318                 DP_NOTICE(p_hwfn, false,
 319                           "The MFW is not responsive. Avoid sending MCP_RESET mailbox command.\n");
 320                 return ECORE_ABORTED;
 321         }
 322
 323         /* Ensure that only a single thread is accessing the mailbox */
 324         OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 325
 326         org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 327
 328         /* Set drv command along with the updated sequence */
 329         ecore_mcp_reread_offsets(p_hwfn, p_ptt);
 330         seq = ++p_hwfn->mcp_info->drv_mb_seq;
 331         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
 332
 333         do {
 334                 /* Wait for MFW response */
 335                 OSAL_UDELAY(delay);
 336                 /* Give the FW up to 500 second (50*1000*10usec) */
 337         } while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
 338                                                 MISCS_REG_GENERIC_POR_0)) &&
 339                  (cnt++ < ECORE_MCP_RESET_RETRIES));
 340
 341         if (org_mcp_reset_seq !=
 342             ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 343                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 344                            "MCP was reset after %d usec\n", cnt * delay);
 345         } else {
 346                 DP_ERR(p_hwfn, "Failed to reset MCP\n");
 347                 rc = ECORE_AGAIN;
 348         }
 349
 350         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 351
 352         return rc;
 353 }
 354
 355 /* Must be called while cmd_lock is acquired */
 356 static bool ecore_mcp_has_pending_cmd(struct ecore_hwfn *p_hwfn)
 357 {
 358         struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
 359
 360         /* There is at most one pending command at a certain time, and if it
 361          * exists - it is placed at the HEAD of the list.
 362          */
 363         if (!OSAL_LIST_IS_EMPTY(&p_hwfn->mcp_info->cmd_list)) {
 364                 p_cmd_elem = OSAL_LIST_FIRST_ENTRY(&p_hwfn->mcp_info->cmd_list,
 365                                                    struct ecore_mcp_cmd_elem,
 366                                                    list);
 367                 return !p_cmd_elem->b_is_completed;
 368         }
 369
 370         return false;
 371 }
 372
 373 /* Must be called while cmd_lock is acquired */
 374 static enum _ecore_status_t
 375 ecore_mcp_update_pending_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
 376 {
 377         struct ecore_mcp_mb_params *p_mb_params;
 378         struct ecore_mcp_cmd_elem *p_cmd_elem;
 379         u32 mcp_resp;
 380         u16 seq_num;
 381
 382         mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
 383         seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK);
 384
 385         /* Return if no new non-handled response has been received */
 386         if (seq_num != p_hwfn->mcp_info->drv_mb_seq)
 387                 return ECORE_AGAIN;
 388
 389         p_cmd_elem = ecore_mcp_cmd_get_elem(p_hwfn, seq_num);
 390         if (!p_cmd_elem) {
 391                 DP_ERR(p_hwfn,
 392                        "Failed to find a pending mailbox cmd that expects sequence number %d\n",
 393                        seq_num);
 394                 return ECORE_UNKNOWN_ERROR;
 395         }
 396
 397         p_mb_params = p_cmd_elem->p_mb_params;
 398
 399         /* Get the MFW response along with the sequence number */
 400         p_mb_params->mcp_resp = mcp_resp;
 401
 402         /* Get the MFW param */
 403         p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
 404
 405         /* Get the union data */
 406         if (p_mb_params->p_data_dst != OSAL_NULL &&
 407             p_mb_params->data_dst_size) {
 408                 u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 409                                       OFFSETOF(struct public_drv_mb,
 410                                                union_data);
 411                 ecore_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
 412                                   union_data_addr, p_mb_params->data_dst_size);
 413         }
 414
 415         p_cmd_elem->b_is_completed = true;
 416
 417         return ECORE_SUCCESS;
 418 }
 419
 420 /* Must be called while cmd_lock is acquired */
 421 static void __ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
 422                                       struct ecore_ptt *p_ptt,
 423                                       struct ecore_mcp_mb_params *p_mb_params,
 424                                       u16 seq_num)
 425 {
 426         union drv_union_data union_data;
 427         u32 union_data_addr;
 428
 429         /* Set the union data */
 430         union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 431                           OFFSETOF(struct public_drv_mb, union_data);
 432         OSAL_MEM_ZERO(&union_data, sizeof(union_data));
 433         if (p_mb_params->p_data_src != OSAL_NULL && p_mb_params->data_src_size)
 434                 OSAL_MEMCPY(&union_data, p_mb_params->p_data_src,
 435                             p_mb_params->data_src_size);
 436         ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
 437                         sizeof(union_data));
 438
 439         /* Set the drv param */
 440         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param);
 441
 442         /* Set the drv command along with the sequence number */
 443         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num));
 444
 445         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 446                    "MFW mailbox: command 0x%08x param 0x%08x\n",
 447                    (p_mb_params->cmd | seq_num), p_mb_params->param);
 448 }
 449
 450 static void ecore_mcp_cmd_set_blocking(struct ecore_hwfn *p_hwfn,
 451                                        bool block_cmd)
 452 {
 453         p_hwfn->mcp_info->b_block_cmd = block_cmd;
 454
 455         DP_INFO(p_hwfn, "%s sending of mailbox commands to the MFW\n",
 456                 block_cmd ? "Block" : "Unblock");
 457 }
 458
 459 void ecore_mcp_print_cpu_info(struct ecore_hwfn *p_hwfn,
 460                               struct ecore_ptt *p_ptt)
 461 {
 462         u32 cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2;
 463
 464         cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
 465         cpu_state = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
 466         cpu_pc_0 = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER);
 467         OSAL_UDELAY(CHIP_MCP_RESP_ITER_US);
 468         cpu_pc_1 = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER);
 469         OSAL_UDELAY(CHIP_MCP_RESP_ITER_US);
 470         cpu_pc_2 = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER);
 471
 472         DP_NOTICE(p_hwfn, false,
 473                   "MCP CPU info: mode 0x%08x, state 0x%08x, pc {0x%08x, 0x%08x, 0x%08x}\n",
 474                   cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2);
 475 }
 476
 477 static enum _ecore_status_t
 478 _ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
 479                          struct ecore_mcp_mb_params *p_mb_params,
 480                          u32 max_retries, u32 delay)
 481 {
 482         struct ecore_mcp_cmd_elem *p_cmd_elem;
 483         u32 cnt = 0;
 484         u16 seq_num;
 485         enum _ecore_status_t rc = ECORE_SUCCESS;
 486
 487         /* Wait until the mailbox is non-occupied */
 488         do {
 489                 /* Exit the loop if there is no pending command, or if the
 490                  * pending command is completed during this iteration.
 491                  * The spinlock stays locked until the command is sent.
 492                  */
 493
 494                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 495
 496                 if (!ecore_mcp_has_pending_cmd(p_hwfn))
 497                         break;
 498
 499                 rc = ecore_mcp_update_pending_cmd(p_hwfn, p_ptt);
 500                 if (rc == ECORE_SUCCESS)
 501                         break;
 502                 else if (rc != ECORE_AGAIN)
 503                         goto err;
 504
 505                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 506                 OSAL_UDELAY(delay);
 507                 OSAL_MFW_CMD_PREEMPT(p_hwfn);
 508         } while (++cnt < max_retries);
 509
 510         if (cnt >= max_retries) {
 511                 DP_NOTICE(p_hwfn, false,
 512                           "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n",
 513                           p_mb_params->cmd, p_mb_params->param);
 514                 return ECORE_AGAIN;
 515         }
 516
 517         /* Send the mailbox command */
 518         ecore_mcp_reread_offsets(p_hwfn, p_ptt);
 519         seq_num = ++p_hwfn->mcp_info->drv_mb_seq;
 520         p_cmd_elem = ecore_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num);
 521         if (!p_cmd_elem) {
 522                 rc = ECORE_NOMEM;
 523                 goto err;
 524         }
 525
 526         __ecore_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num);
 527         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 528
 529         /* Wait for the MFW response */
 530         do {
 531                 /* Exit the loop if the command is already completed, or if the
 532                  * command is completed during this iteration.
 533                  * The spinlock stays locked until the list element is removed.
 534                  */
 535
 536                 OSAL_UDELAY(delay);
 537                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 538
 539                 if (p_cmd_elem->b_is_completed)
 540                         break;
 541
 542                 rc = ecore_mcp_update_pending_cmd(p_hwfn, p_ptt);
 543                 if (rc == ECORE_SUCCESS)
 544                         break;
 545                 else if (rc != ECORE_AGAIN)
 546                         goto err;
 547
 548                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 549                 OSAL_MFW_CMD_PREEMPT(p_hwfn);
 550         } while (++cnt < max_retries);
 551
 552         if (cnt >= max_retries) {
 553                 DP_NOTICE(p_hwfn, false,
 554                           "The MFW failed to respond to command 0x%08x [param 0x%08x].\n",
 555                           p_mb_params->cmd, p_mb_params->param);
 556                 ecore_mcp_print_cpu_info(p_hwfn, p_ptt);
 557
 558                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 559                 ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 560                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 561
 562                 ecore_mcp_cmd_set_blocking(p_hwfn, true);
 563                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_MFW_RESP_FAIL);
 564                 return ECORE_AGAIN;
 565         }
 566
 567         ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 568         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 569
 570         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 571                    "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n",
 572                    p_mb_params->mcp_resp, p_mb_params->mcp_param,
 573                    (cnt * delay) / 1000, (cnt * delay) % 1000);
 574
 575         /* Clear the sequence number from the MFW response */
 576         p_mb_params->mcp_resp &= FW_MSG_CODE_MASK;
 577
 578         return ECORE_SUCCESS;
 579
 580 err:
 581         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 582         return rc;
 583 }
 584
 585 static enum _ecore_status_t
 586 ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
 587                         struct ecore_ptt *p_ptt,
 588                         struct ecore_mcp_mb_params *p_mb_params)
 589 {
 590         osal_size_t union_data_size = sizeof(union drv_union_data);
 591         u32 max_retries = ECORE_DRV_MB_MAX_RETRIES;
 592         u32 delay = CHIP_MCP_RESP_ITER_US;
 593
 594 #ifndef ASIC_ONLY
 595         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 596                 delay = EMUL_MCP_RESP_ITER_US;
 597         /* There is a built-in delay of 100usec in each MFW response read */
 598         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
 599                 max_retries /= 10;
 600 #endif
 601
 602         /* MCP not initialized */
 603         if (!ecore_mcp_is_init(p_hwfn)) {
 604                 DP_NOTICE(p_hwfn, true, "MFW is not initialized!\n");
 605                 return ECORE_BUSY;
 606         }
 607
 608         if (p_mb_params->data_src_size > union_data_size ||
 609             p_mb_params->data_dst_size > union_data_size) {
 610                 DP_ERR(p_hwfn,
 611                        "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
 612                        p_mb_params->data_src_size, p_mb_params->data_dst_size,
 613                        union_data_size);
 614                 return ECORE_INVAL;
 615         }
 616
 617         if (p_hwfn->mcp_info->b_block_cmd) {
 618                 DP_NOTICE(p_hwfn, false,
 619                           "The MFW is not responsive. Avoid sending mailbox command 0x%08x [param 0x%08x].\n",
 620                           p_mb_params->cmd, p_mb_params->param);
 621                 return ECORE_ABORTED;
 622         }
 623
 624         return _ecore_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries,
 625                                         delay);
 626 }
 627
 628 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
 629                                    struct ecore_ptt *p_ptt, u32 cmd, u32 param,
 630                                    u32 *o_mcp_resp, u32 *o_mcp_param)
 631 {
 632         struct ecore_mcp_mb_params mb_params;
 633         enum _ecore_status_t rc;
 634
 635 #ifndef ASIC_ONLY
 636         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 637                 if (cmd == DRV_MSG_CODE_UNLOAD_REQ) {
 638                         loaded--;
 639                         loaded_port[p_hwfn->port_id]--;
 640                         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n",
 641                                    loaded);
 642                 }
 643                 return ECORE_SUCCESS;
 644         }
 645 #endif
 646
 647         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 648         mb_params.cmd = cmd;
 649         mb_params.param = param;
 650         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 651         if (rc != ECORE_SUCCESS)
 652                 return rc;
 653
 654         *o_mcp_resp = mb_params.mcp_resp;
 655         *o_mcp_param = mb_params.mcp_param;
 656
 657         return ECORE_SUCCESS;
 658 }
 659
 660 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
 661                                           struct ecore_ptt *p_ptt,
 662                                           u32 cmd,
 663                                           u32 param,
 664                                           u32 *o_mcp_resp,
 665                                           u32 *o_mcp_param,
 666                                           u32 i_txn_size, u32 *i_buf)
 667 {
 668         struct ecore_mcp_mb_params mb_params;
 669         enum _ecore_status_t rc;
 670
 671         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 672         mb_params.cmd = cmd;
 673         mb_params.param = param;
 674         mb_params.p_data_src = i_buf;
 675         mb_params.data_src_size = (u8)i_txn_size;
 676         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 677         if (rc != ECORE_SUCCESS)
 678                 return rc;
 679
 680         *o_mcp_resp = mb_params.mcp_resp;
 681         *o_mcp_param = mb_params.mcp_param;
 682
 683         return ECORE_SUCCESS;
 684 }
 685
 686 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
 687                                           struct ecore_ptt *p_ptt,
 688                                           u32 cmd,
 689                                           u32 param,
 690                                           u32 *o_mcp_resp,
 691                                           u32 *o_mcp_param,
 692                                           u32 *o_txn_size, u32 *o_buf)
 693 {
 694         struct ecore_mcp_mb_params mb_params;
 695         u8 raw_data[MCP_DRV_NVM_BUF_LEN];
 696         enum _ecore_status_t rc;
 697
 698         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 699         mb_params.cmd = cmd;
 700         mb_params.param = param;
 701         mb_params.p_data_dst = raw_data;
 702
 703         /* Use the maximal value since the actual one is part of the response */
 704         mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
 705
 706         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 707         if (rc != ECORE_SUCCESS)
 708                 return rc;
 709
 710         *o_mcp_resp = mb_params.mcp_resp;
 711         *o_mcp_param = mb_params.mcp_param;
 712
 713         *o_txn_size = *o_mcp_param;
 714         /* @DPDK */
 715         OSAL_MEMCPY(o_buf, raw_data, RTE_MIN(*o_txn_size, MCP_DRV_NVM_BUF_LEN));
 716
 717         return ECORE_SUCCESS;
 718 }
 719
 720 #ifndef ASIC_ONLY
 721 static void ecore_mcp_mf_workaround(struct ecore_hwfn *p_hwfn,
 722                                     u32 *p_load_code)
 723 {
 724         static int load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 725
 726         if (!loaded)
 727                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 728         else if (!loaded_port[p_hwfn->port_id])
 729                 load_phase = FW_MSG_CODE_DRV_LOAD_PORT;
 730         else
 731                 load_phase = FW_MSG_CODE_DRV_LOAD_FUNCTION;
 732
 733         /* On CMT, always tell that it's engine */
 734         if (ECORE_IS_CMT(p_hwfn->p_dev))
 735                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 736
 737         *p_load_code = load_phase;
 738         loaded++;
 739         loaded_port[p_hwfn->port_id]++;
 740
 741         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 742                    "Load phase: %x load cnt: 0x%x port id=%d port_load=%d\n",
 743                    *p_load_code, loaded, p_hwfn->port_id,
 744                    loaded_port[p_hwfn->port_id]);
 745 }
 746 #endif
 747
 748 static bool
 749 ecore_mcp_can_force_load(u8 drv_role, u8 exist_drv_role,
 750                          enum ecore_override_force_load override_force_load)
 751 {
 752         bool can_force_load = false;
 753
 754         switch (override_force_load) {
 755         case ECORE_OVERRIDE_FORCE_LOAD_ALWAYS:
 756                 can_force_load = true;
 757                 break;
 758         case ECORE_OVERRIDE_FORCE_LOAD_NEVER:
 759                 can_force_load = false;
 760                 break;
 761         default:
 762                 can_force_load = (drv_role == DRV_ROLE_OS &&
 763                                   exist_drv_role == DRV_ROLE_PREBOOT) ||
 764                                  (drv_role == DRV_ROLE_KDUMP &&
 765                                   exist_drv_role == DRV_ROLE_OS);
 766                 break;
 767         }
 768
 769         return can_force_load;
 770 }
 771
 772 static enum _ecore_status_t ecore_mcp_cancel_load_req(struct ecore_hwfn *p_hwfn,
 773                                                       struct ecore_ptt *p_ptt)
 774 {
 775         u32 resp = 0, param = 0;
 776         enum _ecore_status_t rc;
 777
 778         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
 779                            &resp, &param);
 780         if (rc != ECORE_SUCCESS)
 781                 DP_NOTICE(p_hwfn, false,
 782                           "Failed to send cancel load request, rc = %d\n", rc);
 783
 784         return rc;
 785 }
 786
 787 #define CONFIG_ECORE_L2_BITMAP_IDX      (0x1 << 0)
 788 #define CONFIG_ECORE_SRIOV_BITMAP_IDX   (0x1 << 1)
 789 #define CONFIG_ECORE_ROCE_BITMAP_IDX    (0x1 << 2)
 790 #define CONFIG_ECORE_IWARP_BITMAP_IDX   (0x1 << 3)
 791 #define CONFIG_ECORE_FCOE_BITMAP_IDX    (0x1 << 4)
 792 #define CONFIG_ECORE_ISCSI_BITMAP_IDX   (0x1 << 5)
 793 #define CONFIG_ECORE_LL2_BITMAP_IDX     (0x1 << 6)
 794
 795 static u32 ecore_get_config_bitmap(void)
 796 {
 797         u32 config_bitmap = 0x0;
 798
 799 #ifdef CONFIG_ECORE_L2
 800         config_bitmap |= CONFIG_ECORE_L2_BITMAP_IDX;
 801 #endif
 802 #ifdef CONFIG_ECORE_SRIOV
 803         config_bitmap |= CONFIG_ECORE_SRIOV_BITMAP_IDX;
 804 #endif
 805 #ifdef CONFIG_ECORE_ROCE
 806         config_bitmap |= CONFIG_ECORE_ROCE_BITMAP_IDX;
 807 #endif
 808 #ifdef CONFIG_ECORE_IWARP
 809         config_bitmap |= CONFIG_ECORE_IWARP_BITMAP_IDX;
 810 #endif
 811 #ifdef CONFIG_ECORE_FCOE
 812         config_bitmap |= CONFIG_ECORE_FCOE_BITMAP_IDX;
 813 #endif
 814 #ifdef CONFIG_ECORE_ISCSI
 815         config_bitmap |= CONFIG_ECORE_ISCSI_BITMAP_IDX;
 816 #endif
 817 #ifdef CONFIG_ECORE_LL2
 818         config_bitmap |= CONFIG_ECORE_LL2_BITMAP_IDX;
 819 #endif
 820
 821         return config_bitmap;
 822 }
 823
 824 struct ecore_load_req_in_params {
 825         u8 hsi_ver;
 826 #define ECORE_LOAD_REQ_HSI_VER_DEFAULT  0
 827 #define ECORE_LOAD_REQ_HSI_VER_1        1
 828         u32 drv_ver_0;
 829         u32 drv_ver_1;
 830         u32 fw_ver;
 831         u8 drv_role;
 832         u8 timeout_val;
 833         u8 force_cmd;
 834         bool avoid_eng_reset;
 835 };
 836
 837 struct ecore_load_req_out_params {
 838         u32 load_code;
 839         u32 exist_drv_ver_0;
 840         u32 exist_drv_ver_1;
 841         u32 exist_fw_ver;
 842         u8 exist_drv_role;
 843         u8 mfw_hsi_ver;
 844         bool drv_exists;
 845 };
 846
 847 static enum _ecore_status_t
 848 __ecore_mcp_load_req(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
 849                      struct ecore_load_req_in_params *p_in_params,
 850                      struct ecore_load_req_out_params *p_out_params)
 851 {
 852         struct ecore_mcp_mb_params mb_params;
 853         struct load_req_stc load_req;
 854         struct load_rsp_stc load_rsp;
 855         u32 hsi_ver;
 856         enum _ecore_status_t rc;
 857
 858         OSAL_MEM_ZERO(&load_req, sizeof(load_req));
 859         load_req.drv_ver_0 = p_in_params->drv_ver_0;
 860         load_req.drv_ver_1 = p_in_params->drv_ver_1;
 861         load_req.fw_ver = p_in_params->fw_ver;
 862         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role);
 863         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
 864                       p_in_params->timeout_val);
 865         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_FORCE, p_in_params->force_cmd);
 866         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
 867                       p_in_params->avoid_eng_reset);
 868
 869         hsi_ver = (p_in_params->hsi_ver == ECORE_LOAD_REQ_HSI_VER_DEFAULT) ?
 870                   DRV_ID_MCP_HSI_VER_CURRENT :
 871                   (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_OFFSET);
 872
 873         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 874         mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
 875         mb_params.param = PDA_COMP | hsi_ver | p_hwfn->p_dev->drv_type;
 876         mb_params.p_data_src = &load_req;
 877         mb_params.data_src_size = sizeof(load_req);
 878         mb_params.p_data_dst = &load_rsp;
 879         mb_params.data_dst_size = sizeof(load_rsp);
 880
 881         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 882                    "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
 883                    mb_params.param,
 884                    GET_MFW_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
 885                    GET_MFW_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
 886                    GET_MFW_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
 887                    GET_MFW_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
 888
 889         if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1)
 890                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 891                            "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
 892                            load_req.drv_ver_0, load_req.drv_ver_1,
 893                            load_req.fw_ver, load_req.misc0,
 894                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE),
 895                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO),
 896                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FORCE),
 897                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FLAGS0));
 898
 899         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 900         if (rc != ECORE_SUCCESS) {
 901                 DP_NOTICE(p_hwfn, false,
 902                           "Failed to send load request, rc = %d\n", rc);
 903                 return rc;
 904         }
 905
 906         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 907                    "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
 908         p_out_params->load_code = mb_params.mcp_resp;
 909
 910         if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
 911             p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 912                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 913                            "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
 914                            load_rsp.drv_ver_0, load_rsp.drv_ver_1,
 915                            load_rsp.fw_ver, load_rsp.misc0,
 916                            GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
 917                            GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
 918                            GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0));
 919
 920                 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
 921                 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
 922                 p_out_params->exist_fw_ver = load_rsp.fw_ver;
 923                 p_out_params->exist_drv_role =
 924                         GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
 925                 p_out_params->mfw_hsi_ver =
 926                         GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
 927                 p_out_params->drv_exists =
 928                         GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
 929                         LOAD_RSP_FLAGS0_DRV_EXISTS;
 930         }
 931
 932         return ECORE_SUCCESS;
 933 }
 934
 935 static void ecore_get_mfw_drv_role(enum ecore_drv_role drv_role,
 936                                    u8 *p_mfw_drv_role)
 937 {
 938         switch (drv_role) {
 939         case ECORE_DRV_ROLE_OS:
 940                 *p_mfw_drv_role = DRV_ROLE_OS;
 941                 break;
 942         case ECORE_DRV_ROLE_KDUMP:
 943                 *p_mfw_drv_role = DRV_ROLE_KDUMP;
 944                 break;
 945         }
 946 }
 947
 948 enum ecore_load_req_force {
 949         ECORE_LOAD_REQ_FORCE_NONE,
 950         ECORE_LOAD_REQ_FORCE_PF,
 951         ECORE_LOAD_REQ_FORCE_ALL,
 952 };
 953
 954 static void ecore_get_mfw_force_cmd(enum ecore_load_req_force force_cmd,
 955                                     u8 *p_mfw_force_cmd)
 956 {
 957         switch (force_cmd) {
 958         case ECORE_LOAD_REQ_FORCE_NONE:
 959                 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
 960                 break;
 961         case ECORE_LOAD_REQ_FORCE_PF:
 962                 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
 963                 break;
 964         case ECORE_LOAD_REQ_FORCE_ALL:
 965                 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
 966                 break;
 967         }
 968 }
 969
 970 enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
 971                                         struct ecore_ptt *p_ptt,
 972                                         struct ecore_load_req_params *p_params)
 973 {
 974         struct ecore_load_req_out_params out_params;
 975         struct ecore_load_req_in_params in_params;
 976         u8 mfw_drv_role = 0, mfw_force_cmd;
 977         enum _ecore_status_t rc;
 978
 979 #ifndef ASIC_ONLY
 980         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 981                 ecore_mcp_mf_workaround(p_hwfn, &p_params->load_code);
 982                 return ECORE_SUCCESS;
 983         }
 984 #endif
 985
 986         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
 987         in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_DEFAULT;
 988         in_params.drv_ver_0 = ECORE_VERSION;
 989         in_params.drv_ver_1 = ecore_get_config_bitmap();
 990         in_params.fw_ver = STORM_FW_VERSION;
 991         ecore_get_mfw_drv_role(p_params->drv_role, &mfw_drv_role);
 992         in_params.drv_role = mfw_drv_role;
 993         in_params.timeout_val = p_params->timeout_val;
 994         ecore_get_mfw_force_cmd(ECORE_LOAD_REQ_FORCE_NONE, &mfw_force_cmd);
 995         in_params.force_cmd = mfw_force_cmd;
 996         in_params.avoid_eng_reset = p_params->avoid_eng_reset;
 997
 998         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
 999         rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
1000         if (rc != ECORE_SUCCESS)
1001                 return rc;
1002
1003         /* First handle cases where another load request should/might be sent:
1004          * - MFW expects the old interface [HSI version = 1]
1005          * - MFW responds that a force load request is required
1006          */
1007         if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
1008                 DP_INFO(p_hwfn,
1009                         "MFW refused a load request due to HSI > 1. Resending with HSI = 1.\n");
1010
1011                 in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_1;
1012                 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
1013                 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
1014                                           &out_params);
1015                 if (rc != ECORE_SUCCESS)
1016                         return rc;
1017         } else if (out_params.load_code ==
1018                    FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
1019                 if (ecore_mcp_can_force_load(in_params.drv_role,
1020                                              out_params.exist_drv_role,
1021                                              p_params->override_force_load)) {
1022                         DP_INFO(p_hwfn,
1023                                 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, 0x%08x_%08x}, existing={%d, 0x%08x, 0x%08x_%08x}]\n",
1024                                 in_params.drv_role, in_params.fw_ver,
1025                                 in_params.drv_ver_0, in_params.drv_ver_1,
1026                                 out_params.exist_drv_role,
1027                                 out_params.exist_fw_ver,
1028                                 out_params.exist_drv_ver_0,
1029                                 out_params.exist_drv_ver_1);
1030
1031                         ecore_get_mfw_force_cmd(ECORE_LOAD_REQ_FORCE_ALL,
1032                                                 &mfw_force_cmd);
1033
1034                         in_params.force_cmd = mfw_force_cmd;
1035                         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
1036                         rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
1037                                                   &out_params);
1038                         if (rc != ECORE_SUCCESS)
1039                                 return rc;
1040                 } else {
1041                         DP_NOTICE(p_hwfn, false,
1042                                   "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n",
1043                                   in_params.drv_role, in_params.fw_ver,
1044                                   in_params.drv_ver_0, in_params.drv_ver_1,
1045                                   out_params.exist_drv_role,
1046                                   out_params.exist_fw_ver,
1047                                   out_params.exist_drv_ver_0,
1048                                   out_params.exist_drv_ver_1);
1049
1050                         ecore_mcp_cancel_load_req(p_hwfn, p_ptt);
1051                         return ECORE_BUSY;
1052                 }
1053         }
1054
1055         /* Now handle the other types of responses.
1056          * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not
1057          * expected here after the additional revised load requests were sent.
1058          */
1059         switch (out_params.load_code) {
1060         case FW_MSG_CODE_DRV_LOAD_ENGINE:
1061         case FW_MSG_CODE_DRV_LOAD_PORT:
1062         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1063                 if (out_params.mfw_hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
1064                     out_params.drv_exists) {
1065                         /* The role and fw/driver version match, but the PF is
1066                          * already loaded and has not been unloaded gracefully.
1067                          * This is unexpected since a quasi-FLR request was
1068                          * previously sent as part of ecore_hw_prepare().
1069                          */
1070                         DP_NOTICE(p_hwfn, false,
1071                                   "PF is already loaded - shouldn't have got here since a quasi-FLR request was previously sent!\n");
1072                         return ECORE_INVAL;
1073                 }
1074                 break;
1075         default:
1076                 DP_NOTICE(p_hwfn, false,
1077                           "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n",
1078                           out_params.load_code);
1079                 return ECORE_BUSY;
1080         }
1081
1082         p_params->load_code = out_params.load_code;
1083
1084         return ECORE_SUCCESS;
1085 }
1086
1087 enum _ecore_status_t ecore_mcp_load_done(struct ecore_hwfn *p_hwfn,
1088                                          struct ecore_ptt *p_ptt)
1089 {
1090         u32 resp = 0, param = 0;
1091         enum _ecore_status_t rc;
1092
1093         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp,
1094                            &param);
1095         if (rc != ECORE_SUCCESS) {
1096                 DP_NOTICE(p_hwfn, false,
1097                           "Failed to send a LOAD_DONE command, rc = %d\n", rc);
1098                 return rc;
1099         }
1100
1101         /* Check if there is a DID mismatch between nvm-cfg/efuse */
1102         if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1103                 DP_NOTICE(p_hwfn, false,
1104                           "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1105
1106         return ECORE_SUCCESS;
1107 }
1108
1109 enum _ecore_status_t ecore_mcp_unload_req(struct ecore_hwfn *p_hwfn,
1110                                           struct ecore_ptt *p_ptt)
1111 {
1112         u32 wol_param, mcp_resp, mcp_param;
1113
1114         /* @DPDK */
1115         wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
1116
1117         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param,
1118                              &mcp_resp, &mcp_param);
1119 }
1120
1121 enum _ecore_status_t ecore_mcp_unload_done(struct ecore_hwfn *p_hwfn,
1122                                            struct ecore_ptt *p_ptt)
1123 {
1124         struct ecore_mcp_mb_params mb_params;
1125         struct mcp_mac wol_mac;
1126
1127         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1128         mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
1129
1130         return ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1131 }
1132
1133 static void ecore_mcp_handle_vf_flr(struct ecore_hwfn *p_hwfn,
1134                                     struct ecore_ptt *p_ptt)
1135 {
1136         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1137                                         PUBLIC_PATH);
1138         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1139         u32 path_addr = SECTION_ADDR(mfw_path_offsize,
1140                                      ECORE_PATH_ID(p_hwfn));
1141         u32 disabled_vfs[VF_MAX_STATIC / 32];
1142         int i;
1143
1144         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1145                    "Reading Disabled VF information from [offset %08x],"
1146                    " path_addr %08x\n",
1147                    mfw_path_offsize, path_addr);
1148
1149         for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
1150                 disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
1151                                            path_addr +
1152                                            OFFSETOF(struct public_path,
1153                                                     mcp_vf_disabled) +
1154                                            sizeof(u32) * i);
1155                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
1156                            "FLR-ed VFs [%08x,...,%08x] - %08x\n",
1157                            i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
1158         }
1159
1160         if (ecore_iov_mark_vf_flr(p_hwfn, disabled_vfs))
1161                 OSAL_VF_FLR_UPDATE(p_hwfn);
1162 }
1163
1164 enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
1165                                           struct ecore_ptt *p_ptt,
1166                                           u32 *vfs_to_ack)
1167 {
1168         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1169                                         PUBLIC_FUNC);
1170         u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1171         u32 func_addr = SECTION_ADDR(mfw_func_offsize,
1172                                      MCP_PF_ID(p_hwfn));
1173         struct ecore_mcp_mb_params mb_params;
1174         enum _ecore_status_t rc;
1175         int i;
1176
1177         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1178                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
1179                            "Acking VFs [%08x,...,%08x] - %08x\n",
1180                            i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
1181
1182         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1183         mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
1184         mb_params.p_data_src = vfs_to_ack;
1185         mb_params.data_src_size = VF_MAX_STATIC / 8;
1186         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt,
1187                                      &mb_params);
1188         if (rc != ECORE_SUCCESS) {
1189                 DP_NOTICE(p_hwfn, false,
1190                           "Failed to pass ACK for VF flr to MFW\n");
1191                 return ECORE_TIMEOUT;
1192         }
1193
1194         /* TMP - clear the ACK bits; should be done by MFW */
1195         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1196                 ecore_wr(p_hwfn, p_ptt,
1197                          func_addr +
1198                          OFFSETOF(struct public_func, drv_ack_vf_disabled) +
1199                          i * sizeof(u32), 0);
1200
1201         return rc;
1202 }
1203
1204 static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
1205                                                 struct ecore_ptt *p_ptt)
1206 {
1207         u32 transceiver_state;
1208
1209         transceiver_state = ecore_rd(p_hwfn, p_ptt,
1210                                      p_hwfn->mcp_info->port_addr +
1211                                      OFFSETOF(struct public_port,
1212                                               transceiver_data));
1213
1214         DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),
1215                    "Received transceiver state update [0x%08x] from mfw"
1216                    " [Addr 0x%x]\n",
1217                    transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +
1218                                             OFFSETOF(struct public_port,
1219                                                      transceiver_data)));
1220
1221         transceiver_state = GET_MFW_FIELD(transceiver_state,
1222                                           ETH_TRANSCEIVER_STATE);
1223
1224         if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1225                 DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
1226         else
1227                 DP_NOTICE(p_hwfn, false, "Transceiver is unplugged.\n");
1228
1229         OSAL_TRANSCEIVER_UPDATE(p_hwfn);
1230 }
1231
1232 static void ecore_mcp_read_eee_config(struct ecore_hwfn *p_hwfn,
1233                                       struct ecore_ptt *p_ptt,
1234                                       struct ecore_mcp_link_state *p_link)
1235 {
1236         u32 eee_status, val;
1237
1238         p_link->eee_adv_caps = 0;
1239         p_link->eee_lp_adv_caps = 0;
1240         eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1241                                      OFFSETOF(struct public_port, eee_status));
1242         p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT);
1243         val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET;
1244         if (val & EEE_1G_ADV)
1245                 p_link->eee_adv_caps |= ECORE_EEE_1G_ADV;
1246         if (val & EEE_10G_ADV)
1247                 p_link->eee_adv_caps |= ECORE_EEE_10G_ADV;
1248         val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET;
1249         if (val & EEE_1G_ADV)
1250                 p_link->eee_lp_adv_caps |= ECORE_EEE_1G_ADV;
1251         if (val & EEE_10G_ADV)
1252                 p_link->eee_lp_adv_caps |= ECORE_EEE_10G_ADV;
1253 }
1254
1255 static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
1256                                     struct ecore_ptt *p_ptt,
1257                                     struct public_func *p_data,
1258                                     int pfid)
1259 {
1260         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1261                                         PUBLIC_FUNC);
1262         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1263         u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1264         u32 i, size;
1265
1266         OSAL_MEM_ZERO(p_data, sizeof(*p_data));
1267
1268         size = OSAL_MIN_T(u32, sizeof(*p_data),
1269                           SECTION_SIZE(mfw_path_offsize));
1270         for (i = 0; i < size / sizeof(u32); i++)
1271                 ((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
1272                                               func_addr + (i << 2));
1273
1274         return size;
1275 }
1276
1277 static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
1278                                          struct ecore_ptt *p_ptt,
1279                                          bool b_reset)
1280 {
1281         struct ecore_mcp_link_state *p_link;
1282         u8 max_bw, min_bw;
1283         u32 status = 0;
1284
1285         /* Prevent SW/attentions from doing this at the same time */
1286         OSAL_SPIN_LOCK(&p_hwfn->mcp_info->link_lock);
1287
1288         p_link = &p_hwfn->mcp_info->link_output;
1289         OSAL_MEMSET(p_link, 0, sizeof(*p_link));
1290         if (!b_reset) {
1291                 status = ecore_rd(p_hwfn, p_ptt,
1292                                   p_hwfn->mcp_info->port_addr +
1293                                   OFFSETOF(struct public_port, link_status));
1294                 DP_VERBOSE(p_hwfn, (ECORE_MSG_LINK | ECORE_MSG_SP),
1295                            "Received link update [0x%08x] from mfw"
1296                            " [Addr 0x%x]\n",
1297                            status, (u32)(p_hwfn->mcp_info->port_addr +
1298                                           OFFSETOF(struct public_port,
1299                                                    link_status)));
1300         } else {
1301                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1302                            "Resetting link indications\n");
1303                 goto out;
1304         }
1305
1306         if (p_hwfn->b_drv_link_init) {
1307                 /* Link indication with modern MFW arrives as per-PF
1308                  * indication.
1309                  */
1310                 if (p_hwfn->mcp_info->capabilities &
1311                     FW_MB_PARAM_FEATURE_SUPPORT_VLINK) {
1312                         struct public_func shmem_info;
1313
1314                         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
1315                                                  MCP_PF_ID(p_hwfn));
1316                         p_link->link_up = !!(shmem_info.status &
1317                                              FUNC_STATUS_VIRTUAL_LINK_UP);
1318                 } else {
1319                         p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1320                 }
1321         } else {
1322                 p_link->link_up = false;
1323         }
1324
1325         p_link->full_duplex = true;
1326         switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1327         case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1328                 p_link->speed = 100000;
1329                 break;
1330         case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1331                 p_link->speed = 50000;
1332                 break;
1333         case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1334                 p_link->speed = 40000;
1335                 break;
1336         case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1337                 p_link->speed = 25000;
1338                 break;
1339         case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1340                 p_link->speed = 20000;
1341                 break;
1342         case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1343                 p_link->speed = 10000;
1344                 break;
1345         case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1346                 p_link->full_duplex = false;
1347                 /* Fall-through */
1348         case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1349                 p_link->speed = 1000;
1350                 break;
1351         default:
1352                 p_link->speed = 0;
1353         }
1354
1355         /* We never store total line speed as p_link->speed is
1356          * again changes according to bandwidth allocation.
1357          */
1358         if (p_link->link_up && p_link->speed)
1359                 p_link->line_speed = p_link->speed;
1360         else
1361                 p_link->line_speed = 0;
1362
1363         max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1364         min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1365
1366         /* Max bandwidth configuration */
1367         __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
1368                                            p_link, max_bw);
1369
1370         /* Min bandwidth configuration */
1371         __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
1372                                            p_link, min_bw);
1373         ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev, p_ptt,
1374                                               p_link->min_pf_rate);
1375
1376         p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1377         p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1378         p_link->parallel_detection = !!(status &
1379                                          LINK_STATUS_PARALLEL_DETECTION_USED);
1380         p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1381
1382         p_link->partner_adv_speed |=
1383             (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1384             ECORE_LINK_PARTNER_SPEED_1G_FD : 0;
1385         p_link->partner_adv_speed |=
1386             (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1387             ECORE_LINK_PARTNER_SPEED_1G_HD : 0;
1388         p_link->partner_adv_speed |=
1389             (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1390             ECORE_LINK_PARTNER_SPEED_10G : 0;
1391         p_link->partner_adv_speed |=
1392             (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1393             ECORE_LINK_PARTNER_SPEED_20G : 0;
1394         p_link->partner_adv_speed |=
1395             (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1396             ECORE_LINK_PARTNER_SPEED_25G : 0;
1397         p_link->partner_adv_speed |=
1398             (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1399             ECORE_LINK_PARTNER_SPEED_40G : 0;
1400         p_link->partner_adv_speed |=
1401             (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1402             ECORE_LINK_PARTNER_SPEED_50G : 0;
1403         p_link->partner_adv_speed |=
1404             (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1405             ECORE_LINK_PARTNER_SPEED_100G : 0;
1406
1407         p_link->partner_tx_flow_ctrl_en =
1408             !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1409         p_link->partner_rx_flow_ctrl_en =
1410             !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1411
1412         switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1413         case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1414                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_SYMMETRIC_PAUSE;
1415                 break;
1416         case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1417                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE;
1418                 break;
1419         case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1420                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_BOTH_PAUSE;
1421                 break;
1422         default:
1423                 p_link->partner_adv_pause = 0;
1424         }
1425
1426         p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1427
1428         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE)
1429                 ecore_mcp_read_eee_config(p_hwfn, p_ptt, p_link);
1430
1431         OSAL_LINK_UPDATE(p_hwfn);
1432 out:
1433         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->link_lock);
1434 }
1435
1436 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
1437                                         struct ecore_ptt *p_ptt, bool b_up)
1438 {
1439         struct ecore_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1440         struct ecore_mcp_mb_params mb_params;
1441         struct eth_phy_cfg phy_cfg;
1442         enum _ecore_status_t rc = ECORE_SUCCESS;
1443         u32 cmd;
1444
1445 #ifndef ASIC_ONLY
1446         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1447                 return ECORE_SUCCESS;
1448 #endif
1449
1450         /* Set the shmem configuration according to params */
1451         OSAL_MEM_ZERO(&phy_cfg, sizeof(phy_cfg));
1452         cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1453         if (!params->speed.autoneg)
1454                 phy_cfg.speed = params->speed.forced_speed;
1455         phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1456         phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1457         phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1458         phy_cfg.adv_speed = params->speed.advertised_speeds;
1459         phy_cfg.loopback_mode = params->loopback_mode;
1460
1461         /* There are MFWs that share this capability regardless of whether
1462          * this is feasible or not. And given that at the very least adv_caps
1463          * would be set internally by ecore, we want to make sure LFA would
1464          * still work.
1465          */
1466         if ((p_hwfn->mcp_info->capabilities &
1467              FW_MB_PARAM_FEATURE_SUPPORT_EEE) &&
1468             params->eee.enable) {
1469                 phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED;
1470                 if (params->eee.tx_lpi_enable)
1471                         phy_cfg.eee_cfg |= EEE_CFG_TX_LPI;
1472                 if (params->eee.adv_caps & ECORE_EEE_1G_ADV)
1473                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G;
1474                 if (params->eee.adv_caps & ECORE_EEE_10G_ADV)
1475                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G;
1476                 phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer <<
1477                                     EEE_TX_TIMER_USEC_OFFSET) &
1478                                         EEE_TX_TIMER_USEC_MASK;
1479         }
1480
1481         p_hwfn->b_drv_link_init = b_up;
1482
1483         if (b_up)
1484                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1485                            "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x\n",
1486                            phy_cfg.speed, phy_cfg.pause, phy_cfg.adv_speed,
1487                            phy_cfg.loopback_mode);
1488         else
1489                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, "Resetting link\n");
1490
1491         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1492         mb_params.cmd = cmd;
1493         mb_params.p_data_src = &phy_cfg;
1494         mb_params.data_src_size = sizeof(phy_cfg);
1495         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1496
1497         /* if mcp fails to respond we must abort */
1498         if (rc != ECORE_SUCCESS) {
1499                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1500                 return rc;
1501         }
1502
1503         /* Mimic link-change attention, done for several reasons:
1504          *  - On reset, there's no guarantee MFW would trigger
1505          *    an attention.
1506          *  - On initialization, older MFWs might not indicate link change
1507          *    during LFA, so we'll never get an UP indication.
1508          */
1509         ecore_mcp_handle_link_change(p_hwfn, p_ptt, !b_up);
1510
1511         return ECORE_SUCCESS;
1512 }
1513
1514 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
1515                                    struct ecore_ptt *p_ptt)
1516 {
1517         u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
1518
1519         /* TODO - Add support for VFs */
1520         if (IS_VF(p_hwfn->p_dev))
1521                 return ECORE_INVAL;
1522
1523         path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1524                                                  PUBLIC_PATH);
1525         path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
1526         path_addr = SECTION_ADDR(path_offsize, ECORE_PATH_ID(p_hwfn));
1527
1528         proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
1529                                  path_addr +
1530                                  OFFSETOF(struct public_path, process_kill)) &
1531             PROCESS_KILL_COUNTER_MASK;
1532
1533         return proc_kill_cnt;
1534 }
1535
1536 static void ecore_mcp_handle_process_kill(struct ecore_hwfn *p_hwfn,
1537                                           struct ecore_ptt *p_ptt)
1538 {
1539         struct ecore_dev *p_dev = p_hwfn->p_dev;
1540         u32 proc_kill_cnt;
1541
1542         /* Prevent possible attentions/interrupts during the recovery handling
1543          * and till its load phase, during which they will be re-enabled.
1544          */
1545         ecore_int_igu_disable_int(p_hwfn, p_ptt);
1546
1547         DP_NOTICE(p_hwfn, false, "Received a process kill indication\n");
1548
1549         /* The following operations should be done once, and thus in CMT mode
1550          * are carried out by only the first HW function.
1551          */
1552         if (p_hwfn != ECORE_LEADING_HWFN(p_dev))
1553                 return;
1554
1555         if (p_dev->recov_in_prog) {
1556                 DP_NOTICE(p_hwfn, false,
1557                           "Ignoring the indication since a recovery"
1558                           " process is already in progress\n");
1559                 return;
1560         }
1561
1562         p_dev->recov_in_prog = true;
1563
1564         proc_kill_cnt = ecore_get_process_kill_counter(p_hwfn, p_ptt);
1565         DP_NOTICE(p_hwfn, false, "Process kill counter: %d\n", proc_kill_cnt);
1566
1567         OSAL_SCHEDULE_RECOVERY_HANDLER(p_hwfn);
1568 }
1569
1570 static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
1571                                           struct ecore_ptt *p_ptt,
1572                                           enum MFW_DRV_MSG_TYPE type)
1573 {
1574         enum ecore_mcp_protocol_type stats_type;
1575         union ecore_mcp_protocol_stats stats;
1576         struct ecore_mcp_mb_params mb_params;
1577         u32 hsi_param;
1578         enum _ecore_status_t rc;
1579
1580         switch (type) {
1581         case MFW_DRV_MSG_GET_LAN_STATS:
1582                 stats_type = ECORE_MCP_LAN_STATS;
1583                 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1584                 break;
1585         default:
1586                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1587                            "Invalid protocol type %d\n", type);
1588                 return;
1589         }
1590
1591         OSAL_GET_PROTOCOL_STATS(p_hwfn->p_dev, stats_type, &stats);
1592
1593         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1594         mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1595         mb_params.param = hsi_param;
1596         mb_params.p_data_src = &stats;
1597         mb_params.data_src_size = sizeof(stats);
1598         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1599         if (rc != ECORE_SUCCESS)
1600                 DP_ERR(p_hwfn, "Failed to send protocol stats, rc = %d\n", rc);
1601 }
1602
1603 static void ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
1604                                     struct public_func *p_shmem_info)
1605 {
1606         struct ecore_mcp_function_info *p_info;
1607
1608         p_info = &p_hwfn->mcp_info->func_info;
1609
1610         /* TODO - bandwidth min/max should have valid values of 1-100,
1611          * as well as some indication that the feature is disabled.
1612          * Until MFW/qlediag enforce those limitations, Assume THERE IS ALWAYS
1613          * limit and correct value to min `1' and max `100' if limit isn't in
1614          * range.
1615          */
1616         p_info->bandwidth_min = (p_shmem_info->config &
1617                                  FUNC_MF_CFG_MIN_BW_MASK) >>
1618             FUNC_MF_CFG_MIN_BW_OFFSET;
1619         if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1620                 DP_INFO(p_hwfn,
1621                         "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1622                         p_info->bandwidth_min);
1623                 p_info->bandwidth_min = 1;
1624         }
1625
1626         p_info->bandwidth_max = (p_shmem_info->config &
1627                                  FUNC_MF_CFG_MAX_BW_MASK) >>
1628             FUNC_MF_CFG_MAX_BW_OFFSET;
1629         if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1630                 DP_INFO(p_hwfn,
1631                         "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1632                         p_info->bandwidth_max);
1633                 p_info->bandwidth_max = 100;
1634         }
1635 }
1636
1637 static void
1638 ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1639 {
1640         struct ecore_mcp_function_info *p_info;
1641         struct public_func shmem_info;
1642         u32 resp = 0, param = 0;
1643
1644         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1645
1646         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1647
1648         p_info = &p_hwfn->mcp_info->func_info;
1649
1650         ecore_configure_pf_min_bandwidth(p_hwfn->p_dev, p_info->bandwidth_min);
1651
1652         ecore_configure_pf_max_bandwidth(p_hwfn->p_dev, p_info->bandwidth_max);
1653
1654         /* Acknowledge the MFW */
1655         ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1656                       &param);
1657 }
1658
1659 static void ecore_mcp_update_stag(struct ecore_hwfn *p_hwfn,
1660                                   struct ecore_ptt *p_ptt)
1661 {
1662         struct public_func shmem_info;
1663         u32 resp = 0, param = 0;
1664
1665         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
1666                                  MCP_PF_ID(p_hwfn));
1667
1668         p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag &
1669                                                  FUNC_MF_CFG_OV_STAG_MASK;
1670         p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan;
1671         if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits)) {
1672                 if (p_hwfn->hw_info.ovlan != ECORE_MCP_VLAN_UNSET) {
1673                         ecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE,
1674                                  p_hwfn->hw_info.ovlan);
1675                         ecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 1);
1676
1677                         /* Configure DB to add external vlan to EDPM packets */
1678                         ecore_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 1);
1679                         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2,
1680                                  p_hwfn->hw_info.ovlan);
1681                 } else {
1682                         ecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 0);
1683                         ecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, 0);
1684
1685                         /* Configure DB to add external vlan to EDPM packets */
1686                         ecore_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 0);
1687                         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 0);
1688                 }
1689
1690                 ecore_sp_pf_update_stag(p_hwfn);
1691         }
1692
1693         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "ovlan  = %d hw_mode = 0x%x\n",
1694                    p_hwfn->mcp_info->func_info.ovlan, p_hwfn->hw_info.hw_mode);
1695         OSAL_HW_INFO_CHANGE(p_hwfn, ECORE_HW_INFO_CHANGE_OVLAN);
1696
1697         /* Acknowledge the MFW */
1698         ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0,
1699                       &resp, &param);
1700 }
1701
1702 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn)
1703 {
1704         /* A single notification should be sent to upper driver in CMT mode */
1705         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1706                 return;
1707
1708         DP_NOTICE(p_hwfn, false,
1709                   "Fan failure was detected on the network interface card"
1710                   " and it's going to be shut down.\n");
1711
1712         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FAN_FAIL);
1713 }
1714
1715 struct ecore_mdump_cmd_params {
1716         u32 cmd;
1717         void *p_data_src;
1718         u8 data_src_size;
1719         void *p_data_dst;
1720         u8 data_dst_size;
1721         u32 mcp_resp;
1722 };
1723
1724 static enum _ecore_status_t
1725 ecore_mcp_mdump_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1726                     struct ecore_mdump_cmd_params *p_mdump_cmd_params)
1727 {
1728         struct ecore_mcp_mb_params mb_params;
1729         enum _ecore_status_t rc;
1730
1731         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1732         mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD;
1733         mb_params.param = p_mdump_cmd_params->cmd;
1734         mb_params.p_data_src = p_mdump_cmd_params->p_data_src;
1735         mb_params.data_src_size = p_mdump_cmd_params->data_src_size;
1736         mb_params.p_data_dst = p_mdump_cmd_params->p_data_dst;
1737         mb_params.data_dst_size = p_mdump_cmd_params->data_dst_size;
1738         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1739         if (rc != ECORE_SUCCESS)
1740                 return rc;
1741
1742         p_mdump_cmd_params->mcp_resp = mb_params.mcp_resp;
1743
1744         if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) {
1745                 DP_INFO(p_hwfn,
1746                         "The mdump sub command is unsupported by the MFW [mdump_cmd 0x%x]\n",
1747                         p_mdump_cmd_params->cmd);
1748                 rc = ECORE_NOTIMPL;
1749         } else if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
1750                 DP_INFO(p_hwfn,
1751                         "The mdump command is not supported by the MFW\n");
1752                 rc = ECORE_NOTIMPL;
1753         }
1754
1755         return rc;
1756 }
1757
1758 static enum _ecore_status_t ecore_mcp_mdump_ack(struct ecore_hwfn *p_hwfn,
1759                                                 struct ecore_ptt *p_ptt)
1760 {
1761         struct ecore_mdump_cmd_params mdump_cmd_params;
1762
1763         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1764         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_ACK;
1765
1766         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1767 }
1768
1769 enum _ecore_status_t ecore_mcp_mdump_set_values(struct ecore_hwfn *p_hwfn,
1770                                                 struct ecore_ptt *p_ptt,
1771                                                 u32 epoch)
1772 {
1773         struct ecore_mdump_cmd_params mdump_cmd_params;
1774
1775         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1776         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_SET_VALUES;
1777         mdump_cmd_params.p_data_src = &epoch;
1778         mdump_cmd_params.data_src_size = sizeof(epoch);
1779
1780         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1781 }
1782
1783 enum _ecore_status_t ecore_mcp_mdump_trigger(struct ecore_hwfn *p_hwfn,
1784                                              struct ecore_ptt *p_ptt)
1785 {
1786         struct ecore_mdump_cmd_params mdump_cmd_params;
1787
1788         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1789         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_TRIGGER;
1790
1791         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1792 }
1793
1794 static enum _ecore_status_t
1795 ecore_mcp_mdump_get_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1796                            struct mdump_config_stc *p_mdump_config)
1797 {
1798         struct ecore_mdump_cmd_params mdump_cmd_params;
1799         enum _ecore_status_t rc;
1800
1801         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1802         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_CONFIG;
1803         mdump_cmd_params.p_data_dst = p_mdump_config;
1804         mdump_cmd_params.data_dst_size = sizeof(*p_mdump_config);
1805
1806         rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1807         if (rc != ECORE_SUCCESS)
1808                 return rc;
1809
1810         if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1811                 DP_INFO(p_hwfn,
1812                         "Failed to get the mdump configuration and logs info [mcp_resp 0x%x]\n",
1813                         mdump_cmd_params.mcp_resp);
1814                 rc = ECORE_UNKNOWN_ERROR;
1815         }
1816
1817         return rc;
1818 }
1819
1820 enum _ecore_status_t
1821 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1822                          struct ecore_mdump_info *p_mdump_info)
1823 {
1824         u32 addr, global_offsize, global_addr;
1825         struct mdump_config_stc mdump_config;
1826         enum _ecore_status_t rc;
1827
1828         OSAL_MEMSET(p_mdump_info, 0, sizeof(*p_mdump_info));
1829
1830         addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1831                                     PUBLIC_GLOBAL);
1832         global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1833         global_addr = SECTION_ADDR(global_offsize, 0);
1834         p_mdump_info->reason = ecore_rd(p_hwfn, p_ptt,
1835                                         global_addr +
1836                                         OFFSETOF(struct public_global,
1837                                                  mdump_reason));
1838
1839         if (p_mdump_info->reason) {
1840                 rc = ecore_mcp_mdump_get_config(p_hwfn, p_ptt, &mdump_config);
1841                 if (rc != ECORE_SUCCESS)
1842                         return rc;
1843
1844                 p_mdump_info->version = mdump_config.version;
1845                 p_mdump_info->config = mdump_config.config;
1846                 p_mdump_info->epoch = mdump_config.epoc;
1847                 p_mdump_info->num_of_logs = mdump_config.num_of_logs;
1848                 p_mdump_info->valid_logs = mdump_config.valid_logs;
1849
1850                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1851                            "MFW mdump info: reason %d, version 0x%x, config 0x%x, epoch 0x%x, num_of_logs 0x%x, valid_logs 0x%x\n",
1852                            p_mdump_info->reason, p_mdump_info->version,
1853                            p_mdump_info->config, p_mdump_info->epoch,
1854                            p_mdump_info->num_of_logs, p_mdump_info->valid_logs);
1855         } else {
1856                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1857                            "MFW mdump info: reason %d\n", p_mdump_info->reason);
1858         }
1859
1860         return ECORE_SUCCESS;
1861 }
1862
1863 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
1864                                                 struct ecore_ptt *p_ptt)
1865 {
1866         struct ecore_mdump_cmd_params mdump_cmd_params;
1867
1868         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1869         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLEAR_LOGS;
1870
1871         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1872 }
1873
1874 enum _ecore_status_t
1875 ecore_mcp_mdump_get_retain(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1876                            struct ecore_mdump_retain_data *p_mdump_retain)
1877 {
1878         struct ecore_mdump_cmd_params mdump_cmd_params;
1879         struct mdump_retain_data_stc mfw_mdump_retain;
1880         enum _ecore_status_t rc;
1881
1882         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1883         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_RETAIN;
1884         mdump_cmd_params.p_data_dst = &mfw_mdump_retain;
1885         mdump_cmd_params.data_dst_size = sizeof(mfw_mdump_retain);
1886
1887         rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1888         if (rc != ECORE_SUCCESS)
1889                 return rc;
1890
1891         if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1892                 DP_INFO(p_hwfn,
1893                         "Failed to get the mdump retained data [mcp_resp 0x%x]\n",
1894                         mdump_cmd_params.mcp_resp);
1895                 return ECORE_UNKNOWN_ERROR;
1896         }
1897
1898         p_mdump_retain->valid = mfw_mdump_retain.valid;
1899         p_mdump_retain->epoch = mfw_mdump_retain.epoch;
1900         p_mdump_retain->pf = mfw_mdump_retain.pf;
1901         p_mdump_retain->status = mfw_mdump_retain.status;
1902
1903         return ECORE_SUCCESS;
1904 }
1905
1906 enum _ecore_status_t ecore_mcp_mdump_clr_retain(struct ecore_hwfn *p_hwfn,
1907                                                 struct ecore_ptt *p_ptt)
1908 {
1909         struct ecore_mdump_cmd_params mdump_cmd_params;
1910
1911         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1912         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLR_RETAIN;
1913
1914         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1915 }
1916
1917 static void ecore_mcp_handle_critical_error(struct ecore_hwfn *p_hwfn,
1918                                             struct ecore_ptt *p_ptt)
1919 {
1920         struct ecore_mdump_retain_data mdump_retain;
1921         enum _ecore_status_t rc;
1922
1923         /* In CMT mode - no need for more than a single acknowledgment to the
1924          * MFW, and no more than a single notification to the upper driver.
1925          */
1926         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1927                 return;
1928
1929         rc = ecore_mcp_mdump_get_retain(p_hwfn, p_ptt, &mdump_retain);
1930         if (rc == ECORE_SUCCESS && mdump_retain.valid) {
1931                 DP_NOTICE(p_hwfn, false,
1932                           "The MFW notified that a critical error occurred in the device [epoch 0x%08x, pf 0x%x, status 0x%08x]\n",
1933                           mdump_retain.epoch, mdump_retain.pf,
1934                           mdump_retain.status);
1935         } else {
1936                 DP_NOTICE(p_hwfn, false,
1937                           "The MFW notified that a critical error occurred in the device\n");
1938         }
1939
1940         if (p_hwfn->p_dev->allow_mdump) {
1941                 DP_NOTICE(p_hwfn, false,
1942                           "Not acknowledging the notification to allow the MFW crash dump\n");
1943                 return;
1944         }
1945
1946         DP_NOTICE(p_hwfn, false,
1947                   "Acknowledging the notification to not allow the MFW crash dump [driver debug data collection is preferable]\n");
1948         ecore_mcp_mdump_ack(p_hwfn, p_ptt);
1949         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
1950 }
1951
1952 void
1953 ecore_mcp_read_ufp_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1954 {
1955         struct public_func shmem_info;
1956         u32 port_cfg, val;
1957
1958         if (!OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits))
1959                 return;
1960
1961         OSAL_MEMSET(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info));
1962         port_cfg = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1963                             OFFSETOF(struct public_port, oem_cfg_port));
1964         val = GET_MFW_FIELD(port_cfg, OEM_CFG_CHANNEL_TYPE);
1965         if (val != OEM_CFG_CHANNEL_TYPE_STAGGED)
1966                 DP_NOTICE(p_hwfn, false, "Incorrect UFP Channel type  %d\n",
1967                           val);
1968
1969         val = GET_MFW_FIELD(port_cfg, OEM_CFG_SCHED_TYPE);
1970         if (val == OEM_CFG_SCHED_TYPE_ETS)
1971                 p_hwfn->ufp_info.mode = ECORE_UFP_MODE_ETS;
1972         else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW)
1973                 p_hwfn->ufp_info.mode = ECORE_UFP_MODE_VNIC_BW;
1974         else
1975                 DP_NOTICE(p_hwfn, false, "Unknown UFP scheduling mode %d\n",
1976                           val);
1977
1978         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
1979                                  MCP_PF_ID(p_hwfn));
1980         val = GET_MFW_FIELD(shmem_info.oem_cfg_func, OEM_CFG_FUNC_TC);
1981         p_hwfn->ufp_info.tc = (u8)val;
1982         val = GET_MFW_FIELD(shmem_info.oem_cfg_func,
1983                             OEM_CFG_FUNC_HOST_PRI_CTRL);
1984         if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC)
1985                 p_hwfn->ufp_info.pri_type = ECORE_UFP_PRI_VNIC;
1986         else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS)
1987                 p_hwfn->ufp_info.pri_type = ECORE_UFP_PRI_OS;
1988         else
1989                 DP_NOTICE(p_hwfn, false, "Unknown Host priority control %d\n",
1990                           val);
1991
1992         DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
1993                    "UFP shmem config: mode = %d tc = %d pri_type = %d\n",
1994                    p_hwfn->ufp_info.mode, p_hwfn->ufp_info.tc,
1995                    p_hwfn->ufp_info.pri_type);
1996 }
1997
1998 static enum _ecore_status_t
1999 ecore_mcp_handle_ufp_event(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
2000 {
2001         ecore_mcp_read_ufp_config(p_hwfn, p_ptt);
2002
2003         if (p_hwfn->ufp_info.mode == ECORE_UFP_MODE_VNIC_BW) {
2004                 p_hwfn->qm_info.ooo_tc = p_hwfn->ufp_info.tc;
2005                 p_hwfn->hw_info.offload_tc = p_hwfn->ufp_info.tc;
2006
2007                 ecore_qm_reconf(p_hwfn, p_ptt);
2008         } else {
2009                 /* Merge UFP TC with the dcbx TC data */
2010                 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
2011                                             ECORE_DCBX_OPERATIONAL_MIB);
2012         }
2013
2014         /* update storm FW with negotiation results */
2015         ecore_sp_pf_update_ufp(p_hwfn);
2016
2017         return ECORE_SUCCESS;
2018 }
2019
2020 enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
2021                                              struct ecore_ptt *p_ptt)
2022 {
2023         struct ecore_mcp_info *info = p_hwfn->mcp_info;
2024         enum _ecore_status_t rc = ECORE_SUCCESS;
2025         bool found = false;
2026         u16 i;
2027
2028         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Received message from MFW\n");
2029
2030         /* Read Messages from MFW */
2031         ecore_mcp_read_mb(p_hwfn, p_ptt);
2032
2033         /* Compare current messages to old ones */
2034         for (i = 0; i < info->mfw_mb_length; i++) {
2035                 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
2036                         continue;
2037
2038                 found = true;
2039
2040                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2041                            "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
2042                            i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
2043
2044                 switch (i) {
2045                 case MFW_DRV_MSG_LINK_CHANGE:
2046                         ecore_mcp_handle_link_change(p_hwfn, p_ptt, false);
2047                         break;
2048                 case MFW_DRV_MSG_VF_DISABLED:
2049                         ecore_mcp_handle_vf_flr(p_hwfn, p_ptt);
2050                         break;
2051                 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
2052                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
2053                                                     ECORE_DCBX_REMOTE_LLDP_MIB);
2054                         break;
2055                 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
2056                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
2057                                                     ECORE_DCBX_REMOTE_MIB);
2058                         break;
2059                 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
2060                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
2061                                                     ECORE_DCBX_OPERATIONAL_MIB);
2062                         /* clear the user-config cache */
2063                         OSAL_MEMSET(&p_hwfn->p_dcbx_info->set, 0,
2064                                     sizeof(struct ecore_dcbx_set));
2065                         break;
2066                 case MFW_DRV_MSG_LLDP_RECEIVED_TLVS_UPDATED:
2067                         ecore_lldp_mib_update_event(p_hwfn, p_ptt);
2068                         break;
2069                 case MFW_DRV_MSG_OEM_CFG_UPDATE:
2070                         ecore_mcp_handle_ufp_event(p_hwfn, p_ptt);
2071                         break;
2072                 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
2073                         ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
2074                         break;
2075                 case MFW_DRV_MSG_ERROR_RECOVERY:
2076                         ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
2077                         break;
2078                 case MFW_DRV_MSG_GET_LAN_STATS:
2079                 case MFW_DRV_MSG_GET_FCOE_STATS:
2080                 case MFW_DRV_MSG_GET_ISCSI_STATS:
2081                 case MFW_DRV_MSG_GET_RDMA_STATS:
2082                         ecore_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
2083                         break;
2084                 case MFW_DRV_MSG_BW_UPDATE:
2085                         ecore_mcp_update_bw(p_hwfn, p_ptt);
2086                         break;
2087                 case MFW_DRV_MSG_S_TAG_UPDATE:
2088                         ecore_mcp_update_stag(p_hwfn, p_ptt);
2089                         break;
2090                 case MFW_DRV_MSG_FAILURE_DETECTED:
2091                         ecore_mcp_handle_fan_failure(p_hwfn);
2092                         break;
2093                 case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED:
2094                         ecore_mcp_handle_critical_error(p_hwfn, p_ptt);
2095                         break;
2096                 default:
2097                         DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
2098                         rc = ECORE_INVAL;
2099                 }
2100         }
2101
2102         /* ACK everything */
2103         for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
2104                 OSAL_BE32 val = OSAL_CPU_TO_BE32(((u32 *)info->mfw_mb_cur)[i]);
2105
2106                 /* MFW expect answer in BE, so we force write in that format */
2107                 ecore_wr(p_hwfn, p_ptt,
2108                          info->mfw_mb_addr + sizeof(u32) +
2109                          MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
2110                          sizeof(u32) + i * sizeof(u32), val);
2111         }
2112
2113         if (!found) {
2114                 DP_NOTICE(p_hwfn, false,
2115                           "Received an MFW message indication but no"
2116                           " new message!\n");
2117                 rc = ECORE_INVAL;
2118         }
2119
2120         /* Copy the new mfw messages into the shadow */
2121         OSAL_MEMCPY(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
2122
2123         return rc;
2124 }
2125
2126 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
2127                                            struct ecore_ptt *p_ptt,
2128                                            u32 *p_mfw_ver,
2129                                            u32 *p_running_bundle_id)
2130 {
2131         u32 global_offsize;
2132
2133 #ifndef ASIC_ONLY
2134         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2135                 DP_NOTICE(p_hwfn, false, "Emulation - can't get MFW version\n");
2136                 return ECORE_SUCCESS;
2137         }
2138 #endif
2139
2140         if (IS_VF(p_hwfn->p_dev)) {
2141                 if (p_hwfn->vf_iov_info) {
2142                         struct pfvf_acquire_resp_tlv *p_resp;
2143
2144                         p_resp = &p_hwfn->vf_iov_info->acquire_resp;
2145                         *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
2146                         return ECORE_SUCCESS;
2147                 } else {
2148                         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2149                                    "VF requested MFW version prior to ACQUIRE\n");
2150                         return ECORE_INVAL;
2151                 }
2152         }
2153
2154         global_offsize = ecore_rd(p_hwfn, p_ptt,
2155                                   SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
2156                                                        public_base,
2157                                                        PUBLIC_GLOBAL));
2158         *p_mfw_ver =
2159             ecore_rd(p_hwfn, p_ptt,
2160                      SECTION_ADDR(global_offsize,
2161                                   0) + OFFSETOF(struct public_global, mfw_ver));
2162
2163         if (p_running_bundle_id != OSAL_NULL) {
2164                 *p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
2165                                                 SECTION_ADDR(global_offsize,
2166                                                              0) +
2167                                                 OFFSETOF(struct public_global,
2168                                                          running_bundle_id));
2169         }
2170
2171         return ECORE_SUCCESS;
2172 }
2173
2174 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_hwfn *p_hwfn,
2175                                               struct ecore_ptt *p_ptt,
2176                                               u32 *p_media_type)
2177 {
2178         enum _ecore_status_t rc = ECORE_SUCCESS;
2179
2180         /* TODO - Add support for VFs */
2181         if (IS_VF(p_hwfn->p_dev))
2182                 return ECORE_INVAL;
2183
2184         if (!ecore_mcp_is_init(p_hwfn)) {
2185                 DP_NOTICE(p_hwfn, false, "MFW is not initialized!\n");
2186                 return ECORE_BUSY;
2187         }
2188
2189         if (!p_ptt) {
2190                 *p_media_type = MEDIA_UNSPECIFIED;
2191                 rc = ECORE_INVAL;
2192         } else {
2193                 *p_media_type = ecore_rd(p_hwfn, p_ptt,
2194                                          p_hwfn->mcp_info->port_addr +
2195                                          OFFSETOF(struct public_port,
2196                                                   media_type));
2197         }
2198
2199         return ECORE_SUCCESS;
2200 }
2201
2202 enum _ecore_status_t ecore_mcp_get_transceiver_data(struct ecore_hwfn *p_hwfn,
2203                                                     struct ecore_ptt *p_ptt,
2204                                                     u32 *p_tranceiver_type)
2205 {
2206         enum _ecore_status_t rc = ECORE_SUCCESS;
2207
2208         /* TODO - Add support for VFs */
2209         if (IS_VF(p_hwfn->p_dev))
2210                 return ECORE_INVAL;
2211
2212         if (!ecore_mcp_is_init(p_hwfn)) {
2213                 DP_NOTICE(p_hwfn, false, "MFW is not initialized!\n");
2214                 return ECORE_BUSY;
2215         }
2216         if (!p_ptt) {
2217                 *p_tranceiver_type = ETH_TRANSCEIVER_TYPE_NONE;
2218                 rc = ECORE_INVAL;
2219         } else {
2220                 *p_tranceiver_type = ecore_rd(p_hwfn, p_ptt,
2221                                 p_hwfn->mcp_info->port_addr +
2222                                 offsetof(struct public_port,
2223                                         transceiver_data));
2224         }
2225
2226         return rc;
2227 }
2228
2229 static int is_transceiver_ready(u32 transceiver_state, u32 transceiver_type)
2230 {
2231         if ((transceiver_state & ETH_TRANSCEIVER_STATE_PRESENT) &&
2232             ((transceiver_state & ETH_TRANSCEIVER_STATE_UPDATING) == 0x0) &&
2233             (transceiver_type != ETH_TRANSCEIVER_TYPE_NONE))
2234                 return 1;
2235
2236         return 0;
2237 }
2238
2239 enum _ecore_status_t ecore_mcp_trans_speed_mask(struct ecore_hwfn *p_hwfn,
2240                                                 struct ecore_ptt *p_ptt,
2241                                                 u32 *p_speed_mask)
2242 {
2243         u32 transceiver_data, transceiver_type, transceiver_state;
2244
2245         ecore_mcp_get_transceiver_data(p_hwfn, p_ptt, &transceiver_data);
2246
2247         transceiver_state = GET_MFW_FIELD(transceiver_data,
2248                             ETH_TRANSCEIVER_STATE);
2249
2250         transceiver_type = GET_MFW_FIELD(transceiver_data,
2251                            ETH_TRANSCEIVER_TYPE);
2252
2253         if (is_transceiver_ready(transceiver_state, transceiver_type) == 0)
2254                 return ECORE_INVAL;
2255
2256         switch (transceiver_type) {
2257         case ETH_TRANSCEIVER_TYPE_1G_LX:
2258         case ETH_TRANSCEIVER_TYPE_1G_SX:
2259         case ETH_TRANSCEIVER_TYPE_1G_PCC:
2260         case ETH_TRANSCEIVER_TYPE_1G_ACC:
2261         case ETH_TRANSCEIVER_TYPE_1000BASET:
2262                 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
2263                 break;
2264
2265         case ETH_TRANSCEIVER_TYPE_10G_SR:
2266         case ETH_TRANSCEIVER_TYPE_10G_LR:
2267         case ETH_TRANSCEIVER_TYPE_10G_LRM:
2268         case ETH_TRANSCEIVER_TYPE_10G_ER:
2269         case ETH_TRANSCEIVER_TYPE_10G_PCC:
2270         case ETH_TRANSCEIVER_TYPE_10G_ACC:
2271         case ETH_TRANSCEIVER_TYPE_4x10G:
2272                 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
2273                 break;
2274
2275         case ETH_TRANSCEIVER_TYPE_40G_LR4:
2276         case ETH_TRANSCEIVER_TYPE_40G_SR4:
2277         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR:
2278         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR:
2279                 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G |
2280                  NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
2281                 break;
2282
2283         case ETH_TRANSCEIVER_TYPE_100G_AOC:
2284         case ETH_TRANSCEIVER_TYPE_100G_SR4:
2285         case ETH_TRANSCEIVER_TYPE_100G_LR4:
2286         case ETH_TRANSCEIVER_TYPE_100G_ER4:
2287         case ETH_TRANSCEIVER_TYPE_100G_ACC:
2288                 *p_speed_mask =
2289                         NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G |
2290                         NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G;
2291                 break;
2292
2293         case ETH_TRANSCEIVER_TYPE_25G_SR:
2294         case ETH_TRANSCEIVER_TYPE_25G_LR:
2295         case ETH_TRANSCEIVER_TYPE_25G_AOC:
2296         case ETH_TRANSCEIVER_TYPE_25G_ACC_S:
2297         case ETH_TRANSCEIVER_TYPE_25G_ACC_M:
2298         case ETH_TRANSCEIVER_TYPE_25G_ACC_L:
2299                 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G;
2300                 break;
2301
2302         case ETH_TRANSCEIVER_TYPE_25G_CA_N:
2303         case ETH_TRANSCEIVER_TYPE_25G_CA_S:
2304         case ETH_TRANSCEIVER_TYPE_25G_CA_L:
2305         case ETH_TRANSCEIVER_TYPE_4x25G_CR:
2306                 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G |
2307                         NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G |
2308                         NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
2309                 break;
2310
2311         case ETH_TRANSCEIVER_TYPE_40G_CR4:
2312         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR:
2313                 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G |
2314                         NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G |
2315                         NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
2316                 break;
2317
2318         case ETH_TRANSCEIVER_TYPE_100G_CR4:
2319         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR:
2320                 *p_speed_mask =
2321                         NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G |
2322                         NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G |
2323                         NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G |
2324                         NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G |
2325                         NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G |
2326                         NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G |
2327                         NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
2328                 break;
2329
2330         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR:
2331         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR:
2332         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC:
2333                 *p_speed_mask =
2334                         NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G |
2335                         NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G |
2336                         NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G |
2337                         NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
2338                 break;
2339
2340         case ETH_TRANSCEIVER_TYPE_XLPPI:
2341                 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G;
2342                 break;
2343
2344         case ETH_TRANSCEIVER_TYPE_10G_BASET:
2345                 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G |
2346                         NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
2347                 break;
2348
2349         default:
2350                 DP_INFO(p_hwfn, "Unknown transcevier type 0x%x\n",
2351                         transceiver_type);
2352                 *p_speed_mask = 0xff;
2353                 break;
2354         }
2355
2356         return ECORE_SUCCESS;
2357 }
2358
2359 enum _ecore_status_t ecore_mcp_get_board_config(struct ecore_hwfn *p_hwfn,
2360                                                 struct ecore_ptt *p_ptt,
2361                                                 u32 *p_board_config)
2362 {
2363         u32 nvm_cfg_addr, nvm_cfg1_offset, port_cfg_addr;
2364         enum _ecore_status_t rc = ECORE_SUCCESS;
2365
2366         /* TODO - Add support for VFs */
2367         if (IS_VF(p_hwfn->p_dev))
2368                 return ECORE_INVAL;
2369
2370         if (!ecore_mcp_is_init(p_hwfn)) {
2371                 DP_NOTICE(p_hwfn, false, "MFW is not initialized!\n");
2372                 return ECORE_BUSY;
2373         }
2374         if (!p_ptt) {
2375                 *p_board_config = NVM_CFG1_PORT_PORT_TYPE_UNDEFINED;
2376                 rc = ECORE_INVAL;
2377         } else {
2378                 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt,
2379                                         MISC_REG_GEN_PURP_CR0);
2380                 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt,
2381                                            nvm_cfg_addr + 4);
2382                 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2383                         offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2384                 *p_board_config  =  ecore_rd(p_hwfn, p_ptt,
2385                                              port_cfg_addr +
2386                                              offsetof(struct nvm_cfg1_port,
2387                                              board_cfg));
2388         }
2389
2390         return rc;
2391 }
2392
2393 /* @DPDK */
2394 /* Old MFW has a global configuration for all PFs regarding RDMA support */
2395 static void
2396 ecore_mcp_get_shmem_proto_legacy(struct ecore_hwfn *p_hwfn,
2397                                  enum ecore_pci_personality *p_proto)
2398 {
2399         *p_proto = ECORE_PCI_ETH;
2400
2401         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
2402                    "According to Legacy capabilities, L2 personality is %08x\n",
2403                    (u32)*p_proto);
2404 }
2405
2406 /* @DPDK */
2407 static enum _ecore_status_t
2408 ecore_mcp_get_shmem_proto_mfw(struct ecore_hwfn *p_hwfn,
2409                               struct ecore_ptt *p_ptt,
2410                               enum ecore_pci_personality *p_proto)
2411 {
2412         u32 resp = 0, param = 0;
2413         enum _ecore_status_t rc;
2414
2415         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
2416                    "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
2417                    (u32)*p_proto, resp, param);
2418         return ECORE_SUCCESS;
2419 }
2420
2421 static enum _ecore_status_t
2422 ecore_mcp_get_shmem_proto(struct ecore_hwfn *p_hwfn,
2423                           struct public_func *p_info,
2424                           struct ecore_ptt *p_ptt,
2425                           enum ecore_pci_personality *p_proto)
2426 {
2427         enum _ecore_status_t rc = ECORE_SUCCESS;
2428
2429         switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
2430         case FUNC_MF_CFG_PROTOCOL_ETHERNET:
2431                 if (ecore_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto) !=
2432                     ECORE_SUCCESS)
2433                         ecore_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
2434                 break;
2435         default:
2436                 rc = ECORE_INVAL;
2437         }
2438
2439         return rc;
2440 }
2441
2442 enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
2443                                                     struct ecore_ptt *p_ptt)
2444 {
2445         struct ecore_mcp_function_info *info;
2446         struct public_func shmem_info;
2447
2448         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
2449         info = &p_hwfn->mcp_info->func_info;
2450
2451         info->pause_on_host = (shmem_info.config &
2452                                FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
2453
2454         if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2455                                       &info->protocol)) {
2456                 DP_ERR(p_hwfn, "Unknown personality %08x\n",
2457                        (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
2458                 return ECORE_INVAL;
2459         }
2460
2461         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
2462
2463         if (shmem_info.mac_upper || shmem_info.mac_lower) {
2464                 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
2465                 info->mac[1] = (u8)(shmem_info.mac_upper);
2466                 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
2467                 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
2468                 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
2469                 info->mac[5] = (u8)(shmem_info.mac_lower);
2470         } else {
2471                 /* TODO - are there protocols for which there's no MAC? */
2472                 DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
2473         }
2474
2475         /* TODO - are these calculations true for BE machine? */
2476         info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
2477                          (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
2478         info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
2479                          (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
2480
2481         info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
2482
2483         info->mtu = (u16)shmem_info.mtu_size;
2484
2485         if (info->mtu == 0)
2486                 info->mtu = 1500;
2487
2488         info->mtu = (u16)shmem_info.mtu_size;
2489
2490         DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
2491                    "Read configuration from shmem: pause_on_host %02x"
2492                     " protocol %02x BW [%02x - %02x]"
2493                     " MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %lx"
2494                     " node %lx ovlan %04x\n",
2495                    info->pause_on_host, info->protocol,
2496                    info->bandwidth_min, info->bandwidth_max,
2497                    info->mac[0], info->mac[1], info->mac[2],
2498                    info->mac[3], info->mac[4], info->mac[5],
2499                    (unsigned long)info->wwn_port,
2500                    (unsigned long)info->wwn_node, info->ovlan);
2501
2502         return ECORE_SUCCESS;
2503 }
2504
2505 struct ecore_mcp_link_params
2506 *ecore_mcp_get_link_params(struct ecore_hwfn *p_hwfn)
2507 {
2508         if (!p_hwfn || !p_hwfn->mcp_info)
2509                 return OSAL_NULL;
2510         return &p_hwfn->mcp_info->link_input;
2511 }
2512
2513 struct ecore_mcp_link_state
2514 *ecore_mcp_get_link_state(struct ecore_hwfn *p_hwfn)
2515 {
2516         if (!p_hwfn || !p_hwfn->mcp_info)
2517                 return OSAL_NULL;
2518
2519 #ifndef ASIC_ONLY
2520         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2521                 DP_INFO(p_hwfn, "Non-ASIC - always notify that link is up\n");
2522                 p_hwfn->mcp_info->link_output.link_up = true;
2523         }
2524 #endif
2525
2526         return &p_hwfn->mcp_info->link_output;
2527 }
2528
2529 struct ecore_mcp_link_capabilities
2530 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn)
2531 {
2532         if (!p_hwfn || !p_hwfn->mcp_info)
2533                 return OSAL_NULL;
2534         return &p_hwfn->mcp_info->link_capabilities;
2535 }
2536
2537 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
2538                                      struct ecore_ptt *p_ptt)
2539 {
2540         u32 resp = 0, param = 0;
2541         enum _ecore_status_t rc;
2542
2543         rc = ecore_mcp_cmd(p_hwfn, p_ptt,
2544                            DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, &param);
2545
2546         /* Wait for the drain to complete before returning */
2547         OSAL_MSLEEP(1020);
2548
2549         return rc;
2550 }
2551
2552 const struct ecore_mcp_function_info
2553 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn)
2554 {
2555         if (!p_hwfn || !p_hwfn->mcp_info)
2556                 return OSAL_NULL;
2557         return &p_hwfn->mcp_info->func_info;
2558 }
2559
2560 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
2561                                   struct ecore_ptt *p_ptt, u32 personalities)
2562 {
2563         enum ecore_pci_personality protocol = ECORE_PCI_DEFAULT;
2564         struct public_func shmem_info;
2565         int i, count = 0, num_pfs;
2566
2567         num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
2568
2569         for (i = 0; i < num_pfs; i++) {
2570                 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
2571                                          MCP_PF_ID_BY_REL(p_hwfn, i));
2572                 if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
2573                         continue;
2574
2575                 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2576                                               &protocol) !=
2577                     ECORE_SUCCESS)
2578                         continue;
2579
2580                 if ((1 << ((u32)protocol)) & personalities)
2581                         count++;
2582         }
2583
2584         return count;
2585 }
2586
2587 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
2588                                               struct ecore_ptt *p_ptt,
2589                                               u32 *p_flash_size)
2590 {
2591         u32 flash_size;
2592
2593 #ifndef ASIC_ONLY
2594         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2595                 DP_NOTICE(p_hwfn, false, "Emulation - can't get flash size\n");
2596                 return ECORE_INVAL;
2597         }
2598 #endif
2599
2600         if (IS_VF(p_hwfn->p_dev))
2601                 return ECORE_INVAL;
2602
2603         flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
2604         flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
2605                      MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
2606         flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_OFFSET));
2607
2608         *p_flash_size = flash_size;
2609
2610         return ECORE_SUCCESS;
2611 }
2612
2613 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
2614                                                   struct ecore_ptt *p_ptt)
2615 {
2616         struct ecore_dev *p_dev = p_hwfn->p_dev;
2617
2618         if (p_dev->recov_in_prog) {
2619                 DP_NOTICE(p_hwfn, false,
2620                           "Avoid triggering a recovery since such a process"
2621                           " is already in progress\n");
2622                 return ECORE_AGAIN;
2623         }
2624
2625         DP_NOTICE(p_hwfn, false, "Triggering a recovery process\n");
2626         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
2627
2628         return ECORE_SUCCESS;
2629 }
2630
2631 static enum _ecore_status_t
2632 ecore_mcp_config_vf_msix_bb(struct ecore_hwfn *p_hwfn,
2633                             struct ecore_ptt *p_ptt,
2634                             u8 vf_id, u8 num)
2635 {
2636         u32 resp = 0, param = 0, rc_param = 0;
2637         enum _ecore_status_t rc;
2638
2639 /* Only Leader can configure MSIX, and need to take CMT into account */
2640
2641         if (!IS_LEAD_HWFN(p_hwfn))
2642                 return ECORE_SUCCESS;
2643         num *= p_hwfn->p_dev->num_hwfns;
2644
2645         param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_OFFSET) &
2646             DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
2647         param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_OFFSET) &
2648             DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
2649
2650         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
2651                            &resp, &rc_param);
2652
2653         if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
2654                 DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
2655                           vf_id);
2656                 rc = ECORE_INVAL;
2657         } else {
2658                 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2659                            "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
2660                             num, vf_id);
2661         }
2662
2663         return rc;
2664 }
2665
2666 static enum _ecore_status_t
2667 ecore_mcp_config_vf_msix_ah(struct ecore_hwfn *p_hwfn,
2668                             struct ecore_ptt *p_ptt,
2669                             u8 num)
2670 {
2671         u32 resp = 0, param = num, rc_param = 0;
2672         enum _ecore_status_t rc;
2673
2674         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX,
2675                            param, &resp, &rc_param);
2676
2677         if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) {
2678                 DP_NOTICE(p_hwfn, true, "MFW failed to set MSI-X for VFs\n");
2679                 rc = ECORE_INVAL;
2680         } else {
2681                 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2682                            "Requested 0x%02x MSI-x interrupts for VFs\n",
2683                            num);
2684         }
2685
2686         return rc;
2687 }
2688
2689 enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
2690                                               struct ecore_ptt *p_ptt,
2691                                               u8 vf_id, u8 num)
2692 {
2693         if (ECORE_IS_BB(p_hwfn->p_dev))
2694                 return ecore_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num);
2695         else
2696                 return ecore_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num);
2697 }
2698
2699 enum _ecore_status_t
2700 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2701                            struct ecore_mcp_drv_version *p_ver)
2702 {
2703         struct ecore_mcp_mb_params mb_params;
2704         struct drv_version_stc drv_version;
2705         u32 num_words, i;
2706         void *p_name;
2707         OSAL_BE32 val;
2708         enum _ecore_status_t rc;
2709
2710 #ifndef ASIC_ONLY
2711         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
2712                 return ECORE_SUCCESS;
2713 #endif
2714
2715         OSAL_MEM_ZERO(&drv_version, sizeof(drv_version));
2716         drv_version.version = p_ver->version;
2717         num_words = (MCP_DRV_VER_STR_SIZE - 4) / 4;
2718         for (i = 0; i < num_words; i++) {
2719                 /* The driver name is expected to be in a big-endian format */
2720                 p_name = &p_ver->name[i * sizeof(u32)];
2721                 val = OSAL_CPU_TO_BE32(*(u32 *)p_name);
2722                 *(u32 *)&drv_version.name[i * sizeof(u32)] = val;
2723         }
2724
2725         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2726         mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
2727         mb_params.p_data_src = &drv_version;
2728         mb_params.data_src_size = sizeof(drv_version);
2729         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2730         if (rc != ECORE_SUCCESS)
2731                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2732
2733         return rc;
2734 }
2735
2736 /* A maximal 100 msec waiting time for the MCP to halt */
2737 #define ECORE_MCP_HALT_SLEEP_MS         10
2738 #define ECORE_MCP_HALT_MAX_RETRIES      10
2739
2740 enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
2741                                     struct ecore_ptt *p_ptt)
2742 {
2743         u32 resp = 0, param = 0, cpu_state, cnt = 0;
2744         enum _ecore_status_t rc;
2745
2746         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
2747                            &param);
2748         if (rc != ECORE_SUCCESS) {
2749                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2750                 return rc;
2751         }
2752
2753         do {
2754                 OSAL_MSLEEP(ECORE_MCP_HALT_SLEEP_MS);
2755                 cpu_state = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
2756                 if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED)
2757                         break;
2758         } while (++cnt < ECORE_MCP_HALT_MAX_RETRIES);
2759
2760         if (cnt == ECORE_MCP_HALT_MAX_RETRIES) {
2761                 DP_NOTICE(p_hwfn, false,
2762                           "Failed to halt the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
2763                           ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state);
2764                 return ECORE_BUSY;
2765         }
2766
2767         ecore_mcp_cmd_set_blocking(p_hwfn, true);
2768
2769         return ECORE_SUCCESS;
2770 }
2771
2772 #define ECORE_MCP_RESUME_SLEEP_MS       10
2773
2774 enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
2775                                       struct ecore_ptt *p_ptt)
2776 {
2777         u32 cpu_mode, cpu_state;
2778
2779         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
2780
2781         cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2782         cpu_mode &= ~MCP_REG_CPU_MODE_SOFT_HALT;
2783         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, cpu_mode);
2784
2785         OSAL_MSLEEP(ECORE_MCP_RESUME_SLEEP_MS);
2786         cpu_state = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
2787
2788         if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) {
2789                 DP_NOTICE(p_hwfn, false,
2790                           "Failed to resume the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
2791                           cpu_mode, cpu_state);
2792                 return ECORE_BUSY;
2793         }
2794
2795         ecore_mcp_cmd_set_blocking(p_hwfn, false);
2796
2797         return ECORE_SUCCESS;
2798 }
2799
2800 enum _ecore_status_t
2801 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
2802                                    struct ecore_ptt *p_ptt,
2803                                    enum ecore_ov_client client)
2804 {
2805         u32 resp = 0, param = 0;
2806         u32 drv_mb_param;
2807         enum _ecore_status_t rc;
2808
2809         switch (client) {
2810         case ECORE_OV_CLIENT_DRV:
2811                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
2812                 break;
2813         case ECORE_OV_CLIENT_USER:
2814                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
2815                 break;
2816         case ECORE_OV_CLIENT_VENDOR_SPEC:
2817                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
2818                 break;
2819         default:
2820                 DP_NOTICE(p_hwfn, true, "Invalid client type %d\n", client);
2821                 return ECORE_INVAL;
2822         }
2823
2824         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
2825                            drv_mb_param, &resp, &param);
2826         if (rc != ECORE_SUCCESS)
2827                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2828
2829         return rc;
2830 }
2831
2832 enum _ecore_status_t
2833 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
2834                                  struct ecore_ptt *p_ptt,
2835                                  enum ecore_ov_driver_state drv_state)
2836 {
2837         u32 resp = 0, param = 0;
2838         u32 drv_mb_param;
2839         enum _ecore_status_t rc;
2840
2841         switch (drv_state) {
2842         case ECORE_OV_DRIVER_STATE_NOT_LOADED:
2843                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
2844                 break;
2845         case ECORE_OV_DRIVER_STATE_DISABLED:
2846                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
2847                 break;
2848         case ECORE_OV_DRIVER_STATE_ACTIVE:
2849                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
2850                 break;
2851         default:
2852                 DP_NOTICE(p_hwfn, true, "Invalid driver state %d\n", drv_state);
2853                 return ECORE_INVAL;
2854         }
2855
2856         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
2857                            drv_mb_param, &resp, &param);
2858         if (rc != ECORE_SUCCESS)
2859                 DP_ERR(p_hwfn, "Failed to send driver state\n");
2860
2861         return rc;
2862 }
2863
2864 enum _ecore_status_t
2865 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2866                          struct ecore_fc_npiv_tbl *p_table)
2867 {
2868         return 0;
2869 }
2870
2871 enum _ecore_status_t
2872 ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2873                         u16 mtu)
2874 {
2875         u32 resp = 0, param = 0, drv_mb_param = 0;
2876         enum _ecore_status_t rc;
2877
2878         SET_MFW_FIELD(drv_mb_param, DRV_MB_PARAM_OV_MTU_SIZE, (u32)mtu);
2879         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU,
2880                            drv_mb_param, &resp, &param);
2881         if (rc != ECORE_SUCCESS)
2882                 DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc);
2883
2884         return rc;
2885 }
2886
2887 enum _ecore_status_t
2888 ecore_mcp_ov_update_mac(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2889                         u8 *mac)
2890 {
2891         struct ecore_mcp_mb_params mb_params;
2892         union drv_union_data union_data;
2893         enum _ecore_status_t rc;
2894
2895         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2896         mb_params.cmd = DRV_MSG_CODE_SET_VMAC;
2897         SET_MFW_FIELD(mb_params.param, DRV_MSG_CODE_VMAC_TYPE,
2898                       DRV_MSG_CODE_VMAC_TYPE_MAC);
2899         mb_params.param |= MCP_PF_ID(p_hwfn);
2900         OSAL_MEMCPY(&union_data.raw_data, mac, ETH_ALEN);
2901         mb_params.p_data_src = &union_data;
2902         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2903         if (rc != ECORE_SUCCESS)
2904                 DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc);
2905
2906         return rc;
2907 }
2908
2909 enum _ecore_status_t
2910 ecore_mcp_ov_update_eswitch(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2911                             enum ecore_ov_eswitch eswitch)
2912 {
2913         enum _ecore_status_t rc;
2914         u32 resp = 0, param = 0;
2915         u32 drv_mb_param;
2916
2917         switch (eswitch) {
2918         case ECORE_OV_ESWITCH_NONE:
2919                 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE;
2920                 break;
2921         case ECORE_OV_ESWITCH_VEB:
2922                 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB;
2923                 break;
2924         case ECORE_OV_ESWITCH_VEPA:
2925                 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA;
2926                 break;
2927         default:
2928                 DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch);
2929                 return ECORE_INVAL;
2930         }
2931
2932         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE,
2933                            drv_mb_param, &resp, &param);
2934         if (rc != ECORE_SUCCESS)
2935                 DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc);
2936
2937         return rc;
2938 }
2939
2940 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
2941                                        struct ecore_ptt *p_ptt,
2942                                        enum ecore_led_mode mode)
2943 {
2944         u32 resp = 0, param = 0, drv_mb_param;
2945         enum _ecore_status_t rc;
2946
2947         switch (mode) {
2948         case ECORE_LED_MODE_ON:
2949                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2950                 break;
2951         case ECORE_LED_MODE_OFF:
2952                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2953                 break;
2954         case ECORE_LED_MODE_RESTORE:
2955                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2956                 break;
2957         default:
2958                 DP_NOTICE(p_hwfn, true, "Invalid LED mode %d\n", mode);
2959                 return ECORE_INVAL;
2960         }
2961
2962         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2963                            drv_mb_param, &resp, &param);
2964         if (rc != ECORE_SUCCESS)
2965                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2966
2967         return rc;
2968 }
2969
2970 enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
2971                                              struct ecore_ptt *p_ptt,
2972                                              u32 mask_parities)
2973 {
2974         u32 resp = 0, param = 0;
2975         enum _ecore_status_t rc;
2976
2977         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2978                            mask_parities, &resp, &param);
2979
2980         if (rc != ECORE_SUCCESS) {
2981                 DP_ERR(p_hwfn,
2982                        "MCP response failure for mask parities, aborting\n");
2983         } else if (resp != FW_MSG_CODE_OK) {
2984                 DP_ERR(p_hwfn,
2985                        "MCP did not ack mask parity request. Old MFW?\n");
2986                 rc = ECORE_INVAL;
2987         }
2988
2989         return rc;
2990 }
2991
2992 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
2993                                         u8 *p_buf, u32 len)
2994 {
2995         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2996         u32 bytes_left, offset, bytes_to_copy, buf_size;
2997         u32 nvm_offset, resp, param;
2998         struct ecore_ptt *p_ptt;
2999         enum _ecore_status_t rc = ECORE_SUCCESS;
3000
3001         p_ptt = ecore_ptt_acquire(p_hwfn);
3002         if (!p_ptt)
3003                 return ECORE_BUSY;
3004
3005         bytes_left = len;
3006         offset = 0;
3007         while (bytes_left > 0) {
3008                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
3009                                            MCP_DRV_NVM_BUF_LEN);
3010                 nvm_offset = (addr + offset) | (bytes_to_copy <<
3011                                                 DRV_MB_PARAM_NVM_LEN_OFFSET);
3012                 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
3013                                           DRV_MSG_CODE_NVM_READ_NVRAM,
3014                                           nvm_offset, &resp, &param, &buf_size,
3015                                           (u32 *)(p_buf + offset));
3016                 if (rc != ECORE_SUCCESS) {
3017                         DP_NOTICE(p_dev, false,
3018                                   "ecore_mcp_nvm_rd_cmd() failed, rc = %d\n",
3019                                   rc);
3020                         resp = FW_MSG_CODE_ERROR;
3021                         break;
3022                 }
3023
3024                 if (resp != FW_MSG_CODE_NVM_OK) {
3025                         DP_NOTICE(p_dev, false,
3026                                   "nvm read failed, resp = 0x%08x\n", resp);
3027                         rc = ECORE_UNKNOWN_ERROR;
3028                         break;
3029                 }
3030
3031                 /* This can be a lengthy process, and it's possible scheduler
3032                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
3033                  */
3034                 if (bytes_left % 0x1000 <
3035                     (bytes_left - buf_size) % 0x1000)
3036                         OSAL_MSLEEP(1);
3037
3038                 offset += buf_size;
3039                 bytes_left -= buf_size;
3040         }
3041
3042         p_dev->mcp_nvm_resp = resp;
3043         ecore_ptt_release(p_hwfn, p_ptt);
3044
3045         return rc;
3046 }
3047
3048 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
3049                                         u32 addr, u8 *p_buf, u32 len)
3050 {
3051         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3052         struct ecore_ptt *p_ptt;
3053         u32 resp, param;
3054         enum _ecore_status_t rc;
3055
3056         p_ptt = ecore_ptt_acquire(p_hwfn);
3057         if (!p_ptt)
3058                 return ECORE_BUSY;
3059
3060         rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
3061                                   (cmd == ECORE_PHY_CORE_READ) ?
3062                                   DRV_MSG_CODE_PHY_CORE_READ :
3063                                   DRV_MSG_CODE_PHY_RAW_READ,
3064                                   addr, &resp, &param, &len, (u32 *)p_buf);
3065         if (rc != ECORE_SUCCESS)
3066                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
3067
3068         p_dev->mcp_nvm_resp = resp;
3069         ecore_ptt_release(p_hwfn, p_ptt);
3070
3071         return rc;
3072 }
3073
3074 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf)
3075 {
3076         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3077         struct ecore_ptt *p_ptt;
3078
3079         p_ptt = ecore_ptt_acquire(p_hwfn);
3080         if (!p_ptt)
3081                 return ECORE_BUSY;
3082
3083         OSAL_MEMCPY(p_buf, &p_dev->mcp_nvm_resp, sizeof(p_dev->mcp_nvm_resp));
3084         ecore_ptt_release(p_hwfn, p_ptt);
3085
3086         return ECORE_SUCCESS;
3087 }
3088
3089 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr)
3090 {
3091         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3092         struct ecore_ptt *p_ptt;
3093         u32 resp, param;
3094         enum _ecore_status_t rc;
3095
3096         p_ptt = ecore_ptt_acquire(p_hwfn);
3097         if (!p_ptt)
3098                 return ECORE_BUSY;
3099         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_DEL_FILE, addr,
3100                            &resp, &param);
3101         p_dev->mcp_nvm_resp = resp;
3102         ecore_ptt_release(p_hwfn, p_ptt);
3103
3104         return rc;
3105 }
3106
3107 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
3108                                                   u32 addr)
3109 {
3110         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3111         struct ecore_ptt *p_ptt;
3112         u32 resp, param;
3113         enum _ecore_status_t rc;
3114
3115         p_ptt = ecore_ptt_acquire(p_hwfn);
3116         if (!p_ptt)
3117                 return ECORE_BUSY;
3118         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, addr,
3119                            &resp, &param);
3120         p_dev->mcp_nvm_resp = resp;
3121         ecore_ptt_release(p_hwfn, p_ptt);
3122
3123         return rc;
3124 }
3125
3126 /* rc receives ECORE_INVAL as default parameter because
3127  * it might not enter the while loop if the len is 0
3128  */
3129 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
3130                                          u32 addr, u8 *p_buf, u32 len)
3131 {
3132         u32 buf_idx, buf_size, nvm_cmd, nvm_offset, resp, param;
3133         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3134         enum _ecore_status_t rc = ECORE_INVAL;
3135         struct ecore_ptt *p_ptt;
3136
3137         p_ptt = ecore_ptt_acquire(p_hwfn);
3138         if (!p_ptt)
3139                 return ECORE_BUSY;
3140
3141         switch (cmd) {
3142         case ECORE_PUT_FILE_DATA:
3143                 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
3144                 break;
3145         case ECORE_NVM_WRITE_NVRAM:
3146                 nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
3147                 break;
3148         case ECORE_EXT_PHY_FW_UPGRADE:
3149                 nvm_cmd = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE;
3150                 break;
3151         default:
3152                 DP_NOTICE(p_hwfn, true, "Invalid nvm write command 0x%x\n",
3153                           cmd);
3154                 rc = ECORE_INVAL;
3155                 goto out;
3156         }
3157
3158         buf_idx = 0;
3159         while (buf_idx < len) {
3160                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
3161                                       MCP_DRV_NVM_BUF_LEN);
3162                 nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_OFFSET) |
3163                               addr) +
3164                              buf_idx;
3165                 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset,
3166                                           &resp, &param, buf_size,
3167                                           (u32 *)&p_buf[buf_idx]);
3168                 if (rc != ECORE_SUCCESS) {
3169                         DP_NOTICE(p_dev, false,
3170                                   "ecore_mcp_nvm_write() failed, rc = %d\n",
3171                                   rc);
3172                         resp = FW_MSG_CODE_ERROR;
3173                         break;
3174                 }
3175
3176                 if (resp != FW_MSG_CODE_OK &&
3177                     resp != FW_MSG_CODE_NVM_OK &&
3178                     resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) {
3179                         DP_NOTICE(p_dev, false,
3180                                   "nvm write failed, resp = 0x%08x\n", resp);
3181                         rc = ECORE_UNKNOWN_ERROR;
3182                         break;
3183                 }
3184
3185                 /* This can be a lengthy process, and it's possible scheduler
3186                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
3187                  */
3188                 if (buf_idx % 0x1000 >
3189                     (buf_idx + buf_size) % 0x1000)
3190                         OSAL_MSLEEP(1);
3191
3192                 buf_idx += buf_size;
3193         }
3194
3195         p_dev->mcp_nvm_resp = resp;
3196 out:
3197         ecore_ptt_release(p_hwfn, p_ptt);
3198
3199         return rc;
3200 }
3201
3202 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
3203                                          u32 addr, u8 *p_buf, u32 len)
3204 {
3205         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3206         struct ecore_ptt *p_ptt;
3207         u32 resp, param, nvm_cmd;
3208         enum _ecore_status_t rc;
3209
3210         p_ptt = ecore_ptt_acquire(p_hwfn);
3211         if (!p_ptt)
3212                 return ECORE_BUSY;
3213
3214         nvm_cmd = (cmd == ECORE_PHY_CORE_WRITE) ?  DRV_MSG_CODE_PHY_CORE_WRITE :
3215                         DRV_MSG_CODE_PHY_RAW_WRITE;
3216         rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, addr,
3217                                   &resp, &param, len, (u32 *)p_buf);
3218         if (rc != ECORE_SUCCESS)
3219                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
3220         p_dev->mcp_nvm_resp = resp;
3221         ecore_ptt_release(p_hwfn, p_ptt);
3222
3223         return rc;
3224 }
3225
3226 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
3227                                                    u32 addr)
3228 {
3229         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3230         struct ecore_ptt *p_ptt;
3231         u32 resp, param;
3232         enum _ecore_status_t rc;
3233
3234         p_ptt = ecore_ptt_acquire(p_hwfn);
3235         if (!p_ptt)
3236                 return ECORE_BUSY;
3237
3238         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_SECURE_MODE, addr,
3239                            &resp, &param);
3240         p_dev->mcp_nvm_resp = resp;
3241         ecore_ptt_release(p_hwfn, p_ptt);
3242
3243         return rc;
3244 }
3245
3246 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
3247                                             struct ecore_ptt *p_ptt,
3248                                             u32 port, u32 addr, u32 offset,
3249                                             u32 len, u8 *p_buf)
3250 {
3251         u32 bytes_left, bytes_to_copy, buf_size, nvm_offset;
3252         u32 resp, param;
3253         enum _ecore_status_t rc;
3254
3255         nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) |
3256                         (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET);
3257         addr = offset;
3258         offset = 0;
3259         bytes_left = len;
3260         while (bytes_left > 0) {
3261                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
3262                                            MAX_I2C_TRANSACTION_SIZE);
3263                 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
3264                                DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
3265                 nvm_offset |= ((addr + offset) <<
3266                                 DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET);
3267                 nvm_offset |= (bytes_to_copy <<
3268                                DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET);
3269                 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
3270                                           DRV_MSG_CODE_TRANSCEIVER_READ,
3271                                           nvm_offset, &resp, &param, &buf_size,
3272                                           (u32 *)(p_buf + offset));
3273                 if (rc != ECORE_SUCCESS) {
3274                         DP_NOTICE(p_hwfn, false,
3275                                   "Failed to send a transceiver read command to the MFW. rc = %d.\n",
3276                                   rc);
3277                         return rc;
3278                 }
3279
3280                 if (resp == FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT)
3281                         return ECORE_NODEV;
3282                 else if (resp != FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
3283                         return ECORE_UNKNOWN_ERROR;
3284
3285                 offset += buf_size;
3286                 bytes_left -= buf_size;
3287         }
3288
3289         return ECORE_SUCCESS;
3290 }
3291
3292 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
3293                                              struct ecore_ptt *p_ptt,
3294                                              u32 port, u32 addr, u32 offset,
3295                                              u32 len, u8 *p_buf)
3296 {
3297         u32 buf_idx, buf_size, nvm_offset, resp, param;
3298         enum _ecore_status_t rc;
3299
3300         nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) |
3301                         (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET);
3302         buf_idx = 0;
3303         while (buf_idx < len) {
3304                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
3305                                       MAX_I2C_TRANSACTION_SIZE);
3306                 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
3307                                  DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
3308                 nvm_offset |= ((offset + buf_idx) <<
3309                                  DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET);
3310                 nvm_offset |= (buf_size <<
3311                                DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET);
3312                 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt,
3313                                           DRV_MSG_CODE_TRANSCEIVER_WRITE,
3314                                           nvm_offset, &resp, &param, buf_size,
3315                                           (u32 *)&p_buf[buf_idx]);
3316                 if (rc != ECORE_SUCCESS) {
3317                         DP_NOTICE(p_hwfn, false,
3318                                   "Failed to send a transceiver write command to the MFW. rc = %d.\n",
3319                                   rc);
3320                         return rc;
3321                 }
3322
3323                 if (resp == FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT)
3324                         return ECORE_NODEV;
3325                 else if (resp != FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
3326                         return ECORE_UNKNOWN_ERROR;
3327
3328                 buf_idx += buf_size;
3329         }
3330
3331         return ECORE_SUCCESS;
3332 }
3333
3334 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
3335                                          struct ecore_ptt *p_ptt,
3336                                          u16 gpio, u32 *gpio_val)
3337 {
3338         enum _ecore_status_t rc = ECORE_SUCCESS;
3339         u32 drv_mb_param = 0, rsp;
3340
3341         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET);
3342
3343         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
3344                            drv_mb_param, &rsp, gpio_val);
3345
3346         if (rc != ECORE_SUCCESS)
3347                 return rc;
3348
3349         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
3350                 return ECORE_UNKNOWN_ERROR;
3351
3352         return ECORE_SUCCESS;
3353 }
3354
3355 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
3356                                           struct ecore_ptt *p_ptt,
3357                                           u16 gpio, u16 gpio_val)
3358 {
3359         enum _ecore_status_t rc = ECORE_SUCCESS;
3360         u32 drv_mb_param = 0, param, rsp;
3361
3362         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET) |
3363                 (gpio_val << DRV_MB_PARAM_GPIO_VALUE_OFFSET);
3364
3365         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
3366                            drv_mb_param, &rsp, &param);
3367
3368         if (rc != ECORE_SUCCESS)
3369                 return rc;
3370
3371         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
3372                 return ECORE_UNKNOWN_ERROR;
3373
3374         return ECORE_SUCCESS;
3375 }
3376
3377 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
3378                                          struct ecore_ptt *p_ptt,
3379                                          u16 gpio, u32 *gpio_direction,
3380                                          u32 *gpio_ctrl)
3381 {
3382         u32 drv_mb_param = 0, rsp, val = 0;
3383         enum _ecore_status_t rc = ECORE_SUCCESS;
3384
3385         drv_mb_param = gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET;
3386
3387         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_INFO,
3388                            drv_mb_param, &rsp, &val);
3389         if (rc != ECORE_SUCCESS)
3390                 return rc;
3391
3392         *gpio_direction = (val & DRV_MB_PARAM_GPIO_DIRECTION_MASK) >>
3393                            DRV_MB_PARAM_GPIO_DIRECTION_OFFSET;
3394         *gpio_ctrl = (val & DRV_MB_PARAM_GPIO_CTRL_MASK) >>
3395                       DRV_MB_PARAM_GPIO_CTRL_OFFSET;
3396
3397         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
3398                 return ECORE_UNKNOWN_ERROR;
3399
3400         return ECORE_SUCCESS;
3401 }
3402
3403 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
3404                                                   struct ecore_ptt *p_ptt)
3405 {
3406         u32 drv_mb_param = 0, rsp, param;
3407         enum _ecore_status_t rc = ECORE_SUCCESS;
3408
3409         drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
3410                         DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3411
3412         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3413                            drv_mb_param, &rsp, &param);
3414
3415         if (rc != ECORE_SUCCESS)
3416                 return rc;
3417
3418         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3419             (param != DRV_MB_PARAM_BIST_RC_PASSED))
3420                 rc = ECORE_UNKNOWN_ERROR;
3421
3422         return rc;
3423 }
3424
3425 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
3426                                                struct ecore_ptt *p_ptt)
3427 {
3428         u32 drv_mb_param, rsp, param;
3429         enum _ecore_status_t rc = ECORE_SUCCESS;
3430
3431         drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
3432                         DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3433
3434         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3435                            drv_mb_param, &rsp, &param);
3436
3437         if (rc != ECORE_SUCCESS)
3438                 return rc;
3439
3440         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3441             (param != DRV_MB_PARAM_BIST_RC_PASSED))
3442                 rc = ECORE_UNKNOWN_ERROR;
3443
3444         return rc;
3445 }
3446
3447 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
3448         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *num_images)
3449 {
3450         u32 drv_mb_param = 0, rsp;
3451         enum _ecore_status_t rc = ECORE_SUCCESS;
3452
3453         drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
3454                         DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3455
3456         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3457                            drv_mb_param, &rsp, num_images);
3458
3459         if (rc != ECORE_SUCCESS)
3460                 return rc;
3461
3462         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
3463                 rc = ECORE_UNKNOWN_ERROR;
3464
3465         return rc;
3466 }
3467
3468 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
3469         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3470         struct bist_nvm_image_att *p_image_att, u32 image_index)
3471 {
3472         u32 buf_size, nvm_offset, resp, param;
3473         enum _ecore_status_t rc;
3474
3475         nvm_offset = (DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
3476                                     DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3477         nvm_offset |= (image_index <<
3478                        DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_OFFSET);
3479         rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3480                                   nvm_offset, &resp, &param, &buf_size,
3481                                   (u32 *)p_image_att);
3482         if (rc != ECORE_SUCCESS)
3483                 return rc;
3484
3485         if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3486             (p_image_att->return_code != 1))
3487                 rc = ECORE_UNKNOWN_ERROR;
3488
3489         return rc;
3490 }
3491
3492 enum _ecore_status_t
3493 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
3494                                struct ecore_ptt *p_ptt,
3495                                struct ecore_temperature_info *p_temp_info)
3496 {
3497         struct ecore_temperature_sensor *p_temp_sensor;
3498         struct temperature_status_stc mfw_temp_info;
3499         struct ecore_mcp_mb_params mb_params;
3500         u32 val;
3501         enum _ecore_status_t rc;
3502         u8 i;
3503
3504         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3505         mb_params.cmd = DRV_MSG_CODE_GET_TEMPERATURE;
3506         mb_params.p_data_dst = &mfw_temp_info;
3507         mb_params.data_dst_size = sizeof(mfw_temp_info);
3508         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3509         if (rc != ECORE_SUCCESS)
3510                 return rc;
3511
3512         OSAL_BUILD_BUG_ON(ECORE_MAX_NUM_OF_SENSORS != MAX_NUM_OF_SENSORS);
3513         p_temp_info->num_sensors = OSAL_MIN_T(u32, mfw_temp_info.num_of_sensors,
3514                                               ECORE_MAX_NUM_OF_SENSORS);
3515         for (i = 0; i < p_temp_info->num_sensors; i++) {
3516                 val = mfw_temp_info.sensor[i];
3517                 p_temp_sensor = &p_temp_info->sensors[i];
3518                 p_temp_sensor->sensor_location = (val & SENSOR_LOCATION_MASK) >>
3519                                                  SENSOR_LOCATION_OFFSET;
3520                 p_temp_sensor->threshold_high = (val & THRESHOLD_HIGH_MASK) >>
3521                                                 THRESHOLD_HIGH_OFFSET;
3522                 p_temp_sensor->critical = (val & CRITICAL_TEMPERATURE_MASK) >>
3523                                           CRITICAL_TEMPERATURE_OFFSET;
3524                 p_temp_sensor->current_temp = (val & CURRENT_TEMP_MASK) >>
3525                                               CURRENT_TEMP_OFFSET;
3526         }
3527
3528         return ECORE_SUCCESS;
3529 }
3530
3531 enum _ecore_status_t ecore_mcp_get_mba_versions(
3532         struct ecore_hwfn *p_hwfn,
3533         struct ecore_ptt *p_ptt,
3534         struct ecore_mba_vers *p_mba_vers)
3535 {
3536         u32 buf_size, resp, param;
3537         enum _ecore_status_t rc;
3538
3539         rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MBA_VERSION,
3540                                   0, &resp, &param, &buf_size,
3541                                   &p_mba_vers->mba_vers[0]);
3542
3543         if (rc != ECORE_SUCCESS)
3544                 return rc;
3545
3546         if ((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_NVM_OK)
3547                 rc = ECORE_UNKNOWN_ERROR;
3548
3549         if (buf_size != MCP_DRV_NVM_BUF_LEN)
3550                 rc = ECORE_UNKNOWN_ERROR;
3551
3552         return rc;
3553 }
3554
3555 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
3556                                               struct ecore_ptt *p_ptt,
3557                                               u64 *num_events)
3558 {
3559         u32 rsp;
3560
3561         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MEM_ECC_EVENTS,
3562                              0, &rsp, (u32 *)num_events);
3563 }
3564
3565 static enum resource_id_enum
3566 ecore_mcp_get_mfw_res_id(enum ecore_resources res_id)
3567 {
3568         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
3569
3570         switch (res_id) {
3571         case ECORE_SB:
3572                 mfw_res_id = RESOURCE_NUM_SB_E;
3573                 break;
3574         case ECORE_L2_QUEUE:
3575                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
3576                 break;
3577         case ECORE_VPORT:
3578                 mfw_res_id = RESOURCE_NUM_VPORT_E;
3579                 break;
3580         case ECORE_RSS_ENG:
3581                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
3582                 break;
3583         case ECORE_PQ:
3584                 mfw_res_id = RESOURCE_NUM_PQ_E;
3585                 break;
3586         case ECORE_RL:
3587                 mfw_res_id = RESOURCE_NUM_RL_E;
3588                 break;
3589         case ECORE_MAC:
3590         case ECORE_VLAN:
3591                 /* Each VFC resource can accommodate both a MAC and a VLAN */
3592                 mfw_res_id = RESOURCE_VFC_FILTER_E;
3593                 break;
3594         case ECORE_ILT:
3595                 mfw_res_id = RESOURCE_ILT_E;
3596                 break;
3597         case ECORE_LL2_QUEUE:
3598                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
3599                 break;
3600         case ECORE_RDMA_CNQ_RAM:
3601         case ECORE_CMDQS_CQS:
3602                 /* CNQ/CMDQS are the same resource */
3603                 mfw_res_id = RESOURCE_CQS_E;
3604                 break;
3605         case ECORE_RDMA_STATS_QUEUE:
3606                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
3607                 break;
3608         case ECORE_BDQ:
3609                 mfw_res_id = RESOURCE_BDQ_E;
3610                 break;
3611         default:
3612                 break;
3613         }
3614
3615         return mfw_res_id;
3616 }
3617
3618 #define ECORE_RESC_ALLOC_VERSION_MAJOR  2
3619 #define ECORE_RESC_ALLOC_VERSION_MINOR  0
3620 #define ECORE_RESC_ALLOC_VERSION                                \
3621         ((ECORE_RESC_ALLOC_VERSION_MAJOR <<                     \
3622           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET) |   \
3623          (ECORE_RESC_ALLOC_VERSION_MINOR <<                     \
3624           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET))
3625
3626 struct ecore_resc_alloc_in_params {
3627         u32 cmd;
3628         enum ecore_resources res_id;
3629         u32 resc_max_val;
3630 };
3631
3632 struct ecore_resc_alloc_out_params {
3633         u32 mcp_resp;
3634         u32 mcp_param;
3635         u32 resc_num;
3636         u32 resc_start;
3637         u32 vf_resc_num;
3638         u32 vf_resc_start;
3639         u32 flags;
3640 };
3641
3642 #define ECORE_RECOVERY_PROLOG_SLEEP_MS  100
3643
3644 enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev)
3645 {
3646         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3647         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
3648         enum _ecore_status_t rc;
3649
3650         /* Allow ongoing PCIe transactions to complete */
3651         OSAL_MSLEEP(ECORE_RECOVERY_PROLOG_SLEEP_MS);
3652
3653         /* Clear the PF's internal FID_enable in the PXP */
3654         rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
3655         if (rc != ECORE_SUCCESS)
3656                 DP_NOTICE(p_hwfn, false,
3657                           "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
3658                           rc);
3659
3660         return rc;
3661 }
3662
3663 static enum _ecore_status_t
3664 ecore_mcp_resc_allocation_msg(struct ecore_hwfn *p_hwfn,
3665                               struct ecore_ptt *p_ptt,
3666                               struct ecore_resc_alloc_in_params *p_in_params,
3667                               struct ecore_resc_alloc_out_params *p_out_params)
3668 {
3669         struct ecore_mcp_mb_params mb_params;
3670         struct resource_info mfw_resc_info;
3671         enum _ecore_status_t rc;
3672
3673         OSAL_MEM_ZERO(&mfw_resc_info, sizeof(mfw_resc_info));
3674
3675         mfw_resc_info.res_id = ecore_mcp_get_mfw_res_id(p_in_params->res_id);
3676         if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
3677                 DP_ERR(p_hwfn,
3678                        "Failed to match resource %d [%s] with the MFW resources\n",
3679                        p_in_params->res_id,
3680                        ecore_hw_get_resc_name(p_in_params->res_id));
3681                 return ECORE_INVAL;
3682         }
3683
3684         switch (p_in_params->cmd) {
3685         case DRV_MSG_SET_RESOURCE_VALUE_MSG:
3686                 mfw_resc_info.size = p_in_params->resc_max_val;
3687                 /* Fallthrough */
3688         case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
3689                 break;
3690         default:
3691                 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
3692                        p_in_params->cmd);
3693                 return ECORE_INVAL;
3694         }
3695
3696         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3697         mb_params.cmd = p_in_params->cmd;
3698         mb_params.param = ECORE_RESC_ALLOC_VERSION;
3699         mb_params.p_data_src = &mfw_resc_info;
3700         mb_params.data_src_size = sizeof(mfw_resc_info);
3701         mb_params.p_data_dst = mb_params.p_data_src;
3702         mb_params.data_dst_size = mb_params.data_src_size;
3703
3704         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3705                    "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
3706                    p_in_params->cmd, p_in_params->res_id,
3707                    ecore_hw_get_resc_name(p_in_params->res_id),
3708                    GET_MFW_FIELD(mb_params.param,
3709                                  DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3710                    GET_MFW_FIELD(mb_params.param,
3711                                  DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3712                    p_in_params->resc_max_val);
3713
3714         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3715         if (rc != ECORE_SUCCESS)
3716                 return rc;
3717
3718         p_out_params->mcp_resp = mb_params.mcp_resp;
3719         p_out_params->mcp_param = mb_params.mcp_param;
3720         p_out_params->resc_num = mfw_resc_info.size;
3721         p_out_params->resc_start = mfw_resc_info.offset;
3722         p_out_params->vf_resc_num = mfw_resc_info.vf_size;
3723         p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
3724         p_out_params->flags = mfw_resc_info.flags;
3725
3726         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3727                    "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
3728                    GET_MFW_FIELD(p_out_params->mcp_param,
3729                                  FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3730                    GET_MFW_FIELD(p_out_params->mcp_param,
3731                                  FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3732                    p_out_params->resc_num, p_out_params->resc_start,
3733                    p_out_params->vf_resc_num, p_out_params->vf_resc_start,
3734                    p_out_params->flags);
3735
3736         return ECORE_SUCCESS;
3737 }
3738
3739 enum _ecore_status_t
3740 ecore_mcp_set_resc_max_val(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3741                            enum ecore_resources res_id, u32 resc_max_val,
3742                            u32 *p_mcp_resp)
3743 {
3744         struct ecore_resc_alloc_out_params out_params;
3745         struct ecore_resc_alloc_in_params in_params;
3746         enum _ecore_status_t rc;
3747
3748         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3749         in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
3750         in_params.res_id = res_id;
3751         in_params.resc_max_val = resc_max_val;
3752         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3753         rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3754                                            &out_params);
3755         if (rc != ECORE_SUCCESS)
3756                 return rc;
3757
3758         *p_mcp_resp = out_params.mcp_resp;
3759
3760         return ECORE_SUCCESS;
3761 }
3762
3763 enum _ecore_status_t
3764 ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3765                         enum ecore_resources res_id, u32 *p_mcp_resp,
3766                         u32 *p_resc_num, u32 *p_resc_start)
3767 {
3768         struct ecore_resc_alloc_out_params out_params;
3769         struct ecore_resc_alloc_in_params in_params;
3770         enum _ecore_status_t rc;
3771
3772         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3773         in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
3774         in_params.res_id = res_id;
3775         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3776         rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3777                                            &out_params);
3778         if (rc != ECORE_SUCCESS)
3779                 return rc;
3780
3781         *p_mcp_resp = out_params.mcp_resp;
3782
3783         if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3784                 *p_resc_num = out_params.resc_num;
3785                 *p_resc_start = out_params.resc_start;
3786         }
3787
3788         return ECORE_SUCCESS;
3789 }
3790
3791 enum _ecore_status_t ecore_mcp_initiate_pf_flr(struct ecore_hwfn *p_hwfn,
3792                                                struct ecore_ptt *p_ptt)
3793 {
3794         u32 mcp_resp, mcp_param;
3795
3796         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
3797                              &mcp_resp, &mcp_param);
3798 }
3799
3800 static enum _ecore_status_t ecore_mcp_resource_cmd(struct ecore_hwfn *p_hwfn,
3801                                                    struct ecore_ptt *p_ptt,
3802                                                    u32 param, u32 *p_mcp_resp,
3803                                                    u32 *p_mcp_param)
3804 {
3805         enum _ecore_status_t rc;
3806
3807         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
3808                            p_mcp_resp, p_mcp_param);
3809         if (rc != ECORE_SUCCESS)
3810                 return rc;
3811
3812         if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3813                 DP_INFO(p_hwfn,
3814                         "The resource command is unsupported by the MFW\n");
3815                 return ECORE_NOTIMPL;
3816         }
3817
3818         if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
3819                 u8 opcode = GET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
3820
3821                 DP_NOTICE(p_hwfn, false,
3822                           "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
3823                           param, opcode);
3824                 return ECORE_INVAL;
3825         }
3826
3827         return rc;
3828 }
3829
3830 enum _ecore_status_t
3831 __ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3832                       struct ecore_resc_lock_params *p_params)
3833 {
3834         u32 param = 0, mcp_resp, mcp_param;
3835         u8 opcode;
3836         enum _ecore_status_t rc;
3837
3838         switch (p_params->timeout) {
3839         case ECORE_MCP_RESC_LOCK_TO_DEFAULT:
3840                 opcode = RESOURCE_OPCODE_REQ;
3841                 p_params->timeout = 0;
3842                 break;
3843         case ECORE_MCP_RESC_LOCK_TO_NONE:
3844                 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
3845                 p_params->timeout = 0;
3846                 break;
3847         default:
3848                 opcode = RESOURCE_OPCODE_REQ_W_AGING;
3849                 break;
3850         }
3851
3852         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3853         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3854         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
3855
3856         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3857                    "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
3858                    param, p_params->timeout, opcode, p_params->resource);
3859
3860         /* Attempt to acquire the resource */
3861         rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3862                                     &mcp_param);
3863         if (rc != ECORE_SUCCESS)
3864                 return rc;
3865
3866         /* Analyze the response */
3867         p_params->owner = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER);
3868         opcode = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3869
3870         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3871                    "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
3872                    mcp_param, opcode, p_params->owner);
3873
3874         switch (opcode) {
3875         case RESOURCE_OPCODE_GNT:
3876                 p_params->b_granted = true;
3877                 break;
3878         case RESOURCE_OPCODE_BUSY:
3879                 p_params->b_granted = false;
3880                 break;
3881         default:
3882                 DP_NOTICE(p_hwfn, false,
3883                           "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
3884                           mcp_param, opcode);
3885                 return ECORE_INVAL;
3886         }
3887
3888         return ECORE_SUCCESS;
3889 }
3890
3891 enum _ecore_status_t
3892 ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3893                     struct ecore_resc_lock_params *p_params)
3894 {
3895         u32 retry_cnt = 0;
3896         enum _ecore_status_t rc;
3897
3898         do {
3899                 /* No need for an interval before the first iteration */
3900                 if (retry_cnt) {
3901                         if (p_params->sleep_b4_retry) {
3902                                 u16 retry_interval_in_ms =
3903                                         DIV_ROUND_UP(p_params->retry_interval,
3904                                                      1000);
3905
3906                                 OSAL_MSLEEP(retry_interval_in_ms);
3907                         } else {
3908                                 OSAL_UDELAY(p_params->retry_interval);
3909                         }
3910                 }
3911
3912                 rc = __ecore_mcp_resc_lock(p_hwfn, p_ptt, p_params);
3913                 if (rc != ECORE_SUCCESS)
3914                         return rc;
3915
3916                 if (p_params->b_granted)
3917                         break;
3918         } while (retry_cnt++ < p_params->retry_num);
3919
3920         return ECORE_SUCCESS;
3921 }
3922
3923 void ecore_mcp_resc_lock_default_init(struct ecore_resc_lock_params *p_lock,
3924                                       struct ecore_resc_unlock_params *p_unlock,
3925                                       enum ecore_resc_lock resource,
3926                                       bool b_is_permanent)
3927 {
3928         if (p_lock != OSAL_NULL) {
3929                 OSAL_MEM_ZERO(p_lock, sizeof(*p_lock));
3930
3931                 /* Permanent resources don't require aging, and there's no
3932                  * point in trying to acquire them more than once since it's
3933                  * unexpected another entity would release them.
3934                  */
3935                 if (b_is_permanent) {
3936                         p_lock->timeout = ECORE_MCP_RESC_LOCK_TO_NONE;
3937                 } else {
3938                         p_lock->retry_num = ECORE_MCP_RESC_LOCK_RETRY_CNT_DFLT;
3939                         p_lock->retry_interval =
3940                                         ECORE_MCP_RESC_LOCK_RETRY_VAL_DFLT;
3941                         p_lock->sleep_b4_retry = true;
3942                 }
3943
3944                 p_lock->resource = resource;
3945         }
3946
3947         if (p_unlock != OSAL_NULL) {
3948                 OSAL_MEM_ZERO(p_unlock, sizeof(*p_unlock));
3949                 p_unlock->resource = resource;
3950         }
3951 }
3952
3953 enum _ecore_status_t
3954 ecore_mcp_resc_unlock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3955                       struct ecore_resc_unlock_params *p_params)
3956 {
3957         u32 param = 0, mcp_resp, mcp_param;
3958         u8 opcode;
3959         enum _ecore_status_t rc;
3960
3961         opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
3962                                    : RESOURCE_OPCODE_RELEASE;
3963         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3964         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3965
3966         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3967                    "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
3968                    param, opcode, p_params->resource);
3969
3970         /* Attempt to release the resource */
3971         rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3972                                     &mcp_param);
3973         if (rc != ECORE_SUCCESS)
3974                 return rc;
3975
3976         /* Analyze the response */
3977         opcode = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3978
3979         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3980                    "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
3981                    mcp_param, opcode);
3982
3983         switch (opcode) {
3984         case RESOURCE_OPCODE_RELEASED_PREVIOUS:
3985                 DP_INFO(p_hwfn,
3986                         "Resource unlock request for an already released resource [%d]\n",
3987                         p_params->resource);
3988                 /* Fallthrough */
3989         case RESOURCE_OPCODE_RELEASED:
3990                 p_params->b_released = true;
3991                 break;
3992         case RESOURCE_OPCODE_WRONG_OWNER:
3993                 p_params->b_released = false;
3994                 break;
3995         default:
3996                 DP_NOTICE(p_hwfn, false,
3997                           "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
3998                           mcp_param, opcode);
3999                 return ECORE_INVAL;
4000         }
4001
4002         return ECORE_SUCCESS;
4003 }
4004
4005 bool ecore_mcp_is_smart_an_supported(struct ecore_hwfn *p_hwfn)
4006 {
4007         return !!(p_hwfn->mcp_info->capabilities &
4008                   FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ);
4009 }
4010
4011 enum _ecore_status_t ecore_mcp_get_capabilities(struct ecore_hwfn *p_hwfn,
4012                                                 struct ecore_ptt *p_ptt)
4013 {
4014         u32 mcp_resp;
4015         enum _ecore_status_t rc;
4016
4017         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
4018                            0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
4019         if (rc == ECORE_SUCCESS)
4020                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_PROBE),
4021                            "MFW supported features: %08x\n",
4022                            p_hwfn->mcp_info->capabilities);
4023
4024         return rc;
4025 }
4026
4027 enum _ecore_status_t ecore_mcp_set_capabilities(struct ecore_hwfn *p_hwfn,
4028                                                 struct ecore_ptt *p_ptt)
4029 {
4030         u32 mcp_resp, mcp_param, features;
4031
4032         features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ |
4033                    DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE |
4034                    DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK;
4035
4036         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
4037                              features, &mcp_resp, &mcp_param);
4038 }
4039
4040 enum _ecore_status_t
4041 ecore_mcp_drv_attribute(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
4042                         struct ecore_mcp_drv_attr *p_drv_attr)
4043 {
4044         struct attribute_cmd_write_stc attr_cmd_write;
4045         enum _attribute_commands_e mfw_attr_cmd;
4046         struct ecore_mcp_mb_params mb_params;
4047         enum _ecore_status_t rc;
4048
4049         switch (p_drv_attr->attr_cmd) {
4050         case ECORE_MCP_DRV_ATTR_CMD_READ:
4051                 mfw_attr_cmd = ATTRIBUTE_CMD_READ;
4052                 break;
4053         case ECORE_MCP_DRV_ATTR_CMD_WRITE:
4054                 mfw_attr_cmd = ATTRIBUTE_CMD_WRITE;
4055                 break;
4056         case ECORE_MCP_DRV_ATTR_CMD_READ_CLEAR:
4057                 mfw_attr_cmd = ATTRIBUTE_CMD_READ_CLEAR;
4058                 break;
4059         case ECORE_MCP_DRV_ATTR_CMD_CLEAR:
4060                 mfw_attr_cmd = ATTRIBUTE_CMD_CLEAR;
4061                 break;
4062         default:
4063                 DP_NOTICE(p_hwfn, false, "Unknown attribute command %d\n",
4064                           p_drv_attr->attr_cmd);
4065                 return ECORE_INVAL;
4066         }
4067
4068         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
4069         mb_params.cmd = DRV_MSG_CODE_ATTRIBUTE;
4070         SET_MFW_FIELD(mb_params.param, DRV_MB_PARAM_ATTRIBUTE_KEY,
4071                       p_drv_attr->attr_num);
4072         SET_MFW_FIELD(mb_params.param, DRV_MB_PARAM_ATTRIBUTE_CMD,
4073                       mfw_attr_cmd);
4074         if (p_drv_attr->attr_cmd == ECORE_MCP_DRV_ATTR_CMD_WRITE) {
4075                 OSAL_MEM_ZERO(&attr_cmd_write, sizeof(attr_cmd_write));
4076                 attr_cmd_write.val = p_drv_attr->val;
4077                 attr_cmd_write.mask = p_drv_attr->mask;
4078                 attr_cmd_write.offset = p_drv_attr->offset;
4079
4080                 mb_params.p_data_src = &attr_cmd_write;
4081                 mb_params.data_src_size = sizeof(attr_cmd_write);
4082         }
4083
4084         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
4085         if (rc != ECORE_SUCCESS)
4086                 return rc;
4087
4088         if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
4089                 DP_INFO(p_hwfn,
4090                         "The attribute command is not supported by the MFW\n");
4091                 return ECORE_NOTIMPL;
4092         } else if (mb_params.mcp_resp != FW_MSG_CODE_OK) {
4093                 DP_INFO(p_hwfn,
4094                         "Failed to send an attribute command [mcp_resp 0x%x, attr_cmd %d, attr_num %d]\n",
4095                         mb_params.mcp_resp, p_drv_attr->attr_cmd,
4096                         p_drv_attr->attr_num);
4097                 return ECORE_INVAL;
4098         }
4099
4100         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
4101                    "Attribute Command: cmd %d [mfw_cmd %d], num %d, in={val 0x%08x, mask 0x%08x, offset 0x%08x}, out={val 0x%08x}\n",
4102                    p_drv_attr->attr_cmd, mfw_attr_cmd, p_drv_attr->attr_num,
4103                    p_drv_attr->val, p_drv_attr->mask, p_drv_attr->offset,
4104                    mb_params.mcp_param);
4105
4106         if (p_drv_attr->attr_cmd == ECORE_MCP_DRV_ATTR_CMD_READ ||
4107             p_drv_attr->attr_cmd == ECORE_MCP_DRV_ATTR_CMD_READ_CLEAR)
4108                 p_drv_attr->val = mb_params.mcp_param;
4109
4110         return ECORE_SUCCESS;
4111 }
4112
4113 void ecore_mcp_wol_wr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
4114                       u32 offset, u32 val)
4115 {
4116         struct ecore_mcp_mb_params mb_params = {0};
4117         enum _ecore_status_t       rc = ECORE_SUCCESS;
4118         u32                        dword = val;
4119
4120         mb_params.cmd = DRV_MSG_CODE_WRITE_WOL_REG;
4121         mb_params.param = offset;
4122         mb_params.p_data_src = &dword;
4123         mb_params.data_src_size = sizeof(dword);
4124
4125         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
4126         if (rc != ECORE_SUCCESS) {
4127                 DP_NOTICE(p_hwfn, false,
4128                           "Failed to wol write request, rc = %d\n", rc);
4129         }
4130
4131         if (mb_params.mcp_resp != FW_MSG_CODE_WOL_READ_WRITE_OK) {
4132                 DP_NOTICE(p_hwfn, false,
4133                           "Failed to write value 0x%x to offset 0x%x [mcp_resp 0x%x]\n",
4134                           val, offset, mb_params.mcp_resp);
4135                 rc = ECORE_UNKNOWN_ERROR;
4136         }
4137 }