drivers/raw/ifpga/ifpga_rawdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2018 Intel Corporation
   3  */
   4
   5 #include <string.h>
   6 #include <dirent.h>
   7 #include <sys/stat.h>
   8 #include <unistd.h>
   9 #include <sys/types.h>
  10 #include <fcntl.h>
  11 #include <sys/ioctl.h>
  12 #include <sys/epoll.h>
  13 #include <rte_log.h>
  14 #include <rte_bus.h>
  15 #include <rte_malloc.h>
  16 #include <rte_devargs.h>
  17 #include <rte_memcpy.h>
  18 #include <rte_pci.h>
  19 #include <rte_bus_pci.h>
  20 #include <rte_kvargs.h>
  21 #include <rte_alarm.h>
  22 #include <rte_interrupts.h>
  23 #include <rte_errno.h>
  24 #include <rte_per_lcore.h>
  25 #include <rte_memory.h>
  26 #include <rte_memzone.h>
  27 #include <rte_eal.h>
  28 #include <rte_common.h>
  29 #include <rte_bus_vdev.h>
  30 #include <rte_string_fns.h>
  31 #include <rte_pmd_i40e.h>
  32
  33 #include "base/opae_hw_api.h"
  34 #include "base/opae_ifpga_hw_api.h"
  35 #include "base/ifpga_api.h"
  36 #include "rte_rawdev.h"
  37 #include "rte_rawdev_pmd.h"
  38 #include "rte_bus_ifpga.h"
  39 #include "ifpga_common.h"
  40 #include "ifpga_logs.h"
  41 #include "ifpga_rawdev.h"
  42 #include "ipn3ke_rawdev_api.h"
  43
  44 #define RTE_PCI_EXT_CAP_ID_ERR           0x01   /* Advanced Error Reporting */
  45 #define RTE_PCI_CFG_SPACE_SIZE           256
  46 #define RTE_PCI_CFG_SPACE_EXP_SIZE       4096
  47 #define RTE_PCI_EXT_CAP_ID(header)       (int)(header & 0x0000ffff)
  48 #define RTE_PCI_EXT_CAP_NEXT(header)     ((header >> 20) & 0xffc)
  49
  50 int ifpga_rawdev_logtype;
  51
  52 #define PCI_VENDOR_ID_INTEL          0x8086
  53 /* PCI Device ID */
  54 #define PCIE_DEVICE_ID_PF_INT_5_X    0xBCBD
  55 #define PCIE_DEVICE_ID_PF_INT_6_X    0xBCC0
  56 #define PCIE_DEVICE_ID_PF_DSC_1_X    0x09C4
  57 #define PCIE_DEVICE_ID_PAC_N3000     0x0B30
  58 /* VF Device */
  59 #define PCIE_DEVICE_ID_VF_INT_5_X    0xBCBF
  60 #define PCIE_DEVICE_ID_VF_INT_6_X    0xBCC1
  61 #define PCIE_DEVICE_ID_VF_DSC_1_X    0x09C5
  62 #define PCIE_DEVICE_ID_VF_PAC_N3000  0x0B31
  63 #define RTE_MAX_RAW_DEVICE           10
  64
  65 static const struct rte_pci_id pci_ifpga_map[] = {
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PAC_N3000),},
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_PAC_N3000),},
  74         { .vendor_id = 0, /* sentinel */ },
  75 };
  76
  77 static struct ifpga_rawdev ifpga_rawdevices[IFPGA_RAWDEV_NUM];
  78
  79 static int ifpga_monitor_start;
  80 static pthread_t ifpga_monitor_start_thread;
  81
  82 #define IFPGA_MAX_IRQ 12
  83 /* 0 for FME interrupt, others are reserved for AFU irq */
  84 static struct rte_intr_handle ifpga_irq_handle[IFPGA_MAX_IRQ];
  85
  86 static struct ifpga_rawdev *
  87 ifpga_rawdev_allocate(struct rte_rawdev *rawdev);
  88 static int set_surprise_link_check_aer(
  89                 struct ifpga_rawdev *ifpga_rdev, int force_disable);
  90 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
  91                 int start, int cap);
  92 static int ifpga_pci_find_ext_capability(unsigned int fd, int cap);
  93
  94 struct ifpga_rawdev *
  95 ifpga_rawdev_get(const struct rte_rawdev *rawdev)
  96 {
  97         struct ifpga_rawdev *dev;
  98         unsigned int i;
  99
 100         if (rawdev == NULL)
 101                 return NULL;
 102
 103         for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
 104                 dev = &ifpga_rawdevices[i];
 105                 if (dev->rawdev == rawdev)
 106                         return dev;
 107         }
 108
 109         return NULL;
 110 }
 111
 112 static inline uint8_t
 113 ifpga_rawdev_find_free_device_index(void)
 114 {
 115         uint16_t dev_id;
 116
 117         for (dev_id = 0; dev_id < IFPGA_RAWDEV_NUM; dev_id++) {
 118                 if (ifpga_rawdevices[dev_id].rawdev == NULL)
 119                         return dev_id;
 120         }
 121
 122         return IFPGA_RAWDEV_NUM;
 123 }
 124 static struct ifpga_rawdev *
 125 ifpga_rawdev_allocate(struct rte_rawdev *rawdev)
 126 {
 127         struct ifpga_rawdev *dev;
 128         uint16_t dev_id;
 129
 130         dev = ifpga_rawdev_get(rawdev);
 131         if (dev != NULL) {
 132                 IFPGA_RAWDEV_PMD_ERR("Event device already allocated!");
 133                 return NULL;
 134         }
 135
 136         dev_id = ifpga_rawdev_find_free_device_index();
 137         if (dev_id == IFPGA_RAWDEV_NUM) {
 138                 IFPGA_RAWDEV_PMD_ERR("Reached maximum number of raw devices");
 139                 return NULL;
 140         }
 141
 142         dev = &ifpga_rawdevices[dev_id];
 143         dev->rawdev = rawdev;
 144         dev->dev_id = dev_id;
 145
 146         return dev;
 147 }
 148
 149 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
 150 int start, int cap)
 151 {
 152         uint32_t header;
 153         int ttl;
 154         int pos = RTE_PCI_CFG_SPACE_SIZE;
 155         int ret;
 156
 157         /* minimum 8 bytes per capability */
 158         ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
 159
 160         if (start)
 161                 pos = start;
 162         ret = pread(fd, &header, sizeof(header), pos);
 163         if (ret == -1)
 164                 return -1;
 165
 166         /*
 167          * If we have no capabilities, this is indicated by cap ID,
 168          * cap version and next pointer all being 0.
 169          */
 170         if (header == 0)
 171                 return 0;
 172
 173         while (ttl-- > 0) {
 174                 if (RTE_PCI_EXT_CAP_ID(header) == cap && pos != start)
 175                         return pos;
 176
 177                 pos = RTE_PCI_EXT_CAP_NEXT(header);
 178                 if (pos < RTE_PCI_CFG_SPACE_SIZE)
 179                         break;
 180                 ret = pread(fd, &header, sizeof(header), pos);
 181                 if (ret == -1)
 182                         return -1;
 183         }
 184
 185         return 0;
 186 }
 187
 188 static int ifpga_pci_find_ext_capability(unsigned int fd, int cap)
 189 {
 190         return ifpga_pci_find_next_ext_capability(fd, 0, cap);
 191 }
 192
 193 static int ifpga_get_dev_vendor_id(const char *bdf,
 194         uint32_t *dev_id, uint32_t *vendor_id)
 195 {
 196         int fd;
 197         char path[1024];
 198         int ret;
 199         uint32_t header;
 200
 201         strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
 202         strlcat(path, bdf, sizeof(path));
 203         strlcat(path, "/config", sizeof(path));
 204         fd = open(path, O_RDWR);
 205         if (fd < 0)
 206                 return -1;
 207         ret = pread(fd, &header, sizeof(header), 0);
 208         if (ret == -1) {
 209                 close(fd);
 210                 return -1;
 211         }
 212         (*vendor_id) = header & 0xffff;
 213         (*dev_id) = (header >> 16) & 0xffff;
 214         close(fd);
 215
 216         return 0;
 217 }
 218 static int ifpga_rawdev_fill_info(struct ifpga_rawdev *ifpga_dev,
 219         const char *bdf)
 220 {
 221         char path[1024] = "/sys/bus/pci/devices/0000:";
 222         char link[1024], link1[1024];
 223         char dir[1024] = "/sys/devices/";
 224         char *c;
 225         int ret;
 226         char sub_brg_bdf[4][16];
 227         int point;
 228         DIR *dp = NULL;
 229         struct dirent *entry;
 230         int i, j;
 231
 232         unsigned int dom, bus, dev;
 233         int func;
 234         uint32_t dev_id, vendor_id;
 235
 236         strlcat(path, bdf, sizeof(path));
 237         memset(link, 0, sizeof(link));
 238         memset(link1, 0, sizeof(link1));
 239         ret = readlink(path, link, (sizeof(link)-1));
 240         if (ret == -1)
 241                 return -1;
 242         strlcpy(link1, link, sizeof(link1));
 243         memset(ifpga_dev->parent_bdf, 0, 16);
 244         point = strlen(link);
 245         if (point < 39)
 246                 return -1;
 247         point -= 39;
 248         link[point] = 0;
 249         if (point < 12)
 250                 return -1;
 251         point -= 12;
 252         rte_memcpy(ifpga_dev->parent_bdf, &link[point], 12);
 253
 254         point = strlen(link1);
 255         if (point < 26)
 256                 return -1;
 257         point -= 26;
 258         link1[point] = 0;
 259         if (point < 12)
 260                 return -1;
 261         point -= 12;
 262         c = strchr(link1, 'p');
 263         if (!c)
 264                 return -1;
 265         strlcat(dir, c, sizeof(dir));
 266
 267         /* scan folder */
 268         dp = opendir(dir);
 269         if (dp == NULL)
 270                 return -1;
 271         i = 0;
 272         while ((entry = readdir(dp)) != NULL) {
 273                 if (i >= 4)
 274                         break;
 275                 if (entry->d_name[0] == '.')
 276                         continue;
 277                 if (strlen(entry->d_name) > 12)
 278                         continue;
 279                 if (sscanf(entry->d_name, "%x:%x:%x.%d",
 280                         &dom, &bus, &dev, &func) < 4)
 281                         continue;
 282                 else {
 283                         strlcpy(sub_brg_bdf[i],
 284                                 entry->d_name,
 285                                 sizeof(sub_brg_bdf[i]));
 286                         i++;
 287                 }
 288         }
 289         closedir(dp);
 290
 291         /* get fpga and fvl */
 292         j = 0;
 293         for (i = 0; i < 4; i++) {
 294                 strlcpy(link, dir, sizeof(link));
 295                 strlcat(link, "/", sizeof(link));
 296                 strlcat(link, sub_brg_bdf[i], sizeof(link));
 297                 dp = opendir(link);
 298                 if (dp == NULL)
 299                         return -1;
 300                 while ((entry = readdir(dp)) != NULL) {
 301                         if (j >= 8)
 302                                 break;
 303                         if (entry->d_name[0] == '.')
 304                                 continue;
 305
 306                         if (strlen(entry->d_name) > 12)
 307                                 continue;
 308                         if (sscanf(entry->d_name, "%x:%x:%x.%d",
 309                                 &dom, &bus, &dev, &func) < 4)
 310                                 continue;
 311                         else {
 312                                 if (ifpga_get_dev_vendor_id(entry->d_name,
 313                                         &dev_id, &vendor_id))
 314                                         continue;
 315                                 if (vendor_id == 0x8086 &&
 316                                         (dev_id == 0x0CF8 ||
 317                                         dev_id == 0x0D58 ||
 318                                         dev_id == 0x1580)) {
 319                                         strlcpy(ifpga_dev->fvl_bdf[j],
 320                                                 entry->d_name,
 321                                                 sizeof(ifpga_dev->fvl_bdf[j]));
 322                                         j++;
 323                                 }
 324                         }
 325                 }
 326                 closedir(dp);
 327         }
 328
 329         return 0;
 330 }
 331
 332 #define HIGH_FATAL(_sens, value)\
 333         (((_sens)->flags & OPAE_SENSOR_HIGH_FATAL_VALID) &&\
 334          (value > (_sens)->high_fatal))
 335
 336 #define HIGH_WARN(_sens, value)\
 337         (((_sens)->flags & OPAE_SENSOR_HIGH_WARN_VALID) &&\
 338          (value > (_sens)->high_warn))
 339
 340 #define LOW_FATAL(_sens, value)\
 341         (((_sens)->flags & OPAE_SENSOR_LOW_FATAL_VALID) &&\
 342          (value > (_sens)->low_fatal))
 343
 344 #define LOW_WARN(_sens, value)\
 345         (((_sens)->flags & OPAE_SENSOR_LOW_WARN_VALID) &&\
 346          (value > (_sens)->low_warn))
 347
 348 #define AUX_VOLTAGE_WARN 11400
 349
 350 static int
 351 ifpga_monitor_sensor(struct rte_rawdev *raw_dev,
 352                bool *gsd_start)
 353 {
 354         struct opae_adapter *adapter;
 355         struct opae_manager *mgr;
 356         struct opae_sensor_info *sensor;
 357         unsigned int value;
 358         int ret;
 359
 360         adapter = ifpga_rawdev_get_priv(raw_dev);
 361         if (!adapter)
 362                 return -ENODEV;
 363
 364         mgr = opae_adapter_get_mgr(adapter);
 365         if (!mgr)
 366                 return -ENODEV;
 367
 368         opae_mgr_for_each_sensor(mgr, sensor) {
 369                 if (!(sensor->flags & OPAE_SENSOR_VALID))
 370                         goto fail;
 371
 372                 ret = opae_mgr_get_sensor_value(mgr, sensor, &value);
 373                 if (ret)
 374                         goto fail;
 375
 376                 if (value == 0xdeadbeef) {
 377                         IFPGA_RAWDEV_PMD_ERR("dev_id %d sensor %s value %x\n",
 378                                         raw_dev->dev_id, sensor->name, value);
 379                         continue;
 380                 }
 381
 382                 /* monitor temperature sensors */
 383                 if (!strcmp(sensor->name, "Board Temperature") ||
 384                                 !strcmp(sensor->name, "FPGA Die Temperature")) {
 385                         IFPGA_RAWDEV_PMD_INFO("read sensor %s %d %d %d\n",
 386                                         sensor->name, value, sensor->high_warn,
 387                                         sensor->high_fatal);
 388
 389                         if (HIGH_WARN(sensor, value) ||
 390                                 LOW_WARN(sensor, value)) {
 391                                 IFPGA_RAWDEV_PMD_INFO("%s reach theshold %d\n",
 392                                         sensor->name, value);
 393                                 *gsd_start = true;
 394                                 break;
 395                         }
 396                 }
 397
 398                 /* monitor 12V AUX sensor */
 399                 if (!strcmp(sensor->name, "12V AUX Voltage")) {
 400                         if (value < AUX_VOLTAGE_WARN) {
 401                                 IFPGA_RAWDEV_PMD_INFO(
 402                                         "%s reach theshold %d mV\n",
 403                                         sensor->name, value);
 404                                 *gsd_start = true;
 405                                 break;
 406                         }
 407                 }
 408         }
 409
 410         return 0;
 411 fail:
 412         return -EFAULT;
 413 }
 414
 415 static int set_surprise_link_check_aer(
 416         struct ifpga_rawdev *ifpga_rdev, int force_disable)
 417 {
 418         struct rte_rawdev *rdev;
 419         int fd = -1;
 420         char path[1024];
 421         int pos;
 422         int ret;
 423         uint32_t data;
 424         bool enable = 0;
 425         uint32_t aer_new0, aer_new1;
 426
 427         if (!ifpga_rdev) {
 428                 printf("\n device does not exist\n");
 429                 return -EFAULT;
 430         }
 431
 432         rdev = ifpga_rdev->rawdev;
 433         if (ifpga_rdev->aer_enable)
 434                 return -EFAULT;
 435         if (ifpga_monitor_sensor(rdev, &enable))
 436                 return -EFAULT;
 437         if (enable || force_disable) {
 438                 IFPGA_RAWDEV_PMD_ERR("Set AER, pls graceful shutdown\n");
 439                 ifpga_rdev->aer_enable = 1;
 440                 /* get bridge fd */
 441                 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
 442                 strlcat(path, ifpga_rdev->parent_bdf, sizeof(path));
 443                 strlcat(path, "/config", sizeof(path));
 444                 fd = open(path, O_RDWR);
 445                 if (fd < 0)
 446                         goto end;
 447                 pos = ifpga_pci_find_ext_capability(fd, RTE_PCI_EXT_CAP_ID_ERR);
 448                 if (!pos)
 449                         goto end;
 450                 /* save previout ECAP_AER+0x08 */
 451                 ret = pread(fd, &data, sizeof(data), pos+0x08);
 452                 if (ret == -1)
 453                         goto end;
 454                 ifpga_rdev->aer_old[0] = data;
 455                 /* save previout ECAP_AER+0x14 */
 456                 ret = pread(fd, &data, sizeof(data), pos+0x14);
 457                 if (ret == -1)
 458                         goto end;
 459                 ifpga_rdev->aer_old[1] = data;
 460
 461                 /* set ECAP_AER+0x08 to 0xFFFFFFFF */
 462                 data = 0xffffffff;
 463                 ret = pwrite(fd, &data, 4, pos+0x08);
 464                 if (ret == -1)
 465                         goto end;
 466                 /* set ECAP_AER+0x14 to 0xFFFFFFFF */
 467                 ret = pwrite(fd, &data, 4, pos+0x14);
 468                 if (ret == -1)
 469                         goto end;
 470
 471                 /* read current ECAP_AER+0x08 */
 472                 ret = pread(fd, &data, sizeof(data), pos+0x08);
 473                 if (ret == -1)
 474                         goto end;
 475                 aer_new0 = data;
 476                 /* read current ECAP_AER+0x14 */
 477                 ret = pread(fd, &data, sizeof(data), pos+0x14);
 478                 if (ret == -1)
 479                         goto end;
 480                 aer_new1 = data;
 481
 482                 if (fd != -1)
 483                         close(fd);
 484
 485                 printf(">>>>>>Set AER %x,%x %x,%x\n",
 486                         ifpga_rdev->aer_old[0], ifpga_rdev->aer_old[1],
 487                         aer_new0, aer_new1);
 488
 489                 return 1;
 490                 }
 491
 492 end:
 493         if (fd != -1)
 494                 close(fd);
 495         return -EFAULT;
 496 }
 497
 498 static void *
 499 ifpga_rawdev_gsd_handle(__rte_unused void *param)
 500 {
 501         struct ifpga_rawdev *ifpga_rdev;
 502         int i;
 503         int gsd_enable, ret;
 504 #define MS 1000
 505
 506         while (1) {
 507                 gsd_enable = 0;
 508                 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
 509                         ifpga_rdev = &ifpga_rawdevices[i];
 510                         if (ifpga_rdev->rawdev) {
 511                                 ret = set_surprise_link_check_aer(ifpga_rdev,
 512                                         gsd_enable);
 513                                 if (ret == 1 && !gsd_enable) {
 514                                         gsd_enable = 1;
 515                                         i = -1;
 516                                 }
 517                         }
 518                 }
 519
 520                 if (gsd_enable)
 521                         printf(">>>>>>Pls Shutdown APP\n");
 522
 523                 rte_delay_us(100 * MS);
 524         }
 525
 526         return NULL;
 527 }
 528
 529 static int
 530 ifpga_monitor_start_func(void)
 531 {
 532         int ret;
 533
 534         if (ifpga_monitor_start == 0) {
 535                 ret = pthread_create(&ifpga_monitor_start_thread,
 536                         NULL,
 537                         ifpga_rawdev_gsd_handle, NULL);
 538                 if (ret) {
 539                         IFPGA_RAWDEV_PMD_ERR(
 540                                 "Fail to create ifpga nonitor thread");
 541                         return -1;
 542                 }
 543                 ifpga_monitor_start = 1;
 544         }
 545
 546         return 0;
 547 }
 548 static int
 549 ifpga_monitor_stop_func(void)
 550 {
 551         int ret;
 552
 553         if (ifpga_monitor_start == 1) {
 554                 ret = pthread_cancel(ifpga_monitor_start_thread);
 555                 if (ret)
 556                         IFPGA_RAWDEV_PMD_ERR("Can't cancel the thread");
 557
 558                 ret = pthread_join(ifpga_monitor_start_thread, NULL);
 559                 if (ret)
 560                         IFPGA_RAWDEV_PMD_ERR("Can't join the thread");
 561
 562                 ifpga_monitor_start = 0;
 563
 564                 return ret;
 565         }
 566
 567         return 0;
 568 }
 569
 570 static int
 571 ifpga_fill_afu_dev(struct opae_accelerator *acc,
 572                 struct rte_afu_device *afu_dev)
 573 {
 574         struct rte_mem_resource *res = afu_dev->mem_resource;
 575         struct opae_acc_region_info region_info;
 576         struct opae_acc_info info;
 577         unsigned long i;
 578         int ret;
 579
 580         ret = opae_acc_get_info(acc, &info);
 581         if (ret)
 582                 return ret;
 583
 584         if (info.num_regions > PCI_MAX_RESOURCE)
 585                 return -EFAULT;
 586
 587         afu_dev->num_region = info.num_regions;
 588
 589         for (i = 0; i < info.num_regions; i++) {
 590                 region_info.index = i;
 591                 ret = opae_acc_get_region_info(acc, &region_info);
 592                 if (ret)
 593                         return ret;
 594
 595                 if ((region_info.flags & ACC_REGION_MMIO) &&
 596                     (region_info.flags & ACC_REGION_READ) &&
 597                     (region_info.flags & ACC_REGION_WRITE)) {
 598                         res[i].phys_addr = region_info.phys_addr;
 599                         res[i].len = region_info.len;
 600                         res[i].addr = region_info.addr;
 601                 } else
 602                         return -EFAULT;
 603         }
 604
 605         return 0;
 606 }
 607
 608 static void
 609 ifpga_rawdev_info_get(struct rte_rawdev *dev,
 610                                      rte_rawdev_obj_t dev_info)
 611 {
 612         struct opae_adapter *adapter;
 613         struct opae_accelerator *acc;
 614         struct rte_afu_device *afu_dev;
 615         struct opae_manager *mgr = NULL;
 616         struct opae_eth_group_region_info opae_lside_eth_info;
 617         struct opae_eth_group_region_info opae_nside_eth_info;
 618         int lside_bar_idx, nside_bar_idx;
 619
 620         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 621
 622         if (!dev_info) {
 623                 IFPGA_RAWDEV_PMD_ERR("Invalid request");
 624                 return;
 625         }
 626
 627         adapter = ifpga_rawdev_get_priv(dev);
 628         if (!adapter)
 629                 return;
 630
 631         afu_dev = dev_info;
 632         afu_dev->rawdev = dev;
 633
 634         /* find opae_accelerator and fill info into afu_device */
 635         opae_adapter_for_each_acc(adapter, acc) {
 636                 if (acc->index != afu_dev->id.port)
 637                         continue;
 638
 639                 if (ifpga_fill_afu_dev(acc, afu_dev)) {
 640                         IFPGA_RAWDEV_PMD_ERR("cannot get info\n");
 641                         return;
 642                 }
 643         }
 644
 645         /* get opae_manager to rawdev */
 646         mgr = opae_adapter_get_mgr(adapter);
 647         if (mgr) {
 648                 /* get LineSide BAR Index */
 649                 if (opae_manager_get_eth_group_region_info(mgr, 0,
 650                         &opae_lside_eth_info)) {
 651                         return;
 652                 }
 653                 lside_bar_idx = opae_lside_eth_info.mem_idx;
 654
 655                 /* get NICSide BAR Index */
 656                 if (opae_manager_get_eth_group_region_info(mgr, 1,
 657                         &opae_nside_eth_info)) {
 658                         return;
 659                 }
 660                 nside_bar_idx = opae_nside_eth_info.mem_idx;
 661
 662                 if (lside_bar_idx >= PCI_MAX_RESOURCE ||
 663                         nside_bar_idx >= PCI_MAX_RESOURCE ||
 664                         lside_bar_idx == nside_bar_idx)
 665                         return;
 666
 667                 /* fill LineSide BAR Index */
 668                 afu_dev->mem_resource[lside_bar_idx].phys_addr =
 669                         opae_lside_eth_info.phys_addr;
 670                 afu_dev->mem_resource[lside_bar_idx].len =
 671                         opae_lside_eth_info.len;
 672                 afu_dev->mem_resource[lside_bar_idx].addr =
 673                         opae_lside_eth_info.addr;
 674
 675                 /* fill NICSide BAR Index */
 676                 afu_dev->mem_resource[nside_bar_idx].phys_addr =
 677                         opae_nside_eth_info.phys_addr;
 678                 afu_dev->mem_resource[nside_bar_idx].len =
 679                         opae_nside_eth_info.len;
 680                 afu_dev->mem_resource[nside_bar_idx].addr =
 681                         opae_nside_eth_info.addr;
 682         }
 683 }
 684
 685 static int
 686 ifpga_rawdev_configure(const struct rte_rawdev *dev,
 687                 rte_rawdev_obj_t config)
 688 {
 689         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 690
 691         RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
 692
 693         return config ? 0 : 1;
 694 }
 695
 696 static int
 697 ifpga_rawdev_start(struct rte_rawdev *dev)
 698 {
 699         int ret = 0;
 700         struct opae_adapter *adapter;
 701
 702         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 703
 704         RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
 705
 706         adapter = ifpga_rawdev_get_priv(dev);
 707         if (!adapter)
 708                 return -ENODEV;
 709
 710         return ret;
 711 }
 712
 713 static void
 714 ifpga_rawdev_stop(struct rte_rawdev *dev)
 715 {
 716         dev->started = 0;
 717 }
 718
 719 static int
 720 ifpga_rawdev_close(struct rte_rawdev *dev)
 721 {
 722         return dev ? 0:1;
 723 }
 724
 725 static int
 726 ifpga_rawdev_reset(struct rte_rawdev *dev)
 727 {
 728         return dev ? 0:1;
 729 }
 730
 731 static int
 732 fpga_pr(struct rte_rawdev *raw_dev, u32 port_id, const char *buffer, u32 size,
 733                         u64 *status)
 734 {
 735
 736         struct opae_adapter *adapter;
 737         struct opae_manager *mgr;
 738         struct opae_accelerator *acc;
 739         struct opae_bridge *br;
 740         int ret;
 741
 742         adapter = ifpga_rawdev_get_priv(raw_dev);
 743         if (!adapter)
 744                 return -ENODEV;
 745
 746         mgr = opae_adapter_get_mgr(adapter);
 747         if (!mgr)
 748                 return -ENODEV;
 749
 750         acc = opae_adapter_get_acc(adapter, port_id);
 751         if (!acc)
 752                 return -ENODEV;
 753
 754         br = opae_acc_get_br(acc);
 755         if (!br)
 756                 return -ENODEV;
 757
 758         ret = opae_manager_flash(mgr, port_id, buffer, size, status);
 759         if (ret) {
 760                 IFPGA_RAWDEV_PMD_ERR("%s pr error %d\n", __func__, ret);
 761                 return ret;
 762         }
 763
 764         ret = opae_bridge_reset(br);
 765         if (ret) {
 766                 IFPGA_RAWDEV_PMD_ERR("%s reset port:%d error %d\n",
 767                                 __func__, port_id, ret);
 768                 return ret;
 769         }
 770
 771         return ret;
 772 }
 773
 774 static int
 775 rte_fpga_do_pr(struct rte_rawdev *rawdev, int port_id,
 776                 const char *file_name)
 777 {
 778         struct stat file_stat;
 779         int file_fd;
 780         int ret = 0;
 781         ssize_t buffer_size;
 782         void *buffer;
 783         u64 pr_error;
 784
 785         if (!file_name)
 786                 return -EINVAL;
 787
 788         file_fd = open(file_name, O_RDONLY);
 789         if (file_fd < 0) {
 790                 IFPGA_RAWDEV_PMD_ERR("%s: open file error: %s\n",
 791                                 __func__, file_name);
 792                 IFPGA_RAWDEV_PMD_ERR("Message : %s\n", strerror(errno));
 793                 return -EINVAL;
 794         }
 795         ret = stat(file_name, &file_stat);
 796         if (ret) {
 797                 IFPGA_RAWDEV_PMD_ERR("stat on bitstream file failed: %s\n",
 798                                 file_name);
 799                 ret = -EINVAL;
 800                 goto close_fd;
 801         }
 802         buffer_size = file_stat.st_size;
 803         if (buffer_size <= 0) {
 804                 ret = -EINVAL;
 805                 goto close_fd;
 806         }
 807
 808         IFPGA_RAWDEV_PMD_INFO("bitstream file size: %zu\n", buffer_size);
 809         buffer = rte_malloc(NULL, buffer_size, 0);
 810         if (!buffer) {
 811                 ret = -ENOMEM;
 812                 goto close_fd;
 813         }
 814
 815         /*read the raw data*/
 816         if (buffer_size != read(file_fd, (void *)buffer, buffer_size)) {
 817                 ret = -EINVAL;
 818                 goto free_buffer;
 819         }
 820
 821         /*do PR now*/
 822         ret = fpga_pr(rawdev, port_id, buffer, buffer_size, &pr_error);
 823         IFPGA_RAWDEV_PMD_INFO("downloading to device port %d....%s.\n", port_id,
 824                 ret ? "failed" : "success");
 825         if (ret) {
 826                 ret = -EINVAL;
 827                 goto free_buffer;
 828         }
 829
 830 free_buffer:
 831         if (buffer)
 832                 rte_free(buffer);
 833 close_fd:
 834         close(file_fd);
 835         file_fd = 0;
 836         return ret;
 837 }
 838
 839 static int
 840 ifpga_rawdev_pr(struct rte_rawdev *dev,
 841         rte_rawdev_obj_t pr_conf)
 842 {
 843         struct opae_adapter *adapter;
 844         struct opae_manager *mgr;
 845         struct opae_board_info *info;
 846         struct rte_afu_pr_conf *afu_pr_conf;
 847         int ret;
 848         struct uuid uuid;
 849         struct opae_accelerator *acc;
 850
 851         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 852
 853         adapter = ifpga_rawdev_get_priv(dev);
 854         if (!adapter)
 855                 return -ENODEV;
 856
 857         if (!pr_conf)
 858                 return -EINVAL;
 859
 860         afu_pr_conf = pr_conf;
 861
 862         if (afu_pr_conf->pr_enable) {
 863                 ret = rte_fpga_do_pr(dev,
 864                                 afu_pr_conf->afu_id.port,
 865                                 afu_pr_conf->bs_path);
 866                 if (ret) {
 867                         IFPGA_RAWDEV_PMD_ERR("do pr error %d\n", ret);
 868                         return ret;
 869                 }
 870         }
 871
 872         mgr = opae_adapter_get_mgr(adapter);
 873         if (!mgr) {
 874                 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
 875                 return -1;
 876         }
 877
 878         if (ifpga_mgr_ops.get_board_info(mgr, &info)) {
 879                 IFPGA_RAWDEV_PMD_ERR("ifpga manager get_board_info fail!");
 880                 return -1;
 881         }
 882
 883         if (info->lightweight) {
 884                 /* set uuid to all 0, when fpga is lightweight image */
 885                 memset(&afu_pr_conf->afu_id.uuid.uuid_low, 0, sizeof(u64));
 886                 memset(&afu_pr_conf->afu_id.uuid.uuid_high, 0, sizeof(u64));
 887         } else {
 888                 acc = opae_adapter_get_acc(adapter, afu_pr_conf->afu_id.port);
 889                 if (!acc)
 890                         return -ENODEV;
 891
 892                 ret = opae_acc_get_uuid(acc, &uuid);
 893                 if (ret)
 894                         return ret;
 895
 896                 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_low, uuid.b,
 897                         sizeof(u64));
 898                 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_high, uuid.b + 8,
 899                         sizeof(u64));
 900
 901                 IFPGA_RAWDEV_PMD_INFO("%s: uuid_l=0x%lx, uuid_h=0x%lx\n",
 902                         __func__,
 903                         (unsigned long)afu_pr_conf->afu_id.uuid.uuid_low,
 904                         (unsigned long)afu_pr_conf->afu_id.uuid.uuid_high);
 905                 }
 906         return 0;
 907 }
 908
 909 static int
 910 ifpga_rawdev_get_attr(struct rte_rawdev *dev,
 911         const char *attr_name, uint64_t *attr_value)
 912 {
 913         struct opae_adapter *adapter;
 914         struct opae_manager *mgr;
 915         struct opae_retimer_info opae_rtm_info;
 916         struct opae_retimer_status opae_rtm_status;
 917         struct opae_eth_group_info opae_eth_grp_info;
 918         struct opae_eth_group_region_info opae_eth_grp_reg_info;
 919         int eth_group_num = 0;
 920         uint64_t port_link_bitmap = 0, port_link_bit;
 921         uint32_t i, j, p, q;
 922
 923 #define MAX_PORT_PER_RETIMER    4
 924
 925         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 926
 927         if (!dev || !attr_name || !attr_value) {
 928                 IFPGA_RAWDEV_PMD_ERR("Invalid arguments for getting attributes");
 929                 return -1;
 930         }
 931
 932         adapter = ifpga_rawdev_get_priv(dev);
 933         if (!adapter) {
 934                 IFPGA_RAWDEV_PMD_ERR("Adapter of dev %s is NULL", dev->name);
 935                 return -1;
 936         }
 937
 938         mgr = opae_adapter_get_mgr(adapter);
 939         if (!mgr) {
 940                 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
 941                 return -1;
 942         }
 943
 944         /* currently, eth_group_num is always 2 */
 945         eth_group_num = opae_manager_get_eth_group_nums(mgr);
 946         if (eth_group_num < 0)
 947                 return -1;
 948
 949         if (!strcmp(attr_name, "LineSideBaseMAC")) {
 950                 /* Currently FPGA not implement, so just set all zeros*/
 951                 *attr_value = (uint64_t)0;
 952                 return 0;
 953         }
 954         if (!strcmp(attr_name, "LineSideMACType")) {
 955                 /* eth_group 0 on FPGA connect to LineSide */
 956                 if (opae_manager_get_eth_group_info(mgr, 0,
 957                         &opae_eth_grp_info))
 958                         return -1;
 959                 switch (opae_eth_grp_info.speed) {
 960                 case ETH_SPEED_10G:
 961                         *attr_value =
 962                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI);
 963                         break;
 964                 case ETH_SPEED_25G:
 965                         *attr_value =
 966                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI);
 967                         break;
 968                 default:
 969                         *attr_value =
 970                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_UNKNOWN);
 971                         break;
 972                 }
 973                 return 0;
 974         }
 975         if (!strcmp(attr_name, "LineSideLinkSpeed")) {
 976                 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
 977                         return -1;
 978                 switch (opae_rtm_status.speed) {
 979                 case MXD_1GB:
 980                         *attr_value =
 981                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 982                         break;
 983                 case MXD_2_5GB:
 984                         *attr_value =
 985                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 986                         break;
 987                 case MXD_5GB:
 988                         *attr_value =
 989                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 990                         break;
 991                 case MXD_10GB:
 992                         *attr_value =
 993                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_10GB);
 994                         break;
 995                 case MXD_25GB:
 996                         *attr_value =
 997                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_25GB);
 998                         break;
 999                 case MXD_40GB:
1000                         *attr_value =
1001                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_40GB);
1002                         break;
1003                 case MXD_100GB:
1004                         *attr_value =
1005                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1006                         break;
1007                 case MXD_SPEED_UNKNOWN:
1008                         *attr_value =
1009                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1010                         break;
1011                 default:
1012                         *attr_value =
1013                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1014                         break;
1015                 }
1016                 return 0;
1017         }
1018         if (!strcmp(attr_name, "LineSideLinkRetimerNum")) {
1019                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1020                         return -1;
1021                 *attr_value = (uint64_t)(opae_rtm_info.nums_retimer);
1022                 return 0;
1023         }
1024         if (!strcmp(attr_name, "LineSideLinkPortNum")) {
1025                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1026                         return -1;
1027                 uint64_t tmp = (uint64_t)opae_rtm_info.ports_per_retimer *
1028                                         (uint64_t)opae_rtm_info.nums_retimer;
1029                 *attr_value = tmp;
1030                 return 0;
1031         }
1032         if (!strcmp(attr_name, "LineSideLinkStatus")) {
1033                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1034                         return -1;
1035                 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
1036                         return -1;
1037                 (*attr_value) = 0;
1038                 q = 0;
1039                 port_link_bitmap = (uint64_t)(opae_rtm_status.line_link_bitmap);
1040                 for (i = 0; i < opae_rtm_info.nums_retimer; i++) {
1041                         p = i * MAX_PORT_PER_RETIMER;
1042                         for (j = 0; j < opae_rtm_info.ports_per_retimer; j++) {
1043                                 port_link_bit = 0;
1044                                 IFPGA_BIT_SET(port_link_bit, (p+j));
1045                                 port_link_bit &= port_link_bitmap;
1046                                 if (port_link_bit)
1047                                         IFPGA_BIT_SET((*attr_value), q);
1048                                 q++;
1049                         }
1050                 }
1051                 return 0;
1052         }
1053         if (!strcmp(attr_name, "LineSideBARIndex")) {
1054                 /* eth_group 0 on FPGA connect to LineSide */
1055                 if (opae_manager_get_eth_group_region_info(mgr, 0,
1056                         &opae_eth_grp_reg_info))
1057                         return -1;
1058                 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1059                 return 0;
1060         }
1061         if (!strcmp(attr_name, "NICSideMACType")) {
1062                 /* eth_group 1 on FPGA connect to NicSide */
1063                 if (opae_manager_get_eth_group_info(mgr, 1,
1064                         &opae_eth_grp_info))
1065                         return -1;
1066                 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1067                 return 0;
1068         }
1069         if (!strcmp(attr_name, "NICSideLinkSpeed")) {
1070                 /* eth_group 1 on FPGA connect to NicSide */
1071                 if (opae_manager_get_eth_group_info(mgr, 1,
1072                         &opae_eth_grp_info))
1073                         return -1;
1074                 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1075                 return 0;
1076         }
1077         if (!strcmp(attr_name, "NICSideLinkPortNum")) {
1078                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1079                         return -1;
1080                 uint64_t tmp = (uint64_t)opae_rtm_info.nums_fvl *
1081                                         (uint64_t)opae_rtm_info.ports_per_fvl;
1082                 *attr_value = tmp;
1083                 return 0;
1084         }
1085         if (!strcmp(attr_name, "NICSideLinkStatus"))
1086                 return 0;
1087         if (!strcmp(attr_name, "NICSideBARIndex")) {
1088                 /* eth_group 1 on FPGA connect to NicSide */
1089                 if (opae_manager_get_eth_group_region_info(mgr, 1,
1090                         &opae_eth_grp_reg_info))
1091                         return -1;
1092                 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1093                 return 0;
1094         }
1095
1096         IFPGA_RAWDEV_PMD_ERR("%s not support", attr_name);
1097         return -1;
1098 }
1099
1100 static const struct rte_rawdev_ops ifpga_rawdev_ops = {
1101         .dev_info_get = ifpga_rawdev_info_get,
1102         .dev_configure = ifpga_rawdev_configure,
1103         .dev_start = ifpga_rawdev_start,
1104         .dev_stop = ifpga_rawdev_stop,
1105         .dev_close = ifpga_rawdev_close,
1106         .dev_reset = ifpga_rawdev_reset,
1107
1108         .queue_def_conf = NULL,
1109         .queue_setup = NULL,
1110         .queue_release = NULL,
1111
1112         .attr_get = ifpga_rawdev_get_attr,
1113         .attr_set = NULL,
1114
1115         .enqueue_bufs = NULL,
1116         .dequeue_bufs = NULL,
1117
1118         .dump = NULL,
1119
1120         .xstats_get = NULL,
1121         .xstats_get_names = NULL,
1122         .xstats_get_by_name = NULL,
1123         .xstats_reset = NULL,
1124
1125         .firmware_status_get = NULL,
1126         .firmware_version_get = NULL,
1127         .firmware_load = ifpga_rawdev_pr,
1128         .firmware_unload = NULL,
1129
1130         .dev_selftest = NULL,
1131 };
1132
1133 static int
1134 ifpga_get_fme_error_prop(struct opae_manager *mgr,
1135                 u64 prop_id, u64 *val)
1136 {
1137         struct feature_prop prop;
1138
1139         prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1140         prop.prop_id = prop_id;
1141
1142         if (opae_manager_ifpga_get_prop(mgr, &prop))
1143                 return -EINVAL;
1144
1145         *val = prop.data;
1146
1147         return 0;
1148 }
1149
1150 static int
1151 ifpga_set_fme_error_prop(struct opae_manager *mgr,
1152                 u64 prop_id, u64 val)
1153 {
1154         struct feature_prop prop;
1155
1156         prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1157         prop.prop_id = prop_id;
1158
1159         prop.data = val;
1160
1161         if (opae_manager_ifpga_set_prop(mgr, &prop))
1162                 return -EINVAL;
1163
1164         return 0;
1165 }
1166
1167 static int
1168 fme_err_read_seu_emr(struct opae_manager *mgr)
1169 {
1170         u64 val;
1171         int ret;
1172
1173         ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_LOW, &val);
1174         if (ret)
1175                 return -EINVAL;
1176
1177         IFPGA_RAWDEV_PMD_INFO("seu emr low: 0x%" PRIx64 "\n", val);
1178
1179         ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_HIGH, &val);
1180         if (ret)
1181                 return -EINVAL;
1182
1183         IFPGA_RAWDEV_PMD_INFO("seu emr high: 0x%" PRIx64 "\n", val);
1184
1185         return 0;
1186 }
1187
1188 static int fme_clear_warning_intr(struct opae_manager *mgr)
1189 {
1190         u64 val;
1191
1192         if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_INJECT_ERRORS, 0))
1193                 return -EINVAL;
1194
1195         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1196                 return -EINVAL;
1197         if ((val & 0x40) != 0)
1198                 IFPGA_RAWDEV_PMD_INFO("clean not done\n");
1199
1200         return 0;
1201 }
1202
1203 static int fme_clean_fme_error(struct opae_manager *mgr)
1204 {
1205         u64 val;
1206
1207         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1208                 return -EINVAL;
1209
1210         IFPGA_RAWDEV_PMD_DEBUG("before clean 0x%" PRIx64 "\n", val);
1211
1212         ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_CLEAR, val);
1213
1214         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1215                 return -EINVAL;
1216
1217         IFPGA_RAWDEV_PMD_DEBUG("after clean 0x%" PRIx64 "\n", val);
1218
1219         return 0;
1220 }
1221
1222 static int
1223 fme_err_handle_error0(struct opae_manager *mgr)
1224 {
1225         struct feature_fme_error0 fme_error0;
1226         u64 val;
1227
1228         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1229                 return -EINVAL;
1230
1231         if (fme_clean_fme_error(mgr))
1232                 return -EINVAL;
1233
1234         fme_error0.csr = val;
1235
1236         if (fme_error0.fabric_err)
1237                 IFPGA_RAWDEV_PMD_ERR("Fabric error\n");
1238         else if (fme_error0.fabfifo_overflow)
1239                 IFPGA_RAWDEV_PMD_ERR("Fabric fifo under/overflow error\n");
1240         else if (fme_error0.afu_acc_mode_err)
1241                 IFPGA_RAWDEV_PMD_ERR("AFU PF/VF access mismatch detected\n");
1242         else if (fme_error0.pcie0cdc_parity_err)
1243                 IFPGA_RAWDEV_PMD_ERR("PCIe0 CDC Parity Error\n");
1244         else if (fme_error0.cvlcdc_parity_err)
1245                 IFPGA_RAWDEV_PMD_ERR("CVL CDC Parity Error\n");
1246         else if (fme_error0.fpgaseuerr)
1247                 fme_err_read_seu_emr(mgr);
1248
1249         /* clean the errors */
1250         if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, val))
1251                 return -EINVAL;
1252
1253         return 0;
1254 }
1255
1256 static int
1257 fme_err_handle_catfatal_error(struct opae_manager *mgr)
1258 {
1259         struct feature_fme_ras_catfaterror fme_catfatal;
1260         u64 val;
1261
1262         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_CATFATAL_ERRORS, &val))
1263                 return -EINVAL;
1264
1265         fme_catfatal.csr = val;
1266
1267         if (fme_catfatal.cci_fatal_err)
1268                 IFPGA_RAWDEV_PMD_ERR("CCI error detected\n");
1269         else if (fme_catfatal.fabric_fatal_err)
1270                 IFPGA_RAWDEV_PMD_ERR("Fabric fatal error detected\n");
1271         else if (fme_catfatal.pcie_poison_err)
1272                 IFPGA_RAWDEV_PMD_ERR("Poison error from PCIe ports\n");
1273         else if (fme_catfatal.inject_fata_err)
1274                 IFPGA_RAWDEV_PMD_ERR("Injected Fatal Error\n");
1275         else if (fme_catfatal.crc_catast_err)
1276                 IFPGA_RAWDEV_PMD_ERR("a catastrophic EDCRC error\n");
1277         else if (fme_catfatal.injected_catast_err)
1278                 IFPGA_RAWDEV_PMD_ERR("Injected Catastrophic Error\n");
1279         else if (fme_catfatal.bmc_seu_catast_err)
1280                 fme_err_read_seu_emr(mgr);
1281
1282         return 0;
1283 }
1284
1285 static int
1286 fme_err_handle_nonfaterror(struct opae_manager *mgr)
1287 {
1288         struct feature_fme_ras_nonfaterror nonfaterr;
1289         u64 val;
1290
1291         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1292                 return -EINVAL;
1293
1294         nonfaterr.csr = val;
1295
1296         if (nonfaterr.temp_thresh_ap1)
1297                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP1\n");
1298         else if (nonfaterr.temp_thresh_ap2)
1299                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP2\n");
1300         else if (nonfaterr.pcie_error)
1301                 IFPGA_RAWDEV_PMD_INFO("an error has occurred in pcie\n");
1302         else if (nonfaterr.portfatal_error)
1303                 IFPGA_RAWDEV_PMD_INFO("fatal error occurred in AFU port.\n");
1304         else if (nonfaterr.proc_hot)
1305                 IFPGA_RAWDEV_PMD_INFO("a ProcHot event\n");
1306         else if (nonfaterr.afu_acc_mode_err)
1307                 IFPGA_RAWDEV_PMD_INFO("an AFU PF/VF access mismatch\n");
1308         else if (nonfaterr.injected_nonfata_err) {
1309                 IFPGA_RAWDEV_PMD_INFO("Injected Warning Error\n");
1310                 fme_clear_warning_intr(mgr);
1311         } else if (nonfaterr.temp_thresh_AP6)
1312                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP6\n");
1313         else if (nonfaterr.power_thresh_AP1)
1314                 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP1\n");
1315         else if (nonfaterr.power_thresh_AP2)
1316                 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP2\n");
1317         else if (nonfaterr.mbp_err)
1318                 IFPGA_RAWDEV_PMD_INFO("an MBP event\n");
1319
1320         return 0;
1321 }
1322
1323 static void
1324 fme_interrupt_handler(void *param)
1325 {
1326         struct opae_manager *mgr = (struct opae_manager *)param;
1327
1328         IFPGA_RAWDEV_PMD_INFO("%s interrupt occurred\n", __func__);
1329
1330         fme_err_handle_error0(mgr);
1331         fme_err_handle_nonfaterror(mgr);
1332         fme_err_handle_catfatal_error(mgr);
1333 }
1334
1335 int
1336 ifpga_unregister_msix_irq(enum ifpga_irq_type type,
1337                 int vec_start, rte_intr_callback_fn handler, void *arg)
1338 {
1339         struct rte_intr_handle intr_handle;
1340
1341         if (type == IFPGA_FME_IRQ)
1342                 intr_handle = ifpga_irq_handle[0];
1343         else if (type == IFPGA_AFU_IRQ)
1344                 intr_handle = ifpga_irq_handle[vec_start + 1];
1345
1346         rte_intr_efd_disable(&intr_handle);
1347
1348         return rte_intr_callback_unregister(&intr_handle,
1349                         handler, arg);
1350 }
1351
1352 int
1353 ifpga_register_msix_irq(struct rte_rawdev *dev, int port_id,
1354                 enum ifpga_irq_type type, int vec_start, int count,
1355                 rte_intr_callback_fn handler, const char *name,
1356                 void *arg)
1357 {
1358         int ret;
1359         struct rte_intr_handle intr_handle;
1360         struct opae_adapter *adapter;
1361         struct opae_manager *mgr;
1362         struct opae_accelerator *acc;
1363
1364         adapter = ifpga_rawdev_get_priv(dev);
1365         if (!adapter)
1366                 return -ENODEV;
1367
1368         mgr = opae_adapter_get_mgr(adapter);
1369         if (!mgr)
1370                 return -ENODEV;
1371
1372         if (type == IFPGA_FME_IRQ) {
1373                 intr_handle = ifpga_irq_handle[0];
1374                 count = 1;
1375         } else if (type == IFPGA_AFU_IRQ)
1376                 intr_handle = ifpga_irq_handle[vec_start + 1];
1377
1378         intr_handle.type = RTE_INTR_HANDLE_VFIO_MSIX;
1379
1380         ret = rte_intr_efd_enable(&intr_handle, count);
1381         if (ret)
1382                 return -ENODEV;
1383
1384         intr_handle.fd = intr_handle.efds[0];
1385
1386         IFPGA_RAWDEV_PMD_DEBUG("register %s irq, vfio_fd=%d, fd=%d\n",
1387                         name, intr_handle.vfio_dev_fd,
1388                         intr_handle.fd);
1389
1390         if (type == IFPGA_FME_IRQ) {
1391                 struct fpga_fme_err_irq_set err_irq_set;
1392                 err_irq_set.evtfd = intr_handle.efds[0];
1393
1394                 ret = opae_manager_ifpga_set_err_irq(mgr, &err_irq_set);
1395                 if (ret)
1396                         return -EINVAL;
1397         } else if (type == IFPGA_AFU_IRQ) {
1398                 acc = opae_adapter_get_acc(adapter, port_id);
1399                 if (!acc)
1400                         return -EINVAL;
1401
1402                 ret = opae_acc_set_irq(acc, vec_start, count, intr_handle.efds);
1403                 if (ret)
1404                         return -EINVAL;
1405         }
1406
1407         /* register interrupt handler using DPDK API */
1408         ret = rte_intr_callback_register(&intr_handle,
1409                         handler, (void *)arg);
1410         if (ret)
1411                 return -EINVAL;
1412
1413         IFPGA_RAWDEV_PMD_INFO("success register %s interrupt\n", name);
1414
1415         return 0;
1416 }
1417
1418 static int
1419 ifpga_rawdev_create(struct rte_pci_device *pci_dev,
1420                         int socket_id)
1421 {
1422         int ret = 0;
1423         struct rte_rawdev *rawdev = NULL;
1424         struct ifpga_rawdev *dev = NULL;
1425         struct opae_adapter *adapter = NULL;
1426         struct opae_manager *mgr = NULL;
1427         struct opae_adapter_data_pci *data = NULL;
1428         char name[RTE_RAWDEV_NAME_MAX_LEN];
1429         int i;
1430
1431         if (!pci_dev) {
1432                 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1433                 ret = -EINVAL;
1434                 goto cleanup;
1435         }
1436
1437         memset(name, 0, sizeof(name));
1438         snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%02x:%02x.%x",
1439                 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1440
1441         IFPGA_RAWDEV_PMD_INFO("Init %s on NUMA node %d", name, rte_socket_id());
1442
1443         /* Allocate device structure */
1444         rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct opae_adapter),
1445                                          socket_id);
1446         if (rawdev == NULL) {
1447                 IFPGA_RAWDEV_PMD_ERR("Unable to allocate rawdevice");
1448                 ret = -EINVAL;
1449                 goto cleanup;
1450         }
1451
1452         ipn3ke_bridge_func.get_ifpga_rawdev = ifpga_rawdev_get;
1453         ipn3ke_bridge_func.set_i40e_sw_dev = rte_pmd_i40e_set_switch_dev;
1454
1455         dev = ifpga_rawdev_allocate(rawdev);
1456         if (dev == NULL) {
1457                 IFPGA_RAWDEV_PMD_ERR("Unable to allocate ifpga_rawdevice");
1458                 ret = -EINVAL;
1459                 goto cleanup;
1460         }
1461         dev->aer_enable = 0;
1462
1463         /* alloc OPAE_FPGA_PCI data to register to OPAE hardware level API */
1464         data = opae_adapter_data_alloc(OPAE_FPGA_PCI);
1465         if (!data) {
1466                 ret = -ENOMEM;
1467                 goto cleanup;
1468         }
1469
1470         /* init opae_adapter_data_pci for device specific information */
1471         for (i = 0; i < PCI_MAX_RESOURCE; i++) {
1472                 data->region[i].phys_addr = pci_dev->mem_resource[i].phys_addr;
1473                 data->region[i].len = pci_dev->mem_resource[i].len;
1474                 data->region[i].addr = pci_dev->mem_resource[i].addr;
1475         }
1476         data->device_id = pci_dev->id.device_id;
1477         data->vendor_id = pci_dev->id.vendor_id;
1478         data->bus = pci_dev->addr.bus;
1479         data->devid = pci_dev->addr.devid;
1480         data->function = pci_dev->addr.function;
1481         data->vfio_dev_fd = pci_dev->intr_handle.vfio_dev_fd;
1482
1483         adapter = rawdev->dev_private;
1484         /* create a opae_adapter based on above device data */
1485         ret = opae_adapter_init(adapter, pci_dev->device.name, data);
1486         if (ret) {
1487                 ret = -ENOMEM;
1488                 goto free_adapter_data;
1489         }
1490
1491         rawdev->dev_ops = &ifpga_rawdev_ops;
1492         rawdev->device = &pci_dev->device;
1493         rawdev->driver_name = pci_dev->driver->driver.name;
1494
1495         /* must enumerate the adapter before use it */
1496         ret = opae_adapter_enumerate(adapter);
1497         if (ret)
1498                 goto free_adapter_data;
1499
1500         /* get opae_manager to rawdev */
1501         mgr = opae_adapter_get_mgr(adapter);
1502         if (mgr) {
1503                 /* PF function */
1504                 IFPGA_RAWDEV_PMD_INFO("this is a PF function");
1505         }
1506
1507         ret = ifpga_register_msix_irq(rawdev, 0, IFPGA_FME_IRQ, 0, 0,
1508                         fme_interrupt_handler, "fme_irq", mgr);
1509         if (ret)
1510                 goto free_adapter_data;
1511
1512         return ret;
1513
1514 free_adapter_data:
1515         if (data)
1516                 opae_adapter_data_free(data);
1517 cleanup:
1518         if (rawdev)
1519                 rte_rawdev_pmd_release(rawdev);
1520
1521         return ret;
1522 }
1523
1524 static int
1525 ifpga_rawdev_destroy(struct rte_pci_device *pci_dev)
1526 {
1527         int ret;
1528         struct rte_rawdev *rawdev;
1529         char name[RTE_RAWDEV_NAME_MAX_LEN];
1530         struct opae_adapter *adapter;
1531         struct opae_manager *mgr;
1532
1533         if (!pci_dev) {
1534                 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1535                 ret = -EINVAL;
1536                 return ret;
1537         }
1538
1539         memset(name, 0, sizeof(name));
1540         snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%x:%02x.%x",
1541                 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1542
1543         IFPGA_RAWDEV_PMD_INFO("Closing %s on NUMA node %d",
1544                 name, rte_socket_id());
1545
1546         rawdev = rte_rawdev_pmd_get_named_dev(name);
1547         if (!rawdev) {
1548                 IFPGA_RAWDEV_PMD_ERR("Invalid device name (%s)", name);
1549                 return -EINVAL;
1550         }
1551
1552         adapter = ifpga_rawdev_get_priv(rawdev);
1553         if (!adapter)
1554                 return -ENODEV;
1555
1556         mgr = opae_adapter_get_mgr(adapter);
1557         if (!mgr)
1558                 return -ENODEV;
1559
1560         if (ifpga_unregister_msix_irq(IFPGA_FME_IRQ, 0,
1561                                 fme_interrupt_handler, mgr))
1562                 return -EINVAL;
1563
1564         opae_adapter_data_free(adapter->data);
1565         opae_adapter_free(adapter);
1566
1567         /* rte_rawdev_close is called by pmd_release */
1568         ret = rte_rawdev_pmd_release(rawdev);
1569         if (ret)
1570                 IFPGA_RAWDEV_PMD_DEBUG("Device cleanup failed");
1571
1572         return ret;
1573 }
1574
1575 static int
1576 ifpga_rawdev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1577         struct rte_pci_device *pci_dev)
1578 {
1579         IFPGA_RAWDEV_PMD_FUNC_TRACE();
1580         return ifpga_rawdev_create(pci_dev, rte_socket_id());
1581 }
1582
1583 static int
1584 ifpga_rawdev_pci_remove(struct rte_pci_device *pci_dev)
1585 {
1586         ifpga_monitor_stop_func();
1587         return ifpga_rawdev_destroy(pci_dev);
1588 }
1589
1590 static struct rte_pci_driver rte_ifpga_rawdev_pmd = {
1591         .id_table  = pci_ifpga_map,
1592         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1593         .probe     = ifpga_rawdev_pci_probe,
1594         .remove    = ifpga_rawdev_pci_remove,
1595 };
1596
1597 RTE_PMD_REGISTER_PCI(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1598 RTE_PMD_REGISTER_PCI_TABLE(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1599 RTE_PMD_REGISTER_KMOD_DEP(ifpga_rawdev_pci_driver, "* igb_uio | uio_pci_generic | vfio-pci");
1600
1601 RTE_INIT(ifpga_rawdev_init_log)
1602 {
1603         ifpga_rawdev_logtype = rte_log_register("driver.raw.init");
1604         if (ifpga_rawdev_logtype >= 0)
1605                 rte_log_set_level(ifpga_rawdev_logtype, RTE_LOG_NOTICE);
1606 }
1607
1608 static const char * const valid_args[] = {
1609 #define IFPGA_ARG_NAME         "ifpga"
1610         IFPGA_ARG_NAME,
1611 #define IFPGA_ARG_PORT         "port"
1612         IFPGA_ARG_PORT,
1613 #define IFPGA_AFU_BTS          "afu_bts"
1614         IFPGA_AFU_BTS,
1615         NULL
1616 };
1617
1618 static int ifpga_rawdev_get_string_arg(const char *key __rte_unused,
1619         const char *value, void *extra_args)
1620 {
1621         int size;
1622         if (!value || !extra_args)
1623                 return -EINVAL;
1624
1625         size = strlen(value) + 1;
1626         *(char **)extra_args = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
1627         if (!*(char **)extra_args)
1628                 return -ENOMEM;
1629
1630         strlcpy(*(char **)extra_args, value, size);
1631
1632         return 0;
1633 }
1634 static int
1635 ifpga_cfg_probe(struct rte_vdev_device *dev)
1636 {
1637         struct rte_devargs *devargs;
1638         struct rte_kvargs *kvlist = NULL;
1639         struct rte_rawdev *rawdev = NULL;
1640         struct ifpga_rawdev *ifpga_dev;
1641         int port;
1642         char *name = NULL;
1643         const char *bdf;
1644         char dev_name[RTE_RAWDEV_NAME_MAX_LEN];
1645         int ret = -1;
1646
1647         devargs = dev->device.devargs;
1648
1649         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1650         if (!kvlist) {
1651                 IFPGA_RAWDEV_PMD_LOG(ERR, "error when parsing param");
1652                 goto end;
1653         }
1654
1655         if (rte_kvargs_count(kvlist, IFPGA_ARG_NAME) == 1) {
1656                 if (rte_kvargs_process(kvlist, IFPGA_ARG_NAME,
1657                                        &ifpga_rawdev_get_string_arg,
1658                                        &name) < 0) {
1659                         IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1660                                      IFPGA_ARG_NAME);
1661                         goto end;
1662                 }
1663         } else {
1664                 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1665                           IFPGA_ARG_NAME);
1666                 goto end;
1667         }
1668
1669         if (rte_kvargs_count(kvlist, IFPGA_ARG_PORT) == 1) {
1670                 if (rte_kvargs_process(kvlist,
1671                         IFPGA_ARG_PORT,
1672                         &rte_ifpga_get_integer32_arg,
1673                         &port) < 0) {
1674                         IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1675                                 IFPGA_ARG_PORT);
1676                         goto end;
1677                 }
1678         } else {
1679                 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1680                           IFPGA_ARG_PORT);
1681                 goto end;
1682         }
1683
1684         memset(dev_name, 0, sizeof(dev_name));
1685         snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%s", name);
1686         rawdev = rte_rawdev_pmd_get_named_dev(dev_name);
1687         if (!rawdev)
1688                 goto end;
1689         ifpga_dev = ifpga_rawdev_get(rawdev);
1690         if (!ifpga_dev)
1691                 goto end;
1692         bdf = name;
1693         ifpga_rawdev_fill_info(ifpga_dev, bdf);
1694
1695         ifpga_monitor_start_func();
1696
1697         memset(dev_name, 0, sizeof(dev_name));
1698         snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "%d|%s",
1699         port, name);
1700
1701         ret = rte_eal_hotplug_add(RTE_STR(IFPGA_BUS_NAME),
1702                         dev_name, devargs->args);
1703 end:
1704         if (kvlist)
1705                 rte_kvargs_free(kvlist);
1706         if (name)
1707                 free(name);
1708
1709         return ret;
1710 }
1711
1712 static int
1713 ifpga_cfg_remove(struct rte_vdev_device *vdev)
1714 {
1715         IFPGA_RAWDEV_PMD_INFO("Remove ifpga_cfg %p",
1716                 vdev);
1717
1718         return 0;
1719 }
1720
1721 static struct rte_vdev_driver ifpga_cfg_driver = {
1722         .probe = ifpga_cfg_probe,
1723         .remove = ifpga_cfg_remove,
1724 };
1725
1726 RTE_PMD_REGISTER_VDEV(ifpga_rawdev_cfg, ifpga_cfg_driver);
1727 RTE_PMD_REGISTER_ALIAS(ifpga_rawdev_cfg, ifpga_cfg);
1728 RTE_PMD_REGISTER_PARAM_STRING(ifpga_rawdev_cfg,
1729         "ifpga=<string> "
1730         "port=<int> "
1731         "afu_bts=<path>");