drivers/raw/ifpga/ifpga_rawdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2018 Intel Corporation
   3  */
   4
   5 #include <string.h>
   6 #include <dirent.h>
   7 #include <sys/stat.h>
   8 #include <unistd.h>
   9 #include <sys/types.h>
  10 #include <fcntl.h>
  11 #include <sys/ioctl.h>
  12 #include <sys/epoll.h>
  13 #include <rte_log.h>
  14 #include <rte_bus.h>
  15 #include <rte_malloc.h>
  16 #include <rte_devargs.h>
  17 #include <rte_memcpy.h>
  18 #include <rte_pci.h>
  19 #include <rte_bus_pci.h>
  20 #include <rte_kvargs.h>
  21 #include <rte_alarm.h>
  22 #include <rte_interrupts.h>
  23 #include <rte_errno.h>
  24 #include <rte_per_lcore.h>
  25 #include <rte_memory.h>
  26 #include <rte_memzone.h>
  27 #include <rte_eal.h>
  28 #include <rte_common.h>
  29 #include <rte_bus_vdev.h>
  30 #include <rte_string_fns.h>
  31 #include <rte_pmd_i40e.h>
  32
  33 #include "base/opae_hw_api.h"
  34 #include "base/opae_ifpga_hw_api.h"
  35 #include "base/ifpga_api.h"
  36 #include "rte_rawdev.h"
  37 #include "rte_rawdev_pmd.h"
  38 #include "rte_bus_ifpga.h"
  39 #include "ifpga_common.h"
  40 #include "ifpga_logs.h"
  41 #include "ifpga_rawdev.h"
  42 #include "ipn3ke_rawdev_api.h"
  43
  44 #define PCI_VENDOR_ID_INTEL          0x8086
  45 /* PCI Device ID */
  46 #define PCIE_DEVICE_ID_PF_INT_5_X    0xBCBD
  47 #define PCIE_DEVICE_ID_PF_INT_6_X    0xBCC0
  48 #define PCIE_DEVICE_ID_PF_DSC_1_X    0x09C4
  49 #define PCIE_DEVICE_ID_PAC_N3000     0x0B30
  50 /* VF Device */
  51 #define PCIE_DEVICE_ID_VF_INT_5_X    0xBCBF
  52 #define PCIE_DEVICE_ID_VF_INT_6_X    0xBCC1
  53 #define PCIE_DEVICE_ID_VF_DSC_1_X    0x09C5
  54 #define PCIE_DEVICE_ID_VF_PAC_N3000  0x0B31
  55 #define RTE_MAX_RAW_DEVICE           10
  56
  57 static const struct rte_pci_id pci_ifpga_map[] = {
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PAC_N3000),},
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_PAC_N3000),},
  66         { .vendor_id = 0, /* sentinel */ },
  67 };
  68
  69 static struct ifpga_rawdev ifpga_rawdevices[IFPGA_RAWDEV_NUM];
  70
  71 static int ifpga_monitor_start;
  72 static pthread_t ifpga_monitor_start_thread;
  73
  74 #define IFPGA_MAX_IRQ 12
  75 /* 0 for FME interrupt, others are reserved for AFU irq */
  76 static struct rte_intr_handle *ifpga_irq_handle[IFPGA_MAX_IRQ];
  77
  78 static struct ifpga_rawdev *
  79 ifpga_rawdev_allocate(struct rte_rawdev *rawdev);
  80 static int set_surprise_link_check_aer(
  81                 struct ifpga_rawdev *ifpga_rdev, int force_disable);
  82 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
  83                                               int start, uint32_t cap);
  84 static int ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap);
  85
  86 struct ifpga_rawdev *
  87 ifpga_rawdev_get(const struct rte_rawdev *rawdev)
  88 {
  89         struct ifpga_rawdev *dev;
  90         unsigned int i;
  91
  92         if (rawdev == NULL)
  93                 return NULL;
  94
  95         for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
  96                 dev = &ifpga_rawdevices[i];
  97                 if (dev->rawdev == rawdev)
  98                         return dev;
  99         }
 100
 101         return NULL;
 102 }
 103
 104 static inline uint8_t
 105 ifpga_rawdev_find_free_device_index(void)
 106 {
 107         uint16_t dev_id;
 108
 109         for (dev_id = 0; dev_id < IFPGA_RAWDEV_NUM; dev_id++) {
 110                 if (ifpga_rawdevices[dev_id].rawdev == NULL)
 111                         return dev_id;
 112         }
 113
 114         return IFPGA_RAWDEV_NUM;
 115 }
 116 static struct ifpga_rawdev *
 117 ifpga_rawdev_allocate(struct rte_rawdev *rawdev)
 118 {
 119         struct ifpga_rawdev *dev;
 120         uint16_t dev_id;
 121
 122         dev = ifpga_rawdev_get(rawdev);
 123         if (dev != NULL) {
 124                 IFPGA_RAWDEV_PMD_ERR("Event device already allocated!");
 125                 return NULL;
 126         }
 127
 128         dev_id = ifpga_rawdev_find_free_device_index();
 129         if (dev_id == IFPGA_RAWDEV_NUM) {
 130                 IFPGA_RAWDEV_PMD_ERR("Reached maximum number of raw devices");
 131                 return NULL;
 132         }
 133
 134         dev = &ifpga_rawdevices[dev_id];
 135         dev->rawdev = rawdev;
 136         dev->dev_id = dev_id;
 137
 138         return dev;
 139 }
 140
 141 static int
 142 ifpga_pci_find_next_ext_capability(unsigned int fd, int start, uint32_t cap)
 143 {
 144         uint32_t header;
 145         int ttl;
 146         int pos = RTE_PCI_CFG_SPACE_SIZE;
 147         int ret;
 148
 149         /* minimum 8 bytes per capability */
 150         ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
 151
 152         if (start)
 153                 pos = start;
 154         ret = pread(fd, &header, sizeof(header), pos);
 155         if (ret == -1)
 156                 return -1;
 157
 158         /*
 159          * If we have no capabilities, this is indicated by cap ID,
 160          * cap version and next pointer all being 0.
 161          */
 162         if (header == 0)
 163                 return 0;
 164
 165         while (ttl-- > 0) {
 166                 if (RTE_PCI_EXT_CAP_ID(header) == cap && pos != start)
 167                         return pos;
 168
 169                 pos = RTE_PCI_EXT_CAP_NEXT(header);
 170                 if (pos < RTE_PCI_CFG_SPACE_SIZE)
 171                         break;
 172                 ret = pread(fd, &header, sizeof(header), pos);
 173                 if (ret == -1)
 174                         return -1;
 175         }
 176
 177         return 0;
 178 }
 179
 180 static int
 181 ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap)
 182 {
 183         return ifpga_pci_find_next_ext_capability(fd, 0, cap);
 184 }
 185
 186 static int ifpga_get_dev_vendor_id(const char *bdf,
 187         uint32_t *dev_id, uint32_t *vendor_id)
 188 {
 189         int fd;
 190         char path[1024];
 191         int ret;
 192         uint32_t header;
 193
 194         strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
 195         strlcat(path, bdf, sizeof(path));
 196         strlcat(path, "/config", sizeof(path));
 197         fd = open(path, O_RDWR);
 198         if (fd < 0)
 199                 return -1;
 200         ret = pread(fd, &header, sizeof(header), 0);
 201         if (ret == -1) {
 202                 close(fd);
 203                 return -1;
 204         }
 205         (*vendor_id) = header & 0xffff;
 206         (*dev_id) = (header >> 16) & 0xffff;
 207         close(fd);
 208
 209         return 0;
 210 }
 211 static int ifpga_rawdev_fill_info(struct ifpga_rawdev *ifpga_dev,
 212         const char *bdf)
 213 {
 214         char path[1024] = "/sys/bus/pci/devices/0000:";
 215         char link[1024], link1[1024];
 216         char dir[1024] = "/sys/devices/";
 217         char *c;
 218         int ret;
 219         char sub_brg_bdf[4][16];
 220         int point;
 221         DIR *dp = NULL;
 222         struct dirent *entry;
 223         int i, j;
 224
 225         unsigned int dom, bus, dev;
 226         int func;
 227         uint32_t dev_id, vendor_id;
 228
 229         strlcat(path, bdf, sizeof(path));
 230         memset(link, 0, sizeof(link));
 231         memset(link1, 0, sizeof(link1));
 232         ret = readlink(path, link, (sizeof(link)-1));
 233         if ((ret < 0) || ((unsigned int)ret > (sizeof(link)-1)))
 234                 return -1;
 235         link[ret] = 0;   /* terminate string with null character */
 236         strlcpy(link1, link, sizeof(link1));
 237         memset(ifpga_dev->parent_bdf, 0, 16);
 238         point = strlen(link);
 239         if (point < 39)
 240                 return -1;
 241         point -= 39;
 242         link[point] = 0;
 243         if (point < 12)
 244                 return -1;
 245         point -= 12;
 246         rte_memcpy(ifpga_dev->parent_bdf, &link[point], 12);
 247
 248         point = strlen(link1);
 249         if (point < 26)
 250                 return -1;
 251         point -= 26;
 252         link1[point] = 0;
 253         if (point < 12)
 254                 return -1;
 255         point -= 12;
 256         c = strchr(link1, 'p');
 257         if (!c)
 258                 return -1;
 259         strlcat(dir, c, sizeof(dir));
 260
 261         /* scan folder */
 262         dp = opendir(dir);
 263         if (dp == NULL)
 264                 return -1;
 265         i = 0;
 266         while ((entry = readdir(dp)) != NULL) {
 267                 if (i >= 4)
 268                         break;
 269                 if (entry->d_name[0] == '.')
 270                         continue;
 271                 if (strlen(entry->d_name) > 12)
 272                         continue;
 273                 if (sscanf(entry->d_name, "%x:%x:%x.%d",
 274                         &dom, &bus, &dev, &func) < 4)
 275                         continue;
 276                 else {
 277                         strlcpy(sub_brg_bdf[i],
 278                                 entry->d_name,
 279                                 sizeof(sub_brg_bdf[i]));
 280                         i++;
 281                 }
 282         }
 283         closedir(dp);
 284
 285         /* get fpga and fvl */
 286         j = 0;
 287         for (i = 0; i < 4; i++) {
 288                 strlcpy(link, dir, sizeof(link));
 289                 strlcat(link, "/", sizeof(link));
 290                 strlcat(link, sub_brg_bdf[i], sizeof(link));
 291                 dp = opendir(link);
 292                 if (dp == NULL)
 293                         return -1;
 294                 while ((entry = readdir(dp)) != NULL) {
 295                         if (j >= 8)
 296                                 break;
 297                         if (entry->d_name[0] == '.')
 298                                 continue;
 299
 300                         if (strlen(entry->d_name) > 12)
 301                                 continue;
 302                         if (sscanf(entry->d_name, "%x:%x:%x.%d",
 303                                 &dom, &bus, &dev, &func) < 4)
 304                                 continue;
 305                         else {
 306                                 if (ifpga_get_dev_vendor_id(entry->d_name,
 307                                         &dev_id, &vendor_id))
 308                                         continue;
 309                                 if (vendor_id == 0x8086 &&
 310                                         (dev_id == 0x0CF8 ||
 311                                         dev_id == 0x0D58 ||
 312                                         dev_id == 0x1580)) {
 313                                         strlcpy(ifpga_dev->fvl_bdf[j],
 314                                                 entry->d_name,
 315                                                 sizeof(ifpga_dev->fvl_bdf[j]));
 316                                         j++;
 317                                 }
 318                         }
 319                 }
 320                 closedir(dp);
 321         }
 322
 323         return 0;
 324 }
 325
 326 #define HIGH_FATAL(_sens, value)\
 327         (((_sens)->flags & OPAE_SENSOR_HIGH_FATAL_VALID) &&\
 328          (value > (_sens)->high_fatal))
 329
 330 #define HIGH_WARN(_sens, value)\
 331         (((_sens)->flags & OPAE_SENSOR_HIGH_WARN_VALID) &&\
 332          (value > (_sens)->high_warn))
 333
 334 #define LOW_FATAL(_sens, value)\
 335         (((_sens)->flags & OPAE_SENSOR_LOW_FATAL_VALID) &&\
 336          (value > (_sens)->low_fatal))
 337
 338 #define LOW_WARN(_sens, value)\
 339         (((_sens)->flags & OPAE_SENSOR_LOW_WARN_VALID) &&\
 340          (value > (_sens)->low_warn))
 341
 342 #define AUX_VOLTAGE_WARN 11400
 343
 344 static int
 345 ifpga_monitor_sensor(struct rte_rawdev *raw_dev,
 346                bool *gsd_start)
 347 {
 348         struct opae_adapter *adapter;
 349         struct opae_manager *mgr;
 350         struct opae_sensor_info *sensor;
 351         unsigned int value;
 352         int ret;
 353
 354         adapter = ifpga_rawdev_get_priv(raw_dev);
 355         if (!adapter)
 356                 return -ENODEV;
 357
 358         mgr = opae_adapter_get_mgr(adapter);
 359         if (!mgr)
 360                 return -ENODEV;
 361
 362         opae_mgr_for_each_sensor(mgr, sensor) {
 363                 if (!(sensor->flags & OPAE_SENSOR_VALID))
 364                         goto fail;
 365
 366                 ret = opae_mgr_get_sensor_value(mgr, sensor, &value);
 367                 if (ret)
 368                         goto fail;
 369
 370                 if (value == 0xdeadbeef) {
 371                         IFPGA_RAWDEV_PMD_ERR("dev_id %d sensor %s value %x\n",
 372                                         raw_dev->dev_id, sensor->name, value);
 373                         continue;
 374                 }
 375
 376                 /* monitor temperature sensors */
 377                 if (!strcmp(sensor->name, "Board Temperature") ||
 378                                 !strcmp(sensor->name, "FPGA Die Temperature")) {
 379                         IFPGA_RAWDEV_PMD_INFO("read sensor %s %d %d %d\n",
 380                                         sensor->name, value, sensor->high_warn,
 381                                         sensor->high_fatal);
 382
 383                         if (HIGH_WARN(sensor, value) ||
 384                                 LOW_WARN(sensor, value)) {
 385                                 IFPGA_RAWDEV_PMD_INFO("%s reach theshold %d\n",
 386                                         sensor->name, value);
 387                                 *gsd_start = true;
 388                                 break;
 389                         }
 390                 }
 391
 392                 /* monitor 12V AUX sensor */
 393                 if (!strcmp(sensor->name, "12V AUX Voltage")) {
 394                         if (value < AUX_VOLTAGE_WARN) {
 395                                 IFPGA_RAWDEV_PMD_INFO(
 396                                         "%s reach theshold %d mV\n",
 397                                         sensor->name, value);
 398                                 *gsd_start = true;
 399                                 break;
 400                         }
 401                 }
 402         }
 403
 404         return 0;
 405 fail:
 406         return -EFAULT;
 407 }
 408
 409 static int set_surprise_link_check_aer(
 410         struct ifpga_rawdev *ifpga_rdev, int force_disable)
 411 {
 412         struct rte_rawdev *rdev;
 413         int fd = -1;
 414         char path[1024];
 415         int pos;
 416         int ret;
 417         uint32_t data;
 418         bool enable = 0;
 419         uint32_t aer_new0, aer_new1;
 420
 421         if (!ifpga_rdev) {
 422                 printf("\n device does not exist\n");
 423                 return -EFAULT;
 424         }
 425
 426         rdev = ifpga_rdev->rawdev;
 427         if (ifpga_rdev->aer_enable)
 428                 return -EFAULT;
 429         if (ifpga_monitor_sensor(rdev, &enable))
 430                 return -EFAULT;
 431         if (enable || force_disable) {
 432                 IFPGA_RAWDEV_PMD_ERR("Set AER, pls graceful shutdown\n");
 433                 ifpga_rdev->aer_enable = 1;
 434                 /* get bridge fd */
 435                 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
 436                 strlcat(path, ifpga_rdev->parent_bdf, sizeof(path));
 437                 strlcat(path, "/config", sizeof(path));
 438                 fd = open(path, O_RDWR);
 439                 if (fd < 0)
 440                         goto end;
 441                 pos = ifpga_pci_find_ext_capability(fd, RTE_PCI_EXT_CAP_ID_ERR);
 442                 if (!pos)
 443                         goto end;
 444                 /* save previout ECAP_AER+0x08 */
 445                 ret = pread(fd, &data, sizeof(data), pos+0x08);
 446                 if (ret == -1)
 447                         goto end;
 448                 ifpga_rdev->aer_old[0] = data;
 449                 /* save previout ECAP_AER+0x14 */
 450                 ret = pread(fd, &data, sizeof(data), pos+0x14);
 451                 if (ret == -1)
 452                         goto end;
 453                 ifpga_rdev->aer_old[1] = data;
 454
 455                 /* set ECAP_AER+0x08 to 0xFFFFFFFF */
 456                 data = 0xffffffff;
 457                 ret = pwrite(fd, &data, 4, pos+0x08);
 458                 if (ret == -1)
 459                         goto end;
 460                 /* set ECAP_AER+0x14 to 0xFFFFFFFF */
 461                 ret = pwrite(fd, &data, 4, pos+0x14);
 462                 if (ret == -1)
 463                         goto end;
 464
 465                 /* read current ECAP_AER+0x08 */
 466                 ret = pread(fd, &data, sizeof(data), pos+0x08);
 467                 if (ret == -1)
 468                         goto end;
 469                 aer_new0 = data;
 470                 /* read current ECAP_AER+0x14 */
 471                 ret = pread(fd, &data, sizeof(data), pos+0x14);
 472                 if (ret == -1)
 473                         goto end;
 474                 aer_new1 = data;
 475
 476                 if (fd != -1)
 477                         close(fd);
 478
 479                 printf(">>>>>>Set AER %x,%x %x,%x\n",
 480                         ifpga_rdev->aer_old[0], ifpga_rdev->aer_old[1],
 481                         aer_new0, aer_new1);
 482
 483                 return 1;
 484                 }
 485
 486 end:
 487         if (fd != -1)
 488                 close(fd);
 489         return -EFAULT;
 490 }
 491
 492 static void *
 493 ifpga_rawdev_gsd_handle(__rte_unused void *param)
 494 {
 495         struct ifpga_rawdev *ifpga_rdev;
 496         int i;
 497         int gsd_enable, ret;
 498 #define MS 1000
 499
 500         while (1) {
 501                 gsd_enable = 0;
 502                 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
 503                         ifpga_rdev = &ifpga_rawdevices[i];
 504                         if (ifpga_rdev->rawdev) {
 505                                 ret = set_surprise_link_check_aer(ifpga_rdev,
 506                                         gsd_enable);
 507                                 if (ret == 1 && !gsd_enable) {
 508                                         gsd_enable = 1;
 509                                         i = -1;
 510                                 }
 511                         }
 512                 }
 513
 514                 if (gsd_enable)
 515                         printf(">>>>>>Pls Shutdown APP\n");
 516
 517                 rte_delay_us(100 * MS);
 518         }
 519
 520         return NULL;
 521 }
 522
 523 static int
 524 ifpga_monitor_start_func(void)
 525 {
 526         int ret;
 527
 528         if (ifpga_monitor_start == 0) {
 529                 ret = rte_ctrl_thread_create(&ifpga_monitor_start_thread,
 530                                              "ifpga-monitor", NULL,
 531                                              ifpga_rawdev_gsd_handle, NULL);
 532                 if (ret != 0) {
 533                         IFPGA_RAWDEV_PMD_ERR(
 534                                 "Fail to create ifpga nonitor thread");
 535                         return -1;
 536                 }
 537                 ifpga_monitor_start = 1;
 538         }
 539
 540         return 0;
 541 }
 542 static int
 543 ifpga_monitor_stop_func(void)
 544 {
 545         int ret;
 546
 547         if (ifpga_monitor_start == 1) {
 548                 ret = pthread_cancel(ifpga_monitor_start_thread);
 549                 if (ret)
 550                         IFPGA_RAWDEV_PMD_ERR("Can't cancel the thread");
 551
 552                 ret = pthread_join(ifpga_monitor_start_thread, NULL);
 553                 if (ret)
 554                         IFPGA_RAWDEV_PMD_ERR("Can't join the thread");
 555
 556                 ifpga_monitor_start = 0;
 557
 558                 return ret;
 559         }
 560
 561         return 0;
 562 }
 563
 564 static int
 565 ifpga_fill_afu_dev(struct opae_accelerator *acc,
 566                 struct rte_afu_device *afu_dev)
 567 {
 568         struct rte_mem_resource *res = afu_dev->mem_resource;
 569         struct opae_acc_region_info region_info;
 570         struct opae_acc_info info;
 571         unsigned long i;
 572         int ret;
 573
 574         ret = opae_acc_get_info(acc, &info);
 575         if (ret)
 576                 return ret;
 577
 578         if (info.num_regions > PCI_MAX_RESOURCE)
 579                 return -EFAULT;
 580
 581         afu_dev->num_region = info.num_regions;
 582
 583         for (i = 0; i < info.num_regions; i++) {
 584                 region_info.index = i;
 585                 ret = opae_acc_get_region_info(acc, &region_info);
 586                 if (ret)
 587                         return ret;
 588
 589                 if ((region_info.flags & ACC_REGION_MMIO) &&
 590                     (region_info.flags & ACC_REGION_READ) &&
 591                     (region_info.flags & ACC_REGION_WRITE)) {
 592                         res[i].phys_addr = region_info.phys_addr;
 593                         res[i].len = region_info.len;
 594                         res[i].addr = region_info.addr;
 595                 } else
 596                         return -EFAULT;
 597         }
 598
 599         return 0;
 600 }
 601
 602 static int
 603 ifpga_rawdev_info_get(struct rte_rawdev *dev,
 604                       rte_rawdev_obj_t dev_info,
 605                       size_t dev_info_size)
 606 {
 607         struct opae_adapter *adapter;
 608         struct opae_accelerator *acc;
 609         struct rte_afu_device *afu_dev;
 610         struct opae_manager *mgr = NULL;
 611         struct opae_eth_group_region_info opae_lside_eth_info;
 612         struct opae_eth_group_region_info opae_nside_eth_info;
 613         int lside_bar_idx, nside_bar_idx;
 614
 615         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 616
 617         if (!dev_info || dev_info_size != sizeof(*afu_dev)) {
 618                 IFPGA_RAWDEV_PMD_ERR("Invalid request");
 619                 return -EINVAL;
 620         }
 621
 622         adapter = ifpga_rawdev_get_priv(dev);
 623         if (!adapter)
 624                 return -ENOENT;
 625
 626         afu_dev = dev_info;
 627         afu_dev->rawdev = dev;
 628
 629         /* find opae_accelerator and fill info into afu_device */
 630         opae_adapter_for_each_acc(adapter, acc) {
 631                 if (acc->index != afu_dev->id.port)
 632                         continue;
 633
 634                 if (ifpga_fill_afu_dev(acc, afu_dev)) {
 635                         IFPGA_RAWDEV_PMD_ERR("cannot get info\n");
 636                         return -ENOENT;
 637                 }
 638         }
 639
 640         /* get opae_manager to rawdev */
 641         mgr = opae_adapter_get_mgr(adapter);
 642         if (mgr) {
 643                 /* get LineSide BAR Index */
 644                 if (opae_manager_get_eth_group_region_info(mgr, 0,
 645                         &opae_lside_eth_info)) {
 646                         return -ENOENT;
 647                 }
 648                 lside_bar_idx = opae_lside_eth_info.mem_idx;
 649
 650                 /* get NICSide BAR Index */
 651                 if (opae_manager_get_eth_group_region_info(mgr, 1,
 652                         &opae_nside_eth_info)) {
 653                         return -ENOENT;
 654                 }
 655                 nside_bar_idx = opae_nside_eth_info.mem_idx;
 656
 657                 if (lside_bar_idx >= PCI_MAX_RESOURCE ||
 658                         nside_bar_idx >= PCI_MAX_RESOURCE ||
 659                         lside_bar_idx == nside_bar_idx)
 660                         return -ENOENT;
 661
 662                 /* fill LineSide BAR Index */
 663                 afu_dev->mem_resource[lside_bar_idx].phys_addr =
 664                         opae_lside_eth_info.phys_addr;
 665                 afu_dev->mem_resource[lside_bar_idx].len =
 666                         opae_lside_eth_info.len;
 667                 afu_dev->mem_resource[lside_bar_idx].addr =
 668                         opae_lside_eth_info.addr;
 669
 670                 /* fill NICSide BAR Index */
 671                 afu_dev->mem_resource[nside_bar_idx].phys_addr =
 672                         opae_nside_eth_info.phys_addr;
 673                 afu_dev->mem_resource[nside_bar_idx].len =
 674                         opae_nside_eth_info.len;
 675                 afu_dev->mem_resource[nside_bar_idx].addr =
 676                         opae_nside_eth_info.addr;
 677         }
 678         return 0;
 679 }
 680
 681 static int
 682 ifpga_rawdev_configure(const struct rte_rawdev *dev,
 683                 rte_rawdev_obj_t config,
 684                 size_t config_size __rte_unused)
 685 {
 686         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 687
 688         RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
 689
 690         return config ? 0 : 1;
 691 }
 692
 693 static int
 694 ifpga_rawdev_start(struct rte_rawdev *dev)
 695 {
 696         int ret = 0;
 697         struct opae_adapter *adapter;
 698
 699         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 700
 701         RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
 702
 703         adapter = ifpga_rawdev_get_priv(dev);
 704         if (!adapter)
 705                 return -ENODEV;
 706
 707         return ret;
 708 }
 709
 710 static void
 711 ifpga_rawdev_stop(struct rte_rawdev *dev)
 712 {
 713         dev->started = 0;
 714 }
 715
 716 static int
 717 ifpga_rawdev_close(struct rte_rawdev *dev)
 718 {
 719         struct opae_adapter *adapter;
 720
 721         if (dev) {
 722                 adapter = ifpga_rawdev_get_priv(dev);
 723                 if (adapter) {
 724                         opae_adapter_destroy(adapter);
 725                         opae_adapter_data_free(adapter->data);
 726                 }
 727         }
 728
 729         return dev ? 0:1;
 730 }
 731
 732 static int
 733 ifpga_rawdev_reset(struct rte_rawdev *dev)
 734 {
 735         return dev ? 0:1;
 736 }
 737
 738 static int
 739 fpga_pr(struct rte_rawdev *raw_dev, u32 port_id, const char *buffer, u32 size,
 740                         u64 *status)
 741 {
 742
 743         struct opae_adapter *adapter;
 744         struct opae_manager *mgr;
 745         struct opae_accelerator *acc;
 746         struct opae_bridge *br;
 747         int ret;
 748
 749         adapter = ifpga_rawdev_get_priv(raw_dev);
 750         if (!adapter)
 751                 return -ENODEV;
 752
 753         mgr = opae_adapter_get_mgr(adapter);
 754         if (!mgr)
 755                 return -ENODEV;
 756
 757         acc = opae_adapter_get_acc(adapter, port_id);
 758         if (!acc)
 759                 return -ENODEV;
 760
 761         br = opae_acc_get_br(acc);
 762         if (!br)
 763                 return -ENODEV;
 764
 765         ret = opae_manager_flash(mgr, port_id, buffer, size, status);
 766         if (ret) {
 767                 IFPGA_RAWDEV_PMD_ERR("%s pr error %d\n", __func__, ret);
 768                 return ret;
 769         }
 770
 771         ret = opae_bridge_reset(br);
 772         if (ret) {
 773                 IFPGA_RAWDEV_PMD_ERR("%s reset port:%d error %d\n",
 774                                 __func__, port_id, ret);
 775                 return ret;
 776         }
 777
 778         return ret;
 779 }
 780
 781 static int
 782 rte_fpga_do_pr(struct rte_rawdev *rawdev, int port_id,
 783                 const char *file_name)
 784 {
 785         struct stat file_stat;
 786         int file_fd;
 787         int ret = 0;
 788         ssize_t buffer_size;
 789         void *buffer, *buf_to_free;
 790         u64 pr_error;
 791
 792         if (!file_name)
 793                 return -EINVAL;
 794
 795         file_fd = open(file_name, O_RDONLY);
 796         if (file_fd < 0) {
 797                 IFPGA_RAWDEV_PMD_ERR("%s: open file error: %s\n",
 798                                 __func__, file_name);
 799                 IFPGA_RAWDEV_PMD_ERR("Message : %s\n", strerror(errno));
 800                 return -EINVAL;
 801         }
 802         ret = stat(file_name, &file_stat);
 803         if (ret) {
 804                 IFPGA_RAWDEV_PMD_ERR("stat on bitstream file failed: %s\n",
 805                                 file_name);
 806                 ret = -EINVAL;
 807                 goto close_fd;
 808         }
 809         buffer_size = file_stat.st_size;
 810         if (buffer_size <= 0) {
 811                 ret = -EINVAL;
 812                 goto close_fd;
 813         }
 814
 815         IFPGA_RAWDEV_PMD_INFO("bitstream file size: %zu\n", buffer_size);
 816         buffer = rte_malloc(NULL, buffer_size, 0);
 817         if (!buffer) {
 818                 ret = -ENOMEM;
 819                 goto close_fd;
 820         }
 821         buf_to_free = buffer;
 822
 823         /*read the raw data*/
 824         if (buffer_size != read(file_fd, (void *)buffer, buffer_size)) {
 825                 ret = -EINVAL;
 826                 goto free_buffer;
 827         }
 828
 829         /*do PR now*/
 830         ret = fpga_pr(rawdev, port_id, buffer, buffer_size, &pr_error);
 831         IFPGA_RAWDEV_PMD_INFO("downloading to device port %d....%s.\n", port_id,
 832                 ret ? "failed" : "success");
 833         if (ret) {
 834                 ret = -EINVAL;
 835                 goto free_buffer;
 836         }
 837
 838 free_buffer:
 839         if (buf_to_free)
 840                 rte_free(buf_to_free);
 841 close_fd:
 842         close(file_fd);
 843         file_fd = 0;
 844         return ret;
 845 }
 846
 847 static int
 848 ifpga_rawdev_pr(struct rte_rawdev *dev,
 849         rte_rawdev_obj_t pr_conf)
 850 {
 851         struct opae_adapter *adapter;
 852         struct opae_manager *mgr;
 853         struct opae_board_info *info;
 854         struct rte_afu_pr_conf *afu_pr_conf;
 855         int ret;
 856         struct uuid uuid;
 857         struct opae_accelerator *acc;
 858
 859         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 860
 861         adapter = ifpga_rawdev_get_priv(dev);
 862         if (!adapter)
 863                 return -ENODEV;
 864
 865         if (!pr_conf)
 866                 return -EINVAL;
 867
 868         afu_pr_conf = pr_conf;
 869
 870         if (afu_pr_conf->pr_enable) {
 871                 ret = rte_fpga_do_pr(dev,
 872                                 afu_pr_conf->afu_id.port,
 873                                 afu_pr_conf->bs_path);
 874                 if (ret) {
 875                         IFPGA_RAWDEV_PMD_ERR("do pr error %d\n", ret);
 876                         return ret;
 877                 }
 878         }
 879
 880         mgr = opae_adapter_get_mgr(adapter);
 881         if (!mgr) {
 882                 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
 883                 return -1;
 884         }
 885
 886         if (ifpga_mgr_ops.get_board_info(mgr, &info)) {
 887                 IFPGA_RAWDEV_PMD_ERR("ifpga manager get_board_info fail!");
 888                 return -1;
 889         }
 890
 891         if (info->lightweight) {
 892                 /* set uuid to all 0, when fpga is lightweight image */
 893                 memset(&afu_pr_conf->afu_id.uuid.uuid_low, 0, sizeof(u64));
 894                 memset(&afu_pr_conf->afu_id.uuid.uuid_high, 0, sizeof(u64));
 895         } else {
 896                 acc = opae_adapter_get_acc(adapter, afu_pr_conf->afu_id.port);
 897                 if (!acc)
 898                         return -ENODEV;
 899
 900                 ret = opae_acc_get_uuid(acc, &uuid);
 901                 if (ret)
 902                         return ret;
 903
 904                 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_low, uuid.b,
 905                         sizeof(u64));
 906                 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_high, uuid.b + 8,
 907                         sizeof(u64));
 908
 909                 IFPGA_RAWDEV_PMD_INFO("%s: uuid_l=0x%lx, uuid_h=0x%lx\n",
 910                         __func__,
 911                         (unsigned long)afu_pr_conf->afu_id.uuid.uuid_low,
 912                         (unsigned long)afu_pr_conf->afu_id.uuid.uuid_high);
 913                 }
 914         return 0;
 915 }
 916
 917 static int
 918 ifpga_rawdev_get_attr(struct rte_rawdev *dev,
 919         const char *attr_name, uint64_t *attr_value)
 920 {
 921         struct opae_adapter *adapter;
 922         struct opae_manager *mgr;
 923         struct opae_retimer_info opae_rtm_info;
 924         struct opae_retimer_status opae_rtm_status;
 925         struct opae_eth_group_info opae_eth_grp_info;
 926         struct opae_eth_group_region_info opae_eth_grp_reg_info;
 927         int eth_group_num = 0;
 928         uint64_t port_link_bitmap = 0, port_link_bit;
 929         uint32_t i, j, p, q;
 930
 931 #define MAX_PORT_PER_RETIMER    4
 932
 933         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 934
 935         if (!dev || !attr_name || !attr_value) {
 936                 IFPGA_RAWDEV_PMD_ERR("Invalid arguments for getting attributes");
 937                 return -1;
 938         }
 939
 940         adapter = ifpga_rawdev_get_priv(dev);
 941         if (!adapter) {
 942                 IFPGA_RAWDEV_PMD_ERR("Adapter of dev %s is NULL", dev->name);
 943                 return -1;
 944         }
 945
 946         mgr = opae_adapter_get_mgr(adapter);
 947         if (!mgr) {
 948                 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
 949                 return -1;
 950         }
 951
 952         /* currently, eth_group_num is always 2 */
 953         eth_group_num = opae_manager_get_eth_group_nums(mgr);
 954         if (eth_group_num < 0)
 955                 return -1;
 956
 957         if (!strcmp(attr_name, "LineSideBaseMAC")) {
 958                 /* Currently FPGA not implement, so just set all zeros*/
 959                 *attr_value = (uint64_t)0;
 960                 return 0;
 961         }
 962         if (!strcmp(attr_name, "LineSideMACType")) {
 963                 /* eth_group 0 on FPGA connect to LineSide */
 964                 if (opae_manager_get_eth_group_info(mgr, 0,
 965                         &opae_eth_grp_info))
 966                         return -1;
 967                 switch (opae_eth_grp_info.speed) {
 968                 case ETH_SPEED_10G:
 969                         *attr_value =
 970                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI);
 971                         break;
 972                 case ETH_SPEED_25G:
 973                         *attr_value =
 974                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI);
 975                         break;
 976                 default:
 977                         *attr_value =
 978                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_UNKNOWN);
 979                         break;
 980                 }
 981                 return 0;
 982         }
 983         if (!strcmp(attr_name, "LineSideLinkSpeed")) {
 984                 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
 985                         return -1;
 986                 switch (opae_rtm_status.speed) {
 987                 case MXD_1GB:
 988                         *attr_value =
 989                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 990                         break;
 991                 case MXD_2_5GB:
 992                         *attr_value =
 993                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 994                         break;
 995                 case MXD_5GB:
 996                         *attr_value =
 997                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 998                         break;
 999                 case MXD_10GB:
1000                         *attr_value =
1001                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_10GB);
1002                         break;
1003                 case MXD_25GB:
1004                         *attr_value =
1005                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_25GB);
1006                         break;
1007                 case MXD_40GB:
1008                         *attr_value =
1009                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_40GB);
1010                         break;
1011                 case MXD_100GB:
1012                         *attr_value =
1013                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1014                         break;
1015                 case MXD_SPEED_UNKNOWN:
1016                         *attr_value =
1017                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1018                         break;
1019                 default:
1020                         *attr_value =
1021                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1022                         break;
1023                 }
1024                 return 0;
1025         }
1026         if (!strcmp(attr_name, "LineSideLinkRetimerNum")) {
1027                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1028                         return -1;
1029                 *attr_value = (uint64_t)(opae_rtm_info.nums_retimer);
1030                 return 0;
1031         }
1032         if (!strcmp(attr_name, "LineSideLinkPortNum")) {
1033                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1034                         return -1;
1035                 uint64_t tmp = (uint64_t)opae_rtm_info.ports_per_retimer *
1036                                         (uint64_t)opae_rtm_info.nums_retimer;
1037                 *attr_value = tmp;
1038                 return 0;
1039         }
1040         if (!strcmp(attr_name, "LineSideLinkStatus")) {
1041                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1042                         return -1;
1043                 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
1044                         return -1;
1045                 (*attr_value) = 0;
1046                 q = 0;
1047                 port_link_bitmap = (uint64_t)(opae_rtm_status.line_link_bitmap);
1048                 for (i = 0; i < opae_rtm_info.nums_retimer; i++) {
1049                         p = i * MAX_PORT_PER_RETIMER;
1050                         for (j = 0; j < opae_rtm_info.ports_per_retimer; j++) {
1051                                 port_link_bit = 0;
1052                                 IFPGA_BIT_SET(port_link_bit, (p+j));
1053                                 port_link_bit &= port_link_bitmap;
1054                                 if (port_link_bit)
1055                                         IFPGA_BIT_SET((*attr_value), q);
1056                                 q++;
1057                         }
1058                 }
1059                 return 0;
1060         }
1061         if (!strcmp(attr_name, "LineSideBARIndex")) {
1062                 /* eth_group 0 on FPGA connect to LineSide */
1063                 if (opae_manager_get_eth_group_region_info(mgr, 0,
1064                         &opae_eth_grp_reg_info))
1065                         return -1;
1066                 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1067                 return 0;
1068         }
1069         if (!strcmp(attr_name, "NICSideMACType")) {
1070                 /* eth_group 1 on FPGA connect to NicSide */
1071                 if (opae_manager_get_eth_group_info(mgr, 1,
1072                         &opae_eth_grp_info))
1073                         return -1;
1074                 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1075                 return 0;
1076         }
1077         if (!strcmp(attr_name, "NICSideLinkSpeed")) {
1078                 /* eth_group 1 on FPGA connect to NicSide */
1079                 if (opae_manager_get_eth_group_info(mgr, 1,
1080                         &opae_eth_grp_info))
1081                         return -1;
1082                 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1083                 return 0;
1084         }
1085         if (!strcmp(attr_name, "NICSideLinkPortNum")) {
1086                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1087                         return -1;
1088                 uint64_t tmp = (uint64_t)opae_rtm_info.nums_fvl *
1089                                         (uint64_t)opae_rtm_info.ports_per_fvl;
1090                 *attr_value = tmp;
1091                 return 0;
1092         }
1093         if (!strcmp(attr_name, "NICSideLinkStatus"))
1094                 return 0;
1095         if (!strcmp(attr_name, "NICSideBARIndex")) {
1096                 /* eth_group 1 on FPGA connect to NicSide */
1097                 if (opae_manager_get_eth_group_region_info(mgr, 1,
1098                         &opae_eth_grp_reg_info))
1099                         return -1;
1100                 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1101                 return 0;
1102         }
1103
1104         IFPGA_RAWDEV_PMD_ERR("%s not support", attr_name);
1105         return -1;
1106 }
1107
1108 static const struct rte_rawdev_ops ifpga_rawdev_ops = {
1109         .dev_info_get = ifpga_rawdev_info_get,
1110         .dev_configure = ifpga_rawdev_configure,
1111         .dev_start = ifpga_rawdev_start,
1112         .dev_stop = ifpga_rawdev_stop,
1113         .dev_close = ifpga_rawdev_close,
1114         .dev_reset = ifpga_rawdev_reset,
1115
1116         .queue_def_conf = NULL,
1117         .queue_setup = NULL,
1118         .queue_release = NULL,
1119
1120         .attr_get = ifpga_rawdev_get_attr,
1121         .attr_set = NULL,
1122
1123         .enqueue_bufs = NULL,
1124         .dequeue_bufs = NULL,
1125
1126         .dump = NULL,
1127
1128         .xstats_get = NULL,
1129         .xstats_get_names = NULL,
1130         .xstats_get_by_name = NULL,
1131         .xstats_reset = NULL,
1132
1133         .firmware_status_get = NULL,
1134         .firmware_version_get = NULL,
1135         .firmware_load = ifpga_rawdev_pr,
1136         .firmware_unload = NULL,
1137
1138         .dev_selftest = NULL,
1139 };
1140
1141 static int
1142 ifpga_get_fme_error_prop(struct opae_manager *mgr,
1143                 u64 prop_id, u64 *val)
1144 {
1145         struct feature_prop prop;
1146
1147         prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1148         prop.prop_id = prop_id;
1149
1150         if (opae_manager_ifpga_get_prop(mgr, &prop))
1151                 return -EINVAL;
1152
1153         *val = prop.data;
1154
1155         return 0;
1156 }
1157
1158 static int
1159 ifpga_set_fme_error_prop(struct opae_manager *mgr,
1160                 u64 prop_id, u64 val)
1161 {
1162         struct feature_prop prop;
1163
1164         prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1165         prop.prop_id = prop_id;
1166
1167         prop.data = val;
1168
1169         if (opae_manager_ifpga_set_prop(mgr, &prop))
1170                 return -EINVAL;
1171
1172         return 0;
1173 }
1174
1175 static int
1176 fme_err_read_seu_emr(struct opae_manager *mgr)
1177 {
1178         u64 val;
1179         int ret;
1180
1181         ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_LOW, &val);
1182         if (ret)
1183                 return -EINVAL;
1184
1185         IFPGA_RAWDEV_PMD_INFO("seu emr low: 0x%" PRIx64 "\n", val);
1186
1187         ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_HIGH, &val);
1188         if (ret)
1189                 return -EINVAL;
1190
1191         IFPGA_RAWDEV_PMD_INFO("seu emr high: 0x%" PRIx64 "\n", val);
1192
1193         return 0;
1194 }
1195
1196 static int fme_clear_warning_intr(struct opae_manager *mgr)
1197 {
1198         u64 val;
1199
1200         if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_INJECT_ERRORS, 0))
1201                 return -EINVAL;
1202
1203         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1204                 return -EINVAL;
1205         if ((val & 0x40) != 0)
1206                 IFPGA_RAWDEV_PMD_INFO("clean not done\n");
1207
1208         return 0;
1209 }
1210
1211 static int fme_clean_fme_error(struct opae_manager *mgr)
1212 {
1213         u64 val;
1214
1215         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1216                 return -EINVAL;
1217
1218         IFPGA_RAWDEV_PMD_DEBUG("before clean 0x%" PRIx64 "\n", val);
1219
1220         ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_CLEAR, val);
1221
1222         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1223                 return -EINVAL;
1224
1225         IFPGA_RAWDEV_PMD_DEBUG("after clean 0x%" PRIx64 "\n", val);
1226
1227         return 0;
1228 }
1229
1230 static int
1231 fme_err_handle_error0(struct opae_manager *mgr)
1232 {
1233         struct feature_fme_error0 fme_error0;
1234         u64 val;
1235
1236         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1237                 return -EINVAL;
1238
1239         if (fme_clean_fme_error(mgr))
1240                 return -EINVAL;
1241
1242         fme_error0.csr = val;
1243
1244         if (fme_error0.fabric_err)
1245                 IFPGA_RAWDEV_PMD_ERR("Fabric error\n");
1246         else if (fme_error0.fabfifo_overflow)
1247                 IFPGA_RAWDEV_PMD_ERR("Fabric fifo under/overflow error\n");
1248         else if (fme_error0.afu_acc_mode_err)
1249                 IFPGA_RAWDEV_PMD_ERR("AFU PF/VF access mismatch detected\n");
1250         else if (fme_error0.pcie0cdc_parity_err)
1251                 IFPGA_RAWDEV_PMD_ERR("PCIe0 CDC Parity Error\n");
1252         else if (fme_error0.cvlcdc_parity_err)
1253                 IFPGA_RAWDEV_PMD_ERR("CVL CDC Parity Error\n");
1254         else if (fme_error0.fpgaseuerr)
1255                 fme_err_read_seu_emr(mgr);
1256
1257         /* clean the errors */
1258         if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, val))
1259                 return -EINVAL;
1260
1261         return 0;
1262 }
1263
1264 static int
1265 fme_err_handle_catfatal_error(struct opae_manager *mgr)
1266 {
1267         struct feature_fme_ras_catfaterror fme_catfatal;
1268         u64 val;
1269
1270         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_CATFATAL_ERRORS, &val))
1271                 return -EINVAL;
1272
1273         fme_catfatal.csr = val;
1274
1275         if (fme_catfatal.cci_fatal_err)
1276                 IFPGA_RAWDEV_PMD_ERR("CCI error detected\n");
1277         else if (fme_catfatal.fabric_fatal_err)
1278                 IFPGA_RAWDEV_PMD_ERR("Fabric fatal error detected\n");
1279         else if (fme_catfatal.pcie_poison_err)
1280                 IFPGA_RAWDEV_PMD_ERR("Poison error from PCIe ports\n");
1281         else if (fme_catfatal.inject_fata_err)
1282                 IFPGA_RAWDEV_PMD_ERR("Injected Fatal Error\n");
1283         else if (fme_catfatal.crc_catast_err)
1284                 IFPGA_RAWDEV_PMD_ERR("a catastrophic EDCRC error\n");
1285         else if (fme_catfatal.injected_catast_err)
1286                 IFPGA_RAWDEV_PMD_ERR("Injected Catastrophic Error\n");
1287         else if (fme_catfatal.bmc_seu_catast_err)
1288                 fme_err_read_seu_emr(mgr);
1289
1290         return 0;
1291 }
1292
1293 static int
1294 fme_err_handle_nonfaterror(struct opae_manager *mgr)
1295 {
1296         struct feature_fme_ras_nonfaterror nonfaterr;
1297         u64 val;
1298
1299         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1300                 return -EINVAL;
1301
1302         nonfaterr.csr = val;
1303
1304         if (nonfaterr.temp_thresh_ap1)
1305                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP1\n");
1306         else if (nonfaterr.temp_thresh_ap2)
1307                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP2\n");
1308         else if (nonfaterr.pcie_error)
1309                 IFPGA_RAWDEV_PMD_INFO("an error has occurred in pcie\n");
1310         else if (nonfaterr.portfatal_error)
1311                 IFPGA_RAWDEV_PMD_INFO("fatal error occurred in AFU port.\n");
1312         else if (nonfaterr.proc_hot)
1313                 IFPGA_RAWDEV_PMD_INFO("a ProcHot event\n");
1314         else if (nonfaterr.afu_acc_mode_err)
1315                 IFPGA_RAWDEV_PMD_INFO("an AFU PF/VF access mismatch\n");
1316         else if (nonfaterr.injected_nonfata_err) {
1317                 IFPGA_RAWDEV_PMD_INFO("Injected Warning Error\n");
1318                 fme_clear_warning_intr(mgr);
1319         } else if (nonfaterr.temp_thresh_AP6)
1320                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP6\n");
1321         else if (nonfaterr.power_thresh_AP1)
1322                 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP1\n");
1323         else if (nonfaterr.power_thresh_AP2)
1324                 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP2\n");
1325         else if (nonfaterr.mbp_err)
1326                 IFPGA_RAWDEV_PMD_INFO("an MBP event\n");
1327
1328         return 0;
1329 }
1330
1331 static void
1332 fme_interrupt_handler(void *param)
1333 {
1334         struct opae_manager *mgr = (struct opae_manager *)param;
1335
1336         IFPGA_RAWDEV_PMD_INFO("%s interrupt occurred\n", __func__);
1337
1338         fme_err_handle_error0(mgr);
1339         fme_err_handle_nonfaterror(mgr);
1340         fme_err_handle_catfatal_error(mgr);
1341 }
1342
1343 int
1344 ifpga_unregister_msix_irq(enum ifpga_irq_type type,
1345                 int vec_start, rte_intr_callback_fn handler, void *arg)
1346 {
1347         struct rte_intr_handle *intr_handle;
1348         int rc, i;
1349
1350         if (type == IFPGA_FME_IRQ)
1351                 intr_handle = ifpga_irq_handle[0];
1352         else if (type == IFPGA_AFU_IRQ)
1353                 intr_handle = ifpga_irq_handle[vec_start + 1];
1354         else
1355                 return 0;
1356
1357         rte_intr_efd_disable(intr_handle);
1358
1359         rc = rte_intr_callback_unregister(intr_handle, handler, arg);
1360
1361         for (i = 0; i < IFPGA_MAX_IRQ; i++)
1362                 rte_intr_instance_free(ifpga_irq_handle[i]);
1363         return rc;
1364 }
1365
1366 int
1367 ifpga_register_msix_irq(struct rte_rawdev *dev, int port_id,
1368                 enum ifpga_irq_type type, int vec_start, int count,
1369                 rte_intr_callback_fn handler, const char *name,
1370                 void *arg)
1371 {
1372         int ret;
1373         struct rte_intr_handle *intr_handle;
1374         struct opae_adapter *adapter;
1375         struct opae_manager *mgr;
1376         struct opae_accelerator *acc;
1377         int *intr_efds = NULL, nb_intr, i;
1378
1379         for (i = 0; i < IFPGA_MAX_IRQ; i++) {
1380                 ifpga_irq_handle[i] =
1381                         rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_PRIVATE);
1382                 if (ifpga_irq_handle[i] == NULL)
1383                         return -ENOMEM;
1384         }
1385
1386         adapter = ifpga_rawdev_get_priv(dev);
1387         if (!adapter)
1388                 return -ENODEV;
1389
1390         mgr = opae_adapter_get_mgr(adapter);
1391         if (!mgr)
1392                 return -ENODEV;
1393
1394         if (type == IFPGA_FME_IRQ) {
1395                 intr_handle = ifpga_irq_handle[0];
1396                 count = 1;
1397         } else if (type == IFPGA_AFU_IRQ) {
1398                 intr_handle = ifpga_irq_handle[vec_start + 1];
1399         } else {
1400                 return -EINVAL;
1401         }
1402
1403         if (rte_intr_type_set(intr_handle, RTE_INTR_HANDLE_VFIO_MSIX))
1404                 return -rte_errno;
1405
1406         ret = rte_intr_efd_enable(intr_handle, count);
1407         if (ret)
1408                 return -ENODEV;
1409
1410         if (rte_intr_fd_set(intr_handle,
1411                         rte_intr_efds_index_get(intr_handle, 0)))
1412                 return -rte_errno;
1413
1414         IFPGA_RAWDEV_PMD_DEBUG("register %s irq, vfio_fd=%d, fd=%d\n",
1415                         name, rte_intr_dev_fd_get(intr_handle),
1416                         rte_intr_fd_get(intr_handle));
1417
1418         if (type == IFPGA_FME_IRQ) {
1419                 struct fpga_fme_err_irq_set err_irq_set;
1420                 err_irq_set.evtfd = rte_intr_efds_index_get(intr_handle,
1421                                                                    0);
1422
1423                 ret = opae_manager_ifpga_set_err_irq(mgr, &err_irq_set);
1424                 if (ret)
1425                         return -EINVAL;
1426         } else if (type == IFPGA_AFU_IRQ) {
1427                 acc = opae_adapter_get_acc(adapter, port_id);
1428                 if (!acc)
1429                         return -EINVAL;
1430
1431                 nb_intr = rte_intr_nb_intr_get(intr_handle);
1432
1433                 intr_efds = calloc(nb_intr, sizeof(int));
1434                 if (!intr_efds)
1435                         return -ENOMEM;
1436
1437                 for (i = 0; i < nb_intr; i++)
1438                         intr_efds[i] = rte_intr_efds_index_get(intr_handle, i);
1439
1440                 ret = opae_acc_set_irq(acc, vec_start, count, intr_efds);
1441                 if (ret) {
1442                         free(intr_efds);
1443                         return -EINVAL;
1444                 }
1445         }
1446
1447         /* register interrupt handler using DPDK API */
1448         ret = rte_intr_callback_register(intr_handle,
1449                         handler, (void *)arg);
1450         if (ret) {
1451                 free(intr_efds);
1452                 return -EINVAL;
1453         }
1454
1455         IFPGA_RAWDEV_PMD_INFO("success register %s interrupt\n", name);
1456
1457         free(intr_efds);
1458         return 0;
1459 }
1460
1461 static int
1462 ifpga_rawdev_create(struct rte_pci_device *pci_dev,
1463                         int socket_id)
1464 {
1465         int ret = 0;
1466         struct rte_rawdev *rawdev = NULL;
1467         struct ifpga_rawdev *dev = NULL;
1468         struct opae_adapter *adapter = NULL;
1469         struct opae_manager *mgr = NULL;
1470         struct opae_adapter_data_pci *data = NULL;
1471         char name[RTE_RAWDEV_NAME_MAX_LEN];
1472         int i;
1473
1474         if (!pci_dev) {
1475                 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1476                 ret = -EINVAL;
1477                 goto cleanup;
1478         }
1479
1480         memset(name, 0, sizeof(name));
1481         snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, IFPGA_RAWDEV_NAME_FMT,
1482                 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1483
1484         IFPGA_RAWDEV_PMD_INFO("Init %s on NUMA node %d", name, rte_socket_id());
1485
1486         /* Allocate device structure */
1487         rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct opae_adapter),
1488                                          socket_id);
1489         if (rawdev == NULL) {
1490                 IFPGA_RAWDEV_PMD_ERR("Unable to allocate rawdevice");
1491                 ret = -EINVAL;
1492                 goto cleanup;
1493         }
1494
1495         ipn3ke_bridge_func.get_ifpga_rawdev = ifpga_rawdev_get;
1496         ipn3ke_bridge_func.set_i40e_sw_dev = rte_pmd_i40e_set_switch_dev;
1497
1498         dev = ifpga_rawdev_allocate(rawdev);
1499         if (dev == NULL) {
1500                 IFPGA_RAWDEV_PMD_ERR("Unable to allocate ifpga_rawdevice");
1501                 ret = -EINVAL;
1502                 goto cleanup;
1503         }
1504         dev->aer_enable = 0;
1505
1506         /* alloc OPAE_FPGA_PCI data to register to OPAE hardware level API */
1507         data = opae_adapter_data_alloc(OPAE_FPGA_PCI);
1508         if (!data) {
1509                 ret = -ENOMEM;
1510                 goto cleanup;
1511         }
1512
1513         /* init opae_adapter_data_pci for device specific information */
1514         for (i = 0; i < PCI_MAX_RESOURCE; i++) {
1515                 data->region[i].phys_addr = pci_dev->mem_resource[i].phys_addr;
1516                 data->region[i].len = pci_dev->mem_resource[i].len;
1517                 data->region[i].addr = pci_dev->mem_resource[i].addr;
1518         }
1519         data->device_id = pci_dev->id.device_id;
1520         data->vendor_id = pci_dev->id.vendor_id;
1521         data->bus = pci_dev->addr.bus;
1522         data->devid = pci_dev->addr.devid;
1523         data->function = pci_dev->addr.function;
1524         data->vfio_dev_fd = rte_intr_dev_fd_get(pci_dev->intr_handle);
1525
1526         adapter = rawdev->dev_private;
1527         /* create a opae_adapter based on above device data */
1528         ret = opae_adapter_init(adapter, pci_dev->device.name, data);
1529         if (ret) {
1530                 ret = -ENOMEM;
1531                 goto free_adapter_data;
1532         }
1533
1534         rawdev->dev_ops = &ifpga_rawdev_ops;
1535         rawdev->device = &pci_dev->device;
1536         rawdev->driver_name = pci_dev->driver->driver.name;
1537
1538         /* must enumerate the adapter before use it */
1539         ret = opae_adapter_enumerate(adapter);
1540         if (ret)
1541                 goto free_adapter_data;
1542
1543         /* get opae_manager to rawdev */
1544         mgr = opae_adapter_get_mgr(adapter);
1545         if (mgr) {
1546                 /* PF function */
1547                 IFPGA_RAWDEV_PMD_INFO("this is a PF function");
1548         }
1549
1550         ret = ifpga_register_msix_irq(rawdev, 0, IFPGA_FME_IRQ, 0, 0,
1551                         fme_interrupt_handler, "fme_irq", mgr);
1552         if (ret)
1553                 goto free_adapter_data;
1554
1555         return ret;
1556
1557 free_adapter_data:
1558         if (data)
1559                 opae_adapter_data_free(data);
1560 cleanup:
1561         if (rawdev)
1562                 rte_rawdev_pmd_release(rawdev);
1563
1564         return ret;
1565 }
1566
1567 static int
1568 ifpga_rawdev_destroy(struct rte_pci_device *pci_dev)
1569 {
1570         int ret;
1571         struct rte_rawdev *rawdev;
1572         char name[RTE_RAWDEV_NAME_MAX_LEN];
1573         struct opae_adapter *adapter;
1574         struct opae_manager *mgr;
1575         struct ifpga_rawdev *dev;
1576
1577         if (!pci_dev) {
1578                 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1579                 ret = -EINVAL;
1580                 return ret;
1581         }
1582
1583         memset(name, 0, sizeof(name));
1584         snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, IFPGA_RAWDEV_NAME_FMT,
1585                 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1586
1587         IFPGA_RAWDEV_PMD_INFO("Closing %s on NUMA node %d",
1588                 name, rte_socket_id());
1589
1590         rawdev = rte_rawdev_pmd_get_named_dev(name);
1591         if (!rawdev) {
1592                 IFPGA_RAWDEV_PMD_ERR("Invalid device name (%s)", name);
1593                 return -EINVAL;
1594         }
1595         dev = ifpga_rawdev_get(rawdev);
1596         if (dev)
1597                 dev->rawdev = NULL;
1598
1599         adapter = ifpga_rawdev_get_priv(rawdev);
1600         if (!adapter)
1601                 return -ENODEV;
1602
1603         mgr = opae_adapter_get_mgr(adapter);
1604         if (!mgr)
1605                 return -ENODEV;
1606
1607         if (ifpga_unregister_msix_irq(IFPGA_FME_IRQ, 0,
1608                                 fme_interrupt_handler, mgr) < 0)
1609                 return -EINVAL;
1610
1611         /* rte_rawdev_close is called by pmd_release */
1612         ret = rte_rawdev_pmd_release(rawdev);
1613         if (ret)
1614                 IFPGA_RAWDEV_PMD_DEBUG("Device cleanup failed");
1615
1616         return ret;
1617 }
1618
1619 static int
1620 ifpga_rawdev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1621         struct rte_pci_device *pci_dev)
1622 {
1623         IFPGA_RAWDEV_PMD_FUNC_TRACE();
1624         return ifpga_rawdev_create(pci_dev, rte_socket_id());
1625 }
1626
1627 static int
1628 ifpga_rawdev_pci_remove(struct rte_pci_device *pci_dev)
1629 {
1630         ifpga_monitor_stop_func();
1631         return ifpga_rawdev_destroy(pci_dev);
1632 }
1633
1634 static struct rte_pci_driver rte_ifpga_rawdev_pmd = {
1635         .id_table  = pci_ifpga_map,
1636         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1637         .probe     = ifpga_rawdev_pci_probe,
1638         .remove    = ifpga_rawdev_pci_remove,
1639 };
1640
1641 RTE_PMD_REGISTER_PCI(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1642 RTE_PMD_REGISTER_PCI_TABLE(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1643 RTE_PMD_REGISTER_KMOD_DEP(ifpga_rawdev_pci_driver, "* igb_uio | uio_pci_generic | vfio-pci");
1644 RTE_LOG_REGISTER_DEFAULT(ifpga_rawdev_logtype, NOTICE);
1645
1646 static const char * const valid_args[] = {
1647 #define IFPGA_ARG_NAME         "ifpga"
1648         IFPGA_ARG_NAME,
1649 #define IFPGA_ARG_PORT         "port"
1650         IFPGA_ARG_PORT,
1651 #define IFPGA_AFU_BTS          "afu_bts"
1652         IFPGA_AFU_BTS,
1653         NULL
1654 };
1655
1656 static int ifpga_rawdev_get_string_arg(const char *key __rte_unused,
1657         const char *value, void *extra_args)
1658 {
1659         int size;
1660         if (!value || !extra_args)
1661                 return -EINVAL;
1662
1663         size = strlen(value) + 1;
1664         *(char **)extra_args = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
1665         if (!*(char **)extra_args)
1666                 return -ENOMEM;
1667
1668         strlcpy(*(char **)extra_args, value, size);
1669
1670         return 0;
1671 }
1672 static int
1673 ifpga_cfg_probe(struct rte_vdev_device *dev)
1674 {
1675         struct rte_devargs *devargs;
1676         struct rte_kvargs *kvlist = NULL;
1677         struct rte_rawdev *rawdev = NULL;
1678         struct ifpga_rawdev *ifpga_dev;
1679         int port;
1680         char *name = NULL;
1681         const char *bdf;
1682         char dev_name[RTE_RAWDEV_NAME_MAX_LEN];
1683         int ret = -1;
1684
1685         devargs = dev->device.devargs;
1686
1687         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1688         if (!kvlist) {
1689                 IFPGA_RAWDEV_PMD_LOG(ERR, "error when parsing param");
1690                 goto end;
1691         }
1692
1693         if (rte_kvargs_count(kvlist, IFPGA_ARG_NAME) == 1) {
1694                 if (rte_kvargs_process(kvlist, IFPGA_ARG_NAME,
1695                                        &ifpga_rawdev_get_string_arg,
1696                                        &name) < 0) {
1697                         IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1698                                      IFPGA_ARG_NAME);
1699                         goto end;
1700                 }
1701         } else {
1702                 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1703                           IFPGA_ARG_NAME);
1704                 goto end;
1705         }
1706
1707         if (rte_kvargs_count(kvlist, IFPGA_ARG_PORT) == 1) {
1708                 if (rte_kvargs_process(kvlist,
1709                         IFPGA_ARG_PORT,
1710                         &rte_ifpga_get_integer32_arg,
1711                         &port) < 0) {
1712                         IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1713                                 IFPGA_ARG_PORT);
1714                         goto end;
1715                 }
1716         } else {
1717                 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1718                           IFPGA_ARG_PORT);
1719                 goto end;
1720         }
1721
1722         memset(dev_name, 0, sizeof(dev_name));
1723         snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%s", name);
1724         rawdev = rte_rawdev_pmd_get_named_dev(dev_name);
1725         if (!rawdev)
1726                 goto end;
1727         ifpga_dev = ifpga_rawdev_get(rawdev);
1728         if (!ifpga_dev)
1729                 goto end;
1730         bdf = name;
1731         ifpga_rawdev_fill_info(ifpga_dev, bdf);
1732
1733         ifpga_monitor_start_func();
1734
1735         memset(dev_name, 0, sizeof(dev_name));
1736         snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "%d|%s",
1737         port, name);
1738
1739         ret = rte_eal_hotplug_add(RTE_STR(IFPGA_BUS_NAME),
1740                         dev_name, devargs->args);
1741 end:
1742         if (kvlist)
1743                 rte_kvargs_free(kvlist);
1744         if (name)
1745                 free(name);
1746
1747         return ret;
1748 }
1749
1750 static int
1751 ifpga_cfg_remove(struct rte_vdev_device *vdev)
1752 {
1753         IFPGA_RAWDEV_PMD_INFO("Remove ifpga_cfg %p",
1754                 vdev);
1755
1756         return 0;
1757 }
1758
1759 static struct rte_vdev_driver ifpga_cfg_driver = {
1760         .probe = ifpga_cfg_probe,
1761         .remove = ifpga_cfg_remove,
1762 };
1763
1764 RTE_PMD_REGISTER_VDEV(ifpga_rawdev_cfg, ifpga_cfg_driver);
1765 RTE_PMD_REGISTER_ALIAS(ifpga_rawdev_cfg, ifpga_cfg);
1766 RTE_PMD_REGISTER_PARAM_STRING(ifpga_rawdev_cfg,
1767         "ifpga=<string> "
1768         "port=<int> "
1769         "afu_bts=<path>");
1770
1771 struct rte_pci_bus *ifpga_get_pci_bus(void)
1772 {
1773         return rte_ifpga_rawdev_pmd.bus;
1774 }
1775
1776 int ifpga_rawdev_partial_reconfigure(struct rte_rawdev *dev, int port,
1777         const char *file)
1778 {
1779         if (!dev) {
1780                 IFPGA_RAWDEV_PMD_ERR("Input parameter is invalid");
1781                 return -EINVAL;
1782         }
1783
1784         return rte_fpga_do_pr(dev, port, file);
1785 }
1786
1787 void ifpga_rawdev_cleanup(void)
1788 {
1789         struct ifpga_rawdev *dev;
1790         unsigned int i;
1791
1792         for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
1793                 dev = &ifpga_rawdevices[i];
1794                 if (dev->rawdev) {
1795                         rte_rawdev_pmd_release(dev->rawdev);
1796                         dev->rawdev = NULL;
1797                 }
1798         }
1799 }