struct acc100_device *d = dev->data->dev_private;
/* Only MSI are currently supported */
- if (dev->intr_handle->type == RTE_INTR_HANDLE_VFIO_MSI ||
- dev->intr_handle->type == RTE_INTR_HANDLE_UIO) {
+ if (rte_intr_type_get(dev->intr_handle) == RTE_INTR_HANDLE_VFIO_MSI ||
+ rte_intr_type_get(dev->intr_handle) == RTE_INTR_HANDLE_UIO) {
ret = allocate_info_ring(dev);
if (ret < 0) {
{
struct acc100_queue *q = dev->data->queues[queue_id].queue_private;
- if (dev->intr_handle->type != RTE_INTR_HANDLE_VFIO_MSI &&
- dev->intr_handle->type != RTE_INTR_HANDLE_UIO)
+ if (rte_intr_type_get(dev->intr_handle) != RTE_INTR_HANDLE_VFIO_MSI &&
+ rte_intr_type_get(dev->intr_handle) != RTE_INTR_HANDLE_UIO)
return -ENOTSUP;
q->irq_enable = 1;
{
struct acc100_queue *q = dev->data->queues[queue_id].queue_private;
- if (dev->intr_handle->type != RTE_INTR_HANDLE_VFIO_MSI &&
- dev->intr_handle->type != RTE_INTR_HANDLE_UIO)
+ if (rte_intr_type_get(dev->intr_handle) != RTE_INTR_HANDLE_VFIO_MSI &&
+ rte_intr_type_get(dev->intr_handle) != RTE_INTR_HANDLE_UIO)
return -ENOTSUP;
q->irq_enable = 0;
/* Fill HW specific part of device structure */
bbdev->device = &pci_dev->device;
- bbdev->intr_handle = &pci_dev->intr_handle;
+ bbdev->intr_handle = pci_dev->intr_handle;
bbdev->data->socket_id = pci_dev->device.numa_node;
/* Invoke ACC100 device initialization function */
* It ensures that callback function assigned to that descriptor will
* invoked when any FPGA queue issues interrupt.
*/
- for (i = 0; i < FPGA_NUM_INTR_VEC; ++i)
- dev->intr_handle->efds[i] = dev->intr_handle->fd;
-
- if (!dev->intr_handle->intr_vec) {
- dev->intr_handle->intr_vec = rte_zmalloc("intr_vec",
- dev->data->num_queues * sizeof(int), 0);
- if (!dev->intr_handle->intr_vec) {
- rte_bbdev_log(ERR, "Failed to allocate %u vectors",
- dev->data->num_queues);
- return -ENOMEM;
- }
+ for (i = 0; i < FPGA_NUM_INTR_VEC; ++i) {
+ if (rte_intr_efds_index_set(dev->intr_handle, i,
+ rte_intr_fd_get(dev->intr_handle)))
+ return -rte_errno;
+ }
+
+ if (rte_intr_vec_list_alloc(dev->intr_handle, "intr_vec",
+ dev->data->num_queues)) {
+ rte_bbdev_log(ERR, "Failed to allocate %u vectors",
+ dev->data->num_queues);
+ return -ENOMEM;
}
ret = rte_intr_enable(dev->intr_handle);
/* Fill HW specific part of device structure */
bbdev->device = &pci_dev->device;
- bbdev->intr_handle = &pci_dev->intr_handle;
+ bbdev->intr_handle = pci_dev->intr_handle;
bbdev->data->socket_id = pci_dev->device.numa_node;
/* Invoke FEC FPGA device initialization function */
* It ensures that callback function assigned to that descriptor will
* invoked when any FPGA queue issues interrupt.
*/
- for (i = 0; i < FPGA_NUM_INTR_VEC; ++i)
- dev->intr_handle->efds[i] = dev->intr_handle->fd;
-
- if (!dev->intr_handle->intr_vec) {
- dev->intr_handle->intr_vec = rte_zmalloc("intr_vec",
- dev->data->num_queues * sizeof(int), 0);
- if (!dev->intr_handle->intr_vec) {
- rte_bbdev_log(ERR, "Failed to allocate %u vectors",
- dev->data->num_queues);
- return -ENOMEM;
- }
+ for (i = 0; i < FPGA_NUM_INTR_VEC; ++i) {
+ if (rte_intr_efds_index_set(dev->intr_handle, i,
+ rte_intr_fd_get(dev->intr_handle)))
+ return -rte_errno;
+ }
+
+ if (rte_intr_vec_list_alloc(dev->intr_handle, "intr_vec",
+ dev->data->num_queues)) {
+ rte_bbdev_log(ERR, "Failed to allocate %u vectors",
+ dev->data->num_queues);
+ return -ENOMEM;
}
ret = rte_intr_enable(dev->intr_handle);
/* Fill HW specific part of device structure */
bbdev->device = &pci_dev->device;
- bbdev->intr_handle = &pci_dev->intr_handle;
+ bbdev->intr_handle = pci_dev->intr_handle;
bbdev->data->socket_id = pci_dev->device.numa_node;
/* Invoke FEC FPGA device initialization function */
return -EINVAL;
}
+ /* Allocate interrupt instance */
+ dev->intr_handle =
+ rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_PRIVATE);
+ if (dev->intr_handle == NULL) {
+ AUXILIARY_LOG(ERR, "Could not allocate interrupt instance for device %s",
+ dev->name);
+ return -ENOMEM;
+ }
+
dev->driver = drv;
AUXILIARY_LOG(INFO, "Probe auxiliary driver: %s device: %s (NUMA node %i)",
drv->driver.name, dev->name, dev->device.numa_node);
ret = drv->probe(drv, dev);
- if (ret != 0)
+ if (ret != 0) {
dev->driver = NULL;
- else
+ rte_intr_instance_free(dev->intr_handle);
+ dev->intr_handle = NULL;
+ } else {
dev->device.driver = &drv->driver;
+ }
return ret;
}
if (ret == 0) {
rte_auxiliary_remove_device(adev);
rte_devargs_remove(dev->devargs);
+ rte_intr_instance_free(adev->intr_handle);
free(adev);
}
return ret;
RTE_TAILQ_ENTRY(rte_auxiliary_device) next; /**< Next probed device. */
struct rte_device device; /**< Inherit core device */
char name[RTE_DEV_NAME_MAX_LEN + 1]; /**< ASCII device name */
- struct rte_intr_handle intr_handle; /**< Interrupt handle */
+ struct rte_intr_handle *intr_handle; /**< Interrupt handle */
struct rte_auxiliary_driver *driver; /**< Device driver */
};
dev->device.bus = &rte_dpaa_bus.bus;
+ /* Allocate interrupt handle instance */
+ dev->intr_handle =
+ rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_PRIVATE);
+ if (dev->intr_handle == NULL) {
+ DPAA_BUS_LOG(ERR, "Failed to allocate intr handle");
+ ret = -ENOMEM;
+ goto cleanup;
+ }
+
cfg = &dpaa_netcfg->port_cfg[i];
fman_intf = cfg->fman_if;
goto cleanup;
}
+ /* Allocate interrupt handle instance */
+ dev->intr_handle =
+ rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_PRIVATE);
+ if (dev->intr_handle == NULL) {
+ DPAA_BUS_LOG(ERR, "Failed to allocate intr handle");
+ ret = -ENOMEM;
+ goto cleanup;
+ }
+
dev->device_type = FSL_DPAA_CRYPTO;
dev->id.dev_id = rte_dpaa_bus.device_count + i;
RTE_TAILQ_FOREACH_SAFE(dev, &rte_dpaa_bus.device_list, next, tdev) {
TAILQ_REMOVE(&rte_dpaa_bus.device_list, dev, next);
+ rte_intr_instance_free(dev->intr_handle);
free(dev);
dev = NULL;
}
return errno;
}
- intr_handle->fd = fd;
- intr_handle->type = RTE_INTR_HANDLE_EXT;
+ if (rte_intr_fd_set(intr_handle, fd))
+ return rte_errno;
+
+ if (rte_intr_type_set(intr_handle, RTE_INTR_HANDLE_EXT))
+ return rte_errno;
return 0;
}
TAILQ_FOREACH(dev, &rte_dpaa_bus.device_list, next) {
if (dev->device_type == FSL_DPAA_ETH) {
- ret = rte_dpaa_setup_intr(&dev->intr_handle);
+ ret = rte_dpaa_setup_intr(dev->intr_handle);
if (ret)
DPAA_BUS_ERR("Error setting up interrupt.\n");
}
};
struct rte_dpaa_driver *driver;
struct dpaa_device_id id;
- struct rte_intr_handle intr_handle;
+ struct rte_intr_handle *intr_handle;
enum rte_dpaa_type device_type; /**< Ethernet or crypto type device */
char name[RTE_ETH_NAME_MAX_LEN];
};
RTE_TAILQ_FOREACH_SAFE(dev, &rte_fslmc_bus.device_list, next, t_dev) {
TAILQ_REMOVE(&rte_fslmc_bus.device_list, dev, next);
+ rte_intr_instance_free(dev->intr_handle);
free(dev);
dev = NULL;
}
dev->device.bus = &rte_fslmc_bus.bus;
+ /* Allocate interrupt instance */
+ dev->intr_handle =
+ rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_PRIVATE);
+ if (dev->intr_handle == NULL) {
+ DPAA2_BUS_ERR("Failed to allocate intr handle");
+ ret = -ENOMEM;
+ goto cleanup;
+ }
+
/* Parse the device name and ID */
t_ptr = strtok(dup_dev_name, ".");
if (!t_ptr) {
cleanup:
if (dup_dev_name)
free(dup_dev_name);
- if (dev)
+ if (dev) {
+ rte_intr_instance_free(dev->intr_handle);
free(dev);
+ }
return ret;
}
int len, ret;
char irq_set_buf[IRQ_SET_BUF_LEN];
struct vfio_irq_set *irq_set;
- int *fd_ptr;
+ int *fd_ptr, vfio_dev_fd;
len = sizeof(irq_set_buf);
irq_set->index = index;
irq_set->start = 0;
fd_ptr = (int *)&irq_set->data;
- *fd_ptr = intr_handle->fd;
+ *fd_ptr = rte_intr_fd_get(intr_handle);
- ret = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);
+ vfio_dev_fd = rte_intr_dev_fd_get(intr_handle);
+ ret = ioctl(vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);
if (ret) {
DPAA2_BUS_ERR("Error:dpaa2 SET IRQs fd=%d, err = %d(%s)",
- intr_handle->fd, errno, strerror(errno));
+ rte_intr_fd_get(intr_handle), errno,
+ strerror(errno));
return ret;
}
{
struct vfio_irq_set *irq_set;
char irq_set_buf[IRQ_SET_BUF_LEN];
- int len, ret;
+ int len, ret, vfio_dev_fd;
len = sizeof(struct vfio_irq_set);
irq_set->start = 0;
irq_set->count = 0;
- ret = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);
+ vfio_dev_fd = rte_intr_dev_fd_get(intr_handle);
+ ret = ioctl(vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);
if (ret)
DPAA2_BUS_ERR(
"Error disabling dpaa2 interrupts for fd %d",
- intr_handle->fd);
+ rte_intr_fd_get(intr_handle));
return ret;
}
return -1;
}
- intr_handle->fd = fd;
- intr_handle->type = RTE_INTR_HANDLE_VFIO_MSI;
- intr_handle->vfio_dev_fd = vfio_dev_fd;
+ if (rte_intr_fd_set(intr_handle, fd))
+ return -rte_errno;
+
+ if (rte_intr_type_set(intr_handle, RTE_INTR_HANDLE_VFIO_MSI))
+ return -rte_errno;
+
+ if (rte_intr_dev_fd_set(intr_handle, vfio_dev_fd))
+ return -rte_errno;
return 0;
}
switch (dev->dev_type) {
case DPAA2_ETH:
- rte_dpaa2_vfio_setup_intr(&dev->intr_handle, dev_fd,
+ rte_dpaa2_vfio_setup_intr(dev->intr_handle, dev_fd,
device_info.num_irqs);
break;
case DPAA2_CON:
int threshold = 0x3, timeout = 0xFF;
dpio_epoll_fd = epoll_create(1);
- ret = rte_dpaa2_intr_enable(&dpio_dev->intr_handle, 0);
+ ret = rte_dpaa2_intr_enable(dpio_dev->intr_handle, 0);
if (ret) {
DPAA2_BUS_ERR("Interrupt registeration failed");
return -1;
qbman_swp_dqrr_thrshld_write(dpio_dev->sw_portal, threshold);
qbman_swp_intr_timeout_write(dpio_dev->sw_portal, timeout);
- eventfd = dpio_dev->intr_handle.fd;
+ eventfd = rte_intr_fd_get(dpio_dev->intr_handle);
epoll_ev.events = EPOLLIN | EPOLLPRI | EPOLLET;
epoll_ev.data.fd = eventfd;
{
int ret;
- ret = rte_dpaa2_intr_disable(&dpio_dev->intr_handle, 0);
+ ret = rte_dpaa2_intr_disable(dpio_dev->intr_handle, 0);
if (ret)
DPAA2_BUS_ERR("DPIO interrupt disable failed");
/* Using single portal for all devices */
dpio_dev->mc_portal = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
+ /* Allocate interrupt instance */
+ dpio_dev->intr_handle =
+ rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED);
+ if (!dpio_dev->intr_handle) {
+ DPAA2_BUS_ERR("Failed to allocate intr handle");
+ goto err;
+ }
+
dpio_dev->dpio = rte_zmalloc(NULL, sizeof(struct fsl_mc_io),
RTE_CACHE_LINE_SIZE);
if (!dpio_dev->dpio) {
io_space_count++;
dpio_dev->index = io_space_count;
- if (rte_dpaa2_vfio_setup_intr(&dpio_dev->intr_handle, vdev_fd, 1)) {
+ if (rte_dpaa2_vfio_setup_intr(dpio_dev->intr_handle, vdev_fd, 1)) {
DPAA2_BUS_ERR("Fail to setup interrupt for %d",
dpio_dev->hw_id);
goto err;
rte_free(dpio_dev->dpio);
}
+ rte_intr_instance_free(dpio_dev->intr_handle);
rte_free(dpio_dev);
/* For each element in the list, cleanup */
dpio_dev->token);
rte_free(dpio_dev->dpio);
}
+ rte_intr_instance_free(dpio_dev->intr_handle);
rte_free(dpio_dev);
}
uintptr_t qbman_portal_ci_paddr;
/**< Physical address of Cache Inhibit Area */
uintptr_t ci_size; /**< Size of the CI region */
- struct rte_intr_handle intr_handle; /* Interrupt related info */
+ struct rte_intr_handle *intr_handle; /* Interrupt related info */
int32_t epoll_fd; /**< File descriptor created for interrupt polling */
int32_t hw_id; /**< An unique ID of this DPIO device instance */
struct dpaa2_portal_dqrr dpaa2_held_bufs;
};
enum rte_dpaa2_dev_type dev_type; /**< Device Type */
uint16_t object_id; /**< DPAA2 Object ID */
- struct rte_intr_handle intr_handle; /**< Interrupt handle */
+ struct rte_intr_handle *intr_handle; /**< Interrupt handle */
struct rte_dpaa2_driver *driver; /**< Associated driver */
char name[FSLMC_OBJECT_MAX_LEN]; /**< DPAA2 Object name*/
};
afu_dev->id.uuid.uuid_high = 0;
afu_dev->id.port = afu_pr_conf.afu_id.port;
+ /* Allocate interrupt instance */
+ afu_dev->intr_handle =
+ rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_PRIVATE);
+ if (afu_dev->intr_handle == NULL) {
+ IFPGA_BUS_ERR("Failed to allocate intr handle");
+ goto end;
+ }
+
if (rawdev->dev_ops && rawdev->dev_ops->dev_info_get)
rawdev->dev_ops->dev_info_get(rawdev, afu_dev, sizeof(*afu_dev));
rte_kvargs_free(kvlist);
if (path)
free(path);
- if (afu_dev)
+ if (afu_dev) {
+ rte_intr_instance_free(afu_dev->intr_handle);
free(afu_dev);
+ }
return NULL;
}
TAILQ_REMOVE(&ifpga_afu_dev_list, afu_dev, next);
rte_devargs_remove(dev->devargs);
+ rte_intr_instance_free(afu_dev->intr_handle);
free(afu_dev);
return 0;
struct rte_mem_resource mem_resource[PCI_MAX_RESOURCE];
/**< AFU Memory Resource */
struct rte_afu_shared shared;
- struct rte_intr_handle intr_handle; /**< Interrupt handle */
+ struct rte_intr_handle *intr_handle; /**< Interrupt handle */
struct rte_afu_driver *driver; /**< Associated driver */
char path[IFPGA_BUS_BITSTREAM_PATH_MAX_LEN];
} __rte_packed;
{
rte_free(uio_res);
- if (dev->intr_handle.fd) {
- close(dev->intr_handle.fd);
- dev->intr_handle.fd = -1;
- dev->intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;
+ if (rte_intr_fd_get(dev->intr_handle)) {
+ close(rte_intr_fd_get(dev->intr_handle));
+ rte_intr_fd_set(dev->intr_handle, -1);
+ rte_intr_type_set(dev->intr_handle, RTE_INTR_HANDLE_UNKNOWN);
}
}
}
/* save fd if in primary process */
- dev->intr_handle.fd = open(devname, O_RDWR);
- if (dev->intr_handle.fd < 0) {
+ if (rte_intr_fd_set(dev->intr_handle, open(devname, O_RDWR))) {
+ RTE_LOG(WARNING, EAL, "Failed to save fd");
+ goto error;
+ }
+
+ if (rte_intr_fd_get(dev->intr_handle) < 0) {
RTE_LOG(ERR, EAL, "Cannot open %s: %s\n",
devname, strerror(errno));
goto error;
}
- dev->intr_handle.type = RTE_INTR_HANDLE_UIO;
+
+ if (rte_intr_type_set(dev->intr_handle, RTE_INTR_HANDLE_UIO))
+ goto error;
/* allocate the mapping details for secondary processes*/
*uio_res = rte_zmalloc("UIO_RES", sizeof(**uio_res), 0);
void *buf, size_t len, off_t offset)
{
char devname[RTE_DEV_NAME_MAX_LEN] = "";
- const struct rte_intr_handle *intr_handle = &device->intr_handle;
+ const struct rte_intr_handle *intr_handle = device->intr_handle;
switch (device->kdrv) {
case RTE_PCI_KDRV_IGB_UIO:
const void *buf, size_t len, off_t offset)
{
char devname[RTE_DEV_NAME_MAX_LEN] = "";
- const struct rte_intr_handle *intr_handle = &device->intr_handle;
+ const struct rte_intr_handle *intr_handle = device->intr_handle;
switch (device->kdrv) {
case RTE_PCI_KDRV_IGB_UIO:
pci_uio_read_config(const struct rte_intr_handle *intr_handle,
void *buf, size_t len, off_t offset)
{
- return pread(intr_handle->uio_cfg_fd, buf, len, offset);
+ int uio_cfg_fd = rte_intr_dev_fd_get(intr_handle);
+
+ return pread(uio_cfg_fd, buf, len, offset);
}
int
pci_uio_write_config(const struct rte_intr_handle *intr_handle,
const void *buf, size_t len, off_t offset)
{
- return pwrite(intr_handle->uio_cfg_fd, buf, len, offset);
+ int uio_cfg_fd = rte_intr_dev_fd_get(intr_handle);
+
+ return pwrite(uio_cfg_fd, buf, len, offset);
}
static int
pci_uio_free_resource(struct rte_pci_device *dev,
struct mapped_pci_resource *uio_res)
{
+ int uio_cfg_fd = rte_intr_dev_fd_get(dev->intr_handle);
+
rte_free(uio_res);
- if (dev->intr_handle.uio_cfg_fd >= 0) {
- close(dev->intr_handle.uio_cfg_fd);
- dev->intr_handle.uio_cfg_fd = -1;
+ if (uio_cfg_fd >= 0) {
+ close(uio_cfg_fd);
+ rte_intr_dev_fd_set(dev->intr_handle, -1);
}
- if (dev->intr_handle.fd >= 0) {
- close(dev->intr_handle.fd);
- dev->intr_handle.fd = -1;
- dev->intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;
+
+ if (rte_intr_fd_get(dev->intr_handle) >= 0) {
+ close(rte_intr_fd_get(dev->intr_handle));
+ rte_intr_fd_set(dev->intr_handle, -1);
+ rte_intr_type_set(dev->intr_handle, RTE_INTR_HANDLE_UNKNOWN);
}
}
char dirname[PATH_MAX];
char cfgname[PATH_MAX];
char devname[PATH_MAX]; /* contains the /dev/uioX */
- int uio_num;
+ int uio_num, fd, uio_cfg_fd;
struct rte_pci_addr *loc;
loc = &dev->addr;
snprintf(devname, sizeof(devname), "/dev/uio%u", uio_num);
/* save fd if in primary process */
- dev->intr_handle.fd = open(devname, O_RDWR);
- if (dev->intr_handle.fd < 0) {
+ fd = open(devname, O_RDWR);
+ if (fd < 0) {
RTE_LOG(ERR, EAL, "Cannot open %s: %s\n",
devname, strerror(errno));
goto error;
}
+ if (rte_intr_fd_set(dev->intr_handle, fd))
+ goto error;
+
snprintf(cfgname, sizeof(cfgname),
"/sys/class/uio/uio%u/device/config", uio_num);
- dev->intr_handle.uio_cfg_fd = open(cfgname, O_RDWR);
- if (dev->intr_handle.uio_cfg_fd < 0) {
+
+ uio_cfg_fd = open(cfgname, O_RDWR);
+ if (uio_cfg_fd < 0) {
RTE_LOG(ERR, EAL, "Cannot open %s: %s\n",
cfgname, strerror(errno));
goto error;
}
- if (dev->kdrv == RTE_PCI_KDRV_IGB_UIO)
- dev->intr_handle.type = RTE_INTR_HANDLE_UIO;
- else {
- dev->intr_handle.type = RTE_INTR_HANDLE_UIO_INTX;
+ if (rte_intr_dev_fd_set(dev->intr_handle, uio_cfg_fd))
+ goto error;
+
+ if (dev->kdrv == RTE_PCI_KDRV_IGB_UIO) {
+ if (rte_intr_type_set(dev->intr_handle, RTE_INTR_HANDLE_UIO))
+ goto error;
+ } else {
+ if (rte_intr_type_set(dev->intr_handle, RTE_INTR_HANDLE_UIO_INTX))
+ goto error;
/* set bus master that is not done by uio_pci_generic */
- if (pci_uio_set_bus_master(dev->intr_handle.uio_cfg_fd)) {
+ if (pci_uio_set_bus_master(uio_cfg_fd)) {
RTE_LOG(ERR, EAL, "Cannot set up bus mastering!\n");
goto error;
}
char buf[BUFSIZ];
uint64_t phys_addr, end_addr, flags;
unsigned long base;
- int i;
+ int i, fd;
/* open and read addresses of the corresponding resource in sysfs */
snprintf(filename, sizeof(filename), "%s/" PCI_PRI_FMT "/resource",
}
/* FIXME only for primary process ? */
- if (dev->intr_handle.type == RTE_INTR_HANDLE_UNKNOWN) {
+ if (rte_intr_type_get(dev->intr_handle) ==
+ RTE_INTR_HANDLE_UNKNOWN) {
int uio_num = pci_get_uio_dev(dev, dirname, sizeof(dirname), 0);
if (uio_num < 0) {
RTE_LOG(ERR, EAL, "cannot open %s: %s\n",
}
snprintf(filename, sizeof(filename), "/dev/uio%u", uio_num);
- dev->intr_handle.fd = open(filename, O_RDWR);
- if (dev->intr_handle.fd < 0) {
+ fd = open(filename, O_RDWR);
+ if (fd < 0) {
RTE_LOG(ERR, EAL, "Cannot open %s: %s\n",
filename, strerror(errno));
goto error;
}
- dev->intr_handle.type = RTE_INTR_HANDLE_UIO;
+ if (rte_intr_fd_set(dev->intr_handle, fd))
+ goto error;
+
+ if (rte_intr_type_set(dev->intr_handle, RTE_INTR_HANDLE_UIO))
+ goto error;
}
RTE_LOG(DEBUG, EAL, "PCI Port IO found start=0x%lx\n", base);
pci_vfio_read_config(const struct rte_intr_handle *intr_handle,
void *buf, size_t len, off_t offs)
{
- return pread64(intr_handle->vfio_dev_fd, buf, len,
+ int vfio_dev_fd = rte_intr_dev_fd_get(intr_handle);
+
+ return pread64(vfio_dev_fd, buf, len,
VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs);
}
pci_vfio_write_config(const struct rte_intr_handle *intr_handle,
const void *buf, size_t len, off_t offs)
{
- return pwrite64(intr_handle->vfio_dev_fd, buf, len,
+ int vfio_dev_fd = rte_intr_dev_fd_get(intr_handle);
+
+ return pwrite64(vfio_dev_fd, buf, len,
VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs);
}
return -1;
}
- dev->intr_handle.fd = fd;
- dev->intr_handle.vfio_dev_fd = vfio_dev_fd;
+ if (rte_intr_fd_set(dev->intr_handle, fd))
+ return -1;
+
+ if (rte_intr_dev_fd_set(dev->intr_handle, vfio_dev_fd))
+ return -1;
switch (i) {
case VFIO_PCI_MSIX_IRQ_INDEX:
intr_mode = RTE_INTR_MODE_MSIX;
- dev->intr_handle.type = RTE_INTR_HANDLE_VFIO_MSIX;
+ rte_intr_type_set(dev->intr_handle,
+ RTE_INTR_HANDLE_VFIO_MSIX);
break;
case VFIO_PCI_MSI_IRQ_INDEX:
intr_mode = RTE_INTR_MODE_MSI;
- dev->intr_handle.type = RTE_INTR_HANDLE_VFIO_MSI;
+ rte_intr_type_set(dev->intr_handle,
+ RTE_INTR_HANDLE_VFIO_MSI);
break;
case VFIO_PCI_INTX_IRQ_INDEX:
intr_mode = RTE_INTR_MODE_LEGACY;
- dev->intr_handle.type = RTE_INTR_HANDLE_VFIO_LEGACY;
+ rte_intr_type_set(dev->intr_handle,
+ RTE_INTR_HANDLE_VFIO_LEGACY);
break;
default:
RTE_LOG(ERR, EAL, "Unknown interrupt type!\n");
return -1;
}
- dev->vfio_req_intr_handle.fd = fd;
- dev->vfio_req_intr_handle.type = RTE_INTR_HANDLE_VFIO_REQ;
- dev->vfio_req_intr_handle.vfio_dev_fd = vfio_dev_fd;
+ if (rte_intr_fd_set(dev->vfio_req_intr_handle, fd))
+ return -1;
+
+ if (rte_intr_type_set(dev->vfio_req_intr_handle, RTE_INTR_HANDLE_VFIO_REQ))
+ return -1;
+
+ if (rte_intr_dev_fd_set(dev->vfio_req_intr_handle, vfio_dev_fd))
+ return -1;
- ret = rte_intr_callback_register(&dev->vfio_req_intr_handle,
+ ret = rte_intr_callback_register(dev->vfio_req_intr_handle,
pci_vfio_req_handler,
(void *)&dev->device);
if (ret) {
goto error;
}
- ret = rte_intr_enable(&dev->vfio_req_intr_handle);
+ ret = rte_intr_enable(dev->vfio_req_intr_handle);
if (ret) {
RTE_LOG(ERR, EAL, "Fail to enable req notifier.\n");
- ret = rte_intr_callback_unregister(&dev->vfio_req_intr_handle,
+ ret = rte_intr_callback_unregister(dev->vfio_req_intr_handle,
pci_vfio_req_handler,
(void *)&dev->device);
if (ret < 0)
error:
close(fd);
- dev->vfio_req_intr_handle.fd = -1;
- dev->vfio_req_intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;
- dev->vfio_req_intr_handle.vfio_dev_fd = -1;
+ rte_intr_fd_set(dev->vfio_req_intr_handle, -1);
+ rte_intr_type_set(dev->vfio_req_intr_handle, RTE_INTR_HANDLE_UNKNOWN);
+ rte_intr_dev_fd_set(dev->vfio_req_intr_handle, -1);
return -1;
}
{
int ret;
- ret = rte_intr_disable(&dev->vfio_req_intr_handle);
+ ret = rte_intr_disable(dev->vfio_req_intr_handle);
if (ret) {
RTE_LOG(ERR, EAL, "fail to disable req notifier.\n");
return -1;
}
- ret = rte_intr_callback_unregister_sync(&dev->vfio_req_intr_handle,
+ ret = rte_intr_callback_unregister_sync(dev->vfio_req_intr_handle,
pci_vfio_req_handler,
(void *)&dev->device);
if (ret < 0) {
return -1;
}
- close(dev->vfio_req_intr_handle.fd);
+ close(rte_intr_fd_get(dev->vfio_req_intr_handle));
- dev->vfio_req_intr_handle.fd = -1;
- dev->vfio_req_intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;
- dev->vfio_req_intr_handle.vfio_dev_fd = -1;
+ rte_intr_fd_set(dev->vfio_req_intr_handle, -1);
+ rte_intr_type_set(dev->vfio_req_intr_handle, RTE_INTR_HANDLE_UNKNOWN);
+ rte_intr_dev_fd_set(dev->vfio_req_intr_handle, -1);
return 0;
}
struct pci_map *maps;
- dev->intr_handle.fd = -1;
+ if (rte_intr_fd_set(dev->intr_handle, -1))
+ return -1;
+
#ifdef HAVE_VFIO_DEV_REQ_INTERFACE
- dev->vfio_req_intr_handle.fd = -1;
+ if (rte_intr_fd_set(dev->vfio_req_intr_handle, -1))
+ return -1;
#endif
/* store PCI address string */
struct pci_map *maps;
- dev->intr_handle.fd = -1;
+ if (rte_intr_fd_set(dev->intr_handle, -1))
+ return -1;
#ifdef HAVE_VFIO_DEV_REQ_INTERFACE
- dev->vfio_req_intr_handle.fd = -1;
+ if (rte_intr_fd_set(dev->vfio_req_intr_handle, -1))
+ return -1;
#endif
/* store PCI address string */
}
/* we need save vfio_dev_fd, so it can be used during release */
- dev->intr_handle.vfio_dev_fd = vfio_dev_fd;
+ if (rte_intr_dev_fd_set(dev->intr_handle, vfio_dev_fd))
+ goto err_vfio_dev_fd;
#ifdef HAVE_VFIO_DEV_REQ_INTERFACE
- dev->vfio_req_intr_handle.vfio_dev_fd = vfio_dev_fd;
+ if (rte_intr_dev_fd_set(dev->vfio_req_intr_handle, vfio_dev_fd))
+ goto err_vfio_dev_fd;
#endif
return 0;
struct rte_pci_addr *loc = &dev->addr;
struct mapped_pci_resource *vfio_res = NULL;
struct mapped_pci_res_list *vfio_res_list;
- int ret;
+ int ret, vfio_dev_fd;
/* store PCI address string */
snprintf(pci_addr, sizeof(pci_addr), PCI_PRI_FMT,
}
#endif
- if (close(dev->intr_handle.fd) < 0) {
+ if (close(rte_intr_fd_get(dev->intr_handle)) < 0) {
RTE_LOG(INFO, EAL, "Error when closing eventfd file descriptor for %s\n",
pci_addr);
return -1;
}
- if (pci_vfio_set_bus_master(dev->intr_handle.vfio_dev_fd, false)) {
+ vfio_dev_fd = rte_intr_dev_fd_get(dev->intr_handle);
+ if (pci_vfio_set_bus_master(vfio_dev_fd, false)) {
RTE_LOG(ERR, EAL, "%s cannot unset bus mastering for PCI device!\n",
pci_addr);
return -1;
}
ret = rte_vfio_release_device(rte_pci_get_sysfs_path(), pci_addr,
- dev->intr_handle.vfio_dev_fd);
+ vfio_dev_fd);
if (ret < 0) {
RTE_LOG(ERR, EAL, "Cannot release VFIO device\n");
return ret;
struct rte_pci_addr *loc = &dev->addr;
struct mapped_pci_resource *vfio_res = NULL;
struct mapped_pci_res_list *vfio_res_list;
- int ret;
+ int ret, vfio_dev_fd;
/* store PCI address string */
snprintf(pci_addr, sizeof(pci_addr), PCI_PRI_FMT,
loc->domain, loc->bus, loc->devid, loc->function);
+ vfio_dev_fd = rte_intr_dev_fd_get(dev->intr_handle);
ret = rte_vfio_release_device(rte_pci_get_sysfs_path(), pci_addr,
- dev->intr_handle.vfio_dev_fd);
+ vfio_dev_fd);
if (ret < 0) {
RTE_LOG(ERR, EAL, "Cannot release VFIO device\n");
return ret;
pci_vfio_ioport_read(struct rte_pci_ioport *p,
void *data, size_t len, off_t offset)
{
- const struct rte_intr_handle *intr_handle = &p->dev->intr_handle;
+ const struct rte_intr_handle *intr_handle = p->dev->intr_handle;
+ int vfio_dev_fd = rte_intr_dev_fd_get(intr_handle);
- if (pread64(intr_handle->vfio_dev_fd, data,
+ if (pread64(vfio_dev_fd, data,
len, p->base + offset) <= 0)
RTE_LOG(ERR, EAL,
"Can't read from PCI bar (%" PRIu64 ") : offset (%x)\n",
pci_vfio_ioport_write(struct rte_pci_ioport *p,
const void *data, size_t len, off_t offset)
{
- const struct rte_intr_handle *intr_handle = &p->dev->intr_handle;
+ const struct rte_intr_handle *intr_handle = p->dev->intr_handle;
+ int vfio_dev_fd = rte_intr_dev_fd_get(intr_handle);
- if (pwrite64(intr_handle->vfio_dev_fd, data,
+ if (pwrite64(vfio_dev_fd, data,
len, p->base + offset) <= 0)
RTE_LOG(ERR, EAL,
"Can't write to PCI bar (%" PRIu64 ") : offset (%x)\n",
return -EINVAL;
}
- dev->driver = dr;
- }
+ /* Allocate interrupt instance for pci device */
+ dev->intr_handle =
+ rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_PRIVATE);
+ if (dev->intr_handle == NULL) {
+ RTE_LOG(ERR, EAL,
+ "Failed to create interrupt instance for %s\n",
+ dev->device.name);
+ return -ENOMEM;
+ }
- if (!already_probed && (dr->drv_flags & RTE_PCI_DRV_NEED_MAPPING)) {
- /* map resources for devices that use igb_uio */
- ret = rte_pci_map_device(dev);
- if (ret != 0) {
- dev->driver = NULL;
- return ret;
+ dev->vfio_req_intr_handle =
+ rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_PRIVATE);
+ if (dev->vfio_req_intr_handle == NULL) {
+ rte_intr_instance_free(dev->intr_handle);
+ dev->intr_handle = NULL;
+ RTE_LOG(ERR, EAL,
+ "Failed to create vfio req interrupt instance for %s\n",
+ dev->device.name);
+ return -ENOMEM;
+ }
+
+ if (dr->drv_flags & RTE_PCI_DRV_NEED_MAPPING) {
+ ret = rte_pci_map_device(dev);
+ if (ret != 0) {
+ rte_intr_instance_free(dev->vfio_req_intr_handle);
+ dev->vfio_req_intr_handle = NULL;
+ rte_intr_instance_free(dev->intr_handle);
+ dev->intr_handle = NULL;
+ return ret;
+ }
}
+
+ dev->driver = dr;
}
RTE_LOG(INFO, EAL, "Probe PCI driver: %s (%x:%x) device: "PCI_PRI_FMT" (socket %i)\n",
return ret; /* no rollback if already succeeded earlier */
if (ret) {
dev->driver = NULL;
+ rte_intr_instance_free(dev->vfio_req_intr_handle);
+ dev->vfio_req_intr_handle = NULL;
+ rte_intr_instance_free(dev->intr_handle);
+ dev->intr_handle = NULL;
if ((dr->drv_flags & RTE_PCI_DRV_NEED_MAPPING) &&
/* Don't unmap if device is unsupported and
* driver needs mapped resources.
/* clear driver structure */
dev->driver = NULL;
dev->device.driver = NULL;
+ rte_intr_instance_free(dev->intr_handle);
+ dev->intr_handle = NULL;
+ rte_intr_instance_free(dev->vfio_req_intr_handle);
+ dev->vfio_req_intr_handle = NULL;
if (dr->drv_flags & RTE_PCI_DRV_NEED_MAPPING)
/* unmap resources for devices that use igb_uio */
struct mapped_pci_res_list *uio_res_list =
RTE_TAILQ_CAST(rte_uio_tailq.head, mapped_pci_res_list);
- dev->intr_handle.fd = -1;
- dev->intr_handle.uio_cfg_fd = -1;
+ if (rte_intr_fd_set(dev->intr_handle, -1))
+ return -1;
+
+ if (rte_intr_dev_fd_set(dev->intr_handle, -1))
+ return -1;
/* secondary processes - use already recorded details */
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
struct mapped_pci_resource *uio_res;
struct mapped_pci_res_list *uio_res_list =
RTE_TAILQ_CAST(rte_uio_tailq.head, mapped_pci_res_list);
+ int uio_cfg_fd;
if (dev == NULL)
return;
rte_free(uio_res);
/* close fd if in primary process */
- close(dev->intr_handle.fd);
- if (dev->intr_handle.uio_cfg_fd >= 0) {
- close(dev->intr_handle.uio_cfg_fd);
- dev->intr_handle.uio_cfg_fd = -1;
+ close(rte_intr_fd_get(dev->intr_handle));
+ uio_cfg_fd = rte_intr_dev_fd_get(dev->intr_handle);
+ if (uio_cfg_fd >= 0) {
+ close(uio_cfg_fd);
+ rte_intr_dev_fd_set(dev->intr_handle, -1);
}
- dev->intr_handle.fd = -1;
- dev->intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;
+ rte_intr_fd_set(dev->intr_handle, -1);
+ rte_intr_type_set(dev->intr_handle, RTE_INTR_HANDLE_UNKNOWN);
}
struct rte_pci_id id; /**< PCI ID. */
struct rte_mem_resource mem_resource[PCI_MAX_RESOURCE];
/**< PCI Memory Resource */
- struct rte_intr_handle intr_handle; /**< Interrupt handle */
+ struct rte_intr_handle *intr_handle; /**< Interrupt handle */
struct rte_pci_driver *driver; /**< PCI driver used in probing */
uint16_t max_vfs; /**< sriov enable if not zero */
enum rte_pci_kernel_driver kdrv; /**< Kernel driver passthrough */
char name[PCI_PRI_STR_SIZE+1]; /**< PCI location (ASCII) */
- struct rte_intr_handle vfio_req_intr_handle;
+ struct rte_intr_handle *vfio_req_intr_handle;
/**< Handler of VFIO request interrupt */
};
dev->device.devargs = vmbus_devargs_lookup(dev);
+ /* Allocate interrupt handle instance */
+ dev->intr_handle =
+ rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_PRIVATE);
+ if (dev->intr_handle == NULL)
+ goto error;
+
/* device is valid, add in list (sorted) */
VMBUS_LOG(DEBUG, "Adding vmbus device %s", name);
/* Control interrupts */
void vmbus_uio_irq_control(struct rte_vmbus_device *dev, int32_t onoff)
{
- if (write(dev->intr_handle.fd, &onoff, sizeof(onoff)) < 0) {
+ if (write(rte_intr_fd_get(dev->intr_handle), &onoff,
+ sizeof(onoff)) < 0) {
VMBUS_LOG(ERR, "cannot write to %d:%s",
- dev->intr_handle.fd, strerror(errno));
+ rte_intr_fd_get(dev->intr_handle),
+ strerror(errno));
}
}
int32_t count;
int cc;
- cc = read(dev->intr_handle.fd, &count, sizeof(count));
+ cc = read(rte_intr_fd_get(dev->intr_handle), &count,
+ sizeof(count));
if (cc < (int)sizeof(count)) {
if (cc < 0) {
VMBUS_LOG(ERR, "IRQ read failed %s",
{
rte_free(uio_res);
- if (dev->intr_handle.uio_cfg_fd >= 0) {
- close(dev->intr_handle.uio_cfg_fd);
- dev->intr_handle.uio_cfg_fd = -1;
+ if (rte_intr_dev_fd_get(dev->intr_handle) >= 0) {
+ close(rte_intr_dev_fd_get(dev->intr_handle));
+ rte_intr_dev_fd_set(dev->intr_handle, -1);
}
- if (dev->intr_handle.fd >= 0) {
- close(dev->intr_handle.fd);
- dev->intr_handle.fd = -1;
- dev->intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;
+ if (rte_intr_fd_get(dev->intr_handle) >= 0) {
+ close(rte_intr_fd_get(dev->intr_handle));
+ rte_intr_fd_set(dev->intr_handle, -1);
+ rte_intr_type_set(dev->intr_handle, RTE_INTR_HANDLE_UNKNOWN);
}
}
struct mapped_vmbus_resource **uio_res)
{
char devname[PATH_MAX]; /* contains the /dev/uioX */
+ int fd;
/* save fd if in primary process */
snprintf(devname, sizeof(devname), "/dev/uio%u", dev->uio_num);
- dev->intr_handle.fd = open(devname, O_RDWR);
- if (dev->intr_handle.fd < 0) {
+ fd = open(devname, O_RDWR);
+ if (fd < 0) {
VMBUS_LOG(ERR, "Cannot open %s: %s",
devname, strerror(errno));
goto error;
}
- dev->intr_handle.type = RTE_INTR_HANDLE_UIO_INTX;
+
+ if (rte_intr_fd_set(dev->intr_handle, fd))
+ goto error;
+
+ if (rte_intr_type_set(dev->intr_handle, RTE_INTR_HANDLE_UIO_INTX))
+ goto error;
/* allocate the mapping details for secondary processes*/
*uio_res = rte_zmalloc("UIO_RES", sizeof(**uio_res), 0);
struct vmbus_channel *primary; /**< VMBUS primary channel */
struct vmbus_mon_page *monitor_page; /**< VMBUS monitor page */
- struct rte_intr_handle intr_handle; /**< Interrupt handle */
+ struct rte_intr_handle *intr_handle; /**< Interrupt handle */
struct rte_mem_resource resource[VMBUS_MAX_RESOURCE];
};
int ret;
/* TODO: handle rescind */
- dev->intr_handle.fd = -1;
- dev->intr_handle.uio_cfg_fd = -1;
- dev->intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;
+ if (rte_intr_fd_set(dev->intr_handle, -1))
+ return -1;
+
+ if (rte_intr_dev_fd_set(dev->intr_handle, -1))
+ return -1;
+
+ if (rte_intr_type_set(dev->intr_handle, RTE_INTR_HANDLE_UNKNOWN))
+ return -1;
/* secondary processes - use already recorded details */
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
rte_free(uio_res);
/* close fd if in primary process */
- close(dev->intr_handle.fd);
- if (dev->intr_handle.uio_cfg_fd >= 0) {
- close(dev->intr_handle.uio_cfg_fd);
- dev->intr_handle.uio_cfg_fd = -1;
+ close(rte_intr_fd_get(dev->intr_handle));
+ if (rte_intr_dev_fd_get(dev->intr_handle) >= 0) {
+ close(rte_intr_dev_fd_get(dev->intr_handle));
+ rte_intr_dev_fd_set(dev->intr_handle, -1);
}
- dev->intr_handle.fd = -1;
- dev->intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;
+ rte_intr_fd_set(dev->intr_handle, -1);
+ rte_intr_type_set(dev->intr_handle, RTE_INTR_HANDLE_UNKNOWN);
}
struct plt_intr_handle *handle;
int rc, vec;
- handle = &pci_dev->intr_handle;
+ handle = pci_dev->intr_handle;
vec = lf->msixoff + CPT_LF_INT_VEC_MISC;
/* Clear err interrupt */
struct plt_intr_handle *handle;
int vec;
- handle = &pci_dev->intr_handle;
+ handle = pci_dev->intr_handle;
vec = lf->msixoff + CPT_LF_INT_VEC_MISC;
/* Clear err interrupt */
struct plt_intr_handle *handle;
int rc, vec;
- handle = &pci_dev->intr_handle;
+ handle = pci_dev->intr_handle;
vec = lf->msixoff + CPT_LF_INT_VEC_DONE;
struct plt_intr_handle *handle;
int vec;
- handle = &pci_dev->intr_handle;
+ handle = pci_dev->intr_handle;
vec = lf->msixoff + CPT_LF_INT_VEC_DONE;
static int
mbox_register_pf_irq(struct plt_pci_device *pci_dev, struct dev *dev)
{
- struct plt_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct plt_intr_handle *intr_handle = pci_dev->intr_handle;
int i, rc;
/* HW clear irq */
static int
mbox_register_vf_irq(struct plt_pci_device *pci_dev, struct dev *dev)
{
- struct plt_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct plt_intr_handle *intr_handle = pci_dev->intr_handle;
int rc;
/* Clear irq */
static void
mbox_unregister_pf_irq(struct plt_pci_device *pci_dev, struct dev *dev)
{
- struct plt_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct plt_intr_handle *intr_handle = pci_dev->intr_handle;
int i;
/* HW clear irq */
static void
mbox_unregister_vf_irq(struct plt_pci_device *pci_dev, struct dev *dev)
{
- struct plt_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct plt_intr_handle *intr_handle = pci_dev->intr_handle;
/* Clear irq */
plt_write64(~0ull, dev->bar2 + RVU_VF_INT_ENA_W1C);
static int
vf_flr_unregister_irqs(struct plt_pci_device *pci_dev, struct dev *dev)
{
- struct plt_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct plt_intr_handle *intr_handle = pci_dev->intr_handle;
int i;
plt_base_dbg("Unregister VF FLR interrupts for %s", pci_dev->name);
static int
vf_flr_register_irqs(struct plt_pci_device *pci_dev, struct dev *dev)
{
- struct plt_intr_handle *handle = &pci_dev->intr_handle;
+ struct plt_intr_handle *handle = pci_dev->intr_handle;
int i, rc;
plt_base_dbg("Register VF FLR interrupts for %s", pci_dev->name);
int
dev_fini(struct dev *dev, struct plt_pci_device *pci_dev)
{
- struct plt_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct plt_intr_handle *intr_handle = pci_dev->intr_handle;
struct mbox *mbox;
/* Check if this dev hosts npalf and has 1+ refs */
irq_get_info(struct plt_intr_handle *intr_handle)
{
struct vfio_irq_info irq = {.argsz = sizeof(irq)};
- int rc;
+ int rc, vfio_dev_fd;
irq.index = VFIO_PCI_MSIX_IRQ_INDEX;
- rc = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_GET_IRQ_INFO, &irq);
+ vfio_dev_fd = plt_intr_dev_fd_get(intr_handle);
+ rc = ioctl(vfio_dev_fd, VFIO_DEVICE_GET_IRQ_INFO, &irq);
if (rc < 0) {
plt_err("Failed to get IRQ info rc=%d errno=%d", rc, errno);
return rc;
if (irq.count > PLT_MAX_RXTX_INTR_VEC_ID) {
plt_err("HW max=%d > PLT_MAX_RXTX_INTR_VEC_ID: %d", irq.count,
PLT_MAX_RXTX_INTR_VEC_ID);
- intr_handle->max_intr = PLT_MAX_RXTX_INTR_VEC_ID;
+ plt_intr_max_intr_set(intr_handle, PLT_MAX_RXTX_INTR_VEC_ID);
} else {
- intr_handle->max_intr = irq.count;
+ if (plt_intr_max_intr_set(intr_handle, irq.count))
+ return -1;
}
return 0;
{
char irq_set_buf[MSIX_IRQ_SET_BUF_LEN];
struct vfio_irq_set *irq_set;
+ int len, rc, vfio_dev_fd;
int32_t *fd_ptr;
- int len, rc;
- if (vec > intr_handle->max_intr) {
+ if (vec > (uint32_t)plt_intr_max_intr_get(intr_handle)) {
plt_err("vector=%d greater than max_intr=%d", vec,
- intr_handle->max_intr);
+ plt_intr_max_intr_get(intr_handle));
return -EINVAL;
}
/* Use vec fd to set interrupt vectors */
fd_ptr = (int32_t *)&irq_set->data[0];
- fd_ptr[0] = intr_handle->efds[vec];
+ fd_ptr[0] = plt_intr_efds_index_get(intr_handle, vec);
- rc = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);
+ vfio_dev_fd = plt_intr_dev_fd_get(intr_handle);
+ rc = ioctl(vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);
if (rc)
plt_err("Failed to set_irqs vector=0x%x rc=%d", vec, rc);
{
char irq_set_buf[MSIX_IRQ_SET_BUF_LEN];
struct vfio_irq_set *irq_set;
+ int len, rc, vfio_dev_fd;
int32_t *fd_ptr;
- int len, rc;
uint32_t i;
- if (intr_handle->max_intr > PLT_MAX_RXTX_INTR_VEC_ID) {
+ if (plt_intr_max_intr_get(intr_handle) >
+ PLT_MAX_RXTX_INTR_VEC_ID) {
plt_err("Max_intr=%d greater than PLT_MAX_RXTX_INTR_VEC_ID=%d",
- intr_handle->max_intr, PLT_MAX_RXTX_INTR_VEC_ID);
+ plt_intr_max_intr_get(intr_handle),
+ PLT_MAX_RXTX_INTR_VEC_ID);
return -ERANGE;
}
len = sizeof(struct vfio_irq_set) +
- sizeof(int32_t) * intr_handle->max_intr;
+ sizeof(int32_t) * plt_intr_max_intr_get(intr_handle);
irq_set = (struct vfio_irq_set *)irq_set_buf;
irq_set->argsz = len;
irq_set->start = 0;
- irq_set->count = intr_handle->max_intr;
+ irq_set->count = plt_intr_max_intr_get(intr_handle);
irq_set->flags =
VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER;
irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX;
for (i = 0; i < irq_set->count; i++)
fd_ptr[i] = -1;
- rc = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);
+ vfio_dev_fd = plt_intr_dev_fd_get(intr_handle);
+ rc = ioctl(vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);
if (rc)
plt_err("Failed to set irqs vector rc=%d", rc);
dev_irqs_disable(struct plt_intr_handle *intr_handle)
{
/* Clear max_intr to indicate re-init next time */
- intr_handle->max_intr = 0;
+ plt_intr_max_intr_set(intr_handle, 0);
return plt_intr_disable(intr_handle);
}
dev_irq_register(struct plt_intr_handle *intr_handle, plt_intr_callback_fn cb,
void *data, unsigned int vec)
{
- struct plt_intr_handle tmp_handle;
- int rc;
+ struct plt_intr_handle *tmp_handle;
+ uint32_t nb_efd, tmp_nb_efd;
+ int rc, fd;
/* If no max_intr read from VFIO */
- if (intr_handle->max_intr == 0) {
+ if (plt_intr_max_intr_get(intr_handle) == 0) {
irq_get_info(intr_handle);
irq_init(intr_handle);
}
- if (vec > intr_handle->max_intr || vec >= PLT_DIM(intr_handle->efds)) {
- plt_err("Vector=%d greater than max_intr=%d or "
- "max_efd=%" PRIu64,
- vec, intr_handle->max_intr, PLT_DIM(intr_handle->efds));
+ if (vec > (uint32_t)plt_intr_max_intr_get(intr_handle)) {
+ plt_err("Vector=%d greater than max_intr=%d or ",
+ vec, plt_intr_max_intr_get(intr_handle));
return -EINVAL;
}
- tmp_handle = *intr_handle;
+ tmp_handle = intr_handle;
/* Create new eventfd for interrupt vector */
- tmp_handle.fd = eventfd(0, EFD_NONBLOCK | EFD_CLOEXEC);
- if (tmp_handle.fd == -1)
+ fd = eventfd(0, EFD_NONBLOCK | EFD_CLOEXEC);
+ if (fd == -1)
return -ENODEV;
+ if (plt_intr_fd_set(tmp_handle, fd))
+ return -errno;
+
/* Register vector interrupt callback */
- rc = plt_intr_callback_register(&tmp_handle, cb, data);
+ rc = plt_intr_callback_register(tmp_handle, cb, data);
if (rc) {
plt_err("Failed to register vector:0x%x irq callback.", vec);
return rc;
}
- intr_handle->efds[vec] = tmp_handle.fd;
- intr_handle->nb_efd =
- (vec > intr_handle->nb_efd) ? vec : intr_handle->nb_efd;
- if ((intr_handle->nb_efd + 1) > intr_handle->max_intr)
- intr_handle->max_intr = intr_handle->nb_efd + 1;
+ plt_intr_efds_index_set(intr_handle, vec, fd);
+ nb_efd = (vec > (uint32_t)plt_intr_nb_efd_get(intr_handle)) ?
+ vec : (uint32_t)plt_intr_nb_efd_get(intr_handle);
+ plt_intr_nb_efd_set(intr_handle, nb_efd);
+ tmp_nb_efd = plt_intr_nb_efd_get(intr_handle) + 1;
+ if (tmp_nb_efd > (uint32_t)plt_intr_max_intr_get(intr_handle))
+ plt_intr_max_intr_set(intr_handle, tmp_nb_efd);
plt_base_dbg("Enable vector:0x%x for vfio (efds: %d, max:%d)", vec,
- intr_handle->nb_efd, intr_handle->max_intr);
+ plt_intr_nb_efd_get(intr_handle),
+ plt_intr_max_intr_get(intr_handle));
/* Enable MSIX vectors to VFIO */
return irq_config(intr_handle, vec);
dev_irq_unregister(struct plt_intr_handle *intr_handle, plt_intr_callback_fn cb,
void *data, unsigned int vec)
{
- struct plt_intr_handle tmp_handle;
+ struct plt_intr_handle *tmp_handle;
uint8_t retries = 5; /* 5 ms */
- int rc;
+ int rc, fd;
- if (vec > intr_handle->max_intr) {
+ if (vec > (uint32_t)plt_intr_max_intr_get(intr_handle)) {
plt_err("Error unregistering MSI-X interrupts vec:%d > %d", vec,
- intr_handle->max_intr);
+ plt_intr_max_intr_get(intr_handle));
return;
}
- tmp_handle = *intr_handle;
- tmp_handle.fd = intr_handle->efds[vec];
- if (tmp_handle.fd == -1)
+ tmp_handle = intr_handle;
+ fd = plt_intr_efds_index_get(intr_handle, vec);
+ if (fd == -1)
+ return;
+
+ if (plt_intr_fd_set(tmp_handle, fd))
return;
do {
/* Un-register callback func from platform lib */
- rc = plt_intr_callback_unregister(&tmp_handle, cb, data);
+ rc = plt_intr_callback_unregister(tmp_handle, cb, data);
/* Retry only if -EAGAIN */
if (rc != -EAGAIN)
break;
}
plt_base_dbg("Disable vector:0x%x for vfio (efds: %d, max:%d)", vec,
- intr_handle->nb_efd, intr_handle->max_intr);
+ plt_intr_nb_efd_get(intr_handle),
+ plt_intr_max_intr_get(intr_handle));
- if (intr_handle->efds[vec] != -1)
- close(intr_handle->efds[vec]);
+ if (plt_intr_efds_index_get(intr_handle, vec) != -1)
+ close(plt_intr_efds_index_get(intr_handle, vec));
/* Disable MSIX vectors from VFIO */
- intr_handle->efds[vec] = -1;
+ plt_intr_efds_index_set(intr_handle, vec, -1);
+
irq_config(intr_handle, vec);
}
int
nix_inl_sso_register_irqs(struct nix_inl_dev *inl_dev)
{
- struct plt_intr_handle *handle = &inl_dev->pci_dev->intr_handle;
+ struct plt_intr_handle *handle = inl_dev->pci_dev->intr_handle;
uintptr_t ssow_base = inl_dev->ssow_base;
uintptr_t sso_base = inl_dev->sso_base;
uint16_t sso_msixoff, ssow_msixoff;
void
nix_inl_sso_unregister_irqs(struct nix_inl_dev *inl_dev)
{
- struct plt_intr_handle *handle = &inl_dev->pci_dev->intr_handle;
+ struct plt_intr_handle *handle = inl_dev->pci_dev->intr_handle;
uintptr_t ssow_base = inl_dev->ssow_base;
uintptr_t sso_base = inl_dev->sso_base;
uint16_t sso_msixoff, ssow_msixoff;
int
nix_inl_nix_register_irqs(struct nix_inl_dev *inl_dev)
{
- struct plt_intr_handle *handle = &inl_dev->pci_dev->intr_handle;
+ struct plt_intr_handle *handle = inl_dev->pci_dev->intr_handle;
uintptr_t nix_base = inl_dev->nix_base;
uint16_t msixoff;
int rc;
void
nix_inl_nix_unregister_irqs(struct nix_inl_dev *inl_dev)
{
- struct plt_intr_handle *handle = &inl_dev->pci_dev->intr_handle;
+ struct plt_intr_handle *handle = inl_dev->pci_dev->intr_handle;
uintptr_t nix_base = inl_dev->nix_base;
uint16_t msixoff;
static int
nix_lf_register_err_irq(struct nix *nix)
{
- struct plt_intr_handle *handle = &nix->pci_dev->intr_handle;
+ struct plt_intr_handle *handle = nix->pci_dev->intr_handle;
int rc, vec;
vec = nix->msixoff + NIX_LF_INT_VEC_ERR_INT;
static void
nix_lf_unregister_err_irq(struct nix *nix)
{
- struct plt_intr_handle *handle = &nix->pci_dev->intr_handle;
+ struct plt_intr_handle *handle = nix->pci_dev->intr_handle;
int vec;
vec = nix->msixoff + NIX_LF_INT_VEC_ERR_INT;
static int
nix_lf_register_ras_irq(struct nix *nix)
{
- struct plt_intr_handle *handle = &nix->pci_dev->intr_handle;
+ struct plt_intr_handle *handle = nix->pci_dev->intr_handle;
int rc, vec;
vec = nix->msixoff + NIX_LF_INT_VEC_POISON;
static void
nix_lf_unregister_ras_irq(struct nix *nix)
{
- struct plt_intr_handle *handle = &nix->pci_dev->intr_handle;
+ struct plt_intr_handle *handle = nix->pci_dev->intr_handle;
int vec;
vec = nix->msixoff + NIX_LF_INT_VEC_POISON;
struct nix *nix;
nix = roc_nix_to_nix_priv(roc_nix);
- handle = &nix->pci_dev->intr_handle;
+ handle = nix->pci_dev->intr_handle;
/* Figure out max qintx required */
rqs = PLT_MIN(nix->qints, nix->nb_rx_queues);
int vec, q;
nix = roc_nix_to_nix_priv(roc_nix);
- handle = &nix->pci_dev->intr_handle;
+ handle = nix->pci_dev->intr_handle;
for (q = 0; q < nix->configured_qints; q++) {
vec = nix->msixoff + NIX_LF_INT_VEC_QINT_START + q;
struct nix *nix;
nix = roc_nix_to_nix_priv(roc_nix);
- handle = &nix->pci_dev->intr_handle;
+ handle = nix->pci_dev->intr_handle;
nix->configured_cints = PLT_MIN(nix->cints, nix->nb_rx_queues);
return rc;
}
- if (!handle->intr_vec) {
- handle->intr_vec = plt_zmalloc(
- nix->configured_cints * sizeof(int), 0);
- if (!handle->intr_vec) {
- plt_err("Failed to allocate %d rx intr_vec",
- nix->configured_cints);
- return -ENOMEM;
- }
+ rc = plt_intr_vec_list_alloc(handle, "cnxk",
+ nix->configured_cints);
+ if (rc) {
+ plt_err("Fail to allocate intr vec list, rc=%d",
+ rc);
+ return rc;
}
/* VFIO vector zero is resereved for misc interrupt so
* doing required adjustment. (b13bfab4cd)
*/
- handle->intr_vec[q] = PLT_INTR_VEC_RXTX_OFFSET + vec;
+ if (plt_intr_vec_list_index_set(handle, q,
+ PLT_INTR_VEC_RXTX_OFFSET + vec))
+ return -1;
/* Configure CQE interrupt coalescing parameters */
plt_write64(((CQ_CQE_THRESH_DEFAULT) |
int vec, q;
nix = roc_nix_to_nix_priv(roc_nix);
- handle = &nix->pci_dev->intr_handle;
+ handle = nix->pci_dev->intr_handle;
for (q = 0; q < nix->configured_cints; q++) {
vec = nix->msixoff + NIX_LF_INT_VEC_CINT_START + q;
dev_irq_unregister(handle, nix_lf_cq_irq, &nix->cints_mem[q],
vec);
}
+
+ plt_intr_vec_list_free(handle);
plt_free(nix->cints_mem);
}
lf->pf_func = dev->pf_func;
lf->npa_msixoff = npa_msixoff;
- lf->intr_handle = &pci_dev->intr_handle;
+ lf->intr_handle = pci_dev->intr_handle;
lf->pci_dev = pci_dev;
idev->npa_pf_func = dev->pf_func;
#define plt_thread_is_intr rte_thread_is_intr
#define plt_intr_callback_fn rte_intr_callback_fn
+#define plt_intr_efd_counter_size_get rte_intr_efd_counter_size_get
+#define plt_intr_efd_counter_size_set rte_intr_efd_counter_size_set
+#define plt_intr_vec_list_index_get rte_intr_vec_list_index_get
+#define plt_intr_vec_list_index_set rte_intr_vec_list_index_set
+#define plt_intr_vec_list_alloc rte_intr_vec_list_alloc
+#define plt_intr_vec_list_free rte_intr_vec_list_free
+#define plt_intr_fd_set rte_intr_fd_set
+#define plt_intr_fd_get rte_intr_fd_get
+#define plt_intr_dev_fd_get rte_intr_dev_fd_get
+#define plt_intr_dev_fd_set rte_intr_dev_fd_set
+#define plt_intr_type_get rte_intr_type_get
+#define plt_intr_type_set rte_intr_type_set
+#define plt_intr_instance_alloc rte_intr_instance_alloc
+#define plt_intr_instance_dup rte_intr_instance_dup
+#define plt_intr_instance_free rte_intr_instance_free
+#define plt_intr_max_intr_get rte_intr_max_intr_get
+#define plt_intr_max_intr_set rte_intr_max_intr_set
+#define plt_intr_nb_efd_get rte_intr_nb_efd_get
+#define plt_intr_nb_efd_set rte_intr_nb_efd_set
+#define plt_intr_nb_intr_get rte_intr_nb_intr_get
+#define plt_intr_nb_intr_set rte_intr_nb_intr_set
+#define plt_intr_efds_index_get rte_intr_efds_index_get
+#define plt_intr_efds_index_set rte_intr_efds_index_set
+#define plt_intr_elist_index_get rte_intr_elist_index_get
+#define plt_intr_elist_index_set rte_intr_elist_index_set
+
#define plt_alarm_set rte_eal_alarm_set
#define plt_alarm_cancel rte_eal_alarm_cancel
#define plt_dbg(subsystem, fmt, args...) \
rte_log(RTE_LOG_DEBUG, cnxk_logtype_##subsystem, \
"[%s] %s():%u " fmt "\n", #subsystem, __func__, __LINE__, \
- ##args)
+##args)
#define plt_base_dbg(fmt, ...) plt_dbg(base, fmt, ##__VA_ARGS__)
#define plt_cpt_dbg(fmt, ...) plt_dbg(cpt, fmt, ##__VA_ARGS__)
#ifdef __cplusplus
#define CNXK_PCI_ID(subsystem_dev, dev) \
- { \
- RTE_CLASS_ANY_ID, PCI_VENDOR_ID_CAVIUM, (dev), RTE_PCI_ANY_ID, \
- (subsystem_dev), \
- }
+{ \
+ RTE_CLASS_ANY_ID, PCI_VENDOR_ID_CAVIUM, (dev), RTE_PCI_ANY_ID, \
+ (subsystem_dev), \
+}
#else
#define CNXK_PCI_ID(subsystem_dev, dev) \
- { \
- .class_id = RTE_CLASS_ANY_ID, \
- .vendor_id = PCI_VENDOR_ID_CAVIUM, .device_id = (dev), \
- .subsystem_vendor_id = RTE_PCI_ANY_ID, \
- .subsystem_device_id = (subsystem_dev), \
- }
+{ \
+ .class_id = RTE_CLASS_ANY_ID, \
+ .vendor_id = PCI_VENDOR_ID_CAVIUM, .device_id = (dev), \
+ .subsystem_vendor_id = RTE_PCI_ANY_ID, \
+ .subsystem_device_id = (subsystem_dev), \
+}
#endif
__rte_internal
goto sso_msix_fail;
}
- rc = sso_register_irqs_priv(roc_sso, &sso->pci_dev->intr_handle, nb_hws,
+ rc = sso_register_irqs_priv(roc_sso, sso->pci_dev->intr_handle, nb_hws,
nb_hwgrp);
if (rc < 0) {
plt_err("Failed to register SSO LF IRQs");
if (!roc_sso->nb_hws && !roc_sso->nb_hwgrp)
return;
- sso_unregister_irqs_priv(roc_sso, &sso->pci_dev->intr_handle,
+ sso_unregister_irqs_priv(roc_sso, sso->pci_dev->intr_handle,
roc_sso->nb_hws, roc_sso->nb_hwgrp);
sso_lf_free(&sso->dev, SSO_LF_TYPE_HWS, roc_sso->nb_hws);
sso_lf_free(&sso->dev, SSO_LF_TYPE_HWGRP, roc_sso->nb_hwgrp);
if (clk)
*clk = rsp->tenns_clk;
- rc = tim_register_irq_priv(roc_tim, &sso->pci_dev->intr_handle, ring_id,
+ rc = tim_register_irq_priv(roc_tim, sso->pci_dev->intr_handle, ring_id,
tim->tim_msix_offsets[ring_id]);
if (rc < 0) {
plt_tim_dbg("Failed to register Ring[%d] IRQ", ring_id);
struct tim_ring_req *req;
int rc = -ENOSPC;
- tim_unregister_irq_priv(roc_tim, &sso->pci_dev->intr_handle, ring_id,
+ tim_unregister_irq_priv(roc_tim, sso->pci_dev->intr_handle, ring_id,
tim->tim_msix_offsets[ring_id]);
req = mbox_alloc_msg_tim_lf_free(dev->mbox);
static int
mbox_register_pf_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
{
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
int i, rc;
/* HW clear irq */
static int
mbox_register_vf_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
{
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
int rc;
/* Clear irq */
static void
mbox_unregister_pf_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
{
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
int i;
/* HW clear irq */
static void
mbox_unregister_vf_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
{
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
/* Clear irq */
otx2_write64(~0ull, dev->bar2 + RVU_VF_INT_ENA_W1C);
static int
vf_flr_unregister_irqs(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
{
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
int i;
otx2_base_dbg("Unregister VF FLR interrupts for %s", pci_dev->name);
static int
vf_flr_register_irqs(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
{
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
int i, rc;
otx2_base_dbg("Register VF FLR interrupts for %s", pci_dev->name);
void
otx2_dev_fini(struct rte_pci_device *pci_dev, void *otx2_dev)
{
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct otx2_dev *dev = otx2_dev;
struct otx2_idev_cfg *idev;
struct otx2_mbox *mbox;
irq_get_info(struct rte_intr_handle *intr_handle)
{
struct vfio_irq_info irq = { .argsz = sizeof(irq) };
- int rc;
+ int rc, vfio_dev_fd;
irq.index = VFIO_PCI_MSIX_IRQ_INDEX;
- rc = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_GET_IRQ_INFO, &irq);
+ vfio_dev_fd = rte_intr_dev_fd_get(intr_handle);
+ rc = ioctl(vfio_dev_fd, VFIO_DEVICE_GET_IRQ_INFO, &irq);
if (rc < 0) {
otx2_err("Failed to get IRQ info rc=%d errno=%d", rc, errno);
return rc;
if (irq.count > MAX_INTR_VEC_ID) {
otx2_err("HW max=%d > MAX_INTR_VEC_ID: %d",
- intr_handle->max_intr, MAX_INTR_VEC_ID);
- intr_handle->max_intr = MAX_INTR_VEC_ID;
+ rte_intr_max_intr_get(intr_handle),
+ MAX_INTR_VEC_ID);
+ if (rte_intr_max_intr_set(intr_handle, MAX_INTR_VEC_ID))
+ return -1;
} else {
- intr_handle->max_intr = irq.count;
+ if (rte_intr_max_intr_set(intr_handle, irq.count))
+ return -1;
}
return 0;
{
char irq_set_buf[MSIX_IRQ_SET_BUF_LEN];
struct vfio_irq_set *irq_set;
+ int len, rc, vfio_dev_fd;
int32_t *fd_ptr;
- int len, rc;
- if (vec > intr_handle->max_intr) {
+ if (vec > (uint32_t)rte_intr_max_intr_get(intr_handle)) {
otx2_err("vector=%d greater than max_intr=%d", vec,
- intr_handle->max_intr);
+ rte_intr_max_intr_get(intr_handle));
return -EINVAL;
}
/* Use vec fd to set interrupt vectors */
fd_ptr = (int32_t *)&irq_set->data[0];
- fd_ptr[0] = intr_handle->efds[vec];
+ fd_ptr[0] = rte_intr_efds_index_get(intr_handle, vec);
- rc = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);
+ vfio_dev_fd = rte_intr_dev_fd_get(intr_handle);
+ rc = ioctl(vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);
if (rc)
otx2_err("Failed to set_irqs vector=0x%x rc=%d", vec, rc);
{
char irq_set_buf[MSIX_IRQ_SET_BUF_LEN];
struct vfio_irq_set *irq_set;
+ int len, rc, vfio_dev_fd;
int32_t *fd_ptr;
- int len, rc;
uint32_t i;
- if (intr_handle->max_intr > MAX_INTR_VEC_ID) {
+ if (rte_intr_max_intr_get(intr_handle) > MAX_INTR_VEC_ID) {
otx2_err("Max_intr=%d greater than MAX_INTR_VEC_ID=%d",
- intr_handle->max_intr, MAX_INTR_VEC_ID);
+ rte_intr_max_intr_get(intr_handle),
+ MAX_INTR_VEC_ID);
return -ERANGE;
}
len = sizeof(struct vfio_irq_set) +
- sizeof(int32_t) * intr_handle->max_intr;
+ sizeof(int32_t) * rte_intr_max_intr_get(intr_handle);
irq_set = (struct vfio_irq_set *)irq_set_buf;
irq_set->argsz = len;
irq_set->start = 0;
- irq_set->count = intr_handle->max_intr;
+ irq_set->count = rte_intr_max_intr_get(intr_handle);
irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD |
VFIO_IRQ_SET_ACTION_TRIGGER;
irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX;
for (i = 0; i < irq_set->count; i++)
fd_ptr[i] = -1;
- rc = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);
+ vfio_dev_fd = rte_intr_dev_fd_get(intr_handle);
+ rc = ioctl(vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);
if (rc)
otx2_err("Failed to set irqs vector rc=%d", rc);
otx2_disable_irqs(struct rte_intr_handle *intr_handle)
{
/* Clear max_intr to indicate re-init next time */
- intr_handle->max_intr = 0;
+ if (rte_intr_max_intr_set(intr_handle, 0))
+ return -1;
return rte_intr_disable(intr_handle);
}
otx2_register_irq(struct rte_intr_handle *intr_handle,
rte_intr_callback_fn cb, void *data, unsigned int vec)
{
- struct rte_intr_handle tmp_handle;
- int rc;
+ struct rte_intr_handle *tmp_handle;
+ uint32_t nb_efd, tmp_nb_efd;
+ int rc, fd;
/* If no max_intr read from VFIO */
- if (intr_handle->max_intr == 0) {
+ if (rte_intr_max_intr_get(intr_handle) == 0) {
irq_get_info(intr_handle);
irq_init(intr_handle);
}
- if (vec > intr_handle->max_intr) {
+ if (vec > (uint32_t)rte_intr_max_intr_get(intr_handle)) {
otx2_err("Vector=%d greater than max_intr=%d", vec,
- intr_handle->max_intr);
+ rte_intr_max_intr_get(intr_handle));
return -EINVAL;
}
- tmp_handle = *intr_handle;
+ tmp_handle = intr_handle;
/* Create new eventfd for interrupt vector */
- tmp_handle.fd = eventfd(0, EFD_NONBLOCK | EFD_CLOEXEC);
- if (tmp_handle.fd == -1)
+ fd = eventfd(0, EFD_NONBLOCK | EFD_CLOEXEC);
+ if (fd == -1)
return -ENODEV;
+ if (rte_intr_fd_set(tmp_handle, fd))
+ return errno;
+
/* Register vector interrupt callback */
- rc = rte_intr_callback_register(&tmp_handle, cb, data);
+ rc = rte_intr_callback_register(tmp_handle, cb, data);
if (rc) {
otx2_err("Failed to register vector:0x%x irq callback.", vec);
return rc;
}
- intr_handle->efds[vec] = tmp_handle.fd;
- intr_handle->nb_efd = (vec > intr_handle->nb_efd) ?
- vec : intr_handle->nb_efd;
- if ((intr_handle->nb_efd + 1) > intr_handle->max_intr)
- intr_handle->max_intr = intr_handle->nb_efd + 1;
+ rte_intr_efds_index_set(intr_handle, vec, fd);
+ nb_efd = (vec > (uint32_t)rte_intr_nb_efd_get(intr_handle)) ?
+ vec : (uint32_t)rte_intr_nb_efd_get(intr_handle);
+ rte_intr_nb_efd_set(intr_handle, nb_efd);
+
+ tmp_nb_efd = rte_intr_nb_efd_get(intr_handle) + 1;
+ if (tmp_nb_efd > (uint32_t)rte_intr_max_intr_get(intr_handle))
+ rte_intr_max_intr_set(intr_handle, tmp_nb_efd);
- otx2_base_dbg("Enable vector:0x%x for vfio (efds: %d, max:%d)",
- vec, intr_handle->nb_efd, intr_handle->max_intr);
+ otx2_base_dbg("Enable vector:0x%x for vfio (efds: %d, max:%d)", vec,
+ rte_intr_nb_efd_get(intr_handle),
+ rte_intr_max_intr_get(intr_handle));
/* Enable MSIX vectors to VFIO */
return irq_config(intr_handle, vec);
otx2_unregister_irq(struct rte_intr_handle *intr_handle,
rte_intr_callback_fn cb, void *data, unsigned int vec)
{
- struct rte_intr_handle tmp_handle;
+ struct rte_intr_handle *tmp_handle;
uint8_t retries = 5; /* 5 ms */
- int rc;
+ int rc, fd;
- if (vec > intr_handle->max_intr) {
+ if (vec > (uint32_t)rte_intr_max_intr_get(intr_handle)) {
otx2_err("Error unregistering MSI-X interrupts vec:%d > %d",
- vec, intr_handle->max_intr);
+ vec, rte_intr_max_intr_get(intr_handle));
return;
}
- tmp_handle = *intr_handle;
- tmp_handle.fd = intr_handle->efds[vec];
- if (tmp_handle.fd == -1)
+ tmp_handle = intr_handle;
+ fd = rte_intr_efds_index_get(intr_handle, vec);
+ if (fd == -1)
+ return;
+
+ if (rte_intr_fd_set(tmp_handle, fd))
return;
do {
- /* Un-register callback func from eal lib */
- rc = rte_intr_callback_unregister(&tmp_handle, cb, data);
+ /* Un-register callback func from platform lib */
+ rc = rte_intr_callback_unregister(tmp_handle, cb, data);
/* Retry only if -EAGAIN */
if (rc != -EAGAIN)
break;
} while (retries);
if (rc < 0) {
- otx2_err("Error unregistering MSI-X intr vec %d cb, rc=%d",
- vec, rc);
+ otx2_err("Error unregistering MSI-X vec %d cb, rc=%d", vec, rc);
return;
}
- otx2_base_dbg("Disable vector:0x%x for vfio (efds: %d, max:%d)",
- vec, intr_handle->nb_efd, intr_handle->max_intr);
+ otx2_base_dbg("Disable vector:0x%x for vfio (efds: %d, max:%d)", vec,
+ rte_intr_nb_efd_get(intr_handle),
+ rte_intr_max_intr_get(intr_handle));
- if (intr_handle->efds[vec] != -1)
- close(intr_handle->efds[vec]);
+ if (rte_intr_efds_index_get(intr_handle, vec) != -1)
+ close(rte_intr_efds_index_get(intr_handle, vec));
/* Disable MSIX vectors from VFIO */
- intr_handle->efds[vec] = -1;
+ rte_intr_efds_index_set(intr_handle, vec, -1);
irq_config(intr_handle, vec);
}
uint16_t msix_off, uintptr_t base)
{
struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
/* Disable error interrupts */
otx2_write64(~0ull, base + OTX2_CPT_LF_MISC_INT_ENA_W1C);
uint16_t msix_off, uintptr_t base)
{
struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
int ret;
/* Disable error interrupts */
uintptr_t base)
{
struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev);
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
int rc, vec;
vec = ggrp_msixoff + SSO_LF_INT_VEC_GRP;
uintptr_t base)
{
struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev);
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
int rc, vec;
vec = gws_msixoff + SSOW_LF_INT_VEC_IOP;
uint16_t ggrp_msixoff, uintptr_t base)
{
struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev);
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
int vec;
vec = ggrp_msixoff + SSO_LF_INT_VEC_GRP;
uint16_t gws_msixoff, uintptr_t base)
{
struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev);
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
int vec;
vec = gws_msixoff + SSOW_LF_INT_VEC_IOP;
tim_lf_register_irq(struct rte_pci_device *pci_dev, uint16_t tim_msixoff,
uintptr_t base)
{
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
int rc, vec;
vec = tim_msixoff + TIM_LF_INT_VEC_NRSPERR_INT;
tim_lf_unregister_irq(struct rte_pci_device *pci_dev, uint16_t tim_msixoff,
uintptr_t base)
{
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
int vec;
vec = tim_msixoff + TIM_LF_INT_VEC_NRSPERR_INT;
lf->pf_func = dev->pf_func;
lf->npa_msixoff = npa_msixoff;
- lf->intr_handle = &pci_dev->intr_handle;
+ lf->intr_handle = pci_dev->intr_handle;
lf->pci_dev = pci_dev;
idev->npa_pf_func = dev->pf_func;
{
struct atl_adapter *adapter = eth_dev->data->dev_private;
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
int err = 0;
{
struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
uint32_t intr_vector = 0;
int status;
int err;
}
}
- if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
- intr_handle->intr_vec = rte_zmalloc("intr_vec",
- dev->data->nb_rx_queues * sizeof(int), 0);
- if (intr_handle->intr_vec == NULL) {
+ if (rte_intr_dp_is_en(intr_handle)) {
+ if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
+ dev->data->nb_rx_queues)) {
PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
" intr_vec", dev->data->nb_rx_queues);
return -ENOMEM;
struct aq_hw_s *hw =
ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
PMD_INIT_FUNC_TRACE();
dev->data->dev_started = 0;
/* Clean datapath event and queue/vec mapping */
rte_intr_efd_disable(intr_handle);
- if (intr_handle->intr_vec != NULL) {
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
- }
+ rte_intr_vec_list_free(intr_handle);
return 0;
}
atl_dev_close(struct rte_eth_dev *dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct aq_hw_s *hw;
int ret;
status);
/* re-enable UIO interrupt handling */
- ret = rte_intr_ack(&pci_dev->intr_handle);
+ ret = rte_intr_ack(pci_dev->intr_handle);
if (ret < 0) {
PMD_DRV_LOG(ERR, "Failed to re-enable UIO interrupts, ret=%d\n",
ret);
return -EINVAL;
/* enable UIO interrupt handling */
- ret = rte_intr_enable(&pci_dev->intr_handle);
+ ret = rte_intr_enable(pci_dev->intr_handle);
if (ret < 0) {
PMD_DRV_LOG(ERR, "Failed to enable UIO interrupts, ret=%d\n",
ret);
RTE_PTR_ADD(registers, RTE_AVP_INTERRUPT_MASK_OFFSET));
/* enable UIO interrupt handling */
- ret = rte_intr_disable(&pci_dev->intr_handle);
+ ret = rte_intr_disable(pci_dev->intr_handle);
if (ret < 0) {
PMD_DRV_LOG(ERR, "Failed to disable UIO interrupts, ret=%d\n",
ret);
int ret;
/* register a callback handler with UIO for interrupt notifications */
- ret = rte_intr_callback_register(&pci_dev->intr_handle,
+ ret = rte_intr_callback_register(pci_dev->intr_handle,
avp_dev_interrupt_handler,
(void *)eth_dev);
if (ret < 0) {
}
}
/* Unmask interrupts since disabled after generation */
- rte_intr_ack(&pdata->pci_dev->intr_handle);
+ rte_intr_ack(pdata->pci_dev->intr_handle);
}
/*
}
/* enable uio/vfio intr/eventfd mapping */
- rte_intr_enable(&pdata->pci_dev->intr_handle);
+ rte_intr_enable(pdata->pci_dev->intr_handle);
/* phy start*/
pdata->phy_if.phy_start(pdata);
PMD_INIT_FUNC_TRACE();
- rte_intr_disable(&pdata->pci_dev->intr_handle);
+ rte_intr_disable(pdata->pci_dev->intr_handle);
if (rte_bit_relaxed_get32(AXGBE_STOPPED, &pdata->dev_state))
return 0;
return ret;
}
- rte_intr_callback_register(&pci_dev->intr_handle,
+ rte_intr_callback_register(pci_dev->intr_handle,
axgbe_dev_interrupt_handler,
(void *)eth_dev);
PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
axgbe_dev_clear_queues(eth_dev);
/* disable uio intr before callback unregister */
- rte_intr_disable(&pci_dev->intr_handle);
- rte_intr_callback_unregister(&pci_dev->intr_handle,
+ rte_intr_disable(pci_dev->intr_handle);
+ rte_intr_callback_unregister(pci_dev->intr_handle,
axgbe_dev_interrupt_handler,
(void *)eth_dev);
}
/* Disable auto-negotiation interrupt */
- rte_intr_disable(&pdata->pci_dev->intr_handle);
+ rte_intr_disable(pdata->pci_dev->intr_handle);
/* Start auto-negotiation in a supported mode */
if (axgbe_use_mode(pdata, AXGBE_MODE_KR)) {
} else if (axgbe_use_mode(pdata, AXGBE_MODE_SGMII_100)) {
axgbe_set_mode(pdata, AXGBE_MODE_SGMII_100);
} else {
- rte_intr_enable(&pdata->pci_dev->intr_handle);
+ rte_intr_enable(pdata->pci_dev->intr_handle);
return -EINVAL;
}
pdata->kx_state = AXGBE_RX_BPA;
/* Re-enable auto-negotiation interrupt */
- rte_intr_enable(&pdata->pci_dev->intr_handle);
+ rte_intr_enable(pdata->pci_dev->intr_handle);
axgbe_an37_enable_interrupts(pdata);
axgbe_an_init(pdata);
PMD_DEBUG_PERIODIC_LOG(INFO, sc, "Interrupt handled");
bnx2x_interrupt_action(dev, 1);
- rte_intr_ack(&sc->pci_dev->intr_handle);
+ rte_intr_ack(sc->pci_dev->intr_handle);
}
static void bnx2x_periodic_start(void *param)
}
if (IS_PF(sc)) {
- rte_intr_callback_register(&sc->pci_dev->intr_handle,
+ rte_intr_callback_register(sc->pci_dev->intr_handle,
bnx2x_interrupt_handler, (void *)dev);
- if (rte_intr_enable(&sc->pci_dev->intr_handle))
+ if (rte_intr_enable(sc->pci_dev->intr_handle))
PMD_DRV_LOG(ERR, sc, "rte_intr_enable failed");
}
bnx2x_dev_rxtx_init_dummy(dev);
if (IS_PF(sc)) {
- rte_intr_disable(&sc->pci_dev->intr_handle);
- rte_intr_callback_unregister(&sc->pci_dev->intr_handle,
+ rte_intr_disable(sc->pci_dev->intr_handle);
+ rte_intr_callback_unregister(sc->pci_dev->intr_handle,
bnx2x_interrupt_handler, (void *)dev);
/* stop the periodic callout */
static int bnxt_start_nic(struct bnxt *bp)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
uint32_t intr_vector = 0;
uint32_t queue_id, base = BNXT_MISC_VEC_ID;
uint32_t vec = BNXT_MISC_VEC_ID;
return rc;
}
- if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
- intr_handle->intr_vec =
- rte_zmalloc("intr_vec",
- bp->eth_dev->data->nb_rx_queues *
- sizeof(int), 0);
- if (intr_handle->intr_vec == NULL) {
+ if (rte_intr_dp_is_en(intr_handle)) {
+ if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
+ bp->eth_dev->data->nb_rx_queues)) {
PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
" intr_vec", bp->eth_dev->data->nb_rx_queues);
rc = -ENOMEM;
goto err_out;
}
- PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
- "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
- intr_handle->intr_vec, intr_handle->nb_efd,
- intr_handle->max_intr);
+ PMD_DRV_LOG(DEBUG, "intr_handle->nb_efd = %d "
+ "intr_handle->max_intr = %d\n",
+ rte_intr_nb_efd_get(intr_handle),
+ rte_intr_max_intr_get(intr_handle));
for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
queue_id++) {
- intr_handle->intr_vec[queue_id] =
- vec + BNXT_RX_VEC_START;
- if (vec < base + intr_handle->nb_efd - 1)
+ rte_intr_vec_list_index_set(intr_handle,
+ queue_id, vec + BNXT_RX_VEC_START);
+ if (vec < base + rte_intr_nb_efd_get(intr_handle)
+ - 1)
vec++;
}
}
{
struct bnxt *bp = eth_dev->data->dev_private;
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct rte_eth_link link;
int ret;
/* Clean queue intr-vector mapping */
rte_intr_efd_disable(intr_handle);
- if (intr_handle->intr_vec != NULL) {
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
- }
+ rte_intr_vec_list_free(intr_handle);
bnxt_hwrm_port_clr_stats(bp);
bnxt_free_tx_mbufs(bp);
int bnxt_free_int(struct bnxt *bp)
{
- struct rte_intr_handle *intr_handle = &bp->pdev->intr_handle;
+ struct rte_intr_handle *intr_handle = bp->pdev->intr_handle;
struct bnxt_irq *irq = bp->irq_tbl;
int rc = 0;
int bnxt_request_int(struct bnxt *bp)
{
- struct rte_intr_handle *intr_handle = &bp->pdev->intr_handle;
+ struct rte_intr_handle *intr_handle = bp->pdev->intr_handle;
struct bnxt_irq *irq = bp->irq_tbl;
int rc = 0;
PMD_INIT_FUNC_TRACE();
dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
- intr_handle = &dpaa_dev->intr_handle;
+ intr_handle = dpaa_dev->intr_handle;
__fif = container_of(fif, struct __fman_if, __if);
/* Rx offloads which are enabled by default */
}
/* if the interrupts were configured on this devices*/
- if (intr_handle && intr_handle->fd) {
+ if (intr_handle && rte_intr_fd_get(intr_handle)) {
if (dev->data->dev_conf.intr_conf.lsc != 0)
rte_intr_callback_register(intr_handle,
dpaa_interrupt_handler,
(void *)dev);
- ret = dpaa_intr_enable(__fif->node_name, intr_handle->fd);
+ ret = dpaa_intr_enable(__fif->node_name,
+ rte_intr_fd_get(intr_handle));
if (ret) {
if (dev->data->dev_conf.intr_conf.lsc != 0) {
rte_intr_callback_unregister(intr_handle,
int bytes_read;
dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
- intr_handle = &dpaa_dev->intr_handle;
+ intr_handle = dpaa_dev->intr_handle;
- bytes_read = read(intr_handle->fd, &buf, sizeof(uint64_t));
+ bytes_read = read(rte_intr_fd_get(intr_handle), &buf,
+ sizeof(uint64_t));
if (bytes_read < 0)
DPAA_PMD_ERR("Error reading eventfd\n");
dpaa_eth_link_update(dev, 0);
}
dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
- intr_handle = &dpaa_dev->intr_handle;
+ intr_handle = dpaa_dev->intr_handle;
__fif = container_of(fif, struct __fman_if, __if);
ret = dpaa_eth_dev_stop(dev);
if (link->link_status && !link->link_autoneg)
dpaa_restart_link_autoneg(__fif->node_name);
- if (intr_handle && intr_handle->fd &&
+ if (intr_handle && rte_intr_fd_get(intr_handle) &&
dev->data->dev_conf.intr_conf.lsc != 0) {
dpaa_intr_disable(__fif->node_name);
rte_intr_callback_unregister(intr_handle,
rxq->qp = qp;
/* Set up the device interrupt handler */
- if (!dev->intr_handle) {
+ if (dev->intr_handle == NULL) {
struct rte_dpaa_device *dpaa_dev;
struct rte_device *rdev = dev->device;
dpaa_dev = container_of(rdev, struct rte_dpaa_device,
device);
- dev->intr_handle = &dpaa_dev->intr_handle;
- dev->intr_handle->intr_vec = rte_zmalloc(NULL,
- dpaa_push_mode_max_queue, 0);
- if (!dev->intr_handle->intr_vec) {
+ dev->intr_handle = dpaa_dev->intr_handle;
+ if (rte_intr_vec_list_alloc(dev->intr_handle,
+ NULL, dpaa_push_mode_max_queue)) {
DPAA_PMD_ERR("intr_vec alloc failed");
return -ENOMEM;
}
- dev->intr_handle->nb_efd = dpaa_push_mode_max_queue;
- dev->intr_handle->max_intr = dpaa_push_mode_max_queue;
+ if (rte_intr_nb_efd_set(dev->intr_handle,
+ dpaa_push_mode_max_queue))
+ return -rte_errno;
+
+ if (rte_intr_max_intr_set(dev->intr_handle,
+ dpaa_push_mode_max_queue))
+ return -rte_errno;
}
- dev->intr_handle->type = RTE_INTR_HANDLE_EXT;
- dev->intr_handle->intr_vec[queue_idx] = queue_idx + 1;
- dev->intr_handle->efds[queue_idx] = q_fd;
+ if (rte_intr_type_set(dev->intr_handle, RTE_INTR_HANDLE_EXT))
+ return -rte_errno;
+
+ if (rte_intr_vec_list_index_set(dev->intr_handle,
+ queue_idx, queue_idx + 1))
+ return -rte_errno;
+
+ if (rte_intr_efds_index_set(dev->intr_handle, queue_idx,
+ q_fd))
+ return -rte_errno;
+
rxq->q_fd = q_fd;
}
rxq->bp_array = rte_dpaa_bpid_info;
struct rte_intr_handle *intr_handle;
dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
- intr_handle = &dpaa2_dev->intr_handle;
+ intr_handle = dpaa2_dev->intr_handle;
PMD_INIT_FUNC_TRACE();
}
/* if the interrupts were configured on this devices*/
- if (intr_handle && (intr_handle->fd) &&
- (dev->data->dev_conf.intr_conf.lsc != 0)) {
+ if (intr_handle && rte_intr_fd_get(intr_handle) &&
+ dev->data->dev_conf.intr_conf.lsc != 0) {
/* Registering LSC interrupt handler */
rte_intr_callback_register(intr_handle,
dpaa2_interrupt_handler,
PMD_INIT_FUNC_TRACE();
/* reset interrupt callback */
- if (intr_handle && (intr_handle->fd) &&
- (dev->data->dev_conf.intr_conf.lsc != 0)) {
+ if (intr_handle && rte_intr_fd_get(intr_handle) &&
+ dev->data->dev_conf.intr_conf.lsc != 0) {
/*disable dpni irqs */
dpaa2_eth_setup_irqs(dev, 0);
eth_em_dev_init(struct rte_eth_dev *eth_dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct e1000_adapter *adapter =
E1000_DEV_PRIVATE(eth_dev->data->dev_private);
struct e1000_hw *hw =
struct e1000_hw *hw =
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
int ret, mask;
uint32_t intr_vector = 0;
uint32_t *speeds;
}
if (rte_intr_dp_is_en(intr_handle)) {
- intr_handle->intr_vec =
- rte_zmalloc("intr_vec",
- dev->data->nb_rx_queues * sizeof(int), 0);
- if (intr_handle->intr_vec == NULL) {
+ if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
+ dev->data->nb_rx_queues)) {
PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
- " intr_vec", dev->data->nb_rx_queues);
+ " intr_vec", dev->data->nb_rx_queues);
return -ENOMEM;
}
struct rte_eth_link link;
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
dev->data->dev_started = 0;
/* Clean datapath event and queue/vec mapping */
rte_intr_efd_disable(intr_handle);
- if (intr_handle->intr_vec != NULL) {
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
- }
+ rte_intr_vec_list_free(intr_handle);
return 0;
}
struct e1000_adapter *adapter =
E1000_DEV_PRIVATE(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
int ret;
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
{
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
em_rxq_intr_enable(hw);
rte_intr_ack(intr_handle);
struct e1000_hw *hw =
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
if (rte_intr_allow_others(intr_handle) &&
dev->data->dev_conf.intr_conf.lsc != 0) {
struct e1000_hw *hw =
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
if (rte_intr_allow_others(intr_handle) &&
dev->data->dev_conf.intr_conf.lsc != 0) {
eth_dev->data->port_id, pci_dev->id.vendor_id,
pci_dev->id.device_id);
- rte_intr_callback_register(&pci_dev->intr_handle,
+ rte_intr_callback_register(pci_dev->intr_handle,
eth_igb_interrupt_handler,
(void *)eth_dev);
/* enable uio/vfio intr/eventfd mapping */
- rte_intr_enable(&pci_dev->intr_handle);
+ rte_intr_enable(pci_dev->intr_handle);
/* enable support intr */
igb_intr_enable(eth_dev);
eth_dev->data->port_id, pci_dev->id.vendor_id,
pci_dev->id.device_id, "igb_mac_82576_vf");
- intr_handle = &pci_dev->intr_handle;
+ intr_handle = pci_dev->intr_handle;
rte_intr_callback_register(intr_handle,
eth_igbvf_interrupt_handler, eth_dev);
struct e1000_adapter *adapter =
E1000_DEV_PRIVATE(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
int ret, mask;
uint32_t intr_vector = 0;
uint32_t ctrl_ext;
return -1;
}
- if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
- intr_handle->intr_vec =
- rte_zmalloc("intr_vec",
- dev->data->nb_rx_queues * sizeof(int), 0);
- if (intr_handle->intr_vec == NULL) {
+ /* Allocate the vector list */
+ if (rte_intr_dp_is_en(intr_handle)) {
+ if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
+ dev->data->nb_rx_queues)) {
PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
" intr_vec", dev->data->nb_rx_queues);
return -ENOMEM;
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
struct rte_eth_link link;
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct e1000_adapter *adapter =
E1000_DEV_PRIVATE(dev->data->dev_private);
/* Clean datapath event and queue/vec mapping */
rte_intr_efd_disable(intr_handle);
- if (intr_handle->intr_vec != NULL) {
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
- }
+ rte_intr_vec_list_free(intr_handle);
adapter->stopped = true;
dev->data->dev_started = 0;
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_eth_link link;
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct e1000_filter_info *filter_info =
E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
int ret;
igb_dev_free_queues(dev);
- if (intr_handle->intr_vec) {
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
- }
+ /* Cleanup vector list */
+ rte_intr_vec_list_free(intr_handle);
memset(&link, 0, sizeof(link));
rte_eth_linkstatus_set(dev, &link);
struct e1000_hw *hw =
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
struct rte_eth_dev_info dev_info;
struct e1000_adapter *adapter =
E1000_DEV_PRIVATE(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
int ret;
uint32_t intr_vector = 0;
return ret;
}
- if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
- intr_handle->intr_vec =
- rte_zmalloc("intr_vec",
- dev->data->nb_rx_queues * sizeof(int), 0);
- if (!intr_handle->intr_vec) {
+ /* Allocate the vector list */
+ if (rte_intr_dp_is_en(intr_handle)) {
+ if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
+ dev->data->nb_rx_queues)) {
PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
" intr_vec", dev->data->nb_rx_queues);
return -ENOMEM;
igbvf_dev_stop(struct rte_eth_dev *dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct e1000_adapter *adapter =
E1000_DEV_PRIVATE(dev->data->dev_private);
/* Clean datapath event and queue/vec mapping */
rte_intr_efd_disable(intr_handle);
- if (intr_handle->intr_vec) {
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
- }
+
+ /* Clean vector list */
+ rte_intr_vec_list_free(intr_handle);
adapter->stopped = true;
dev->data->dev_started = 0;
memset(&addr, 0, sizeof(addr));
igbvf_default_mac_addr_set(dev, &addr);
- rte_intr_callback_unregister(&pci_dev->intr_handle,
+ rte_intr_callback_unregister(pci_dev->intr_handle,
eth_igbvf_interrupt_handler,
(void *)dev);
struct e1000_hw *hw =
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
uint32_t vec = E1000_MISC_VEC_ID;
if (rte_intr_allow_others(intr_handle))
struct e1000_hw *hw =
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
uint32_t vec = E1000_MISC_VEC_ID;
if (rte_intr_allow_others(intr_handle))
uint32_t base = E1000_MISC_VEC_ID;
uint32_t misc_shift = 0;
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
/* won't configure msix register if no mapping is done
* between intr vector and event fd
E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
E1000_GPIE_PBA | E1000_GPIE_EIAME |
E1000_GPIE_NSICR);
- intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
- misc_shift;
+ intr_mask =
+ RTE_LEN2MASK(rte_intr_nb_efd_get(intr_handle),
+ uint32_t) << misc_shift;
if (dev->data->dev_conf.intr_conf.lsc != 0)
intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
/* use EIAM to auto-mask when MSI-X interrupt
* is asserted, this saves a register write for every interrupt
*/
- intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
- misc_shift;
+ intr_mask = RTE_LEN2MASK(rte_intr_nb_efd_get(intr_handle),
+ uint32_t) << misc_shift;
if (dev->data->dev_conf.intr_conf.lsc != 0)
intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
- intr_handle->intr_vec[queue_id] = vec;
- if (vec < base + intr_handle->nb_efd - 1)
+ rte_intr_vec_list_index_set(intr_handle, queue_id, vec);
+ if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1)
vec++;
}
static int ena_close(struct rte_eth_dev *dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct ena_adapter *adapter = dev->data->dev_private;
int ret = 0;
struct ena_adapter *adapter = dev->data->dev_private;
struct ena_com_dev *ena_dev = &adapter->ena_dev;
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
int rc;
/* Cannot free memory in secondary process */
rte_intr_disable(intr_handle);
rte_intr_efd_disable(intr_handle);
- if (intr_handle->intr_vec != NULL) {
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
- }
+
+ /* Cleanup vector list */
+ rte_intr_vec_list_free(intr_handle);
rte_intr_enable(intr_handle);
struct ena_adapter *adapter = ring->adapter;
struct ena_com_dev *ena_dev = &adapter->ena_dev;
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct ena_com_create_io_ctx ctx =
/* policy set to _HOST just to satisfy icc compiler */
{ ENA_ADMIN_PLACEMENT_POLICY_HOST,
ena_qid = ENA_IO_RXQ_IDX(ring->id);
ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
if (rte_intr_dp_is_en(intr_handle))
- ctx.msix_vector = intr_handle->intr_vec[ring->id];
+ ctx.msix_vector =
+ rte_intr_vec_list_index_get(intr_handle,
+ ring->id);
+
for (i = 0; i < ring->ring_size; i++)
ring->empty_rx_reqs[i] = i;
}
pci_dev->addr.devid,
pci_dev->addr.function);
- intr_handle = &pci_dev->intr_handle;
+ intr_handle = pci_dev->intr_handle;
adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
static int ena_setup_rx_intr(struct rte_eth_dev *dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
int rc;
uint16_t vectors_nb, i;
bool rx_intr_requested = dev->data->dev_conf.intr_conf.rxq;
goto enable_intr;
}
- intr_handle->intr_vec = rte_zmalloc("intr_vec",
- dev->data->nb_rx_queues * sizeof(*intr_handle->intr_vec), 0);
- if (intr_handle->intr_vec == NULL) {
+ /* Allocate the vector list */
+ if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
+ dev->data->nb_rx_queues)) {
PMD_DRV_LOG(ERR,
"Failed to allocate interrupt vector for %d queues\n",
dev->data->nb_rx_queues);
}
for (i = 0; i < vectors_nb; ++i)
- intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + i;
+ if (rte_intr_vec_list_index_set(intr_handle, i,
+ RTE_INTR_VEC_RXTX_OFFSET + i))
+ goto disable_intr_efd;
rte_intr_enable(intr_handle);
return 0;
disable_intr_efd:
rte_intr_efd_disable(intr_handle);
free_intr_vec:
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
+ rte_intr_vec_list_free(intr_handle);
enable_intr:
rte_intr_enable(intr_handle);
return rc;
rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
enic_log_q_error(enic);
/* Re-enable irq in case of INTx */
- rte_intr_ack(&enic->pdev->intr_handle);
+ rte_intr_ack(enic->pdev->intr_handle);
}
static int enic_rxq_intr_init(struct enic *enic)
" interrupts\n");
return err;
}
- intr_handle->intr_vec = rte_zmalloc("enic_intr_vec",
- rxq_intr_count * sizeof(int), 0);
- if (intr_handle->intr_vec == NULL) {
+
+ if (rte_intr_vec_list_alloc(intr_handle, "enic_intr_vec",
+ rxq_intr_count)) {
dev_err(enic, "Failed to allocate intr_vec\n");
return -ENOMEM;
}
for (i = 0; i < rxq_intr_count; i++)
- intr_handle->intr_vec[i] = i + ENICPMD_RXQ_INTR_OFFSET;
+ if (rte_intr_vec_list_index_set(intr_handle, i,
+ i + ENICPMD_RXQ_INTR_OFFSET))
+ return -rte_errno;
return 0;
}
intr_handle = enic->rte_dev->intr_handle;
rte_intr_efd_disable(intr_handle);
- if (intr_handle->intr_vec != NULL) {
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
- }
+
+ rte_intr_vec_list_free(intr_handle);
}
static void enic_prep_wq_for_simple_tx(struct enic *enic, uint16_t queue_idx)
vnic_dev_enable_wait(enic->vdev);
/* Register and enable error interrupt */
- rte_intr_callback_register(&(enic->pdev->intr_handle),
+ rte_intr_callback_register(enic->pdev->intr_handle,
enic_intr_handler, (void *)enic->rte_dev);
- rte_intr_enable(&(enic->pdev->intr_handle));
+ rte_intr_enable(enic->pdev->intr_handle);
/* Unmask LSC interrupt */
vnic_intr_unmask(&enic->intr[ENICPMD_LSC_INTR_OFFSET]);
(void)vnic_intr_masked(&enic->intr[i]); /* flush write */
}
enic_rxq_intr_deinit(enic);
- rte_intr_disable(&enic->pdev->intr_handle);
- rte_intr_callback_unregister(&enic->pdev->intr_handle,
+ rte_intr_disable(enic->pdev->intr_handle);
+ rte_intr_callback_unregister(enic->pdev->intr_handle,
enic_intr_handler,
(void *)enic->rte_dev);
RTE_ETHER_ADDR_BYTES(mac));
dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC |
RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
- PRIV(dev)->intr_handle = (struct rte_intr_handle){
- .fd = -1,
- .type = RTE_INTR_HANDLE_EXT,
- };
+
+ /* Allocate interrupt instance */
+ PRIV(dev)->intr_handle =
+ rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED);
+ if (PRIV(dev)->intr_handle == NULL) {
+ ERROR("Failed to allocate intr handle");
+ goto cancel_alarm;
+ }
+
+ if (rte_intr_fd_set(PRIV(dev)->intr_handle, -1))
+ goto cancel_alarm;
+
+ if (rte_intr_type_set(PRIV(dev)->intr_handle, RTE_INTR_HANDLE_EXT))
+ goto cancel_alarm;
+
rte_eth_dev_probing_finish(dev);
+
return 0;
cancel_alarm:
failsafe_hotplug_alarm_cancel(dev);
return 0; /* port already released */
ret = failsafe_eth_dev_close(dev);
rte_eth_dev_release_port(dev);
+ rte_intr_instance_free(PRIV(dev)->intr_handle);
return ret;
}
{
struct rte_intr_handle *intr_handle;
- intr_handle = &priv->intr_handle;
- if (intr_handle->intr_vec != NULL) {
- free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
- }
- intr_handle->nb_efd = 0;
+ intr_handle = priv->intr_handle;
+ rte_intr_vec_list_free(intr_handle);
+
+ rte_intr_nb_efd_set(intr_handle, 0);
}
/**
rxqs_n = priv->data->nb_rx_queues;
n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
count = 0;
- intr_handle = &priv->intr_handle;
- RTE_ASSERT(intr_handle->intr_vec == NULL);
+ intr_handle = priv->intr_handle;
/* Allocate the interrupt vector of the failsafe Rx proxy interrupts */
- intr_handle->intr_vec = malloc(n * sizeof(intr_handle->intr_vec[0]));
- if (intr_handle->intr_vec == NULL) {
+ if (rte_intr_vec_list_alloc(intr_handle, NULL, n)) {
fs_rx_intr_vec_uninstall(priv);
rte_errno = ENOMEM;
ERROR("Failed to allocate memory for interrupt vector,"
/* Skip queues that cannot request interrupts. */
if (rxq == NULL || rxq->event_fd < 0) {
/* Use invalid intr_vec[] index to disable entry. */
- intr_handle->intr_vec[i] =
- RTE_INTR_VEC_RXTX_OFFSET +
- RTE_MAX_RXTX_INTR_VEC_ID;
+ if (rte_intr_vec_list_index_set(intr_handle, i,
+ RTE_INTR_VEC_RXTX_OFFSET + RTE_MAX_RXTX_INTR_VEC_ID))
+ return -rte_errno;
continue;
}
if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
fs_rx_intr_vec_uninstall(priv);
return -rte_errno;
}
- intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
- intr_handle->efds[count] = rxq->event_fd;
+ if (rte_intr_vec_list_index_set(intr_handle, i,
+ RTE_INTR_VEC_RXTX_OFFSET + count))
+ return -rte_errno;
+
+ if (rte_intr_efds_index_set(intr_handle, count,
+ rxq->event_fd))
+ return -rte_errno;
count++;
}
if (count == 0) {
fs_rx_intr_vec_uninstall(priv);
} else {
- intr_handle->nb_efd = count;
- intr_handle->efd_counter_size = sizeof(uint64_t);
+ if (rte_intr_nb_efd_set(intr_handle, count))
+ return -rte_errno;
+
+ if (rte_intr_efd_counter_size_set(intr_handle,
+ sizeof(uint64_t)))
+ return -rte_errno;
}
return 0;
}
struct rte_intr_handle *intr_handle;
priv = PRIV(dev);
- intr_handle = &priv->intr_handle;
+ intr_handle = priv->intr_handle;
rte_intr_free_epoll_fd(intr_handle);
fs_rx_event_proxy_uninstall(priv);
fs_rx_intr_vec_uninstall(priv);
fs_rx_intr_vec_uninstall(priv);
return -rte_errno;
}
- dev->intr_handle = &priv->intr_handle;
+ dev->intr_handle = priv->intr_handle;
return 0;
}
* For the time being, fake as if we are using MSIX interrupts,
* this will cause rte_intr_efd_enable to allocate an eventfd for us.
*/
- struct rte_intr_handle intr_handle = {
- .type = RTE_INTR_HANDLE_VFIO_MSIX,
- .efds = { -1, },
- };
+ struct rte_intr_handle *intr_handle;
struct sub_device *sdev;
struct rxq *rxq;
uint8_t i;
int ret;
+ intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_PRIVATE);
+ if (intr_handle == NULL)
+ return -ENOMEM;
+
+ if (rte_intr_type_set(intr_handle, RTE_INTR_HANDLE_VFIO_MSIX))
+ return -rte_errno;
+
+ if (rte_intr_efds_index_set(intr_handle, 0, -1))
+ return -rte_errno;
+
fs_lock(dev, 0);
if (rx_conf->rx_deferred_start) {
FOREACH_SUBDEV_STATE(sdev, i, dev, DEV_PROBED) {
rxq->info.nb_desc = nb_rx_desc;
rxq->priv = PRIV(dev);
rxq->sdev = PRIV(dev)->subs;
- ret = rte_intr_efd_enable(&intr_handle, 1);
+ ret = rte_intr_efd_enable(intr_handle, 1);
if (ret < 0) {
fs_unlock(dev, 0);
return ret;
}
- rxq->event_fd = intr_handle.efds[0];
+ rxq->event_fd = rte_intr_efds_index_get(intr_handle, 0);
dev->data->rx_queues[rx_queue_id] = rxq;
FOREACH_SUBDEV_STATE(sdev, i, dev, DEV_ACTIVE) {
ret = rte_eth_rx_queue_setup(PORT_ID(sdev),
struct rte_ether_addr *mcast_addrs;
/* current capabilities */
struct rte_eth_dev_owner my_owner; /* Unique owner. */
- struct rte_intr_handle intr_handle; /* Port interrupt handle. */
+ struct rte_intr_handle *intr_handle; /* Port interrupt handle. */
/*
* Fail-safe state machine.
* This level will be tracking state of the EAL and eth
#define BIT_MASK_PER_UINT32 ((1 << CHARS_PER_UINT32) - 1)
/* default 1:1 map from queue ID to interrupt vector ID */
-#define Q2V(pci_dev, queue_id) ((pci_dev)->intr_handle.intr_vec[queue_id])
+#define Q2V(pci_dev, queue_id) \
+ (rte_intr_vec_list_index_get((pci_dev)->intr_handle, queue_id))
/* First 64 Logical ports for PF/VMDQ, second 64 for Flow director */
#define MAX_LPORT_NUM 128
struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct fm10k_macvlan_filter_info *macvlan;
struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pdev->intr_handle;
+ struct rte_intr_handle *intr_handle = pdev->intr_handle;
int i, ret;
struct fm10k_rx_queue *rxq;
uint64_t base_addr;
{
struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pdev->intr_handle;
+ struct rte_intr_handle *intr_handle = pdev->intr_handle;
int i;
PMD_INIT_FUNC_TRACE();
}
/* Clean datapath event and queue/vec mapping */
rte_intr_efd_disable(intr_handle);
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
+ rte_intr_vec_list_free(intr_handle);
return 0;
}
else
FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, queue_id)),
FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
- rte_intr_ack(&pdev->intr_handle);
+ rte_intr_ack(pdev->intr_handle);
return 0;
}
{
struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pdev->intr_handle;
+ struct rte_intr_handle *intr_handle = pdev->intr_handle;
uint32_t intr_vector, vec;
uint16_t queue_id;
int result = 0;
}
if (rte_intr_dp_is_en(intr_handle) && !result) {
- intr_handle->intr_vec = rte_zmalloc("intr_vec",
- dev->data->nb_rx_queues * sizeof(int), 0);
- if (intr_handle->intr_vec) {
+ if (!rte_intr_vec_list_alloc(intr_handle, "intr_vec",
+ dev->data->nb_rx_queues)) {
for (queue_id = 0, vec = FM10K_RX_VEC_START;
queue_id < dev->data->nb_rx_queues;
queue_id++) {
- intr_handle->intr_vec[queue_id] = vec;
- if (vec < intr_handle->nb_efd - 1
- + FM10K_RX_VEC_START)
+ rte_intr_vec_list_index_set(intr_handle,
+ queue_id, vec);
+ int nb_efd =
+ rte_intr_nb_efd_get(intr_handle);
+ if (vec < (uint32_t)nb_efd - 1 +
+ FM10K_RX_VEC_START)
vec++;
}
} else {
{
struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pdev->intr_handle;
+ struct rte_intr_handle *intr_handle = pdev->intr_handle;
int ret;
PMD_INIT_FUNC_TRACE();
{
struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pdev->intr_handle;
+ struct rte_intr_handle *intr_handle = pdev->intr_handle;
int diag, i;
struct fm10k_macvlan_filter_info *macvlan;
hinic_set_msix_state(nic_dev->hwdev, 0, HINIC_MSIX_DISABLE);
/* disable rte interrupt */
- ret = rte_intr_disable(&pci_dev->intr_handle);
+ ret = rte_intr_disable(pci_dev->intr_handle);
if (ret)
PMD_DRV_LOG(ERR, "Disable intr failed: %d", ret);
do {
ret =
- rte_intr_callback_unregister(&pci_dev->intr_handle,
+ rte_intr_callback_unregister(pci_dev->intr_handle,
hinic_dev_interrupt_handler, dev);
if (ret >= 0) {
break;
}
/* register callback func to eal lib */
- rc = rte_intr_callback_register(&pci_dev->intr_handle,
+ rc = rte_intr_callback_register(pci_dev->intr_handle,
hinic_dev_interrupt_handler,
(void *)eth_dev);
if (rc) {
}
/* enable uio/vfio intr/eventfd mapping */
- rc = rte_intr_enable(&pci_dev->intr_handle);
+ rc = rte_intr_enable(pci_dev->intr_handle);
if (rc) {
PMD_DRV_LOG(ERR, "Enable rte interrupt failed, dev_name: %s",
eth_dev->data->name);
return 0;
enable_intr_fail:
- (void)rte_intr_callback_unregister(&pci_dev->intr_handle,
+ (void)rte_intr_callback_unregister(pci_dev->intr_handle,
hinic_dev_interrupt_handler,
(void *)eth_dev);
hns3_config_all_msix_error(hw, true);
- ret = rte_intr_callback_register(&pci_dev->intr_handle,
+ ret = rte_intr_callback_register(pci_dev->intr_handle,
hns3_interrupt_handler,
eth_dev);
if (ret) {
goto err_get_config;
/* Enable interrupt */
- rte_intr_enable(&pci_dev->intr_handle);
+ rte_intr_enable(pci_dev->intr_handle);
hns3_pf_enable_irq0(hw);
/* Get configuration */
hns3_tqp_stats_uninit(hw);
err_get_config:
hns3_pf_disable_irq0(hw);
- rte_intr_disable(&pci_dev->intr_handle);
- hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
+ rte_intr_disable(pci_dev->intr_handle);
+ hns3_intr_unregister(pci_dev->intr_handle, hns3_interrupt_handler,
eth_dev);
err_intr_callback_register:
err_cmd_init:
hns3_tqp_stats_uninit(hw);
hns3_config_mac_tnl_int(hw, false);
hns3_pf_disable_irq0(hw);
- rte_intr_disable(&pci_dev->intr_handle);
- hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
+ rte_intr_disable(pci_dev->intr_handle);
+ hns3_intr_unregister(pci_dev->intr_handle, hns3_interrupt_handler,
eth_dev);
hns3_config_all_msix_error(hw, false);
hns3_cmd_uninit(hw);
hns3_map_rx_interrupt(struct rte_eth_dev *dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
if (rte_intr_efd_enable(intr_handle, intr_vector))
return -EINVAL;
- if (intr_handle->intr_vec == NULL) {
- intr_handle->intr_vec =
- rte_zmalloc("intr_vec",
- hw->used_rx_queues * sizeof(int), 0);
- if (intr_handle->intr_vec == NULL) {
- hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
- hw->used_rx_queues);
- ret = -ENOMEM;
- goto alloc_intr_vec_error;
- }
+ /* Allocate vector list */
+ if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
+ hw->used_rx_queues)) {
+ hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
+ hw->used_rx_queues);
+ ret = -ENOMEM;
+ goto alloc_intr_vec_error;
}
if (rte_intr_allow_others(intr_handle)) {
HNS3_RING_TYPE_RX, q_id);
if (ret)
goto bind_vector_error;
- intr_handle->intr_vec[q_id] = vec;
+
+ if (rte_intr_vec_list_index_set(intr_handle, q_id, vec))
+ goto bind_vector_error;
/*
* If there are not enough efds (e.g. not enough interrupt),
* remaining queues will be bond to the last interrupt.
*/
- if (vec < base + intr_handle->nb_efd - 1)
+ if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1)
vec++;
}
rte_intr_enable(intr_handle);
return 0;
bind_vector_error:
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
+ rte_intr_vec_list_free(intr_handle);
alloc_intr_vec_error:
rte_intr_efd_disable(intr_handle);
return ret;
{
struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
uint16_t q_id;
int ret;
if (rte_intr_dp_is_en(intr_handle)) {
for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
ret = hns3_bind_ring_with_vector(hw,
- intr_handle->intr_vec[q_id], true,
- HNS3_RING_TYPE_RX, q_id);
+ rte_intr_vec_list_index_get(intr_handle,
+ q_id),
+ true, HNS3_RING_TYPE_RX, q_id);
if (ret)
return ret;
}
hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
(void)hns3_bind_ring_with_vector(hw, vec, false,
HNS3_RING_TYPE_RX,
q_id);
- if (vec < base + intr_handle->nb_efd - 1)
+ if (vec < base + rte_intr_nb_efd_get(intr_handle)
+ - 1)
vec++;
}
}
/* Clean datapath event and queue/vec mapping */
rte_intr_efd_disable(intr_handle);
- if (intr_handle->intr_vec) {
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
- }
+ rte_intr_vec_list_free(intr_handle);
}
static int
hns3vf_clear_event_cause(hw, 0);
- ret = rte_intr_callback_register(&pci_dev->intr_handle,
+ ret = rte_intr_callback_register(pci_dev->intr_handle,
hns3vf_interrupt_handler, eth_dev);
if (ret) {
PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
}
/* Enable interrupt */
- rte_intr_enable(&pci_dev->intr_handle);
+ rte_intr_enable(pci_dev->intr_handle);
hns3vf_enable_irq0(hw);
/* Get configuration from PF */
err_get_config:
hns3vf_disable_irq0(hw);
- rte_intr_disable(&pci_dev->intr_handle);
- hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
+ rte_intr_disable(pci_dev->intr_handle);
+ hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
eth_dev);
err_intr_callback_register:
err_cmd_init:
hns3_flow_uninit(eth_dev);
hns3_tqp_stats_uninit(hw);
hns3vf_disable_irq0(hw);
- rte_intr_disable(&pci_dev->intr_handle);
- hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
+ rte_intr_disable(pci_dev->intr_handle);
+ hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
eth_dev);
hns3_cmd_uninit(hw);
hns3_cmd_destroy_queue(hw);
{
struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
uint16_t q_id;
(void)hns3vf_bind_ring_with_vector(hw, vec, false,
HNS3_RING_TYPE_RX,
q_id);
- if (vec < base + intr_handle->nb_efd - 1)
+ if (vec < base + rte_intr_nb_efd_get(intr_handle)
+ - 1)
vec++;
}
}
/* Clean datapath event and queue/vec mapping */
rte_intr_efd_disable(intr_handle);
- if (intr_handle->intr_vec) {
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
- }
+
+ /* Cleanup vector list */
+ rte_intr_vec_list_free(intr_handle);
}
static int
hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
if (rte_intr_efd_enable(intr_handle, intr_vector))
return -EINVAL;
- if (intr_handle->intr_vec == NULL) {
- intr_handle->intr_vec =
- rte_zmalloc("intr_vec",
- hw->used_rx_queues * sizeof(int), 0);
- if (intr_handle->intr_vec == NULL) {
- hns3_err(hw, "Failed to allocate %u rx_queues"
- " intr_vec", hw->used_rx_queues);
- ret = -ENOMEM;
- goto vf_alloc_intr_vec_error;
- }
+ /* Allocate vector list */
+ if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
+ hw->used_rx_queues)) {
+ hns3_err(hw, "Failed to allocate %u rx_queues"
+ " intr_vec", hw->used_rx_queues);
+ ret = -ENOMEM;
+ goto vf_alloc_intr_vec_error;
}
if (rte_intr_allow_others(intr_handle)) {
HNS3_RING_TYPE_RX, q_id);
if (ret)
goto vf_bind_vector_error;
- intr_handle->intr_vec[q_id] = vec;
+
+ if (rte_intr_vec_list_index_set(intr_handle, q_id, vec))
+ goto vf_bind_vector_error;
+
/*
* If there are not enough efds (e.g. not enough interrupt),
* remaining queues will be bond to the last interrupt.
*/
- if (vec < base + intr_handle->nb_efd - 1)
+ if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1)
vec++;
}
rte_intr_enable(intr_handle);
return 0;
vf_bind_vector_error:
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
+ rte_intr_vec_list_free(intr_handle);
vf_alloc_intr_vec_error:
rte_intr_efd_disable(intr_handle);
return ret;
{
struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
uint16_t q_id;
int ret;
if (rte_intr_dp_is_en(intr_handle)) {
for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
ret = hns3vf_bind_ring_with_vector(hw,
- intr_handle->intr_vec[q_id], true,
- HNS3_RING_TYPE_RX, q_id);
+ rte_intr_vec_list_index_get(intr_handle,
+ q_id),
+ true, HNS3_RING_TYPE_RX, q_id);
if (ret)
return ret;
}
int ret;
if (hw->reset.level == HNS3_VF_FULL_RESET) {
- rte_intr_disable(&pci_dev->intr_handle);
+ rte_intr_disable(pci_dev->intr_handle);
ret = hns3vf_set_bus_master(pci_dev, true);
if (ret < 0) {
hns3_err(hw, "failed to set pci bus, ret = %d", ret);
hns3_err(hw, "Failed to enable msix");
}
- rte_intr_enable(&pci_dev->intr_handle);
+ rte_intr_enable(pci_dev->intr_handle);
}
ret = hns3_reset_all_tqps(hns);
hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
if (dev->data->dev_conf.intr_conf.rxq == 0)
}
i40e_set_default_ptype_table(dev);
pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- intr_handle = &pci_dev->intr_handle;
+ intr_handle = pci_dev->intr_handle;
rte_eth_copy_pci_info(dev, pci_dev);
{
struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
uint16_t msix_vect = vsi->msix_intr;
uint16_t i;
{
struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
uint16_t msix_vect = vsi->msix_intr;
- uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
+ uint16_t nb_msix = RTE_MIN(vsi->nb_msix,
+ rte_intr_nb_efd_get(intr_handle));
uint16_t queue_idx = 0;
int record = 0;
int i;
vsi->nb_used_qps - i,
itr_idx);
for (; !!record && i < vsi->nb_used_qps; i++)
- intr_handle->intr_vec[queue_idx + i] =
- msix_vect;
+ rte_intr_vec_list_index_set(intr_handle,
+ queue_idx + i, msix_vect);
break;
}
/* 1:1 queue/msix_vect mapping */
vsi->base_queue + i, 1,
itr_idx);
if (!!record)
- intr_handle->intr_vec[queue_idx + i] = msix_vect;
+ if (rte_intr_vec_list_index_set(intr_handle,
+ queue_idx + i, msix_vect))
+ return -rte_errno;
msix_vect++;
nb_msix--;
{
struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
uint16_t msix_intr, i;
{
struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
uint16_t msix_intr, i;
struct i40e_vsi *main_vsi = pf->main_vsi;
int ret, i;
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
uint32_t intr_vector = 0;
struct i40e_vsi *vsi;
uint16_t nb_rxq, nb_txq;
return ret;
}
- if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
- intr_handle->intr_vec =
- rte_zmalloc("intr_vec",
- dev->data->nb_rx_queues * sizeof(int),
- 0);
- if (!intr_handle->intr_vec) {
+ if (rte_intr_dp_is_en(intr_handle)) {
+ if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
+ dev->data->nb_rx_queues)) {
PMD_INIT_LOG(ERR,
"Failed to allocate %d rx_queues intr_vec",
dev->data->nb_rx_queues);
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct i40e_vsi *main_vsi = pf->main_vsi;
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
int i;
if (hw->adapter_stopped == 1)
/* Clean datapath event and queue/vec mapping */
rte_intr_efd_disable(intr_handle);
- if (intr_handle->intr_vec) {
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
- }
+
+ /* Cleanup vector list */
+ rte_intr_vec_list_free(intr_handle);
/* reset hierarchy commit */
pf->tm_conf.committed = false;
struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct i40e_filter_control_settings settings;
struct rte_flow *p_flow;
uint32_t reg;
i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
uint16_t msix_intr;
- msix_intr = intr_handle->intr_vec[queue_id];
+ msix_intr = rte_intr_vec_list_index_get(intr_handle, queue_id);
if (msix_intr == I40E_MISC_VEC_ID)
I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
I40E_PFINT_DYN_CTL0_INTENA_MASK |
I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
I40E_WRITE_FLUSH(hw);
- rte_intr_ack(&pci_dev->intr_handle);
+ rte_intr_ack(pci_dev->intr_handle);
return 0;
}
i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
uint16_t msix_intr;
- msix_intr = intr_handle->intr_vec[queue_id];
+ msix_intr = rte_intr_vec_list_index_get(intr_handle, queue_id);
if (msix_intr == I40E_MISC_VEC_ID)
I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
return -1;
}
- if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
- intr_handle->intr_vec =
- rte_zmalloc("intr_vec",
- dev->data->nb_rx_queues * sizeof(int), 0);
- if (!intr_handle->intr_vec) {
+ if (rte_intr_dp_is_en(intr_handle)) {
+ if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
+ dev->data->nb_rx_queues)) {
PMD_DRV_LOG(ERR, "Failed to allocate %d rx intr_vec",
dev->data->nb_rx_queues);
return -1;
}
}
+
qv_map = rte_zmalloc("qv_map",
dev->data->nb_rx_queues * sizeof(struct iavf_qv_map), 0);
if (!qv_map) {
for (i = 0; i < dev->data->nb_rx_queues; i++) {
qv_map[i].queue_id = i;
qv_map[i].vector_id = vf->msix_base;
- intr_handle->intr_vec[i] = IAVF_MISC_VEC_ID;
+ rte_intr_vec_list_index_set(intr_handle,
+ i, IAVF_MISC_VEC_ID);
}
vf->qv_map = qv_map;
PMD_DRV_LOG(DEBUG,
/* If Rx interrupt is reuquired, and we can use
* multi interrupts, then the vec is from 1
*/
- vf->nb_msix = RTE_MIN(intr_handle->nb_efd,
- (uint16_t)(vf->vf_res->max_vectors - 1));
+ vf->nb_msix =
+ RTE_MIN(rte_intr_nb_efd_get(intr_handle),
+ (uint16_t)(vf->vf_res->max_vectors - 1));
vf->msix_base = IAVF_RX_VEC_START;
vec = IAVF_RX_VEC_START;
for (i = 0; i < dev->data->nb_rx_queues; i++) {
qv_map[i].queue_id = i;
qv_map[i].vector_id = vec;
- intr_handle->intr_vec[i] = vec++;
+ rte_intr_vec_list_index_set(intr_handle,
+ i, vec++);
if (vec >= vf->nb_msix + IAVF_RX_VEC_START)
vec = IAVF_RX_VEC_START;
}
vf->qv_map = NULL;
qv_map_alloc_err:
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
+ rte_intr_vec_list_free(intr_handle);
return -1;
}
/* Disable the interrupt for Rx */
rte_intr_efd_disable(intr_handle);
/* Rx interrupt vector mapping free */
- if (intr_handle->intr_vec) {
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
- }
+ rte_intr_vec_list_free(intr_handle);
/* remove all mac addrs */
iavf_add_del_all_mac_addr(adapter, false);
struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(adapter);
uint16_t msix_intr;
- msix_intr = pci_dev->intr_handle.intr_vec[queue_id];
+ msix_intr = rte_intr_vec_list_index_get(pci_dev->intr_handle,
+ queue_id);
if (msix_intr == IAVF_MISC_VEC_ID) {
PMD_DRV_LOG(INFO, "MISC is also enabled for control");
IAVF_WRITE_REG(hw, IAVF_VFINT_DYN_CTL01,
IAVF_WRITE_FLUSH(hw);
if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_WB_ON_ITR)
- rte_intr_ack(&pci_dev->intr_handle);
+ rte_intr_ack(pci_dev->intr_handle);
return 0;
}
struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
uint16_t msix_intr;
- msix_intr = pci_dev->intr_handle.intr_vec[queue_id];
+ msix_intr = rte_intr_vec_list_index_get(pci_dev->intr_handle,
+ queue_id);
if (msix_intr == IAVF_MISC_VEC_ID) {
PMD_DRV_LOG(ERR, "MISC is used for control, cannot disable it");
return -EIO;
if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_WB_ON_ITR) {
/* register callback func to eal lib */
- rte_intr_callback_register(&pci_dev->intr_handle,
+ rte_intr_callback_register(pci_dev->intr_handle,
iavf_dev_interrupt_handler,
(void *)eth_dev);
/* enable uio intr after callback register */
- rte_intr_enable(&pci_dev->intr_handle);
+ rte_intr_enable(pci_dev->intr_handle);
} else {
rte_eal_alarm_set(IAVF_ALARM_INTERVAL,
iavf_dev_alarm_handler, eth_dev);
{
struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct iavf_adapter *adapter =
IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
/* disable interrupt to avoid the admin queue message to be read
* before iavf_read_msg_from_pf.
*/
- rte_intr_disable(&pci_dev->intr_handle);
+ rte_intr_disable(pci_dev->intr_handle);
err = iavf_execute_vf_cmd(adapter, &args);
- rte_intr_enable(&pci_dev->intr_handle);
+ rte_intr_enable(pci_dev->intr_handle);
} else {
rte_eal_alarm_cancel(iavf_dev_alarm_handler, dev);
err = iavf_execute_vf_cmd(adapter, &args);
rte_spinlock_lock(&hw->vc_cmd_send_lock);
- rte_intr_disable(&pci_dev->intr_handle);
+ rte_intr_disable(pci_dev->intr_handle);
ice_dcf_disable_irq0(hw);
for (;;) {
rte_delay_ms(ICE_DCF_ARQ_CHECK_TIME);
}
- rte_intr_enable(&pci_dev->intr_handle);
+ rte_intr_enable(pci_dev->intr_handle);
ice_dcf_enable_irq0(hw);
rte_spinlock_unlock(&hw->vc_cmd_send_lock);
}
hw->eth_dev = eth_dev;
- rte_intr_callback_register(&pci_dev->intr_handle,
+ rte_intr_callback_register(pci_dev->intr_handle,
ice_dcf_dev_interrupt_handler, hw);
- rte_intr_enable(&pci_dev->intr_handle);
+ rte_intr_enable(pci_dev->intr_handle);
ice_dcf_enable_irq0(hw);
return 0;
ice_dcf_uninit_hw(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
if (hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS)
if (hw->tm_conf.committed) {
return -1;
}
- if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
- intr_handle->intr_vec =
- rte_zmalloc("intr_vec",
- dev->data->nb_rx_queues * sizeof(int), 0);
- if (!intr_handle->intr_vec) {
+ if (rte_intr_dp_is_en(intr_handle)) {
+ if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
+ dev->data->nb_rx_queues)) {
PMD_DRV_LOG(ERR, "Failed to allocate %d rx intr_vec",
dev->data->nb_rx_queues);
return -1;
hw->msix_base = IAVF_MISC_VEC_ID;
for (i = 0; i < dev->data->nb_rx_queues; i++) {
hw->rxq_map[hw->msix_base] |= 1 << i;
- intr_handle->intr_vec[i] = IAVF_MISC_VEC_ID;
+ rte_intr_vec_list_index_set(intr_handle,
+ i, IAVF_MISC_VEC_ID);
}
PMD_DRV_LOG(DEBUG,
"vector %u are mapping to all Rx queues",
* multi interrupts, then the vec is from 1
*/
hw->nb_msix = RTE_MIN(hw->vf_res->max_vectors,
- intr_handle->nb_efd);
+ rte_intr_nb_efd_get(intr_handle));
hw->msix_base = IAVF_MISC_VEC_ID;
vec = IAVF_MISC_VEC_ID;
for (i = 0; i < dev->data->nb_rx_queues; i++) {
hw->rxq_map[vec] |= 1 << i;
- intr_handle->intr_vec[i] = vec++;
+ rte_intr_vec_list_index_set(intr_handle,
+ i, vec++);
if (vec >= hw->nb_msix)
vec = IAVF_RX_VEC_START;
}
ice_dcf_stop_queues(dev);
rte_intr_efd_disable(intr_handle);
- if (intr_handle->intr_vec) {
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
- }
+ rte_intr_vec_list_free(intr_handle);
ice_dcf_add_del_all_mac_addr(&dcf_ad->real_hw, false);
dev->data->dev_link.link_status = RTE_ETH_LINK_DOWN;
ice_set_default_ptype_table(dev);
pci_dev = RTE_DEV_TO_PCI(dev->device);
- intr_handle = &pci_dev->intr_handle;
+ intr_handle = pci_dev->intr_handle;
pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
pf->dev_data = dev->data;
{
struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
uint16_t msix_intr, i;
struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
struct ice_vsi *main_vsi = pf->main_vsi;
struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
uint16_t i;
/* avoid stopping again */
/* Clean datapath event and queue/vec mapping */
rte_intr_efd_disable(intr_handle);
- if (intr_handle->intr_vec) {
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
- }
+ rte_intr_vec_list_free(intr_handle);
pf->adapter_stopped = true;
dev->data->dev_started = 0;
struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct ice_adapter *ad =
ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
int ret;
{
struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
uint16_t msix_vect = vsi->msix_intr;
- uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
+ uint16_t nb_msix = RTE_MIN(vsi->nb_msix,
+ rte_intr_nb_efd_get(intr_handle));
uint16_t queue_idx = 0;
int record = 0;
int i;
vsi->nb_used_qps - i);
for (; !!record && i < vsi->nb_used_qps; i++)
- intr_handle->intr_vec[queue_idx + i] =
- msix_vect;
+ rte_intr_vec_list_index_set(intr_handle,
+ queue_idx + i, msix_vect);
+
break;
}
vsi->base_queue + i, 1);
if (!!record)
- intr_handle->intr_vec[queue_idx + i] = msix_vect;
+ rte_intr_vec_list_index_set(intr_handle,
+ queue_idx + i,
+ msix_vect);
msix_vect++;
nb_msix--;
{
struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
uint16_t msix_intr, i;
{
struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct ice_vsi *vsi = pf->main_vsi;
uint32_t intr_vector = 0;
return -1;
}
- if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
- intr_handle->intr_vec =
- rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
- 0);
- if (!intr_handle->intr_vec) {
+ if (rte_intr_dp_is_en(intr_handle)) {
+ if (rte_intr_vec_list_alloc(intr_handle, NULL,
+ dev->data->nb_rx_queues)) {
PMD_DRV_LOG(ERR,
"Failed to allocate %d rx_queues intr_vec",
dev->data->nb_rx_queues);
uint16_t queue_id)
{
struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
uint32_t val;
uint16_t msix_intr;
- msix_intr = intr_handle->intr_vec[queue_id];
+ msix_intr = rte_intr_vec_list_index_get(intr_handle, queue_id);
val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
GLINT_DYN_CTL_ITR_INDX_M;
val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
- rte_intr_ack(&pci_dev->intr_handle);
+ rte_intr_ack(pci_dev->intr_handle);
return 0;
}
uint16_t queue_id)
{
struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
uint16_t msix_intr;
- msix_intr = intr_handle->intr_vec[queue_id];
+ msix_intr = rte_intr_vec_list_index_get(intr_handle, queue_id);
ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
{
struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
if (rte_intr_allow_others(intr_handle) &&
dev->data->dev_conf.intr_conf.lsc) {
struct igc_interrupt *intr = IGC_DEV_PRIVATE_INTR(dev);
struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
if (rte_intr_allow_others(intr_handle) &&
dev->data->dev_conf.intr_conf.lsc) {
struct igc_adapter *adapter = IGC_DEV_PRIVATE(dev);
struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct rte_eth_link link;
dev->data->dev_started = 0;
/* Clean datapath event and queue/vec mapping */
rte_intr_efd_disable(intr_handle);
- if (intr_handle->intr_vec != NULL) {
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
- }
+ rte_intr_vec_list_free(intr_handle);
return 0;
}
{
struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
uint32_t intr_mask;
uint32_t vec = IGC_MISC_VEC_ID;
IGC_WRITE_REG(hw, IGC_GPIE, IGC_GPIE_MSIX_MODE |
IGC_GPIE_PBA | IGC_GPIE_EIAME |
IGC_GPIE_NSICR);
- intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
- misc_shift;
+ intr_mask = RTE_LEN2MASK(rte_intr_nb_efd_get(intr_handle),
+ uint32_t) << misc_shift;
if (dev->data->dev_conf.intr_conf.lsc)
intr_mask |= (1u << IGC_MSIX_OTHER_INTR_VEC);
for (i = 0; i < dev->data->nb_rx_queues; i++) {
igc_write_ivar(hw, i, 0, vec);
- intr_handle->intr_vec[i] = vec;
- if (vec < base + intr_handle->nb_efd - 1)
+ rte_intr_vec_list_index_set(intr_handle, i, vec);
+ if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1)
vec++;
}
uint32_t mask;
struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
/* won't configure msix register if no mapping is done
if (!rte_intr_dp_is_en(intr_handle))
return;
- mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) << misc_shift;
+ mask = RTE_LEN2MASK(rte_intr_nb_efd_get(intr_handle), uint32_t)
+ << misc_shift;
IGC_WRITE_REG(hw, IGC_EIMS, mask);
}
struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
struct igc_adapter *adapter = IGC_DEV_PRIVATE(dev);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
uint32_t *speeds;
int ret;
return -1;
}
- if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
- intr_handle->intr_vec = rte_zmalloc("intr_vec",
- dev->data->nb_rx_queues * sizeof(int), 0);
- if (intr_handle->intr_vec == NULL) {
+ if (rte_intr_dp_is_en(intr_handle)) {
+ if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
+ dev->data->nb_rx_queues)) {
PMD_DRV_LOG(ERR,
"Failed to allocate %d rx_queues intr_vec",
dev->data->nb_rx_queues);
eth_igc_close(struct rte_eth_dev *dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
struct igc_adapter *adapter = IGC_DEV_PRIVATE(dev);
int retry = 0;
dev->data->port_id, pci_dev->id.vendor_id,
pci_dev->id.device_id);
- rte_intr_callback_register(&pci_dev->intr_handle,
+ rte_intr_callback_register(pci_dev->intr_handle,
eth_igc_interrupt_handler, (void *)dev);
/* enable uio/vfio intr/eventfd mapping */
- rte_intr_enable(&pci_dev->intr_handle);
+ rte_intr_enable(pci_dev->intr_handle);
/* enable support intr */
igc_intr_other_enable(dev);
{
struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
uint32_t vec = IGC_MISC_VEC_ID;
if (rte_intr_allow_others(intr_handle))
{
struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
uint32_t vec = IGC_MISC_VEC_ID;
if (rte_intr_allow_others(intr_handle))
ionic_configure_intr(struct ionic_adapter *adapter)
{
struct rte_pci_device *pci_dev = adapter->pci_dev;
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
int err;
IONIC_PRINT(DEBUG, "Configuring %u intrs", adapter->nintrs);
IONIC_PRINT(DEBUG,
"Packet I/O interrupt on datapath is enabled");
- if (!intr_handle->intr_vec) {
- intr_handle->intr_vec = rte_zmalloc("intr_vec",
- adapter->nintrs * sizeof(int), 0);
-
- if (!intr_handle->intr_vec) {
- IONIC_PRINT(ERR, "Failed to allocate %u vectors",
- adapter->nintrs);
- return -ENOMEM;
- }
+ if (rte_intr_vec_list_alloc(intr_handle, "intr_vec", adapter->nintrs)) {
+ IONIC_PRINT(ERR, "Failed to allocate %u vectors",
+ adapter->nintrs);
+ return -ENOMEM;
}
err = rte_intr_callback_register(intr_handle,
ionic_unconfigure_intr(struct ionic_adapter *adapter)
{
struct rte_pci_device *pci_dev = adapter->pci_dev;
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
rte_intr_disable(intr_handle);
{
struct ixgbe_adapter *ad = eth_dev->data->dev_private;
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct ixgbe_hw *hw =
IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
struct ixgbe_vfta *shadow_vfta =
uint32_t tc, tcs;
struct ixgbe_adapter *ad = eth_dev->data->dev_private;
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct ixgbe_hw *hw =
IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
struct ixgbe_vfta *shadow_vfta =
struct ixgbe_vf_info *vfinfo =
*IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
uint32_t intr_vector = 0;
int err;
bool link_up = false, negotiate = 0;
return -1;
}
- if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
- intr_handle->intr_vec =
- rte_zmalloc("intr_vec",
- dev->data->nb_rx_queues * sizeof(int), 0);
- if (intr_handle->intr_vec == NULL) {
+ if (rte_intr_dp_is_en(intr_handle)) {
+ if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
+ dev->data->nb_rx_queues)) {
PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
" intr_vec", dev->data->nb_rx_queues);
return -ENOMEM;
struct ixgbe_vf_info *vfinfo =
*IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
int vf;
struct ixgbe_tm_conf *tm_conf =
IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
/* Clean datapath event and queue/vec mapping */
rte_intr_efd_disable(intr_handle);
- if (intr_handle->intr_vec != NULL) {
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
- }
+ rte_intr_vec_list_free(intr_handle);
/* reset hierarchy commit */
tm_conf->committed = false;
struct ixgbe_hw *hw =
IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
int retries = 0;
int ret;
{
struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct ixgbe_interrupt *intr =
IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
struct ixgbe_hw *hw =
IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
uint32_t intr_vector = 0;
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
int err, mask = 0;
}
}
- if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
- intr_handle->intr_vec =
- rte_zmalloc("intr_vec",
- dev->data->nb_rx_queues * sizeof(int), 0);
- if (intr_handle->intr_vec == NULL) {
+ if (rte_intr_dp_is_en(intr_handle)) {
+ if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
+ dev->data->nb_rx_queues)) {
PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
" intr_vec", dev->data->nb_rx_queues);
ixgbe_dev_clear_queues(dev);
struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct ixgbe_adapter *adapter = dev->data->dev_private;
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
if (hw->adapter_stopped)
return 0;
/* Clean datapath event and queue/vec mapping */
rte_intr_efd_disable(intr_handle);
- if (intr_handle->intr_vec != NULL) {
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
- }
+ rte_intr_vec_list_free(intr_handle);
adapter->rss_reta_updated = 0;
{
struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
int ret;
PMD_INIT_FUNC_TRACE();
ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct ixgbe_interrupt *intr =
IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
struct ixgbe_hw *hw =
struct ixgbe_hw *hw =
IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
uint32_t vec = IXGBE_MISC_VEC_ID;
if (rte_intr_allow_others(intr_handle))
ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
uint32_t mask;
struct ixgbe_hw *hw =
IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
ixgbevf_configure_msix(struct rte_eth_dev *dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct ixgbe_hw *hw =
IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
uint32_t q_idx;
* as IXGBE_VF_MAXMSIVECOTR = 1
*/
ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
- intr_handle->intr_vec[q_idx] = vector_idx;
- if (vector_idx < base + intr_handle->nb_efd - 1)
+ rte_intr_vec_list_index_set(intr_handle, q_idx,
+ vector_idx);
+ if (vector_idx < base + rte_intr_nb_efd_get(intr_handle)
+ - 1)
vector_idx++;
}
ixgbe_configure_msix(struct rte_eth_dev *dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct ixgbe_hw *hw =
IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
queue_id++) {
/* by default, 1:1 mapping */
ixgbe_set_ivar_map(hw, 0, queue_id, vec);
- intr_handle->intr_vec[queue_id] = vec;
- if (vec < base + intr_handle->nb_efd - 1)
+ rte_intr_vec_list_index_set(intr_handle,
+ queue_id, vec);
+ if (vec < base + rte_intr_nb_efd_get(intr_handle)
+ - 1)
vec++;
}
if (e == NULL)
return 0;
- size = memif_msg_send(cc->intr_handle.fd, &e->msg, e->fd);
+ size = memif_msg_send(rte_intr_fd_get(cc->intr_handle), &e->msg,
+ e->fd);
if (size != sizeof(memif_msg_t)) {
MIF_LOG(ERR, "sendmsg fail: %s.", strerror(errno));
ret = -1;
mq = (ar->flags & MEMIF_MSG_ADD_RING_FLAG_C2S) ?
dev->data->rx_queues[ar->index] : dev->data->tx_queues[ar->index];
- mq->intr_handle.fd = fd;
+ if (rte_intr_fd_set(mq->intr_handle, fd))
+ return -1;
+
mq->log2_ring_size = ar->log2_ring_size;
mq->region = ar->region;
mq->ring_offset = ar->offset;
dev->data->rx_queues[idx];
e->msg.type = MEMIF_MSG_TYPE_ADD_RING;
- e->fd = mq->intr_handle.fd;
+ e->fd = rte_intr_fd_get(mq->intr_handle);
ar->index = idx;
ar->offset = mq->ring_offset;
ar->region = mq->region;
struct memif_control_channel *cc = arg;
/* close control channel fd */
- close(intr_handle->fd);
+ close(rte_intr_fd_get(intr_handle));
/* clear message queue */
while ((elt = TAILQ_FIRST(&cc->msg_queue)) != NULL) {
TAILQ_REMOVE(&cc->msg_queue, elt, next);
rte_free(elt);
}
+ rte_intr_instance_free(cc->intr_handle);
/* free control channel */
rte_free(cc);
}
"Unexpected message(s) in message queue.");
}
- ih = &pmd->cc->intr_handle;
- if (ih->fd > 0) {
+ ih = pmd->cc->intr_handle;
+ if (rte_intr_fd_get(ih) > 0) {
ret = rte_intr_callback_unregister(ih,
memif_intr_handler,
pmd->cc);
pmd->cc,
memif_intr_unregister_handler);
} else if (ret > 0) {
- close(ih->fd);
+ close(rte_intr_fd_get(ih));
+ rte_intr_instance_free(ih);
rte_free(pmd->cc);
}
pmd->cc = NULL;
else
continue;
}
- if (mq->intr_handle.fd > 0) {
- close(mq->intr_handle.fd);
- mq->intr_handle.fd = -1;
+
+ if (rte_intr_fd_get(mq->intr_handle) > 0) {
+ close(rte_intr_fd_get(mq->intr_handle));
+ rte_intr_fd_set(mq->intr_handle, -1);
}
}
for (i = 0; i < pmd->cfg.num_s2c_rings; i++) {
else
continue;
}
- if (mq->intr_handle.fd > 0) {
- close(mq->intr_handle.fd);
- mq->intr_handle.fd = -1;
+
+ if (rte_intr_fd_get(mq->intr_handle) > 0) {
+ close(rte_intr_fd_get(mq->intr_handle));
+ rte_intr_fd_set(mq->intr_handle, -1);
}
}
mh.msg_control = ctl;
mh.msg_controllen = sizeof(ctl);
- size = recvmsg(cc->intr_handle.fd, &mh, 0);
+ size = recvmsg(rte_intr_fd_get(cc->intr_handle), &mh, 0);
if (size != sizeof(memif_msg_t)) {
MIF_LOG(DEBUG, "Invalid message size = %zd", size);
if (size > 0)
/* if driver failed to assign device */
if (cc->dev == NULL) {
memif_msg_send_from_queue(cc);
- ret = rte_intr_callback_unregister_pending(&cc->intr_handle,
+ ret = rte_intr_callback_unregister_pending(cc->intr_handle,
memif_intr_handler,
cc,
memif_intr_unregister_handler);
int ret;
addr_len = sizeof(client);
- sockfd = accept(socket->intr_handle.fd, (struct sockaddr *)&client,
- (socklen_t *)&addr_len);
+ sockfd = accept(rte_intr_fd_get(socket->intr_handle),
+ (struct sockaddr *)&client, (socklen_t *)&addr_len);
if (sockfd < 0) {
MIF_LOG(ERR,
"Failed to accept connection request on socket fd %d",
- socket->intr_handle.fd);
+ rte_intr_fd_get(socket->intr_handle));
return;
}
goto error;
}
- cc->intr_handle.fd = sockfd;
- cc->intr_handle.type = RTE_INTR_HANDLE_EXT;
+ /* Allocate interrupt instance */
+ cc->intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED);
+ if (cc->intr_handle == NULL) {
+ MIF_LOG(ERR, "Failed to allocate intr handle");
+ goto error;
+ }
+
+ if (rte_intr_fd_set(cc->intr_handle, sockfd))
+ goto error;
+
+ if (rte_intr_type_set(cc->intr_handle, RTE_INTR_HANDLE_EXT))
+ goto error;
+
cc->socket = socket;
cc->dev = NULL;
TAILQ_INIT(&cc->msg_queue);
- ret = rte_intr_callback_register(&cc->intr_handle, memif_intr_handler, cc);
+ ret = rte_intr_callback_register(cc->intr_handle, memif_intr_handler,
+ cc);
if (ret < 0) {
MIF_LOG(ERR, "Failed to register control channel callback.");
goto error;
close(sockfd);
sockfd = -1;
}
- if (cc != NULL)
+ if (cc != NULL) {
+ rte_intr_instance_free(cc->intr_handle);
rte_free(cc);
+ }
}
static struct memif_socket *
MIF_LOG(DEBUG, "Memif listener socket %s created.", sock->filename);
- sock->intr_handle.fd = sockfd;
- sock->intr_handle.type = RTE_INTR_HANDLE_EXT;
- ret = rte_intr_callback_register(&sock->intr_handle,
+ /* Allocate interrupt instance */
+ sock->intr_handle =
+ rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED);
+ if (sock->intr_handle == NULL) {
+ MIF_LOG(ERR, "Failed to allocate intr handle");
+ goto error;
+ }
+
+ if (rte_intr_fd_set(sock->intr_handle, sockfd))
+ goto error;
+
+ if (rte_intr_type_set(sock->intr_handle, RTE_INTR_HANDLE_EXT))
+ goto error;
+
+ ret = rte_intr_callback_register(sock->intr_handle,
memif_listener_handler, sock);
if (ret < 0) {
MIF_LOG(ERR, "Failed to register interrupt "
error:
MIF_LOG(ERR, "Failed to setup socket %s: %s", key, strerror(errno));
- if (sock != NULL)
+ if (sock != NULL) {
+ rte_intr_instance_free(sock->intr_handle);
rte_free(sock);
+ }
if (sockfd >= 0)
close(sockfd);
return NULL;
MIF_LOG(ERR, "Failed to remove socket file: %s",
socket->filename);
}
+ if (pmd->role != MEMIF_ROLE_CLIENT)
+ rte_intr_instance_free(socket->intr_handle);
rte_free(socket);
}
}
goto error;
}
- pmd->cc->intr_handle.fd = sockfd;
- pmd->cc->intr_handle.type = RTE_INTR_HANDLE_EXT;
+ /* Allocate interrupt instance */
+ pmd->cc->intr_handle =
+ rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED);
+ if (pmd->cc->intr_handle == NULL) {
+ MIF_LOG(ERR, "Failed to allocate intr handle");
+ goto error;
+ }
+
+ if (rte_intr_fd_set(pmd->cc->intr_handle, sockfd))
+ goto error;
+
+ if (rte_intr_type_set(pmd->cc->intr_handle, RTE_INTR_HANDLE_EXT))
+ goto error;
+
pmd->cc->socket = NULL;
pmd->cc->dev = dev;
TAILQ_INIT(&pmd->cc->msg_queue);
- ret = rte_intr_callback_register(&pmd->cc->intr_handle,
+ ret = rte_intr_callback_register(pmd->cc->intr_handle,
memif_intr_handler, pmd->cc);
if (ret < 0) {
MIF_LOG(ERR, "Failed to register interrupt callback for control fd");
sockfd = -1;
}
if (pmd->cc != NULL) {
+ rte_intr_instance_free(pmd->cc->intr_handle);
rte_free(pmd->cc);
pmd->cc = NULL;
}
(sizeof(struct sockaddr_un) - offsetof(struct sockaddr_un, sun_path))
struct memif_socket {
- struct rte_intr_handle intr_handle; /**< interrupt handle */
+ struct rte_intr_handle *intr_handle; /**< interrupt handle */
char filename[MEMIF_SOCKET_UN_SIZE]; /**< socket filename */
TAILQ_HEAD(, memif_socket_dev_list_elt) dev_queue;
};
struct memif_control_channel {
- struct rte_intr_handle intr_handle; /**< interrupt handle */
+ struct rte_intr_handle *intr_handle; /**< interrupt handle */
TAILQ_HEAD(, memif_msg_queue_elt) msg_queue; /**< control message queue */
struct memif_socket *socket; /**< pointer to socket */
struct rte_eth_dev *dev; /**< pointer to device */
/* consume interrupt */
if ((ring->flags & MEMIF_RING_FLAG_MASK_INT) == 0)
- size = read(mq->intr_handle.fd, &b, sizeof(b));
+ size = read(rte_intr_fd_get(mq->intr_handle), &b,
+ sizeof(b));
ring_size = 1 << mq->log2_ring_size;
mask = ring_size - 1;
if ((ring->flags & MEMIF_RING_FLAG_MASK_INT) == 0) {
uint64_t b;
ssize_t size __rte_unused;
- size = read(mq->intr_handle.fd, &b, sizeof(b));
+ size = read(rte_intr_fd_get(mq->intr_handle), &b,
+ sizeof(b));
}
ring_size = 1 << mq->log2_ring_size;
if ((ring->flags & MEMIF_RING_FLAG_MASK_INT) == 0) {
a = 1;
- size = write(mq->intr_handle.fd, &a, sizeof(a));
+ size = write(rte_intr_fd_get(mq->intr_handle), &a,
+ sizeof(a));
if (unlikely(size < 0)) {
MIF_LOG(WARNING,
"Failed to send interrupt. %s", strerror(errno));
/* Send interrupt, if enabled. */
if ((ring->flags & MEMIF_RING_FLAG_MASK_INT) == 0) {
uint64_t a = 1;
- ssize_t size = write(mq->intr_handle.fd, &a, sizeof(a));
+ ssize_t size = write(rte_intr_fd_get(mq->intr_handle),
+ &a, sizeof(a));
if (unlikely(size < 0)) {
MIF_LOG(WARNING,
"Failed to send interrupt. %s", strerror(errno));
mq->ring_offset = memif_get_ring_offset(dev, mq, MEMIF_RING_C2S, i);
mq->last_head = 0;
mq->last_tail = 0;
- mq->intr_handle.fd = eventfd(0, EFD_NONBLOCK);
- if (mq->intr_handle.fd < 0) {
+ if (rte_intr_fd_set(mq->intr_handle, eventfd(0, EFD_NONBLOCK)))
+ return -rte_errno;
+
+ if (rte_intr_fd_get(mq->intr_handle) < 0) {
MIF_LOG(WARNING,
"Failed to create eventfd for tx queue %d: %s.", i,
strerror(errno));
mq->ring_offset = memif_get_ring_offset(dev, mq, MEMIF_RING_S2C, i);
mq->last_head = 0;
mq->last_tail = 0;
- mq->intr_handle.fd = eventfd(0, EFD_NONBLOCK);
- if (mq->intr_handle.fd < 0) {
+ if (rte_intr_fd_set(mq->intr_handle, eventfd(0, EFD_NONBLOCK)))
+ return -rte_errno;
+ if (rte_intr_fd_get(mq->intr_handle) < 0) {
MIF_LOG(WARNING,
"Failed to create eventfd for rx queue %d: %s.", i,
strerror(errno));
return -ENOMEM;
}
+ /* Allocate interrupt instance */
+ mq->intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED);
+ if (mq->intr_handle == NULL) {
+ MIF_LOG(ERR, "Failed to allocate intr handle");
+ return -ENOMEM;
+ }
+
mq->type =
(pmd->role == MEMIF_ROLE_CLIENT) ? MEMIF_RING_C2S : MEMIF_RING_S2C;
mq->n_pkts = 0;
mq->n_bytes = 0;
- mq->intr_handle.fd = -1;
- mq->intr_handle.type = RTE_INTR_HANDLE_EXT;
+
+ if (rte_intr_fd_set(mq->intr_handle, -1))
+ return -rte_errno;
+
+ if (rte_intr_type_set(mq->intr_handle, RTE_INTR_HANDLE_EXT))
+ return -rte_errno;
+
mq->in_port = dev->data->port_id;
dev->data->tx_queues[qid] = mq;
return -ENOMEM;
}
+ /* Allocate interrupt instance */
+ mq->intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED);
+ if (mq->intr_handle == NULL) {
+ MIF_LOG(ERR, "Failed to allocate intr handle");
+ return -ENOMEM;
+ }
+
mq->type = (pmd->role == MEMIF_ROLE_CLIENT) ? MEMIF_RING_S2C : MEMIF_RING_C2S;
mq->n_pkts = 0;
mq->n_bytes = 0;
- mq->intr_handle.fd = -1;
- mq->intr_handle.type = RTE_INTR_HANDLE_EXT;
+
+ if (rte_intr_fd_set(mq->intr_handle, -1))
+ return -rte_errno;
+
+ if (rte_intr_type_set(mq->intr_handle, RTE_INTR_HANDLE_EXT))
+ return -rte_errno;
+
mq->mempool = mb_pool;
mq->in_port = dev->data->port_id;
dev->data->rx_queues[qid] = mq;
if (!mq)
return;
+ rte_intr_instance_free(mq->intr_handle);
rte_free(mq);
}
uint64_t n_pkts; /**< number of rx/tx packets */
uint64_t n_bytes; /**< number of rx/tx bytes */
- struct rte_intr_handle intr_handle; /**< interrupt handle */
+ struct rte_intr_handle *intr_handle; /**< interrupt handle */
memif_log2_ring_size_t log2_ring_size; /**< log2 of ring size */
};
rte_eth_copy_pci_info(eth_dev, pci_dev);
eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
/* Initialize local interrupt handle for current port. */
- memset(&priv->intr_handle, 0, sizeof(struct rte_intr_handle));
- priv->intr_handle.fd = -1;
- priv->intr_handle.type = RTE_INTR_HANDLE_EXT;
+ priv->intr_handle =
+ rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED);
+ if (priv->intr_handle == NULL) {
+ RTE_LOG(ERR, EAL, "Fail to allocate intr_handle\n");
+ goto port_error;
+ }
+
+ if (rte_intr_fd_set(priv->intr_handle, -1))
+ goto port_error;
+
+ if (rte_intr_type_set(priv->intr_handle, RTE_INTR_HANDLE_EXT))
+ goto port_error;
+
/*
* Override ethdev interrupt handle pointer with private
* handle instead of that of the parent PCI device used by
* besides setting up eth_dev->intr_handle, the rest is
* handled by rte_intr_rx_ctl().
*/
- eth_dev->intr_handle = &priv->intr_handle;
+ eth_dev->intr_handle = priv->intr_handle;
priv->dev_data = eth_dev->data;
eth_dev->dev_ops = &mlx4_dev_ops;
#ifdef HAVE_IBV_MLX4_BUF_ALLOCATORS
prev_dev = eth_dev;
continue;
port_error:
+ rte_intr_instance_free(priv->intr_handle);
rte_free(priv);
if (eth_dev != NULL)
eth_dev->data->dev_private = NULL;
uint32_t tso_max_payload_sz; /**< Max supported TSO payload size. */
uint32_t hw_rss_max_qps; /**< Max Rx Queues supported by RSS. */
uint64_t hw_rss_sup; /**< Supported RSS hash fields (Verbs format). */
- struct rte_intr_handle intr_handle; /**< Port interrupt handle. */
+ struct rte_intr_handle *intr_handle; /**< Port interrupt handle. */
struct mlx4_drop *drop; /**< Shared resources for drop flow rules. */
struct {
uint32_t dev_gen; /* Generation number to flush local caches. */
static void
mlx4_rx_intr_vec_disable(struct mlx4_priv *priv)
{
- struct rte_intr_handle *intr_handle = &priv->intr_handle;
+ struct rte_intr_handle *intr_handle = priv->intr_handle;
rte_intr_free_epoll_fd(intr_handle);
- free(intr_handle->intr_vec);
- intr_handle->nb_efd = 0;
- intr_handle->intr_vec = NULL;
+ rte_intr_vec_list_free(intr_handle);
+
+ rte_intr_nb_efd_set(intr_handle, 0);
}
/**
unsigned int rxqs_n = ETH_DEV(priv)->data->nb_rx_queues;
unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
unsigned int count = 0;
- struct rte_intr_handle *intr_handle = &priv->intr_handle;
+ struct rte_intr_handle *intr_handle = priv->intr_handle;
mlx4_rx_intr_vec_disable(priv);
- intr_handle->intr_vec = malloc(n * sizeof(intr_handle->intr_vec[0]));
- if (intr_handle->intr_vec == NULL) {
+ if (rte_intr_vec_list_alloc(intr_handle, NULL, n)) {
rte_errno = ENOMEM;
ERROR("failed to allocate memory for interrupt vector,"
" Rx interrupts will not be supported");
/* Skip queues that cannot request interrupts. */
if (!rxq || !rxq->channel) {
/* Use invalid intr_vec[] index to disable entry. */
- intr_handle->intr_vec[i] =
- RTE_INTR_VEC_RXTX_OFFSET +
- RTE_MAX_RXTX_INTR_VEC_ID;
+ if (rte_intr_vec_list_index_set(intr_handle, i,
+ RTE_INTR_VEC_RXTX_OFFSET + RTE_MAX_RXTX_INTR_VEC_ID))
+ return -rte_errno;
continue;
}
if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
mlx4_rx_intr_vec_disable(priv);
return -rte_errno;
}
- intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
- intr_handle->efds[count] = rxq->channel->fd;
+
+ if (rte_intr_vec_list_index_set(intr_handle, i,
+ RTE_INTR_VEC_RXTX_OFFSET + count))
+ return -rte_errno;
+
+ if (rte_intr_efds_index_set(intr_handle, i,
+ rxq->channel->fd))
+ return -rte_errno;
+
count++;
}
if (!count)
mlx4_rx_intr_vec_disable(priv);
- else
- intr_handle->nb_efd = count;
+ else if (rte_intr_nb_efd_set(intr_handle, count))
+ return -rte_errno;
return 0;
}
{
int err = rte_errno; /* Make sure rte_errno remains unchanged. */
- if (priv->intr_handle.fd != -1) {
- rte_intr_callback_unregister(&priv->intr_handle,
+ if (rte_intr_fd_get(priv->intr_handle) != -1) {
+ rte_intr_callback_unregister(priv->intr_handle,
(void (*)(void *))
mlx4_interrupt_handler,
priv);
- priv->intr_handle.fd = -1;
+ if (rte_intr_fd_set(priv->intr_handle, -1))
+ return -rte_errno;
}
rte_eal_alarm_cancel((void (*)(void *))mlx4_link_status_alarm, priv);
priv->intr_alarm = 0;
mlx4_intr_uninstall(priv);
if (intr_conf->lsc | intr_conf->rmv) {
- priv->intr_handle.fd = priv->ctx->async_fd;
- rc = rte_intr_callback_register(&priv->intr_handle,
+ if (rte_intr_fd_set(priv->intr_handle, priv->ctx->async_fd))
+ return -rte_errno;
+
+ rc = rte_intr_callback_register(priv->intr_handle,
(void (*)(void *))
mlx4_interrupt_handler,
priv);
* Representor interrupts handle is released in mlx5_dev_stop().
*/
if (list[i].info.representor) {
- struct rte_intr_handle *intr_handle;
- intr_handle = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO,
- sizeof(*intr_handle), 0,
- SOCKET_ID_ANY);
- if (!intr_handle) {
+ struct rte_intr_handle *intr_handle =
+ rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED);
+ if (intr_handle == NULL) {
DRV_LOG(ERR,
"port %u failed to allocate memory for interrupt handler "
"Rx interrupts will not be supported",
if (eth_dev == NULL)
return -rte_errno;
/* Post create. */
- eth_dev->intr_handle = &adev->intr_handle;
+ eth_dev->intr_handle = adev->intr_handle;
if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_RMV;
int flags;
struct ibv_context *ctx = sh->cdev->ctx;
- sh->intr_handle.fd = -1;
+ sh->intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED);
+ if (sh->intr_handle == NULL) {
+ DRV_LOG(ERR, "Fail to allocate intr_handle");
+ rte_errno = ENOMEM;
+ return;
+ }
+ rte_intr_fd_set(sh->intr_handle, -1);
+
flags = fcntl(ctx->async_fd, F_GETFL);
ret = fcntl(ctx->async_fd, F_SETFL, flags | O_NONBLOCK);
if (ret) {
DRV_LOG(INFO, "failed to change file descriptor async event"
" queue");
} else {
- sh->intr_handle.fd = ctx->async_fd;
- sh->intr_handle.type = RTE_INTR_HANDLE_EXT;
- if (rte_intr_callback_register(&sh->intr_handle,
+ rte_intr_fd_set(sh->intr_handle, ctx->async_fd);
+ rte_intr_type_set(sh->intr_handle, RTE_INTR_HANDLE_EXT);
+ if (rte_intr_callback_register(sh->intr_handle,
mlx5_dev_interrupt_handler, sh)) {
DRV_LOG(INFO, "Fail to install the shared interrupt.");
- sh->intr_handle.fd = -1;
+ rte_intr_fd_set(sh->intr_handle, -1);
}
}
if (sh->devx) {
#ifdef HAVE_IBV_DEVX_ASYNC
- sh->intr_handle_devx.fd = -1;
+ sh->intr_handle_devx =
+ rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED);
+ if (!sh->intr_handle_devx) {
+ DRV_LOG(ERR, "Fail to allocate intr_handle");
+ rte_errno = ENOMEM;
+ return;
+ }
+ rte_intr_fd_set(sh->intr_handle_devx, -1);
sh->devx_comp = (void *)mlx5_glue->devx_create_cmd_comp(ctx);
struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp;
if (!devx_comp) {
" devx comp");
return;
}
- sh->intr_handle_devx.fd = devx_comp->fd;
- sh->intr_handle_devx.type = RTE_INTR_HANDLE_EXT;
- if (rte_intr_callback_register(&sh->intr_handle_devx,
+ rte_intr_fd_set(sh->intr_handle_devx, devx_comp->fd);
+ rte_intr_type_set(sh->intr_handle_devx,
+ RTE_INTR_HANDLE_EXT);
+ if (rte_intr_callback_register(sh->intr_handle_devx,
mlx5_dev_interrupt_handler_devx, sh)) {
DRV_LOG(INFO, "Fail to install the devx shared"
" interrupt.");
- sh->intr_handle_devx.fd = -1;
+ rte_intr_fd_set(sh->intr_handle_devx, -1);
}
#endif /* HAVE_IBV_DEVX_ASYNC */
}
void
mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh)
{
- if (sh->intr_handle.fd >= 0)
- mlx5_intr_callback_unregister(&sh->intr_handle,
+ if (rte_intr_fd_get(sh->intr_handle) >= 0)
+ mlx5_intr_callback_unregister(sh->intr_handle,
mlx5_dev_interrupt_handler, sh);
+ rte_intr_instance_free(sh->intr_handle);
#ifdef HAVE_IBV_DEVX_ASYNC
- if (sh->intr_handle_devx.fd >= 0)
- rte_intr_callback_unregister(&sh->intr_handle_devx,
+ if (rte_intr_fd_get(sh->intr_handle_devx) >= 0)
+ rte_intr_callback_unregister(sh->intr_handle_devx,
mlx5_dev_interrupt_handler_devx, sh);
+ rte_intr_instance_free(sh->intr_handle_devx);
if (sh->devx_comp)
mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp);
#endif
#define MLX5_SOCKET_PATH "/var/tmp/dpdk_net_mlx5_%d"
int server_socket; /* Unix socket for primary process. */
-struct rte_intr_handle server_intr_handle; /* Interrupt handler. */
+struct rte_intr_handle *server_intr_handle; /* Interrupt handler. */
/**
* Handle server pmd socket interrupts.
mlx5_pmd_interrupt_handler_install(void)
{
MLX5_ASSERT(server_socket);
- server_intr_handle.fd = server_socket;
- server_intr_handle.type = RTE_INTR_HANDLE_EXT;
- return rte_intr_callback_register(&server_intr_handle,
+ server_intr_handle =
+ rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_PRIVATE);
+ if (server_intr_handle == NULL) {
+ DRV_LOG(ERR, "Fail to allocate intr_handle");
+ return -ENOMEM;
+ }
+ if (rte_intr_fd_set(server_intr_handle, server_socket))
+ return -rte_errno;
+
+ if (rte_intr_type_set(server_intr_handle, RTE_INTR_HANDLE_EXT))
+ return -rte_errno;
+
+ return rte_intr_callback_register(server_intr_handle,
mlx5_pmd_socket_handle, NULL);
}
mlx5_pmd_interrupt_handler_uninstall(void)
{
if (server_socket) {
- mlx5_intr_callback_unregister(&server_intr_handle,
+ mlx5_intr_callback_unregister(server_intr_handle,
mlx5_pmd_socket_handle,
NULL);
}
- server_intr_handle.fd = 0;
- server_intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;
+ rte_intr_fd_set(server_intr_handle, 0);
+ rte_intr_type_set(server_intr_handle, RTE_INTR_HANDLE_UNKNOWN);
+ rte_intr_instance_free(server_intr_handle);
}
/**
uint32_t tick; /* Completion tick duration in nanoseconds. */
uint32_t test; /* Packet pacing test mode. */
int32_t skew; /* Scheduling skew. */
- struct rte_intr_handle intr_handle; /* Periodic interrupt. */
+ struct rte_intr_handle *intr_handle; /* Periodic interrupt. */
void *echan; /* Event Channel. */
struct mlx5_txpp_wq clock_queue; /* Clock Queue. */
struct mlx5_txpp_wq rearm_queue; /* Clock Queue. */
struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX];
struct mlx5_indexed_pool *mdh_ipools[MLX5_MAX_MODIFY_NUM];
/* Shared interrupt handler section. */
- struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
- struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
+ struct rte_intr_handle *intr_handle; /* Interrupt handler for device. */
+ struct rte_intr_handle *intr_handle_devx; /* DEVX interrupt handler. */
void *devx_comp; /* DEVX async comp obj. */
struct mlx5_devx_obj *tis[16]; /* TIS object. */
struct mlx5_devx_obj *td; /* Transport domain. */
if (!dev->data->dev_conf.intr_conf.rxq)
return 0;
mlx5_rx_intr_vec_disable(dev);
- intr_handle->intr_vec = mlx5_malloc(0,
- n * sizeof(intr_handle->intr_vec[0]),
- 0, SOCKET_ID_ANY);
- if (intr_handle->intr_vec == NULL) {
+ if (rte_intr_vec_list_alloc(intr_handle, NULL, n)) {
DRV_LOG(ERR,
"port %u failed to allocate memory for interrupt"
" vector, Rx interrupts will not be supported",
rte_errno = ENOMEM;
return -rte_errno;
}
- intr_handle->type = RTE_INTR_HANDLE_EXT;
+
+ if (rte_intr_type_set(intr_handle, RTE_INTR_HANDLE_EXT))
+ return -rte_errno;
+
for (i = 0; i != n; ++i) {
/* This rxq obj must not be released in this function. */
struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_get(dev, i);
if (!rxq_obj || (!rxq_obj->ibv_channel &&
!rxq_obj->devx_channel)) {
/* Use invalid intr_vec[] index to disable entry. */
- intr_handle->intr_vec[i] =
- RTE_INTR_VEC_RXTX_OFFSET +
- RTE_MAX_RXTX_INTR_VEC_ID;
+ if (rte_intr_vec_list_index_set(intr_handle, i,
+ RTE_INTR_VEC_RXTX_OFFSET + RTE_MAX_RXTX_INTR_VEC_ID))
+ return -rte_errno;
/* Decrease the rxq_ctrl's refcnt */
if (rxq_ctrl)
mlx5_rxq_release(dev, i);
mlx5_rx_intr_vec_disable(dev);
return -rte_errno;
}
- intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
- intr_handle->efds[count] = rxq_obj->fd;
+
+ if (rte_intr_vec_list_index_set(intr_handle, i,
+ RTE_INTR_VEC_RXTX_OFFSET + count))
+ return -rte_errno;
+ if (rte_intr_efds_index_set(intr_handle, count,
+ rxq_obj->fd))
+ return -rte_errno;
count++;
}
if (!count)
mlx5_rx_intr_vec_disable(dev);
- else
- intr_handle->nb_efd = count;
+ else if (rte_intr_nb_efd_set(intr_handle, count))
+ return -rte_errno;
return 0;
}
if (!dev->data->dev_conf.intr_conf.rxq)
return;
- if (!intr_handle->intr_vec)
+ if (rte_intr_vec_list_index_get(intr_handle, 0) < 0)
goto free;
for (i = 0; i != n; ++i) {
- if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
- RTE_MAX_RXTX_INTR_VEC_ID)
+ if (rte_intr_vec_list_index_get(intr_handle, i) ==
+ RTE_INTR_VEC_RXTX_OFFSET + RTE_MAX_RXTX_INTR_VEC_ID)
continue;
/**
* Need to access directly the queue to release the reference
}
free:
rte_intr_free_epoll_fd(intr_handle);
- if (intr_handle->intr_vec)
- mlx5_free(intr_handle->intr_vec);
- intr_handle->nb_efd = 0;
- intr_handle->intr_vec = NULL;
+
+ rte_intr_vec_list_free(intr_handle);
+
+ rte_intr_nb_efd_set(intr_handle, 0);
}
/**
dev->rx_pkt_burst = mlx5_select_rx_function(dev);
/* Enable datapath on secondary process. */
mlx5_mp_os_req_start_rxtx(dev);
- if (priv->sh->intr_handle.fd >= 0) {
+ if (rte_intr_fd_get(priv->sh->intr_handle) >= 0) {
priv->sh->port[priv->dev_port - 1].ih_port_id =
(uint32_t)dev->data->port_id;
} else {
dev->data->dev_conf.intr_conf.lsc = 0;
dev->data->dev_conf.intr_conf.rmv = 0;
}
- if (priv->sh->intr_handle_devx.fd >= 0)
+ if (rte_intr_fd_get(priv->sh->intr_handle_devx) >= 0)
priv->sh->port[priv->dev_port - 1].devx_ih_port_id =
(uint32_t)dev->data->port_id;
return 0;
static void
mlx5_txpp_stop_service(struct mlx5_dev_ctx_shared *sh)
{
- if (!sh->txpp.intr_handle.fd)
+ if (!rte_intr_fd_get(sh->txpp.intr_handle))
return;
- mlx5_intr_callback_unregister(&sh->txpp.intr_handle,
+ mlx5_intr_callback_unregister(sh->txpp.intr_handle,
mlx5_txpp_interrupt_handler, sh);
- sh->txpp.intr_handle.fd = 0;
+ rte_intr_instance_free(sh->txpp.intr_handle);
}
/* Attach interrupt handler and fires first request to Rearm Queue. */
rte_errno = errno;
return -rte_errno;
}
- memset(&sh->txpp.intr_handle, 0, sizeof(sh->txpp.intr_handle));
+ sh->txpp.intr_handle =
+ rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED);
+ if (sh->txpp.intr_handle == NULL) {
+ DRV_LOG(ERR, "Fail to allocate intr_handle");
+ return -ENOMEM;
+ }
fd = mlx5_os_get_devx_channel_fd(sh->txpp.echan);
- sh->txpp.intr_handle.fd = fd;
- sh->txpp.intr_handle.type = RTE_INTR_HANDLE_EXT;
- if (rte_intr_callback_register(&sh->txpp.intr_handle,
+ if (rte_intr_fd_set(sh->txpp.intr_handle, fd))
+ return -rte_errno;
+
+ if (rte_intr_type_set(sh->txpp.intr_handle, RTE_INTR_HANDLE_EXT))
+ return -rte_errno;
+
+ if (rte_intr_callback_register(sh->txpp.intr_handle,
mlx5_txpp_interrupt_handler, sh)) {
- sh->txpp.intr_handle.fd = 0;
+ rte_intr_fd_set(sh->txpp.intr_handle, 0);
DRV_LOG(ERR, "Failed to register CQE interrupt %d.", rte_errno);
return -rte_errno;
}
eth_dev->device = &dev->device;
/* interrupt is simulated */
- dev->intr_handle.type = RTE_INTR_HANDLE_EXT;
+ rte_intr_type_set(dev->intr_handle, RTE_INTR_HANDLE_EXT);
eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
- eth_dev->intr_handle = &dev->intr_handle;
+ eth_dev->intr_handle = dev->intr_handle;
return eth_dev;
}
struct nfp_net_hw *hw;
int i;
- if (!intr_handle->intr_vec) {
- intr_handle->intr_vec =
- rte_zmalloc("intr_vec",
- dev->data->nb_rx_queues * sizeof(int), 0);
- if (!intr_handle->intr_vec) {
- PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
- " intr_vec", dev->data->nb_rx_queues);
- return -ENOMEM;
- }
+ if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
+ dev->data->nb_rx_queues)) {
+ PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
+ " intr_vec", dev->data->nb_rx_queues);
+ return -ENOMEM;
}
hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
+ if (rte_intr_type_get(intr_handle) == RTE_INTR_HANDLE_UIO) {
PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
/* UIO just supports one queue and no LSC*/
nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
- intr_handle->intr_vec[0] = 0;
+ if (rte_intr_vec_list_index_set(intr_handle, 0, 0))
+ return -1;
} else {
PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
for (i = 0; i < dev->data->nb_rx_queues; i++) {
* efd interrupts
*/
nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
- intr_handle->intr_vec[i] = i + 1;
+ if (rte_intr_vec_list_index_set(intr_handle, i,
+ i + 1))
+ return -1;
PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
- intr_handle->intr_vec[i]);
+ rte_intr_vec_list_index_get(intr_handle,
+ i));
}
}
hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
+ if (rte_intr_type_get(pci_dev->intr_handle) !=
+ RTE_INTR_HANDLE_UIO)
base = 1;
/* Make sure all updates are written before un-masking */
hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
+ if (rte_intr_type_get(pci_dev->intr_handle) !=
+ RTE_INTR_HANDLE_UIO)
base = 1;
/* Make sure all updates are written before un-masking */
if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
/* If MSI-X auto-masking is used, clear the entry */
rte_wmb();
- rte_intr_ack(&pci_dev->intr_handle);
+ rte_intr_ack(pci_dev->intr_handle);
} else {
/* Make sure all updates are written before un-masking */
rte_wmb();
nfp_net_start(struct rte_eth_dev *dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
uint32_t new_ctrl, update = 0;
struct nfp_net_hw *hw;
struct nfp_pf_dev *pf_dev;
"with NFP multiport PF");
return -EINVAL;
}
- if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
+ if (rte_intr_type_get(intr_handle) ==
+ RTE_INTR_HANDLE_UIO) {
/*
* Better not to share LSC with RX interrupts.
* Unregistering LSC interrupt handler
*/
- rte_intr_callback_unregister(&pci_dev->intr_handle,
+ rte_intr_callback_unregister(pci_dev->intr_handle,
nfp_net_dev_interrupt_handler, (void *)dev);
if (dev->data->nb_rx_queues > 1) {
nfp_cpp_free(pf_dev->cpp);
rte_free(pf_dev);
- rte_intr_disable(&pci_dev->intr_handle);
+ rte_intr_disable(pci_dev->intr_handle);
/* unregister callback func from eal lib */
- rte_intr_callback_unregister(&pci_dev->intr_handle,
+ rte_intr_callback_unregister(pci_dev->intr_handle,
nfp_net_dev_interrupt_handler,
(void *)dev);
if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
/* Registering LSC interrupt handler */
- rte_intr_callback_register(&pci_dev->intr_handle,
+ rte_intr_callback_register(pci_dev->intr_handle,
nfp_net_dev_interrupt_handler,
(void *)eth_dev);
/* Telling the firmware about the LSC interrupt entry */
nfp_netvf_start(struct rte_eth_dev *dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
uint32_t new_ctrl, update = 0;
struct nfp_net_hw *hw;
struct rte_eth_conf *dev_conf;
/* check and configure queue intr-vector mapping */
if (dev->data->dev_conf.intr_conf.rxq != 0) {
- if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
+ if (rte_intr_type_get(intr_handle) ==
+ RTE_INTR_HANDLE_UIO) {
/*
* Better not to share LSC with RX interrupts.
* Unregistering LSC interrupt handler
*/
- rte_intr_callback_unregister(&pci_dev->intr_handle,
+ rte_intr_callback_unregister(pci_dev->intr_handle,
nfp_net_dev_interrupt_handler, (void *)dev);
if (dev->data->nb_rx_queues > 1) {
nfp_net_reset_rx_queue(this_rx_q);
}
- rte_intr_disable(&pci_dev->intr_handle);
+ rte_intr_disable(pci_dev->intr_handle);
/* unregister callback func from eal lib */
- rte_intr_callback_unregister(&pci_dev->intr_handle,
+ rte_intr_callback_unregister(pci_dev->intr_handle,
nfp_net_dev_interrupt_handler,
(void *)dev);
if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
/* Registering LSC interrupt handler */
- rte_intr_callback_register(&pci_dev->intr_handle,
+ rte_intr_callback_register(pci_dev->intr_handle,
nfp_net_dev_interrupt_handler,
(void *)eth_dev);
/* Telling the firmware about the LSC interrupt entry */
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
struct ngbe_hw *hw = ngbe_dev_hw(eth_dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
const struct rte_memzone *mz;
uint32_t ctrl_ext;
int err;
{
struct ngbe_hw *hw = ngbe_dev_hw(dev);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
uint32_t intr_vector = 0;
int err;
bool link_up = false, negotiate = false;
return -1;
}
- if (rte_intr_dp_is_en(intr_handle) && intr_handle->intr_vec == NULL) {
- intr_handle->intr_vec =
- rte_zmalloc("intr_vec",
- dev->data->nb_rx_queues * sizeof(int), 0);
- if (intr_handle->intr_vec == NULL) {
+ if (rte_intr_dp_is_en(intr_handle)) {
+ if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
+ dev->data->nb_rx_queues)) {
PMD_INIT_LOG(ERR,
"Failed to allocate %d rx_queues intr_vec",
dev->data->nb_rx_queues);
struct rte_eth_link link;
struct ngbe_hw *hw = ngbe_dev_hw(dev);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
if (hw->adapter_stopped)
return 0;
/* Clean datapath event and queue/vec mapping */
rte_intr_efd_disable(intr_handle);
- if (intr_handle->intr_vec != NULL) {
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
- }
+ rte_intr_vec_list_free(intr_handle);
hw->adapter_stopped = true;
dev->data->dev_started = 0;
{
struct ngbe_hw *hw = ngbe_dev_hw(dev);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
int retries = 0;
int ret;
ngbe_configure_msix(struct rte_eth_dev *dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct ngbe_hw *hw = ngbe_dev_hw(dev);
uint32_t queue_id, base = NGBE_MISC_VEC_ID;
uint32_t vec = NGBE_MISC_VEC_ID;
queue_id++) {
/* by default, 1:1 mapping */
ngbe_set_ivar_map(hw, 0, queue_id, vec);
- intr_handle->intr_vec[queue_id] = vec;
- if (vec < base + intr_handle->nb_efd - 1)
+ rte_intr_vec_list_index_set(intr_handle,
+ queue_id, vec);
+ if (vec < base + rte_intr_nb_efd_get(intr_handle)
+ - 1)
vec++;
}
nix_lf_register_err_irq(struct rte_eth_dev *eth_dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
int rc, vec;
nix_lf_unregister_err_irq(struct rte_eth_dev *eth_dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
int vec;
nix_lf_register_ras_irq(struct rte_eth_dev *eth_dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
int rc, vec;
nix_lf_unregister_ras_irq(struct rte_eth_dev *eth_dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
int vec;
oxt2_nix_register_queue_irqs(struct rte_eth_dev *eth_dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
int vec, q, sqs, rqs, qs, rc = 0;
oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
int vec, q;
oxt2_nix_register_cq_irqs(struct rte_eth_dev *eth_dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
uint8_t rc = 0, vec, q;
return rc;
}
- if (!handle->intr_vec) {
- handle->intr_vec = rte_zmalloc("intr_vec",
- dev->configured_cints *
- sizeof(int), 0);
- if (!handle->intr_vec) {
- otx2_err("Failed to allocate %d rx intr_vec",
- dev->configured_cints);
- return -ENOMEM;
- }
+ rc = rte_intr_vec_list_alloc(handle, "intr_vec",
+ dev->configured_cints);
+ if (rc) {
+ otx2_err("Fail to allocate intr vec list, "
+ "rc=%d", rc);
+ return rc;
}
/* VFIO vector zero is resereved for misc interrupt so
* doing required adjustment. (b13bfab4cd)
*/
- handle->intr_vec[q] = RTE_INTR_VEC_RXTX_OFFSET + vec;
+ if (rte_intr_vec_list_index_set(handle, q,
+ RTE_INTR_VEC_RXTX_OFFSET + vec))
+ return -1;
/* Configure CQE interrupt coalescing parameters */
otx2_write64(((CQ_CQE_THRESH_DEFAULT) |
oxt2_nix_unregister_cq_irqs(struct rte_eth_dev *eth_dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
int vec, q;
qdev->ops->common->slowpath_stop(edev);
qdev->ops->common->remove(edev);
- rte_intr_disable(&pci_dev->intr_handle);
+ rte_intr_disable(pci_dev->intr_handle);
- switch (pci_dev->intr_handle.type) {
+ switch (rte_intr_type_get(pci_dev->intr_handle)) {
case RTE_INTR_HANDLE_UIO_INTX:
case RTE_INTR_HANDLE_VFIO_LEGACY:
- rte_intr_callback_unregister(&pci_dev->intr_handle,
+ rte_intr_callback_unregister(pci_dev->intr_handle,
qede_interrupt_handler_intx,
(void *)eth_dev);
break;
default:
- rte_intr_callback_unregister(&pci_dev->intr_handle,
+ rte_intr_callback_unregister(pci_dev->intr_handle,
qede_interrupt_handler,
(void *)eth_dev);
}
}
qede_update_pf_params(edev);
- switch (pci_dev->intr_handle.type) {
+ switch (rte_intr_type_get(pci_dev->intr_handle)) {
case RTE_INTR_HANDLE_UIO_INTX:
case RTE_INTR_HANDLE_VFIO_LEGACY:
int_mode = ECORE_INT_MODE_INTA;
- rte_intr_callback_register(&pci_dev->intr_handle,
+ rte_intr_callback_register(pci_dev->intr_handle,
qede_interrupt_handler_intx,
(void *)eth_dev);
break;
default:
int_mode = ECORE_INT_MODE_MSIX;
- rte_intr_callback_register(&pci_dev->intr_handle,
+ rte_intr_callback_register(pci_dev->intr_handle,
qede_interrupt_handler,
(void *)eth_dev);
}
- if (rte_intr_enable(&pci_dev->intr_handle)) {
+ if (rte_intr_enable(pci_dev->intr_handle)) {
DP_ERR(edev, "rte_intr_enable() failed\n");
rc = -ENODEV;
goto err;
if (qmask & (1 << sa->mgmt_evq_index))
sfc_intr_handle_mgmt_evq(sa);
- if (rte_intr_ack(&pci_dev->intr_handle) != 0)
+ if (rte_intr_ack(pci_dev->intr_handle) != 0)
sfc_err(sa, "cannot reenable interrupts");
sfc_log_init(sa, "done");
sfc_intr_handle_mgmt_evq(sa);
- if (rte_intr_ack(&pci_dev->intr_handle) != 0)
+ if (rte_intr_ack(pci_dev->intr_handle) != 0)
sfc_err(sa, "cannot reenable interrupts");
sfc_log_init(sa, "done");
goto fail_intr_init;
pci_dev = RTE_ETH_DEV_TO_PCI(sa->eth_dev);
- intr_handle = &pci_dev->intr_handle;
+ intr_handle = pci_dev->intr_handle;
if (intr->handler != NULL) {
if (intr->rxq_intr && rte_intr_cap_multiple(intr_handle)) {
goto fail_rte_intr_efd_enable;
}
if (rte_intr_dp_is_en(intr_handle)) {
- intr_handle->intr_vec =
- rte_calloc("intr_vec",
- sa->eth_dev->data->nb_rx_queues, sizeof(int),
- 0);
- if (intr_handle->intr_vec == NULL) {
+ if (rte_intr_vec_list_alloc(intr_handle,
+ "intr_vec",
+ sa->eth_dev->data->nb_rx_queues)) {
sfc_err(sa,
"Failed to allocate %d rx_queues intr_vec",
sa->eth_dev->data->nb_rx_queues);
goto fail_intr_vector_alloc;
}
+
}
sfc_log_init(sa, "rte_intr_callback_register");
efx_intr_enable(sa->nic);
}
- sfc_log_init(sa, "done type=%u max_intr=%d nb_efd=%u vec=%p",
- intr_handle->type, intr_handle->max_intr,
- intr_handle->nb_efd, intr_handle->intr_vec);
+ sfc_log_init(sa, "done type=%u max_intr=%d nb_efd=%u",
+ rte_intr_type_get(intr_handle),
+ rte_intr_max_intr_get(intr_handle),
+ rte_intr_nb_efd_get(intr_handle));
return 0;
fail_rte_intr_enable:
rte_intr_callback_unregister(intr_handle, intr->handler, (void *)sa);
fail_rte_intr_cb_reg:
- rte_free(intr_handle->intr_vec);
+ rte_intr_vec_list_free(intr_handle);
fail_intr_vector_alloc:
rte_intr_efd_disable(intr_handle);
efx_intr_disable(sa->nic);
- intr_handle = &pci_dev->intr_handle;
+ intr_handle = pci_dev->intr_handle;
- rte_free(intr_handle->intr_vec);
+ rte_intr_vec_list_free(intr_handle);
rte_intr_efd_disable(intr_handle);
if (rte_intr_disable(intr_handle) != 0)
sfc_log_init(sa, "entry");
- switch (pci_dev->intr_handle.type) {
+ switch (rte_intr_type_get(pci_dev->intr_handle)) {
#ifdef RTE_EXEC_ENV_LINUX
case RTE_INTR_HANDLE_UIO_INTX:
case RTE_INTR_HANDLE_VFIO_LEGACY:
struct rte_eth_dev *dev = cb_arg;
struct pmd_internals *pmd = dev->data->dev_private;
- tap_nl_recv(pmd->intr_handle.fd, tap_nl_msg_handler, dev);
+ tap_nl_recv(rte_intr_fd_get(pmd->intr_handle),
+ tap_nl_msg_handler, dev);
}
static int
/* In any case, disable interrupt if the conf is no longer there. */
if (!dev->data->dev_conf.intr_conf.lsc) {
- if (pmd->intr_handle.fd != -1) {
+ if (rte_intr_fd_get(pmd->intr_handle) != -1)
goto clean;
- }
+
return 0;
}
if (set) {
- pmd->intr_handle.fd = tap_nl_init(RTMGRP_LINK);
- if (unlikely(pmd->intr_handle.fd == -1))
+ rte_intr_fd_set(pmd->intr_handle, tap_nl_init(RTMGRP_LINK));
+ if (unlikely(rte_intr_fd_get(pmd->intr_handle) == -1))
return -EBADF;
return rte_intr_callback_register(
- &pmd->intr_handle, tap_dev_intr_handler, dev);
+ pmd->intr_handle, tap_dev_intr_handler, dev);
}
clean:
do {
- ret = rte_intr_callback_unregister(&pmd->intr_handle,
+ ret = rte_intr_callback_unregister(pmd->intr_handle,
tap_dev_intr_handler, dev);
if (ret >= 0) {
break;
}
} while (true);
- tap_nl_final(pmd->intr_handle.fd);
- pmd->intr_handle.fd = -1;
+ tap_nl_final(rte_intr_fd_get(pmd->intr_handle));
+ rte_intr_fd_set(pmd->intr_handle, -1);
return 0;
}
goto error_exit;
}
+ /* Allocate interrupt instance */
+ pmd->intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED);
+ if (pmd->intr_handle == NULL) {
+ TAP_LOG(ERR, "Failed to allocate intr handle");
+ goto error_exit;
+ }
+
/* Setup some default values */
data = dev->data;
data->dev_private = pmd;
dev->rx_pkt_burst = pmd_rx_burst;
dev->tx_pkt_burst = pmd_tx_burst;
- pmd->intr_handle.type = RTE_INTR_HANDLE_EXT;
- pmd->intr_handle.fd = -1;
- dev->intr_handle = &pmd->intr_handle;
+ rte_intr_type_set(pmd->intr_handle, RTE_INTR_HANDLE_EXT);
+ rte_intr_fd_set(pmd->intr_handle, -1);
+ dev->intr_handle = pmd->intr_handle;
/* Presetup the fds to -1 as being not valid */
for (i = 0; i < RTE_PMD_TAP_MAX_QUEUES; i++) {
/* mac_addrs must not be freed alone because part of dev_private */
dev->data->mac_addrs = NULL;
rte_eth_dev_release_port(dev);
+ rte_intr_instance_free(pmd->intr_handle);
error_exit_nodev:
TAP_LOG(ERR, "%s Unable to initialize %s",
LIST_HEAD(tap_implicit_flows, rte_flow) implicit_flows;
struct rx_queue rxq[RTE_PMD_TAP_MAX_QUEUES]; /* List of RX queues */
struct tx_queue txq[RTE_PMD_TAP_MAX_QUEUES]; /* List of TX queues */
- struct rte_intr_handle intr_handle; /* LSC interrupt handle. */
+ struct rte_intr_handle *intr_handle; /* LSC interrupt handle. */
int ka_fd; /* keep-alive file descriptor */
struct rte_mempool *gso_ctx_mp; /* Mempool for GSO packets */
};
tap_rx_intr_vec_uninstall(struct rte_eth_dev *dev)
{
struct pmd_internals *pmd = dev->data->dev_private;
- struct rte_intr_handle *intr_handle = &pmd->intr_handle;
+ struct rte_intr_handle *intr_handle = pmd->intr_handle;
rte_intr_free_epoll_fd(intr_handle);
- free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
- intr_handle->nb_efd = 0;
+ rte_intr_vec_list_free(intr_handle);
+ rte_intr_nb_efd_set(intr_handle, 0);
+
+ rte_intr_instance_free(intr_handle);
}
/**
struct pmd_internals *pmd = dev->data->dev_private;
struct pmd_process_private *process_private = dev->process_private;
unsigned int rxqs_n = pmd->dev->data->nb_rx_queues;
- struct rte_intr_handle *intr_handle = &pmd->intr_handle;
+ struct rte_intr_handle *intr_handle = pmd->intr_handle;
unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
unsigned int i;
unsigned int count = 0;
if (!dev->data->dev_conf.intr_conf.rxq)
return 0;
- intr_handle->intr_vec = malloc(sizeof(int) * rxqs_n);
- if (intr_handle->intr_vec == NULL) {
+
+ if (rte_intr_vec_list_alloc(intr_handle, NULL, rxqs_n)) {
rte_errno = ENOMEM;
TAP_LOG(ERR,
"failed to allocate memory for interrupt vector,"
/* Skip queues that cannot request interrupts. */
if (!rxq || process_private->rxq_fds[i] == -1) {
/* Use invalid intr_vec[] index to disable entry. */
- intr_handle->intr_vec[i] =
- RTE_INTR_VEC_RXTX_OFFSET +
- RTE_MAX_RXTX_INTR_VEC_ID;
+ if (rte_intr_vec_list_index_set(intr_handle, i,
+ RTE_INTR_VEC_RXTX_OFFSET + RTE_MAX_RXTX_INTR_VEC_ID))
+ return -rte_errno;
continue;
}
- intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
- intr_handle->efds[count] = process_private->rxq_fds[i];
+ if (rte_intr_vec_list_index_set(intr_handle, i,
+ RTE_INTR_VEC_RXTX_OFFSET + count))
+ return -rte_errno;
+ if (rte_intr_efds_index_set(intr_handle, count,
+ process_private->rxq_fds[i]))
+ return -rte_errno;
count++;
}
if (!count)
tap_rx_intr_vec_uninstall(dev);
- else
- intr_handle->nb_efd = count;
+ else if (rte_intr_nb_efd_set(intr_handle, count))
+ return -rte_errno;
return 0;
}
nicvf_periodic_alarm_stop(nicvf_vf_interrupt, nic->snicvf[i]);
}
+ rte_intr_instance_free(nic->intr_handle);
+
return 0;
}
goto fail;
}
+ /* Allocate interrupt instance */
+ nic->intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED);
+ if (nic->intr_handle == NULL) {
+ PMD_INIT_LOG(ERR, "Failed to allocate intr handle");
+ ret = -ENODEV;
+ goto fail;
+ }
+
nicvf_disable_all_interrupts(nic);
ret = nicvf_periodic_alarm_start(nicvf_interrupt, eth_dev);
uint16_t subsystem_vendor_id;
struct nicvf_rbdr *rbdr;
struct nicvf_rss_reta_info rss_info;
- struct rte_intr_handle intr_handle;
+ struct rte_intr_handle *intr_handle;
uint8_t cpi_alg;
uint16_t mtu;
int skip_bytes;
struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(eth_dev);
struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
struct txgbe_bw_conf *bw_conf = TXGBE_DEV_BW_CONF(eth_dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
const struct rte_memzone *mz;
uint32_t ctrl_ext;
uint16_t csum;
struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
uint32_t intr_vector = 0;
int err;
bool link_up = false, negotiate = 0;
return -1;
}
- if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
- intr_handle->intr_vec =
- rte_zmalloc("intr_vec",
- dev->data->nb_rx_queues * sizeof(int), 0);
- if (intr_handle->intr_vec == NULL) {
+ if (rte_intr_dp_is_en(intr_handle)) {
+ if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
+ dev->data->nb_rx_queues)) {
PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
" intr_vec", dev->data->nb_rx_queues);
return -ENOMEM;
}
}
-
/* confiugre msix for sleep until rx interrupt */
txgbe_configure_msix(dev);
struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
int vf;
struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev);
/* Clean datapath event and queue/vec mapping */
rte_intr_efd_disable(intr_handle);
- if (intr_handle->intr_vec != NULL) {
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
- }
+ rte_intr_vec_list_free(intr_handle);
/* reset hierarchy commit */
tm_conf->committed = false;
{
struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
int retries = 0;
int ret;
struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
- if (intr_handle->type != RTE_INTR_HANDLE_UIO &&
- intr_handle->type != RTE_INTR_HANDLE_VFIO_MSIX)
+ if (rte_intr_type_get(intr_handle) != RTE_INTR_HANDLE_UIO &&
+ rte_intr_type_get(intr_handle) != RTE_INTR_HANDLE_VFIO_MSIX)
wr32(hw, TXGBE_PX_INTA, 1);
/* clear all cause mask */
{
struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
uint32_t eicr;
txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
uint32_t mask;
struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
txgbe_configure_msix(struct rte_eth_dev *dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
uint32_t queue_id, base = TXGBE_MISC_VEC_ID;
uint32_t vec = TXGBE_MISC_VEC_ID;
queue_id++) {
/* by default, 1:1 mapping */
txgbe_set_ivar_map(hw, 0, queue_id, vec);
- intr_handle->intr_vec[queue_id] = vec;
- if (vec < base + intr_handle->nb_efd - 1)
+ rte_intr_vec_list_index_set(intr_handle,
+ queue_id, vec);
+ if (vec < base + rte_intr_nb_efd_get(intr_handle)
+ - 1)
vec++;
}
int err;
uint32_t tc, tcs;
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(eth_dev);
struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(eth_dev);
struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
uint32_t intr_vector = 0;
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
int err, mask = 0;
return -1;
}
- if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
- intr_handle->intr_vec =
- rte_zmalloc("intr_vec",
- dev->data->nb_rx_queues * sizeof(int), 0);
- if (intr_handle->intr_vec == NULL) {
+ if (rte_intr_dp_is_en(intr_handle)) {
+ if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
+ dev->data->nb_rx_queues)) {
PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
" intr_vec", dev->data->nb_rx_queues);
return -ENOMEM;
struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
if (hw->adapter_stopped)
return 0;
/* Clean datapath event and queue/vec mapping */
rte_intr_efd_disable(intr_handle);
- if (intr_handle->intr_vec != NULL) {
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
- }
+ rte_intr_vec_list_free(intr_handle);
adapter->rss_reta_updated = 0;
hw->dev_start = false;
{
struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
int ret;
PMD_INIT_FUNC_TRACE();
txgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
uint32_t vec = TXGBE_MISC_VEC_ID;
struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
uint32_t vec = TXGBE_MISC_VEC_ID;
if (rte_intr_allow_others(intr_handle))
txgbevf_configure_msix(struct rte_eth_dev *dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
- struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
uint32_t q_idx;
uint32_t vector_idx = TXGBE_MISC_VEC_ID;
* as TXGBE_VF_MAXMSIVECOTR = 1
*/
txgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
- intr_handle->intr_vec[q_idx] = vector_idx;
- if (vector_idx < base + intr_handle->nb_efd - 1)
+ rte_intr_vec_list_index_set(intr_handle, q_idx,
+ vector_idx);
+ if (vector_idx < base + rte_intr_nb_efd_get(intr_handle)
+ - 1)
vector_idx++;
}
eth_vhost_update_intr(struct rte_eth_dev *eth_dev, uint16_t rxq_idx)
{
struct rte_intr_handle *handle = eth_dev->intr_handle;
- struct rte_epoll_event rev;
+ struct rte_epoll_event rev, *elist;
int epfd, ret;
- if (!handle)
+ if (handle == NULL)
return 0;
- if (handle->efds[rxq_idx] == handle->elist[rxq_idx].fd)
+ elist = rte_intr_elist_index_get(handle, rxq_idx);
+ if (rte_intr_efds_index_get(handle, rxq_idx) == elist->fd)
return 0;
VHOST_LOG(INFO, "kickfd for rxq-%d was changed, updating handler.\n",
rxq_idx);
- if (handle->elist[rxq_idx].fd != -1)
+ if (elist->fd != -1)
VHOST_LOG(ERR, "Unexpected previous kickfd value (Got %d, expected -1).\n",
- handle->elist[rxq_idx].fd);
+ elist->fd);
/*
* First remove invalid epoll event, and then install
* the new one. May be solved with a proper API in the
* future.
*/
- epfd = handle->elist[rxq_idx].epfd;
- rev = handle->elist[rxq_idx];
+ epfd = elist->epfd;
+ rev = *elist;
ret = rte_epoll_ctl(epfd, EPOLL_CTL_DEL, rev.fd,
- &handle->elist[rxq_idx]);
+ elist);
if (ret) {
VHOST_LOG(ERR, "Delete epoll event failed.\n");
return ret;
}
- rev.fd = handle->efds[rxq_idx];
- handle->elist[rxq_idx] = rev;
- ret = rte_epoll_ctl(epfd, EPOLL_CTL_ADD, rev.fd,
- &handle->elist[rxq_idx]);
+ rev.fd = rte_intr_efds_index_get(handle, rxq_idx);
+ if (rte_intr_elist_index_set(handle, rxq_idx, rev))
+ return -rte_errno;
+
+ elist = rte_intr_elist_index_get(handle, rxq_idx);
+ ret = rte_epoll_ctl(epfd, EPOLL_CTL_ADD, rev.fd, elist);
if (ret) {
VHOST_LOG(ERR, "Add epoll event failed.\n");
return ret;
{
struct rte_intr_handle *intr_handle = dev->intr_handle;
- if (intr_handle) {
- if (intr_handle->intr_vec)
- free(intr_handle->intr_vec);
- free(intr_handle);
+ if (intr_handle != NULL) {
+ rte_intr_vec_list_free(intr_handle);
+ rte_intr_instance_free(intr_handle);
}
-
dev->intr_handle = NULL;
}
int ret;
/* uninstall firstly if we are reconnecting */
- if (dev->intr_handle)
+ if (dev->intr_handle != NULL)
eth_vhost_uninstall_intr(dev);
- dev->intr_handle = malloc(sizeof(*dev->intr_handle));
- if (!dev->intr_handle) {
+ dev->intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_PRIVATE);
+ if (dev->intr_handle == NULL) {
VHOST_LOG(ERR, "Fail to allocate intr_handle\n");
return -ENOMEM;
}
- memset(dev->intr_handle, 0, sizeof(*dev->intr_handle));
-
- dev->intr_handle->efd_counter_size = sizeof(uint64_t);
+ if (rte_intr_efd_counter_size_set(dev->intr_handle, sizeof(uint64_t)))
+ return -rte_errno;
- dev->intr_handle->intr_vec =
- malloc(nb_rxq * sizeof(dev->intr_handle->intr_vec[0]));
-
- if (!dev->intr_handle->intr_vec) {
+ if (rte_intr_vec_list_alloc(dev->intr_handle, NULL, nb_rxq)) {
VHOST_LOG(ERR,
"Failed to allocate memory for interrupt vector\n");
- free(dev->intr_handle);
+ rte_intr_instance_free(dev->intr_handle);
return -ENOMEM;
}
+
VHOST_LOG(INFO, "Prepare intr vec\n");
for (i = 0; i < nb_rxq; i++) {
- dev->intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + i;
- dev->intr_handle->efds[i] = -1;
+ if (rte_intr_vec_list_index_set(dev->intr_handle, i, RTE_INTR_VEC_RXTX_OFFSET + i))
+ return -rte_errno;
+ if (rte_intr_efds_index_set(dev->intr_handle, i, -1))
+ return -rte_errno;
vq = dev->data->rx_queues[i];
if (!vq) {
VHOST_LOG(INFO, "rxq-%d not setup yet, skip!\n", i);
"rxq-%d's kickfd is invalid, skip!\n", i);
continue;
}
- dev->intr_handle->efds[i] = vring.kickfd;
+
+ if (rte_intr_efds_index_set(dev->intr_handle, i, vring.kickfd))
+ continue;
VHOST_LOG(INFO, "Installed intr vec for rxq-%d\n", i);
}
- dev->intr_handle->nb_efd = nb_rxq;
- dev->intr_handle->max_intr = nb_rxq + 1;
- dev->intr_handle->type = RTE_INTR_HANDLE_VDEV;
+ if (rte_intr_nb_efd_set(dev->intr_handle, nb_rxq))
+ return -rte_errno;
+
+ if (rte_intr_max_intr_set(dev->intr_handle, nb_rxq + 1))
+ return -rte_errno;
+
+ if (rte_intr_type_set(dev->intr_handle, RTE_INTR_HANDLE_VDEV))
+ return -rte_errno;
return 0;
}
vring_id);
return ret;
}
- eth_dev->intr_handle->efds[rx_idx] = vring.kickfd;
+
+ if (rte_intr_efds_index_set(eth_dev->intr_handle, rx_idx,
+ vring.kickfd))
+ return -rte_errno;
vq = eth_dev->data->rx_queues[rx_idx];
if (!vq) {
if (intr_conf->lsc || intr_conf->rxq) {
virtio_intr_disable(dev);
rte_intr_efd_disable(dev->intr_handle);
- rte_free(dev->intr_handle->intr_vec);
- dev->intr_handle->intr_vec = NULL;
+ rte_intr_vec_list_free(dev->intr_handle);
}
virtio_reset(hw);
PMD_INIT_LOG(INFO, "queue/interrupt binding");
for (i = 0; i < dev->data->nb_rx_queues; ++i) {
- dev->intr_handle->intr_vec[i] = i + 1;
+ if (rte_intr_vec_list_index_set(dev->intr_handle, i,
+ i + 1))
+ return -rte_errno;
if (VIRTIO_OPS(hw)->set_queue_irq(hw, hw->vqs[i * 2], i + 1) ==
VIRTIO_MSI_NO_VECTOR) {
PMD_DRV_LOG(ERR, "failed to set queue vector");
return -1;
}
- if (!dev->intr_handle->intr_vec) {
- dev->intr_handle->intr_vec =
- rte_zmalloc("intr_vec",
- hw->max_queue_pairs * sizeof(int), 0);
- if (!dev->intr_handle->intr_vec) {
- PMD_INIT_LOG(ERR, "Failed to allocate %u rxq vectors",
- hw->max_queue_pairs);
- return -ENOMEM;
- }
+ if (rte_intr_vec_list_alloc(dev->intr_handle, "intr_vec",
+ hw->max_queue_pairs)) {
+ PMD_INIT_LOG(ERR, "Failed to allocate %u rxq vectors",
+ hw->max_queue_pairs);
+ return -ENOMEM;
}
if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) {
uint32_t i;
struct rte_eth_dev *eth_dev = &rte_eth_devices[dev->hw.port_id];
- if (!eth_dev->intr_handle) {
- eth_dev->intr_handle = malloc(sizeof(*eth_dev->intr_handle));
- if (!eth_dev->intr_handle) {
+ if (eth_dev->intr_handle == NULL) {
+ eth_dev->intr_handle =
+ rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_PRIVATE);
+ if (eth_dev->intr_handle == NULL) {
PMD_DRV_LOG(ERR, "(%s) failed to allocate intr_handle", dev->path);
return -1;
}
- memset(eth_dev->intr_handle, 0, sizeof(*eth_dev->intr_handle));
}
- for (i = 0; i < dev->max_queue_pairs; ++i)
- eth_dev->intr_handle->efds[i] = dev->callfds[2 * i];
- eth_dev->intr_handle->nb_efd = dev->max_queue_pairs;
- eth_dev->intr_handle->max_intr = dev->max_queue_pairs + 1;
- eth_dev->intr_handle->type = RTE_INTR_HANDLE_VDEV;
+ for (i = 0; i < dev->max_queue_pairs; ++i) {
+ if (rte_intr_efds_index_set(eth_dev->intr_handle, i,
+ dev->callfds[i]))
+ return -rte_errno;
+ }
+
+ if (rte_intr_nb_efd_set(eth_dev->intr_handle, dev->max_queue_pairs))
+ return -rte_errno;
+
+ if (rte_intr_max_intr_set(eth_dev->intr_handle,
+ dev->max_queue_pairs + 1))
+ return -rte_errno;
+
+ if (rte_intr_type_set(eth_dev->intr_handle, RTE_INTR_HANDLE_VDEV))
+ return -rte_errno;
+
/* For virtio vdev, no need to read counter for clean */
- eth_dev->intr_handle->efd_counter_size = 0;
- eth_dev->intr_handle->fd = dev->ops->get_intr_fd(dev);
+ if (rte_intr_efd_counter_size_set(eth_dev->intr_handle, 0))
+ return -rte_errno;
+
+ if (rte_intr_fd_set(eth_dev->intr_handle, dev->ops->get_intr_fd(dev)))
+ return -rte_errno;
return 0;
}
{
struct rte_eth_dev *eth_dev = &rte_eth_devices[dev->hw.port_id];
- if (eth_dev->intr_handle) {
- free(eth_dev->intr_handle);
- eth_dev->intr_handle = NULL;
- }
+ rte_intr_instance_free(eth_dev->intr_handle);
+ eth_dev->intr_handle = NULL;
virtio_user_stop_device(dev);
return;
}
PMD_DRV_LOG(DEBUG, "Unregistering intr fd: %d",
- eth_dev->intr_handle->fd);
+ rte_intr_fd_get(eth_dev->intr_handle));
if (rte_intr_callback_unregister(eth_dev->intr_handle,
virtio_interrupt_handler,
eth_dev) != 1)
if (dev->ops->server_disconnect)
dev->ops->server_disconnect(dev);
- eth_dev->intr_handle->fd = dev->ops->get_intr_fd(dev);
+ rte_intr_fd_set(eth_dev->intr_handle,
+ dev->ops->get_intr_fd(dev));
PMD_DRV_LOG(DEBUG, "Registering intr fd: %d",
- eth_dev->intr_handle->fd);
+ rte_intr_fd_get(eth_dev->intr_handle));
if (rte_intr_callback_register(eth_dev->intr_handle,
virtio_interrupt_handler,
struct rte_eth_dev *eth_dev = &rte_eth_devices[dev->hw.port_id];
PMD_DRV_LOG(DEBUG, "Unregistering intr fd: %d",
- eth_dev->intr_handle->fd);
+ rte_intr_fd_get(eth_dev->intr_handle));
if (rte_intr_callback_unregister(eth_dev->intr_handle,
virtio_interrupt_handler,
eth_dev) != 1)
PMD_DRV_LOG(ERR, "interrupt unregister failed");
- eth_dev->intr_handle->fd = dev->ops->get_intr_fd(dev);
+ rte_intr_fd_set(eth_dev->intr_handle, dev->ops->get_intr_fd(dev));
- PMD_DRV_LOG(DEBUG, "Registering intr fd: %d", eth_dev->intr_handle->fd);
+ PMD_DRV_LOG(DEBUG, "Registering intr fd: %d",
+ rte_intr_fd_get(eth_dev->intr_handle));
if (rte_intr_callback_register(eth_dev->intr_handle,
virtio_interrupt_handler, eth_dev))
return -1;
}
- if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
- intr_handle->intr_vec =
- rte_zmalloc("intr_vec",
- dev->data->nb_rx_queues * sizeof(int), 0);
- if (intr_handle->intr_vec == NULL) {
+ if (rte_intr_dp_is_en(intr_handle)) {
+ if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
+ dev->data->nb_rx_queues)) {
PMD_INIT_LOG(ERR, "Failed to allocate %d Rx queues intr_vec",
dev->data->nb_rx_queues);
rte_intr_efd_disable(intr_handle);
if (!rte_intr_allow_others(intr_handle) &&
dev->data->dev_conf.intr_conf.lsc != 0) {
PMD_INIT_LOG(ERR, "not enough intr vector to support both Rx interrupt and LSC");
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
+ rte_intr_vec_list_free(intr_handle);
rte_intr_efd_disable(intr_handle);
return -1;
}
/* if we cannot allocate one MSI-X vector per queue, don't enable
* interrupt mode.
*/
- if (hw->intr.num_intrs != (intr_handle->nb_efd + 1)) {
+ if (hw->intr.num_intrs !=
+ (rte_intr_nb_efd_get(intr_handle) + 1)) {
PMD_INIT_LOG(ERR, "Device configured with %d Rx intr vectors, expecting %d",
- hw->intr.num_intrs, intr_handle->nb_efd + 1);
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
+ hw->intr.num_intrs,
+ rte_intr_nb_efd_get(intr_handle) + 1);
+ rte_intr_vec_list_free(intr_handle);
rte_intr_efd_disable(intr_handle);
return -1;
}
for (i = 0; i < dev->data->nb_rx_queues; i++)
- intr_handle->intr_vec[i] = i + 1;
+ if (rte_intr_vec_list_index_set(intr_handle, i, i + 1))
+ return -rte_errno;
for (i = 0; i < hw->intr.num_intrs; i++)
hw->intr.mod_levels[i] = UPT1_IML_ADAPTIVE;
if (hw->intr.lsc_only)
tqd->conf.intrIdx = 1;
else
- tqd->conf.intrIdx = intr_handle->intr_vec[i];
+ tqd->conf.intrIdx =
+ rte_intr_vec_list_index_get(intr_handle,
+ i);
tqd->status.stopped = TRUE;
tqd->status.error = 0;
memset(&tqd->stats, 0, sizeof(tqd->stats));
if (hw->intr.lsc_only)
rqd->conf.intrIdx = 1;
else
- rqd->conf.intrIdx = intr_handle->intr_vec[i];
+ rqd->conf.intrIdx =
+ rte_intr_vec_list_index_get(intr_handle,
+ i);
rqd->status.stopped = TRUE;
rqd->status.error = 0;
memset(&rqd->stats, 0, sizeof(rqd->stats));
/* Clean datapath event and queue/vector mapping */
rte_intr_efd_disable(intr_handle);
- if (intr_handle->intr_vec != NULL) {
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
- }
+ rte_intr_vec_list_free(intr_handle);
/* quiesce the device first */
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
{
struct vmxnet3_hw *hw = dev->data->dev_private;
- vmxnet3_enable_intr(hw, dev->intr_handle->intr_vec[queue_id]);
+ vmxnet3_enable_intr(hw,
+ rte_intr_vec_list_index_get(dev->intr_handle,
+ queue_id));
return 0;
}
{
struct vmxnet3_hw *hw = dev->data->dev_private;
- vmxnet3_disable_intr(hw, dev->intr_handle->intr_vec[queue_id]);
+ vmxnet3_disable_intr(hw,
+ rte_intr_vec_list_index_get(dev->intr_handle, queue_id));
return 0;
}
#define IFPGA_MAX_IRQ 12
/* 0 for FME interrupt, others are reserved for AFU irq */
-static struct rte_intr_handle ifpga_irq_handle[IFPGA_MAX_IRQ];
+static struct rte_intr_handle *ifpga_irq_handle[IFPGA_MAX_IRQ];
static struct ifpga_rawdev *
ifpga_rawdev_allocate(struct rte_rawdev *rawdev);
int vec_start, rte_intr_callback_fn handler, void *arg)
{
struct rte_intr_handle *intr_handle;
+ int rc, i;
if (type == IFPGA_FME_IRQ)
- intr_handle = &ifpga_irq_handle[0];
+ intr_handle = ifpga_irq_handle[0];
else if (type == IFPGA_AFU_IRQ)
- intr_handle = &ifpga_irq_handle[vec_start + 1];
+ intr_handle = ifpga_irq_handle[vec_start + 1];
else
return 0;
rte_intr_efd_disable(intr_handle);
- return rte_intr_callback_unregister(intr_handle, handler, arg);
+ rc = rte_intr_callback_unregister(intr_handle, handler, arg);
+
+ for (i = 0; i < IFPGA_MAX_IRQ; i++)
+ rte_intr_instance_free(ifpga_irq_handle[i]);
+ return rc;
}
int
struct opae_adapter *adapter;
struct opae_manager *mgr;
struct opae_accelerator *acc;
+ int *intr_efds = NULL, nb_intr, i;
+
+ for (i = 0; i < IFPGA_MAX_IRQ; i++) {
+ ifpga_irq_handle[i] =
+ rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_PRIVATE);
+ if (ifpga_irq_handle[i] == NULL)
+ return -ENOMEM;
+ }
adapter = ifpga_rawdev_get_priv(dev);
if (!adapter)
return -ENODEV;
if (type == IFPGA_FME_IRQ) {
- intr_handle = &ifpga_irq_handle[0];
+ intr_handle = ifpga_irq_handle[0];
count = 1;
} else if (type == IFPGA_AFU_IRQ) {
- intr_handle = &ifpga_irq_handle[vec_start + 1];
+ intr_handle = ifpga_irq_handle[vec_start + 1];
} else {
return -EINVAL;
}
- intr_handle->type = RTE_INTR_HANDLE_VFIO_MSIX;
+ if (rte_intr_type_set(intr_handle, RTE_INTR_HANDLE_VFIO_MSIX))
+ return -rte_errno;
ret = rte_intr_efd_enable(intr_handle, count);
if (ret)
return -ENODEV;
- intr_handle->fd = intr_handle->efds[0];
+ if (rte_intr_fd_set(intr_handle,
+ rte_intr_efds_index_get(intr_handle, 0)))
+ return -rte_errno;
IFPGA_RAWDEV_PMD_DEBUG("register %s irq, vfio_fd=%d, fd=%d\n",
- name, intr_handle->vfio_dev_fd,
- intr_handle->fd);
+ name, rte_intr_dev_fd_get(intr_handle),
+ rte_intr_fd_get(intr_handle));
if (type == IFPGA_FME_IRQ) {
struct fpga_fme_err_irq_set err_irq_set;
- err_irq_set.evtfd = intr_handle->efds[0];
+ err_irq_set.evtfd = rte_intr_efds_index_get(intr_handle,
+ 0);
ret = opae_manager_ifpga_set_err_irq(mgr, &err_irq_set);
if (ret)
if (!acc)
return -EINVAL;
- ret = opae_acc_set_irq(acc, vec_start, count,
- intr_handle->efds);
- if (ret)
+ nb_intr = rte_intr_nb_intr_get(intr_handle);
+
+ intr_efds = calloc(nb_intr, sizeof(int));
+ if (!intr_efds)
+ return -ENOMEM;
+
+ for (i = 0; i < nb_intr; i++)
+ intr_efds[i] = rte_intr_efds_index_get(intr_handle, i);
+
+ ret = opae_acc_set_irq(acc, vec_start, count, intr_efds);
+ if (ret) {
+ free(intr_efds);
return -EINVAL;
+ }
}
/* register interrupt handler using DPDK API */
ret = rte_intr_callback_register(intr_handle,
handler, (void *)arg);
- if (ret)
+ if (ret) {
+ free(intr_efds);
return -EINVAL;
+ }
IFPGA_RAWDEV_PMD_INFO("success register %s interrupt\n", name);
+ free(intr_efds);
return 0;
}
data->bus = pci_dev->addr.bus;
data->devid = pci_dev->addr.devid;
data->function = pci_dev->addr.function;
- data->vfio_dev_fd = pci_dev->intr_handle.vfio_dev_fd;
+ data->vfio_dev_fd = rte_intr_dev_fd_get(pci_dev->intr_handle);
adapter = rawdev->dev_private;
/* create a opae_adapter based on above device data */
ntb_queue_release(dev, i);
hw->queue_pairs = 0;
- intr_handle = &hw->pci_dev->intr_handle;
+ intr_handle = hw->pci_dev->intr_handle;
/* Clean datapath event and vec mapping */
rte_intr_efd_disable(intr_handle);
- if (intr_handle->intr_vec) {
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
- }
+ rte_intr_vec_list_free(intr_handle);
/* Disable uio intr before callback unregister */
rte_intr_disable(intr_handle);
/* Init doorbell. */
hw->db_valid_mask = RTE_LEN2MASK(hw->db_cnt, uint64_t);
- intr_handle = &pci_dev->intr_handle;
+ intr_handle = pci_dev->intr_handle;
/* Register callback func to eal lib */
rte_intr_callback_register(intr_handle,
ntb_dev_intr_handler, dev);
uintptr_t base)
{
struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
/* Disable error interrupts */
otx2_write64(~0ull, base + OTX2_REE_LF_MISC_INT_ENA_W1C);
uintptr_t base)
{
struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
int ret;
/* Disable error interrupts */
if (rte_pci_map_device(dev))
goto err;
- internal->vfio_dev_fd = dev->intr_handle.vfio_dev_fd;
+ internal->vfio_dev_fd = rte_intr_dev_fd_get(dev->intr_handle);
for (i = 0; i < RTE_MIN(PCI_MAX_RESOURCE, IFCVF_PCI_MAX_RESOURCE);
i++) {
irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX;
irq_set->start = 0;
fd_ptr = (int *)&irq_set->data;
- fd_ptr[RTE_INTR_VEC_ZERO_OFFSET] = internal->pdev->intr_handle.fd;
+ fd_ptr[RTE_INTR_VEC_ZERO_OFFSET] =
+ rte_intr_fd_get(internal->pdev->intr_handle);
for (i = 0; i < nr_vring; i++)
internal->intr_fd[i] = -1;
DRV_LOG(ERR, "Failed to allocate VAR %u.", errno);
goto error;
}
+ priv->err_intr_handle =
+ rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED);
+ if (priv->err_intr_handle == NULL) {
+ DRV_LOG(ERR, "Fail to allocate intr_handle");
+ goto error;
+ }
priv->vdev = rte_vdpa_register_device(cdev->dev, &mlx5_vdpa_ops);
if (priv->vdev == NULL) {
DRV_LOG(ERR, "Failed to register vDPA device.");
if (priv) {
if (priv->var)
mlx5_glue->dv_free_var(priv->var);
+ rte_intr_instance_free(priv->err_intr_handle);
rte_free(priv);
}
return -rte_errno;
if (priv->vdev)
rte_vdpa_unregister_device(priv->vdev);
pthread_mutex_destroy(&priv->vq_config_lock);
+ rte_intr_instance_free(priv->err_intr_handle);
rte_free(priv);
}
return 0;
void *buf;
uint32_t size;
} umems[3];
- struct rte_intr_handle intr_handle;
+ struct rte_intr_handle *intr_handle;
uint64_t err_time[3]; /* RDTSC time of recent errors. */
uint32_t n_retry;
struct mlx5_devx_virtio_q_couners_attr reset;
struct mlx5dv_devx_event_channel *eventc;
struct mlx5dv_devx_event_channel *err_chnl;
struct mlx5dv_devx_uar *uar;
- struct rte_intr_handle err_intr_handle;
+ struct rte_intr_handle *err_intr_handle;
struct mlx5_devx_obj *td;
struct mlx5_devx_obj *tiss[16]; /* TIS list for each LAG port. */
uint16_t nr_virtqs;
DRV_LOG(ERR, "Failed to change device event channel FD.");
goto error;
}
- priv->err_intr_handle.fd = priv->err_chnl->fd;
- priv->err_intr_handle.type = RTE_INTR_HANDLE_EXT;
- if (rte_intr_callback_register(&priv->err_intr_handle,
+
+ if (rte_intr_fd_set(priv->err_intr_handle, priv->err_chnl->fd))
+ goto error;
+
+ if (rte_intr_type_set(priv->err_intr_handle, RTE_INTR_HANDLE_EXT))
+ goto error;
+
+ if (rte_intr_callback_register(priv->err_intr_handle,
mlx5_vdpa_err_interrupt_handler,
priv)) {
- priv->err_intr_handle.fd = 0;
+ rte_intr_fd_set(priv->err_intr_handle, 0);
DRV_LOG(ERR, "Failed to register error interrupt for device %d.",
priv->vid);
goto error;
int retries = MLX5_VDPA_INTR_RETRIES;
int ret = -EAGAIN;
- if (!priv->err_intr_handle.fd)
+ if (!rte_intr_fd_get(priv->err_intr_handle))
return;
while (retries-- && ret == -EAGAIN) {
- ret = rte_intr_callback_unregister(&priv->err_intr_handle,
+ ret = rte_intr_callback_unregister(priv->err_intr_handle,
mlx5_vdpa_err_interrupt_handler,
priv);
if (ret == -EAGAIN) {
DRV_LOG(DEBUG, "Try again to unregister fd %d "
"of error interrupt, retries = %d.",
- priv->err_intr_handle.fd, retries);
+ rte_intr_fd_get(priv->err_intr_handle),
+ retries);
rte_pause();
}
}
- memset(&priv->err_intr_handle, 0, sizeof(priv->err_intr_handle));
if (priv->err_chnl) {
#ifdef HAVE_IBV_DEVX_EVENT
union {
int nbytes;
do {
- nbytes = read(virtq->intr_handle.fd, &buf, 8);
+ nbytes = read(rte_intr_fd_get(virtq->intr_handle), &buf,
+ 8);
if (nbytes < 0) {
if (errno == EINTR ||
errno == EWOULDBLOCK ||
int retries = MLX5_VDPA_INTR_RETRIES;
int ret = -EAGAIN;
- if (virtq->intr_handle.fd != -1) {
+ if (rte_intr_fd_get(virtq->intr_handle) != -1) {
while (retries-- && ret == -EAGAIN) {
- ret = rte_intr_callback_unregister(&virtq->intr_handle,
+ ret = rte_intr_callback_unregister(virtq->intr_handle,
mlx5_vdpa_virtq_handler,
virtq);
if (ret == -EAGAIN) {
DRV_LOG(DEBUG, "Try again to unregister fd %d "
- "of virtq %d interrupt, retries = %d.",
- virtq->intr_handle.fd,
- (int)virtq->index, retries);
+ "of virtq %d interrupt, retries = %d.",
+ rte_intr_fd_get(virtq->intr_handle),
+ (int)virtq->index, retries);
+
usleep(MLX5_VDPA_INTR_RETRIES_USEC);
}
}
- virtq->intr_handle.fd = -1;
+ rte_intr_fd_set(virtq->intr_handle, -1);
}
+ rte_intr_instance_free(virtq->intr_handle);
if (virtq->virtq) {
ret = mlx5_vdpa_virtq_stop(virtq->priv, virtq->index);
if (ret)
virtq->priv = priv;
rte_write32(virtq->index, priv->virtq_db_addr);
/* Setup doorbell mapping. */
- virtq->intr_handle.fd = vq.kickfd;
- if (virtq->intr_handle.fd == -1) {
+ virtq->intr_handle =
+ rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED);
+ if (virtq->intr_handle == NULL) {
+ DRV_LOG(ERR, "Fail to allocate intr_handle");
+ goto error;
+ }
+
+ if (rte_intr_fd_set(virtq->intr_handle, vq.kickfd))
+ goto error;
+
+ if (rte_intr_fd_get(virtq->intr_handle) == -1) {
DRV_LOG(WARNING, "Virtq %d kickfd is invalid.", index);
} else {
- virtq->intr_handle.type = RTE_INTR_HANDLE_EXT;
- if (rte_intr_callback_register(&virtq->intr_handle,
+ if (rte_intr_type_set(virtq->intr_handle, RTE_INTR_HANDLE_EXT))
+ goto error;
+
+ if (rte_intr_callback_register(virtq->intr_handle,
mlx5_vdpa_virtq_handler,
virtq)) {
- virtq->intr_handle.fd = -1;
+ rte_intr_fd_set(virtq->intr_handle, -1);
DRV_LOG(ERR, "Failed to register virtq %d interrupt.",
index);
goto error;
} else {
DRV_LOG(DEBUG, "Register fd %d interrupt for virtq %d.",
- virtq->intr_handle.fd, index);
+ rte_intr_fd_get(virtq->intr_handle),
+ index);
}
}
/* Subscribe virtq error event. */
if (ret)
return -1;
- if (vq.size != virtq->vq_size || vq.kickfd != virtq->intr_handle.fd)
+ if (vq.size != virtq->vq_size || vq.kickfd !=
+ rte_intr_fd_get(virtq->intr_handle))
return 1;
if (virtq->eqp.cq.cq_obj.cq) {
if (vq.callfd != virtq->eqp.cq.callfd)
return;
}
- eth_dev->intr_handle = &pci_dev->intr_handle;
+ eth_dev->intr_handle = pci_dev->intr_handle;
if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
eth_dev->data->dev_flags = 0;
git.droids-corp.org / dpdk.git / commitdiff