#include "mlx5_glue.h"
#include "mlx5_prm.h"
+#include <rte_compat.h>
-
-/* devX creation object */
-struct mlx5_devx_obj {
- void *obj; /* The DV object. */
- int id; /* The object ID. */
-};
-
-/* UMR memory buffer used to define 1 entry in indirect mkey. */
-struct mlx5_klm {
- uint32_t byte_count;
- uint32_t mkey;
- uint64_t address;
-};
+/*
+ * Defines the amount of retries to allocate the first UAR in the page.
+ * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
+ * UAR base address if UAR was not the first object in the UAR page.
+ * It caused the PMD failure and we should try to get another UAR
+ * till we get the first one with non-NULL base address returned.
+ */
+#define MLX5_ALLOC_UAR_RETRY 32
/* This is limitation of libibverbs: in length variable type is u16. */
#define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \
uint32_t pd;
uint32_t log_entity_size;
uint32_t pg_access:1;
- uint32_t relaxed_ordering:1;
+ uint32_t relaxed_ordering_write:1;
+ uint32_t relaxed_ordering_read:1;
struct mlx5_klm *klm_array;
int klm_num;
};
struct mlx5_hca_qos_attr {
uint32_t sup:1; /* Whether QOS is supported. */
uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */
+ uint32_t packet_pacing:1; /* Packet pacing is supported. */
+ uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */
uint32_t flow_meter_reg_share:1;
/* Whether reg_c share is supported. */
uint8_t log_max_flow_meter;
uint32_t event_mode:3;
uint32_t log_doorbell_stride:5;
uint32_t log_doorbell_bar_size:5;
+ uint32_t queue_counters_valid:1;
uint32_t max_num_virtio_queues;
struct {
uint32_t a;
uint32_t eswitch_manager:1;
uint32_t flow_counters_dump:1;
uint32_t log_max_rqt_size:5;
+ uint32_t parse_graph_flex_node:1;
uint8_t flow_counter_bulk_alloc_bitmap;
uint32_t eth_net_offloads:1;
uint32_t eth_virt:1;
uint32_t tunnel_lro_vxlan:1;
uint32_t lro_max_msg_sz_mode:2;
uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
+ uint16_t lro_min_mss_size;
uint32_t flex_parser_protocols;
uint32_t hairpin:1;
uint32_t log_max_hairpin_queues:5;
uint32_t vhca_id:16;
uint32_t relaxed_ordering_write:1;
uint32_t relaxed_ordering_read:1;
+ uint32_t access_register_user:1;
+ uint32_t wqe_index_ignore:1;
+ uint32_t cross_channel:1;
+ uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */
+ uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */
+ uint32_t num_lag_ports:4; /* Number of ports can be bonded. */
+ uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */
+ uint32_t scatter_fcs_w_decap_disable:1;
+ uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */
+ uint32_t regex:1;
+ uint32_t regexp_num_of_engines;
+ uint32_t log_max_ft_sampler_num:8;
struct mlx5_hca_qos_attr qos;
struct mlx5_hca_vdpa_attr vdpa;
+ int log_max_qp_sz;
+ int log_max_cq_sz;
+ int log_max_qp;
+ int log_max_cq;
+ uint32_t log_max_pd;
+ uint32_t log_max_mrw_sz;
+ uint32_t log_max_srq;
+ uint32_t log_max_srq_sz;
+ uint32_t rss_ind_tbl_cap;
};
struct mlx5_devx_wq_attr {
struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
};
+/* TIR attributes structure, used by TIR modify. */
+struct mlx5_devx_modify_tir_attr {
+ uint32_t tirn:24;
+ uint64_t modify_bitmask;
+ struct mlx5_devx_tir_attr tir;
+};
+
/* RQT attributes structure, used by RQT operations. */
struct mlx5_devx_rqt_attr {
uint8_t rq_type;
uint32_t reg_umr:1;
uint32_t allow_swp:1;
uint32_t hairpin:1;
+ uint32_t non_wire:1;
+ uint32_t static_sq_wq:1;
uint32_t user_index:24;
uint32_t cqn:24;
uint32_t packet_pacing_rate_limit_index:16;
uint32_t db_umem_valid:1;
uint32_t use_first_only:1;
uint32_t overrun_ignore:1;
+ uint32_t cqe_comp_en:1;
+ uint32_t mini_cqe_res_format:2;
+ uint32_t mini_cqe_res_format_ext:2;
+ uint32_t cqe_size:3;
uint32_t log_cq_size:5;
uint32_t log_page_size:5;
uint32_t uar_page_id;
uint16_t hw_available_index;
uint16_t hw_used_index;
uint16_t q_size;
+ uint32_t pd:24;
uint32_t virtio_version_1_0:1;
uint32_t tso_ipv4:1;
uint32_t tso_ipv6:1;
uint32_t rx_csum:1;
uint32_t event_mode:3;
uint32_t state:4;
+ uint32_t hw_latency_mode:2;
+ uint32_t hw_max_latency_us:12;
+ uint32_t hw_max_pending_comp:16;
uint32_t dirty_bitmap_dump_enable:1;
uint32_t dirty_bitmap_mkey;
uint32_t dirty_bitmap_size;
uint32_t qp_id;
uint32_t queue_index;
uint32_t tis_id;
+ uint32_t counters_obj_id;
uint64_t dirty_bitmap_addr;
uint64_t type;
uint64_t desc_addr;
uint32_t size;
uint64_t offset;
} umems[3];
+ uint8_t error_type;
};
uint64_t wq_umem_offset;
};
+struct mlx5_devx_virtio_q_couners_attr {
+ uint64_t received_desc;
+ uint64_t completed_desc;
+ uint32_t error_cqes;
+ uint32_t bad_desc_errors;
+ uint32_t exceed_max_chain;
+ uint32_t invalid_buffer;
+};
+
+/*
+ * graph flow match sample attributes structure,
+ * used by flex parser operations.
+ */
+struct mlx5_devx_match_sample_attr {
+ uint32_t flow_match_sample_en:1;
+ uint32_t flow_match_sample_field_offset:16;
+ uint32_t flow_match_sample_offset_mode:4;
+ uint32_t flow_match_sample_field_offset_mask;
+ uint32_t flow_match_sample_field_offset_shift:4;
+ uint32_t flow_match_sample_field_base_offset:8;
+ uint32_t flow_match_sample_tunnel_mode:3;
+ uint32_t flow_match_sample_field_id;
+};
+
+/* graph node arc attributes structure, used by flex parser operations. */
+struct mlx5_devx_graph_arc_attr {
+ uint32_t compare_condition_value:16;
+ uint32_t start_inner_tunnel:1;
+ uint32_t arc_parse_graph_node:8;
+ uint32_t parse_graph_node_handle;
+};
+
+/* Maximal number of samples per graph node. */
+#define MLX5_GRAPH_NODE_SAMPLE_NUM 8
+
+/* Maximal number of input/output arcs per graph node. */
+#define MLX5_GRAPH_NODE_ARC_NUM 8
+
+/* parse graph node attributes structure, used by flex parser operations. */
+struct mlx5_devx_graph_node_attr {
+ uint32_t modify_field_select;
+ uint32_t header_length_mode:4;
+ uint32_t header_length_base_value:16;
+ uint32_t header_length_field_shift:4;
+ uint32_t header_length_field_offset:16;
+ uint32_t header_length_field_mask;
+ struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM];
+ uint32_t next_header_field_offset:16;
+ uint32_t next_header_field_size:5;
+ struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM];
+ struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM];
+};
+
/* mlx5_devx_cmds.c */
__rte_internal
__rte_internal
int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
struct mlx5_devx_rqt_attr *rqt_attr);
+__rte_internal
+int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
+ struct mlx5_devx_modify_tir_attr *tir_attr);
+__rte_internal
+int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
+ uint32_t ids[], uint32_t num);
+
+__rte_internal
+struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx,
+ struct mlx5_devx_graph_node_attr *data);
+
+__rte_internal
+int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id,
+ uint32_t arg, uint32_t *data, uint32_t dw_cnt);
+/**
+ * Create virtio queue counters object DevX API.
+ *
+ * @param[in] ctx
+ * Device context.
+ * @return
+ * The DevX object created, NULL otherwise and rte_errno is set.
+ */
+__rte_internal
+struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx);
+
+/**
+ * Query virtio queue counters object using DevX API.
+ *
+ * @param[in] couners_obj
+ * Pointer to virtq object structure.
+ * @param [in/out] attr
+ * Pointer to virtio queue counters attributes structure.
+ *
+ * @return
+ * 0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+__rte_internal
+int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
+ struct mlx5_devx_virtio_q_couners_attr *attr);
+__rte_internal
+struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx,
+ uint32_t pd);
+
+__rte_internal
+struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx);
#endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */
git.droids-corp.org / dpdk.git / blobdiff