common/mlx5: support vDPA completion queue moderation

This patch introduces new parameters for VirtQ CQ moderation, used for
performance tuning.

Signed-off-by: Xueming Li <xuemingl@nvidia.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index 12f51a9..3bf5279 100644 (file)
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -1662,6 +1662,9 @@ mlx5_devx_cmd_create_virtq(void *ctx,
        MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
        MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
        MLX5_SET(virtio_q, virtctx, pd, attr->pd);
+       MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode);
+       MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us);
+       MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp);
        MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
        virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
                                                    sizeof(out));

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index b335b7c..94e9bbb 100644 (file)
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -302,6 +302,9 @@ struct mlx5_devx_virtq_attr {
        uint32_t rx_csum:1;
        uint32_t event_mode:3;
        uint32_t state:4;
+       uint32_t hw_latency_mode:2;
+       uint32_t hw_max_latency_us:12;
+       uint32_t hw_max_pending_comp:16;
        uint32_t dirty_bitmap_dump_enable:1;
        uint32_t dirty_bitmap_mkey;
        uint32_t dirty_bitmap_size;

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 8c9b53c..7d5cf96 100644 (file)
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -2379,7 +2379,11 @@ struct mlx5_ifc_virtio_q_bits {
        u8 counter_set_id[0x20];
        u8 reserved_at_320[0x8];
        u8 pd[0x18];
-       u8 reserved_at_340[0xc0];
+       u8 reserved_at_340[0x2];
+       u8 queue_period_mode[0x2];
+       u8 queue_period_us[0xc];
+       u8 queue_max_count[0x10];
+       u8 reserved_at_360[0xa0];
 };
 
 struct mlx5_ifc_virtio_net_q_bits {