rxq->max_pkt_len = max_pkt_len;
if ((dev_data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER) ||
- (rxq->max_pkt_len + 2 * ICE_VLAN_TAG_SIZE) > buf_size) {
+ (rxq->max_pkt_len + 2 * RTE_VLAN_HLEN) > buf_size) {
dev_data->scattered_rx = 1;
}
rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
return -1;
}
- if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
- intr_handle->intr_vec =
- rte_zmalloc("intr_vec",
- dev->data->nb_rx_queues * sizeof(int), 0);
- if (!intr_handle->intr_vec) {
+ if (rte_intr_dp_is_en(intr_handle)) {
+ if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
+ dev->data->nb_rx_queues)) {
PMD_DRV_LOG(ERR, "Failed to allocate %d rx intr_vec",
dev->data->nb_rx_queues);
return -1;
hw->msix_base = IAVF_MISC_VEC_ID;
for (i = 0; i < dev->data->nb_rx_queues; i++) {
hw->rxq_map[hw->msix_base] |= 1 << i;
- intr_handle->intr_vec[i] = IAVF_MISC_VEC_ID;
+ rte_intr_vec_list_index_set(intr_handle,
+ i, IAVF_MISC_VEC_ID);
}
PMD_DRV_LOG(DEBUG,
"vector %u are mapping to all Rx queues",
* multi interrupts, then the vec is from 1
*/
hw->nb_msix = RTE_MIN(hw->vf_res->max_vectors,
- intr_handle->nb_efd);
+ rte_intr_nb_efd_get(intr_handle));
hw->msix_base = IAVF_MISC_VEC_ID;
vec = IAVF_MISC_VEC_ID;
for (i = 0; i < dev->data->nb_rx_queues; i++) {
hw->rxq_map[vec] |= 1 << i;
- intr_handle->intr_vec[i] = vec++;
+ rte_intr_vec_list_index_set(intr_handle,
+ i, vec++);
if (vec >= hw->nb_msix)
vec = IAVF_RX_VEC_START;
}
ice_dcf_stop_queues(dev);
rte_intr_efd_disable(intr_handle);
- if (intr_handle->intr_vec) {
- rte_free(intr_handle->intr_vec);
- intr_handle->intr_vec = NULL;
- }
+ rte_intr_vec_list_free(intr_handle);
ice_dcf_add_del_all_mac_addr(&dcf_ad->real_hw, false);
dev->data->dev_link.link_status = RTE_ETH_LINK_DOWN;
dev_info->hash_key_size = hw->vf_res->rss_key_size;
dev_info->reta_size = hw->vf_res->rss_lut_size;
dev_info->flow_type_rss_offloads = ICE_RSS_OFFLOAD_ALL;
+ dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
dev_info->rx_offload_capa =
RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
return 0;
}
+static inline void
+ice_dcf_reset_hw(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw)
+{
+ ice_dcf_uninit_hw(eth_dev, hw);
+ ice_dcf_init_hw(eth_dev, hw);
+}
+
+/* Check if reset has been triggered by PF */
+static inline bool
+ice_dcf_is_reset(struct rte_eth_dev *dev)
+{
+ struct ice_dcf_adapter *ad = dev->data->dev_private;
+ struct iavf_hw *hw = &ad->real_hw.avf;
+
+ return !(IAVF_READ_REG(hw, IAVF_VF_ARQLEN1) &
+ IAVF_VF_ARQLEN1_ARQENABLE_MASK);
+}
+
static int
ice_dcf_dev_reset(struct rte_eth_dev *dev)
{
+ struct ice_dcf_adapter *ad = dev->data->dev_private;
+ struct ice_dcf_hw *hw = &ad->real_hw;
int ret;
+ if (ice_dcf_is_reset(dev)) {
+ if (!ad->real_hw.resetting)
+ ad->real_hw.resetting = true;
+ PMD_DRV_LOG(ERR, "The DCF has been reset by PF");
+
+ /*
+ * Simply reset hw to trigger an additional DCF enable/disable
+ * cycle which help to workaround the issue that kernel driver
+ * may not clean up resource during previous reset.
+ */
+ ice_dcf_reset_hw(dev, hw);
+ }
+
ret = ice_dcf_dev_uninit(dev);
if (ret)
return ret;
{
struct ice_dcf_adapter *adapter = eth_dev->data->dev_private;
- adapter->real_hw.resetting = false;
eth_dev->dev_ops = &ice_dcf_eth_dev_ops;
eth_dev->rx_pkt_burst = ice_dcf_recv_pkts;
eth_dev->tx_pkt_burst = ice_dcf_xmit_pkts;