dpdk.git
7 years agocrypto/qat: support AES-CCM
Arek Kusztal [Thu, 21 Sep 2017 13:11:20 +0000 (14:11 +0100)]
crypto/qat: support AES-CCM

This patch adds AES-CCM AEAD cipher and hash algorithm to
Intel QuickAssist Technology driver.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
7 years agocrypto/openssl: support AES-CCM
Pablo de Lara [Thu, 21 Sep 2017 13:11:19 +0000 (14:11 +0100)]
crypto/openssl: support AES-CCM

Add support to AES-CCM, for 128, 192 and 256-bit keys.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
7 years agocrypto/openssl: init GCM key at session creation
Pablo de Lara [Thu, 21 Sep 2017 13:11:18 +0000 (14:11 +0100)]
crypto/openssl: init GCM key at session creation

When creating a session for AES-GCM, since the key is going
to be constant, the OpenSSL context can initialize the key
at that moment, leaving the setting of the IV for the
operation handling.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
7 years agocrypto/openssl: fix AEAD parameters
Pablo de Lara [Thu, 21 Sep 2017 13:11:17 +0000 (14:11 +0100)]
crypto/openssl: fix AEAD parameters

When using AES-GCM with OpenSSL, cipher direction
and authentication operation were being set incorrectly,
as the PMD was looking at the cipher and authentication
transform, instead of the new AEAD.

Fixes: b79e4c00af0e ("cryptodev: use AES-GCM/CCM as AEAD algorithms")
Cc: stable@dpdk.org
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
7 years agoapp/crypto-perf: support AES-CCM
Pablo de Lara [Thu, 21 Sep 2017 13:11:16 +0000 (14:11 +0100)]
app/crypto-perf: support AES-CCM

According to the API, AES-CCM has special requirements
when setting IV and AAD fields.
The L2fwd-crypto app is updated to set the nonce (IV)
and AAD in the right positions in these two fields
(1 byte after start of IV field and 18 bytes after start
of AAD).

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
7 years agoexamples/l2fwd-crypto: support AES-CCM
Pablo de Lara [Thu, 21 Sep 2017 13:11:15 +0000 (14:11 +0100)]
examples/l2fwd-crypto: support AES-CCM

According to the API, AES-CCM has special requirements
when setting IV and AAD fields.
The L2fwd-crypto app is updated to set the nonce (IV)
and AAD in the right positions in these two fields
(1 byte after start of IV field and 18 bytes after start
of AAD).

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
7 years agocryptodev: clarify API for AES-CCM
Pablo de Lara [Thu, 21 Sep 2017 13:11:14 +0000 (14:11 +0100)]
cryptodev: clarify API for AES-CCM

AES-CCM algorithm has some restrictions when
handling nonce (IV) and AAD information.

As the API stated, the nonce needs to be place 1 byte
after the start of the IV field. This field needs
to be 16 bytes long, regardless the length of the nonce,
but it is important to clarify that the first byte
and the padding added after the nonce may be modified
by the PMDs using this algorithm.

Same happens with the AAD. It needs to be placed 18 bytes
after the start of the AAD field. The field also needs
to be multiple of 16 bytes long and all memory reserved
(the first bytes and the padding (may be modified by the PMDs).

Lastly, nonce is not needed to be placed in the first 16 bytes
of the AAD, as the API stated, as that depends on the PMD
used, so the comment has been removed.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
7 years agoapp/crypto-perf: use single mempool
Pablo de Lara [Wed, 4 Oct 2017 03:46:13 +0000 (04:46 +0100)]
app/crypto-perf: use single mempool

In order to improve memory utilization, a single mempool
is created, containing the crypto operation and mbufs
(one if operation is in-place, two if out-of-place).
This way, a single object is allocated and freed
per operation, reducing the amount of memory in cache,
which improves scalability.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
7 years agoapp/crypto-perf: support multiple queue pairs
Pablo de Lara [Wed, 4 Oct 2017 03:46:12 +0000 (04:46 +0100)]
app/crypto-perf: support multiple queue pairs

Add support for multiple queue pairs, when there are
more logical cores available than crypto devices enabled.
For instance, if there are 4 cores available and
2 crypto devices, each device will have two queue pairs.

This is useful to have multiple logical cores using
a single crypto device, without needing to initialize
a crypto device per core.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
7 years agoapp/crypto-perf: do not populate the mbufs at init
Pablo de Lara [Wed, 4 Oct 2017 03:46:11 +0000 (04:46 +0100)]
app/crypto-perf: do not populate the mbufs at init

For throughput and latency tests, it is not required
to populate the mbufs with any test vector.
For verify test, there is already a function that rewrites
the mbufs every time they are going to be used with
crypto operations.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
7 years agoapp/crypto-perf: overwrite mbuf when verifying
Pablo de Lara [Wed, 4 Oct 2017 03:46:10 +0000 (04:46 +0100)]
app/crypto-perf: overwrite mbuf when verifying

When running the verify test, mbufs in the pool were
populated with the test vector loaded from a file.
To avoid limiting the number of operations to the pool size,
mbufs will be rewritten with the test vector, before
linking them to the crypto operations.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
7 years agoapp/crypto-perf: parse segment size
Pablo de Lara [Wed, 4 Oct 2017 03:46:09 +0000 (04:46 +0100)]
app/crypto-perf: parse segment size

Instead of parsing number of segments, from the command line,
parse segment size, as it is a more usual case to have
the segment size fixed and then different packet sizes
will require different number of segments.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
7 years agoapp/crypto-perf: parse AEAD data from vectors
Pablo de Lara [Wed, 4 Oct 2017 03:46:08 +0000 (04:46 +0100)]
app/crypto-perf: parse AEAD data from vectors

Since DPDK 17.08, there is specific parameters
for AEAD algorithm, like AES-GCM. When verifying
crypto operations with test vectors, the parser
was not reading AEAD data (such as IV or key).

Fixes: 8a5b494a7f99 ("app/test-crypto-perf: add AEAD parameters")
Cc: stable@dpdk.org
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
7 years agoapp/crypto-perf: set AAD after the crypto operation
Pablo de Lara [Wed, 4 Oct 2017 03:46:07 +0000 (04:46 +0100)]
app/crypto-perf: set AAD after the crypto operation

Instead of prepending the AAD (Additional Authenticated Data)
in the mbuf, it is easier to set after the crypto operation,
as it is a read-only value, like the IV, and then it is not
restricted to the size of the mbuf headroom.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
7 years agoapp/crypto-perf: refactor common test code
Pablo de Lara [Wed, 4 Oct 2017 03:46:06 +0000 (04:46 +0100)]
app/crypto-perf: refactor common test code

Currently, there is some duplication in all the test types,
in the crypto performance application.

In order to improve maintainability of this code,
and ease future work on it, common functions have been separated
in a different file that gets included in all the tests.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
7 years agocryptodev: add function to retrieve device name
Pablo de Lara [Tue, 3 Oct 2017 02:32:54 +0000 (03:32 +0100)]
cryptodev: add function to retrieve device name

Currently, in order to get the name of a crypto device,
a user needs to access to it using the crypto device structure.

It is a better practise to have a function to retrieve this
name, given a device id.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
7 years agoapp/crypto-perf: fix packet length check
Pablo de Lara [Thu, 5 Oct 2017 05:28:00 +0000 (06:28 +0100)]
app/crypto-perf: fix packet length check

When using DES-CBC, packet size has to be multiple
of 8 bytes, but if a list of packets is provided.
the check was not correct.

Fixes: fc4600fb2520 ("app/crypto-perf: add extra option checks")
Cc: stable@dpdk.org
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Radu Nicolau <radu.nicolau@intel.com>
7 years agocrypto/openssl: support DES-CBC
Pablo de Lara [Thu, 5 Oct 2017 05:27:59 +0000 (06:27 +0100)]
crypto/openssl: support DES-CBC

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Radu Nicolau <radu.nicolau@intel.com>
7 years agocrypto/aesni_mb: support DES
Pablo de Lara [Thu, 5 Oct 2017 05:27:58 +0000 (06:27 +0100)]
crypto/aesni_mb: support DES

The Multi-buffer library now supports DES-CBC
and DES-DOCSISBPI algorithms, so this commit
extends adds support for them in the PMD.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
Reviewed-by: Radu Nicolau <radu.nicolau@intel.com>
7 years agodoc: update IPSec Multi-buffer lib versioning
Pablo de Lara [Thu, 5 Oct 2017 05:27:57 +0000 (06:27 +0100)]
doc: update IPSec Multi-buffer lib versioning

IPSec Multi-buffer library v0.47 has been released,
which includes, among other features, support for DES-CBC
and DES-DOCSIS.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: John McNamara <john.mcnamara@intel.com>
7 years agotest/crypto: remove crypto perf tests
Pablo de Lara [Wed, 4 Oct 2017 06:48:38 +0000 (07:48 +0100)]
test/crypto: remove crypto perf tests

Since the crypto perf application is flexible enough
to cover all the crypto performance tests, these are not needed
anymore, so they will be removed to avoid duplications.
Besides, the crypto perf application gives the user more options
to get performance, for every single supported algorithm,
such as varying the buffer size as the user wants.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
7 years agotest/crypto: fix dpaa2 sec macros and definitions
Akhil Goyal [Thu, 5 Oct 2017 12:50:08 +0000 (18:20 +0530)]
test/crypto: fix dpaa2 sec macros and definitions

Fixes: 7a364faef185 ("cryptodev: remove crypto device type enumeration")

Cc: stable@dpdk.org
Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
7 years agocrypto/armv8: rename map file to standard name
Bruce Richardson [Thu, 14 Sep 2017 16:02:14 +0000 (17:02 +0100)]
crypto/armv8: rename map file to standard name

Naming convention for crypto drivers is "rte_pmd_<name>_version.map"

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
7 years agocrypto/aesni_mb: rename map file to standard name
Bruce Richardson [Thu, 14 Sep 2017 16:02:13 +0000 (17:02 +0100)]
crypto/aesni_mb: rename map file to standard name

Naming convention for crypto drivers is "rte_pmd_<name>_version.map"

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
7 years agoapp/crypto-perf: add new PMD benchmarking mode
Anatoly Burakov [Tue, 12 Sep 2017 09:36:26 +0000 (10:36 +0100)]
app/crypto-perf: add new PMD benchmarking mode

This patch adds a new benchmarking mode, which is intended for
microbenchmarking individual parts of the cryptodev framework,
specifically crypto ops alloc-build-free, cryptodev PMD enqueue
and cryptodev PMD dequeue.

It works by first benchmarking crypto operation alloc-build-free
loop (no enqueues/dequeues happening), and then benchmarking
enqueue and dequeue separately, by first completely filling up the
TX queue, and then completely draining the RX queue.

Results are shown as cycle counts per alloc/build/free, PMD enqueue
and PMD dequeue.

One new test mode is added: "pmd-cyclecount"
  (called with --ptest=pmd-cyclecount)

New command-line argument is also added:
  --pmd-cyclecount-delay-ms: this is a pmd-cyclecount-specific parameter
      that controls the delay between enqueue and dequeue. This is
      useful for benchmarking hardware acceleration, as hardware may
      not be able to keep up with enqueued packets. This parameter
      can be increased if there are large amounts of dequeue
      retries.

Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
Reviewed-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
7 years agoapp/crypto-perf: add nb-desc parameter
Anatoly Burakov [Tue, 12 Sep 2017 09:36:25 +0000 (10:36 +0100)]
app/crypto-perf: add nb-desc parameter

This parameter makes number of cryptodev descriptors adjustable
and defaults to earlier hardcoded default of 2048.

Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
Reviewed-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
7 years agocrypto/qat: enable Tx tail writes coalescing
Anatoly Burakov [Tue, 12 Sep 2017 09:31:18 +0000 (10:31 +0100)]
crypto/qat: enable Tx tail writes coalescing

Don't write CSR tail until we processed enough TX descriptors.

To avoid crypto operations sitting in the TX ring indefinitely,
the "force write" threshold is used:
 - on TX, no tail write coalescing will occur if number of inflights
   is below force write threshold
 - on RX, check if we have a number of crypto ops enqueued that is
   below force write threshold that are not yet submitted to
   processing.

Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
7 years agocrypto/qat: enable Rx head writes coalescing
Anatoly Burakov [Tue, 12 Sep 2017 09:31:17 +0000 (10:31 +0100)]
crypto/qat: enable Rx head writes coalescing

Don't write CSR head until we processed enough RX descriptors.
Also delay marking them as free until we are writing CSR head.

Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
7 years agocrypto/qat: remove atomics
Anatoly Burakov [Tue, 12 Sep 2017 09:31:16 +0000 (10:31 +0100)]
crypto/qat: remove atomics

Replacing atomics in the QAT driver with simple 16-bit integers for
number of inflight packets.

This adds a new limitation to the QAT driver: each queue pair is
now explicitly single-threaded.

Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
7 years agocrypto/aesni_mb: fix invalid session error
Sergio Gonzalez Monroy [Thu, 7 Sep 2017 11:50:36 +0000 (12:50 +0100)]
crypto/aesni_mb: fix invalid session error

Setting an invalid session in the crypto op results in SEGFAULT because
the JOB user_data was never set to the crypto op.

Fixes: 0f548b50a160 ("crypto/aesni_mb: process crypto op on dequeue")
Cc: stable@dpdk.org
Signed-off-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
7 years agotest/crypto: do not allocate extra memory for digest
Pablo de Lara [Tue, 5 Sep 2017 02:20:07 +0000 (03:20 +0100)]
test/crypto: do not allocate extra memory for digest

Now that PMDs do not need extra space in the mbuf
to store temporarily the digest when verifying
an authentication tag, it is not required to allocate
more memory in the mbufs passed to cryptodev.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
7 years agocrypto/aesni_mb: do not append digest
Pablo de Lara [Tue, 5 Sep 2017 02:20:06 +0000 (03:20 +0100)]
crypto/aesni_mb: do not append digest

When performing an authentication verification,
the PMD was using memory at the end of the input buffer,
to store temporarily the digest.
This operation requires the buffer to have enough
tailroom unnecessarily.
Instead, memory is allocated for each queue pair, to store
temporarily the digest generated by the driver, so it can
be compared with the one provided in the crypto operation,
without needing to touch the input buffer.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
7 years agocrypto/zuc: do not append digest
Pablo de Lara [Tue, 5 Sep 2017 02:20:05 +0000 (03:20 +0100)]
crypto/zuc: do not append digest

When performing an authentication verification,
the PMD was using memory at the end of the input buffer,
to store temporarily the digest.
This operation requires the buffer to have enough
tailroom unnecessarily.
Instead, memory is allocated for each queue pair, to store
temporarily the digest generated by the driver, so it can
be compared with the one provided in the crypto operation,
without needing to touch the input buffer.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
7 years agocrypto/snow3g: do not append digest
Pablo de Lara [Tue, 5 Sep 2017 02:20:04 +0000 (03:20 +0100)]
crypto/snow3g: do not append digest

When performing an authentication verification,
the PMD was using memory at the end of the input buffer,
to store temporarily the digest.
This operation requires the buffer to have enough
tailroom unnecessarily.
Instead, memory is allocated for each queue pair, to store
temporarily the digest generated by the driver, so it can
be compared with the one provided in the crypto operation,
without needing to touch the input buffer.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
7 years agocrypto/kasumi: do not append digest
Pablo de Lara [Tue, 5 Sep 2017 02:20:03 +0000 (03:20 +0100)]
crypto/kasumi: do not append digest

When performing an authentication verification,
the PMD was using memory at the end of the input buffer,
to store temporarily the digest.
This operation requires the buffer to have enough
tailroom unnecessarily.
Instead, memory is allocated for each queue pair, to store
temporarily the digest generated by the driver, so it can
be compared with the one provided in the crypto operation,
without needing to touch the input buffer.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
7 years agocrypto/openssl: do not append digest
Pablo de Lara [Tue, 5 Sep 2017 02:20:02 +0000 (03:20 +0100)]
crypto/openssl: do not append digest

When performing an authentication verification,
the PMD was using memory at the end of the input buffer,
to store temporarily the digest.
This operation requires the buffer to have enough
tailroom unnecessarily.
Instead, memory is allocated for each queue pair, to store
temporarily the digest generated by the driver, so it can
be compared with the one provided in the crypto operation,
without needing to touch the input buffer.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
7 years agocrypto/armv8: do not append digest
Pablo de Lara [Tue, 5 Sep 2017 02:20:01 +0000 (03:20 +0100)]
crypto/armv8: do not append digest

When performing an authentication verification,
the PMD was using memory at the end of the input buffer,
to store temporarily the digest.
This operation requires the buffer to have enough
tailroom unnecessarily.
Instead, memory is allocated for each queue pair, to store
temporarily the digest generated by the driver, so it can
be compared with the one provided in the crypto operation,
without needing to touch the input buffer.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
7 years agocrypto/aesni_gcm: do not append digest
Pablo de Lara [Tue, 5 Sep 2017 02:20:00 +0000 (03:20 +0100)]
crypto/aesni_gcm: do not append digest

When performing an authentication verification,
the PMD was using memory at the end of the input buffer,
to store temporarily the digest.
This operation requires the buffer to have enough
tailroom unnecessarily.
Instead, memory is allocated for each queue pair, to store
temporarily the digest generated by the driver, so it can
be compared with the one provided in the crypto operation,
without needing to touch the input buffer.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
7 years agocryptodev: allocate driver structure statically
Pablo de Lara [Wed, 16 Aug 2017 02:41:51 +0000 (03:41 +0100)]
cryptodev: allocate driver structure statically

When register a crypto driver, a cryptodev driver
structure was being allocated, using malloc.
Since this call may fail, it is safer to allocate
this memory statically in each PMD, so driver registration
will never fail.

Coverity issue: 158645
Fixes: 7a364faef185 ("cryptodev: remove crypto device type enumeration")

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Reviewed-by: Kirill Rybalchenko <kirill.rybalchenko@intel.com>
7 years agocrypto/aesni_gcm: fix zero data operation
Pablo de Lara [Mon, 14 Aug 2017 00:45:21 +0000 (01:45 +0100)]
crypto/aesni_gcm: fix zero data operation

When data length passed to the PMD was zero,
the PMD was trying to get more data from a non-existent
next segment.

Fixes: 9c2a5775c028 ("crypto/aesni_gcm: migrate from MB library to ISA-L")
Cc: stable@dpdk.org
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Reviewed-by: Kirill Rybalchenko <kirill.rybalchenko@intel.com>
7 years agocrypto/openssl: update key and algo during session init
Akhil Goyal [Tue, 5 Sep 2017 05:57:49 +0000 (11:27 +0530)]
crypto/openssl: update key and algo during session init

Key and algo are added in the openssl ctx during
session initialization instead of adding it for
each packet, since it remains constant for that session,
improving the performance.

Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
Reviewed-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
7 years agocrypto/openssl: replace evp APIs with HMAC APIs
Akhil Goyal [Tue, 5 Sep 2017 05:57:48 +0000 (11:27 +0530)]
crypto/openssl: replace evp APIs with HMAC APIs

in case of HMAC the openssl APIs HMAC_XXX give
better performance for all HMAC cases as compared with
EVP_XXX

Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
Reviewed-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
7 years agoapp/crypto-perf: fix uninitialized errno value
Hemant Agrawal [Tue, 5 Sep 2017 06:17:01 +0000 (11:47 +0530)]
app/crypto-perf: fix uninitialized errno value

errno should be initialized to 0 before calling strtol

Fixes: f6cefe253cc8 ("app/crypto-perf: add range/list of sizes")
Cc: stable@dpdk.org
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Reviewed-by: Kirill Rybalchenko <kirill.rybalchenko@intel.com>
7 years agoexamples/l2fwd-crypto: fix uninitialized errno value
Hemant Agrawal [Wed, 23 Aug 2017 12:24:03 +0000 (17:54 +0530)]
examples/l2fwd-crypto: fix uninitialized errno value

errno should be initialized to 0 before calling strtol

Fixes: 1df9c0109f4c ("examples/l2fwd-crypto: parse key parameters")
Cc: stable@dpdk.org
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Reviewed-by: Kirill Rybalchenko <kirill.rybalchenko@intel.com>
7 years agomempool/dpaa2: improve error handling
Hemant Agrawal [Tue, 10 Oct 2017 14:12:03 +0000 (19:42 +0530)]
mempool/dpaa2: improve error handling

Reverting the config on encountering errors.

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
7 years agomempool: remove get capability debug log
Hemant Agrawal [Tue, 10 Oct 2017 14:17:11 +0000 (19:47 +0530)]
mempool: remove get capability debug log

This is not required to be printed for every mempool call.

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Reviewed-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
7 years agoapp/testpmd: remove unnecessary cast
Zhiyong Yang [Wed, 11 Oct 2017 06:59:50 +0000 (14:59 +0800)]
app/testpmd: remove unnecessary cast

Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
7 years agonet/ixgbe: fix uninitialized variable
Yong Wang [Tue, 19 Sep 2017 03:17:24 +0000 (23:17 -0400)]
net/ixgbe: fix uninitialized variable

In func ixgbe_dev_link_update(), "link.link_autoneg" is used in func
call rte_ixgbe_dev_atomic_write_link_status(), but is uninitialized.

Fixes: 82113036e4e5 ("ethdev: redesign link speed config")
Cc: stable@dpdk.org
Signed-off-by: Yong Wang <wang.yong19@zte.com.cn>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
7 years agoethdev: revert use port name from device structure
Ferruh Yigit [Fri, 22 Sep 2017 11:30:07 +0000 (12:30 +0100)]
ethdev: revert use port name from device structure

This reverts commit a1e7c17555e8f77d520ba5f06ed26c00e77a2bd1.

Original commit assumes there is 1:1 mapping between physical device and
ethdev port, so that device name can be used per port instead of ethdev
name field.

But one physical device may have multiple ethdev ports and each port
needs its own unique name.

One issue reported here:
http://dpdk.org/ml/archives/users/2017-September/002484.html

So reverting back the commit to continue using ethdev name field per
port.

Fixes: a1e7c17555e8 ("ethdev: use device name from device structure")
Cc: stable@dpdk.org
Reported-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
7 years agoapp/testpmd: add commands for RSS queue region
Wei Zhao [Wed, 11 Oct 2017 08:55:33 +0000 (16:55 +0800)]
app/testpmd: add commands for RSS queue region

This patch add a API configuration of queue region in rss.
It can parse the parameters of region index, queue number,
queue start index, user priority, traffic classes and so on.
According to commands from command line, it will call i40e
private API and start the process of set or flush queue region
configure. As this feature is specific for i40e, so private API
will be used. Aslo add a document for these new commands.
Queue region only support PF by now, so this document is
only for configuration of queue region on PF port.

Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
7 years agonet/i40e: support queue region set and flush
Wei Zhao [Wed, 11 Oct 2017 08:55:32 +0000 (16:55 +0800)]
net/i40e: support queue region set and flush

This feature enable queue regions configuration for RSS in PF,
so that different traffic classes or different packet
classification types can be separated to different queues in
different queue regions.This patch can set queue region range,
it include queue number in a region and the index of first queue.
This patch enable mapping between different priorities (UP) and
different traffic classes.It also enable mapping between a region
index and a sepcific flowtype(PCTYPE).It also provide the solution
of flush all configuration about queue region the above described.

Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
7 years agonet/liquidio: support promiscuous mode
Intiyaz Basha [Wed, 11 Oct 2017 07:47:47 +0000 (13:17 +0530)]
net/liquidio: support promiscuous mode

Signed-off-by: Intiyaz Basha <intiyaz.basha@caviumnetworks.com>
Signed-off-by: Shijith Thotton <shijith.thotton@caviumnetworks.com>
7 years agonet/ixgbe: fix VFIO interrupt mapping in VF
Wei Dai [Thu, 28 Sep 2017 02:28:33 +0000 (10:28 +0800)]
net/ixgbe: fix VFIO interrupt mapping in VF

When a VF port is bound to VFIO-PIC, only miscellaneous interrupt
is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
In ixgbevf_dev_start(), if previous VFIO interrupt mapping set in
eth_ixgbevf_dev_init( ) is not cleard, it will fail when calling
rte_intr_enable( ) tries to map Rx queue interrupt to other VFIO
vectors. This patch clears the VFIO interrupt mappings before
setting both miscellaneous and Rx queue interrupt mappings again
to avoid failure.

Fixes: 77234603fba0 ("net/ixgbe: support VF mailbox interrupt for link up/down")
Cc: stable@dpdk.org
Signed-off-by: Wei Dai <wei.dai@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Tested-by: Jianwei Ma <jianwei.ma@intel.com>
7 years agonet/ixgbe: fix Rx queue interrupt mapping in VF
Wei Dai [Wed, 20 Sep 2017 10:18:13 +0000 (18:18 +0800)]
net/ixgbe: fix Rx queue interrupt mapping in VF

When a VF port is bound to VFIO-PCI, miscellaneous interrupt is
mapped to MSI-X vector 0 and Rx queues interrupt are mapped to
other vectors in vfio_enable_msix( ). To simplify implementation,
all VFIO-PCI bound ixgbe VF Rx queue interrupts can be mapped in
vector 1. And as current igb_uio only support only one vector,
ixgbe VF PMD should use vector 0 for igb_uio and vector 1 for
VFIO-PCI. Without this patch, VF Rx queue interrupt is mapped
to vector 0 in register settings and mapped to VFIO vector 1
in vfio_enable_msix( ), and then all Rx queue interrupts will
be missed.

Fixes: b13bfab4cdbe ("eal: reserve VFIO vector zero for misc interrupt")
Cc: stable@dpdk.org
Signed-off-by: Wei Dai <wei.dai@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Tested-by: Jianwei Ma <jianwei.ma@intel.com>
7 years agodoc: update the SDK version for DPAA2
Hemant Agrawal [Tue, 10 Oct 2017 14:13:21 +0000 (19:43 +0530)]
doc: update the SDK version for DPAA2

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
7 years agodoc: minor corrections in DPAA NIC guide
Hemant Agrawal [Tue, 10 Oct 2017 14:13:20 +0000 (19:43 +0530)]
doc: minor corrections in DPAA NIC guide

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
7 years agoethdev: add return value to stats get dev op
Matan Azrad [Tue, 10 Oct 2017 20:20:18 +0000 (20:20 +0000)]
ethdev: add return value to stats get dev op

The stats_get dev op API doesn't include return value, so PMD cannot
return an error in case of failure at stats getting process time.

Since PCI devices can be removed and there is a time between the
physical removal to the RMV interrupt, the user may get invalid stats
without any indication.

This patch changes the stats_get API return value to be int instead of
void.

All the net PMDs stats_get dev ops are adjusted by this patch.

Signed-off-by: Matan Azrad <matan@mellanox.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
7 years agonet/bnxt: fix the association of a MACVLAN per VNIC
Ajit Khaparde [Tue, 10 Oct 2017 14:23:03 +0000 (09:23 -0500)]
net/bnxt: fix the association of a MACVLAN per VNIC

We were not associating a MAC+VLAN per VNIC filter correctly.
This patch fixes that. Also set the VLAN type appropriately.

Fixes: f92735db1e4c ("net/bnxt: add L2 filter alloc/init/free")
Cc: stable@dpdk.org
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
7 years agonet/bnxt: support FDIR
Ajit Khaparde [Tue, 10 Oct 2017 14:23:02 +0000 (09:23 -0500)]
net/bnxt: support FDIR

This patch brings support for Flow Director.

Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
7 years agonet/bnxt: prevent programming a duplicate flow
Ajit Khaparde [Tue, 10 Oct 2017 14:23:01 +0000 (09:23 -0500)]
net/bnxt: prevent programming a duplicate flow

Match a flow against existing flows programmed in the HW
and prevent overlapping entries. Also change log level of
some logs to DEBUG.

Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
7 years agonet/bnxt: fix cleanup if a filter allocation fails
Ajit Khaparde [Tue, 10 Oct 2017 14:23:00 +0000 (09:23 -0500)]
net/bnxt: fix cleanup if a filter allocation fails

We are not checking if a filter allocation succeeded.
And we end up accessing a null pointer after that.
Also invalidate the fw_l2_filter_id to prevent unnecessary
HW access and hence HWRM command failures during exit.

Fixes: 5ef3b79fdfe6 ("net/bnxt: support flow filter ops")
Cc: stable@dpdk.org
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
7 years agonet/mlx5: flow counter support
Ori Kam [Tue, 10 Oct 2017 14:22:54 +0000 (16:22 +0200)]
net/mlx5: flow counter support

Example for setting rule for counting packets with dest
ip = 192.168.3.1 in testpmd:

testpmd: flow create 0 ingress pattern eth / ipv4 dst is 192.168.3.1
/ end actions queue index 0 / count / end

Reading the number of packets and bytes for the rule:

testpmd: flow query 0 0 count

Note: This feature is only supported starting Mellanox OFED 4.2

Signed-off-by: Ori Kam <orika@mellanox.com>
Signed-off-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
Acked-by: Yongseok Koh <yskoh@mellanox.com>
7 years agonet/mlx5: add Rx HW timestamp
Raslan Darawsheh [Tue, 10 Oct 2017 14:37:07 +0000 (17:37 +0300)]
net/mlx5: add Rx HW timestamp

Expose Rx HW timestamp to packet mbufs.

Signed-off-by: Raslan Darawsheh <rasland@mellanox.com>
Acked-by: Yongseok Koh <yskoh@mellanox.com>
7 years agoapp/testpmd: add Rx HW timestamp
Raslan Darawsheh [Tue, 10 Oct 2017 14:37:06 +0000 (17:37 +0300)]
app/testpmd: add Rx HW timestamp

Add enabling/disabling Rx HW timestamp from
command line and parameter.

Signed-off-by: Raslan Darawsheh <rasland@mellanox.com>
Acked-by: Yongseok Koh <yskoh@mellanox.com>
7 years agoethdev: add Rx HW timestamp capability
Raslan Darawsheh [Tue, 10 Oct 2017 14:37:05 +0000 (17:37 +0300)]
ethdev: add Rx HW timestamp capability

Add a new offload capability flag for Rx HW
timestamp and enabling/disabling this via rte_eth_rxmode.

Signed-off-by: Raslan Darawsheh <rasland@mellanox.com>
Reviewed-by: Shahaf Shuler <shahafs@mellanox.com>
Acked-by: Yongseok Koh <yskoh@mellanox.com>
7 years agonet/mlx5: fix deadlock due to buffered slots in Rx SW ring
Yongseok Koh [Tue, 10 Oct 2017 14:04:02 +0000 (07:04 -0700)]
net/mlx5: fix deadlock due to buffered slots in Rx SW ring

When replenishing Rx ring, there're always buffered slots reserved
between consumed entries and HW owned entries. These have to be filled
with fake mbufs to protect from possible overflow rather than
optimistically expecting successful replenishment which can cause
deadlock with small-sized queue.

Fixes: fc048bd52cb7 ("net/mlx5: fix overflow of Rx SW ring")
Cc: stable@dpdk.org
Reported-by: Martin Weiser <martin.weiser@allegro-packets.com>
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Tested-by: Martin Weiser <martin.weiser@allegro-packets.com>
7 years agonet/i40e: fix uninitialized variable
Yong Wang [Tue, 10 Oct 2017 11:24:20 +0000 (07:24 -0400)]
net/i40e: fix uninitialized variable

In func i40evf_dev_link_update(), "new_link.link_autoneg" is used in
func call i40evf_dev_atomic_write_link_status(), but is uninitialized.

Fixes: 2a73125b7041 ("i40evf: fix link info update")
Cc: stable@dpdk.org
Signed-off-by: Yong Wang <wang.yong19@zte.com.cn>
Acked-by: Jingjing Wu <jingjing.wu@intel.com>
7 years agonet/enic: remove ancillary assignment
Aaron Conole [Tue, 26 Sep 2017 18:53:29 +0000 (14:53 -0400)]
net/enic: remove ancillary assignment

The assignment at initialization is overwritten immediately.  Drop the
assignment.

Signed-off-by: Aaron Conole <aconole@redhat.com>
Reviewed-by: John Daley <johndale@cisco.com>
7 years agonet/enic: remove unused code
Aaron Conole [Tue, 26 Sep 2017 18:53:28 +0000 (14:53 -0400)]
net/enic: remove unused code

The functions here aren't called anywhere in code, at least according to
both the compiler, and some greps.

Signed-off-by: Aaron Conole <aconole@redhat.com>
Reviewed-by: John Daley <johndale@cisco.com>
7 years agonet/enic: fix assignment
Aaron Conole [Tue, 26 Sep 2017 18:53:27 +0000 (14:53 -0400)]
net/enic: fix assignment

As it stands, the existing assignment to mbuf has no effect outside of
the function.  Prior to this change, the mbuf argument would contain
an invalid address, but it would not be null.  After this change, the
caller gets a null mbuf back.

Fixes: 947d860c821f ("enic: improve Rx performance")
Cc: stable@dpdk.org
Signed-off-by: Aaron Conole <aconole@redhat.com>
Reviewed-by: John Daley <johndale@cisco.com>
7 years agonet/enic: update format string to match arg types
Aaron Conole [Tue, 26 Sep 2017 18:53:26 +0000 (14:53 -0400)]
net/enic: update format string to match arg types

The argument `index` (and unique_id) is unsigned, but the format
string type used was for signed types.

Signed-off-by: Aaron Conole <aconole@redhat.com>
Reviewed-by: John Daley <johndale@cisco.com>
7 years agonet/bonding: strengthen the judgment of LACP packets
Ganghui Zeng [Wed, 30 Aug 2017 03:46:14 +0000 (11:46 +0800)]
net/bonding: strengthen the judgment of LACP packets

When the NIC does not support VLAN Rx offload may be wrong, resulting in
LACP packets will not be processed.

Signed-off-by: Ganghui Zeng <zengganghui@huawei.com>
Reviewed-by: Radu Nicolau <radu.nicolau@intel.com>
Acked-by: Declan Doherty <declan.doherty@intel.com>
7 years agoapp/testpmd: add traffic management forwarding mode
Jasvinder Singh [Tue, 10 Oct 2017 10:18:18 +0000 (11:18 +0100)]
app/testpmd: add traffic management forwarding mode

This commit extends the testpmd application with new forwarding engine
that demonstrates the use of ethdev traffic management APIs and softnic
PMD for QoS traffic management.

In this mode, 5-level hierarchical tree of the QoS scheduler is built
with the help of ethdev TM APIs such as shaper profile add/delete,
shared shaper add/update, node add/delete, hierarchy commit, etc.
The hierarchical tree has following nodes; root node(x1, level 0),
subport node(x1, level 1), pipe node(x4096, level 2),
tc node(x16348, level 3), queue node(x65536, level 4).

During runtime, each received packet is first classified by mapping the
packet fields information to 5-tuples (HQoS subport, pipe, traffic class,
queue within traffic class, and color) and storing it in the packet mbuf
sched field. After classification, each packet is sent to softnic port
which prioritizes the transmission of the received packets, and
accordingly sends them on to the output interface.

To enable traffic management mode, following testpmd command is used;

$ ./testpmd -c c -n 4 --vdev
'net_softnic0,hard_name=0000:06:00.1,soft_tm=on' -- -i
--forward-mode=tm

Signed-off-by: Jasvinder Singh <jasvinder.singh@intel.com>
Acked-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
7 years agonet/softnic: add TM hierarchy related ops
Jasvinder Singh [Tue, 10 Oct 2017 10:18:17 +0000 (11:18 +0100)]
net/softnic: add TM hierarchy related ops

Implement ethdev TM hierarchy related APIs in SoftNIC PMD.

Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
Signed-off-by: Jasvinder Singh <jasvinder.singh@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
7 years agonet/softnic: add TM capabilities ops
Jasvinder Singh [Tue, 10 Oct 2017 10:18:16 +0000 (11:18 +0100)]
net/softnic: add TM capabilities ops

Implement ethdev TM capability APIs in SoftNIC PMD.

Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
Signed-off-by: Jasvinder Singh <jasvinder.singh@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
7 years agonet/softnic: support traffic management
Jasvinder Singh [Tue, 10 Oct 2017 10:18:15 +0000 (11:18 +0100)]
net/softnic: support traffic management

Add ethdev Traffic Management API support to SoftNIC PMD.

Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
Signed-off-by: Jasvinder Singh <jasvinder.singh@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
7 years agonet/softnic: add softnic PMD
Jasvinder Singh [Tue, 10 Oct 2017 10:18:14 +0000 (11:18 +0100)]
net/softnic: add softnic PMD

Add SoftNIC PMD to provide SW fall-back for ethdev APIs.

Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
Signed-off-by: Jasvinder Singh <jasvinder.singh@intel.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
7 years agoethdev: add return code to stats reset function
David Harton [Wed, 20 Sep 2017 14:11:30 +0000 (10:11 -0400)]
ethdev: add return code to stats reset function

Some devices do not support reset of eth stats.  An application may
need to know not to clear shadow stats if the device cannot.

rte_eth_stats_reset is updated to provide a return code to share
whether the device supports reset or not.

Signed-off-by: David Harton <dharton@cisco.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
7 years agoethdev: increase device internal name length
Stephen Hemminger [Wed, 27 Sep 2017 09:23:20 +0000 (10:23 +0100)]
ethdev: increase device internal name length

Allow sufficient space for UUID in string form (36+1).
Needed to use UUID with Hyper-V.

Signed-off-by: Stephen Hemminger <sthemmin@microsoft.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
7 years agoethdev: fix a comment for config struct
Tonghao Zhang [Tue, 19 Sep 2017 05:24:30 +0000 (22:24 -0700)]
ethdev: fix a comment for config struct

We have change the type of rx_adv_conf, so change the comment for it.

Fixes: 4bdefaade6d1 ("ethdev: VMDQ enhancements")
Cc: stable@dpdk.org
Signed-off-by: Tonghao Zhang <xiangxia.m.yue@gmail.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
7 years agodoc: add mrvl NIC guide
Tomasz Duszynski [Mon, 9 Oct 2017 15:00:44 +0000 (17:00 +0200)]
doc: add mrvl NIC guide

Add documentation for the MRVL NET PMD driver.

Signed-off-by: Jacek Siuda <jck@semihalf.com>
Signed-off-by: Tomasz Duszynski <tdu@semihalf.com>
7 years agonet/mrvl: support basic stats
Tomasz Duszynski [Mon, 9 Oct 2017 15:00:42 +0000 (17:00 +0200)]
net/mrvl: support basic stats

Add support for both per queue and overall basic statistics.

Signed-off-by: Jacek Siuda <jck@semihalf.com>
Signed-off-by: Tomasz Duszynski <tdu@semihalf.com>
7 years agonet/mrvl: support packet type parsing
Tomasz Duszynski [Mon, 9 Oct 2017 15:00:41 +0000 (17:00 +0200)]
net/mrvl: support packet type parsing

Add packet type parsing support.

Signed-off-by: Jacek Siuda <jck@semihalf.com>
Signed-off-by: Tomasz Duszynski <tdu@semihalf.com>
7 years agonet/mrvl: support CRC and L3/L4 offloads
Tomasz Duszynski [Mon, 9 Oct 2017 15:00:40 +0000 (17:00 +0200)]
net/mrvl: support CRC and L3/L4 offloads

Add support for crc offload and l3/l4 checksum offloads.

Signed-off-by: Jacek Siuda <jck@semihalf.com>
Signed-off-by: Tomasz Duszynski <tdu@semihalf.com>
7 years agonet/mrvl: support VLAN filtering
Tomasz Duszynski [Mon, 9 Oct 2017 15:00:39 +0000 (17:00 +0200)]
net/mrvl: support VLAN filtering

Add support for vlan filtering.

Signed-off-by: Jacek Siuda <jck@semihalf.com>
Signed-off-by: Tomasz Duszynski <tdu@semihalf.com>
7 years agonet/mrvl: support RSS hashing
Tomasz Duszynski [Mon, 9 Oct 2017 15:00:38 +0000 (17:00 +0200)]
net/mrvl: support RSS hashing

Add support for rss hashing on rx.

Signed-off-by: Jacek Siuda <jck@semihalf.com>
Signed-off-by: Tomasz Duszynski <tdu@semihalf.com>
7 years agonet/mrvl: support MAC filtering
Tomasz Duszynski [Mon, 9 Oct 2017 15:00:37 +0000 (17:00 +0200)]
net/mrvl: support MAC filtering

Add support for unicast and multicast mac filters.

Signed-off-by: Jacek Siuda <jck@semihalf.com>
Signed-off-by: Tomasz Duszynski <tdu@semihalf.com>
7 years agonet/mrvl: support for promiscuous and allmulticast
Tomasz Duszynski [Mon, 9 Oct 2017 15:00:36 +0000 (17:00 +0200)]
net/mrvl: support for promiscuous and allmulticast

Add support for promiscuous and allmulticast modes.

Signed-off-by: Jacek Siuda <jck@semihalf.com>
Signed-off-by: Tomasz Duszynski <tdu@semihalf.com>
7 years agonet/mrvl: support jumbo frame
Tomasz Duszynski [Mon, 9 Oct 2017 15:00:35 +0000 (17:00 +0200)]
net/mrvl: support jumbo frame

Add jumbo frame support.

Signed-off-by: Jacek Siuda <jck@semihalf.com>
Signed-off-by: Tomasz Duszynski <tdu@semihalf.com>
7 years agonet/mrvl: support updating MTU
Tomasz Duszynski [Mon, 9 Oct 2017 15:00:34 +0000 (17:00 +0200)]
net/mrvl: support updating MTU

Add support for updating mtu.

Signed-off-by: Jacek Siuda <jck@semihalf.com>
Signed-off-by: Tomasz Duszynski <tdu@semihalf.com>
7 years agonet/mrvl: add link speed capabilities
Tomasz Duszynski [Mon, 9 Oct 2017 15:00:33 +0000 (17:00 +0200)]
net/mrvl: add link speed capabilities

Return supported link speed capabilities via rte_dev_info_get().

Signed-off-by: Jacek Siuda <jck@semihalf.com>
Signed-off-by: Tomasz Duszynski <tdu@semihalf.com>
7 years agonet/mrvl: add link update
Tomasz Duszynski [Mon, 9 Oct 2017 15:00:32 +0000 (17:00 +0200)]
net/mrvl: add link update

Add support for retrieving physical link information i.e:
speed, duplex and link status.

Signed-off-by: Jacek Siuda <jck@semihalf.com>
Signed-off-by: Tomasz Duszynski <tdu@semihalf.com>
7 years agonet/mrvl: add Rx/Tx support
Tomasz Duszynski [Mon, 9 Oct 2017 15:00:31 +0000 (17:00 +0200)]
net/mrvl: add Rx/Tx support

Add rx/tx support.

Signed-off-by: Jacek Siuda <jck@semihalf.com>
Signed-off-by: Tomasz Duszynski <tdu@semihalf.com>
7 years agonet/mrvl: add net PMD skeleton
Tomasz Duszynski [Mon, 9 Oct 2017 15:00:30 +0000 (17:00 +0200)]
net/mrvl: add net PMD skeleton

Add mrvl net pmd driver skeleton providing base for the further
development. Besides the basic functionality QoS configuration is
introduced as well.

Signed-off-by: Jacek Siuda <jck@semihalf.com>
Signed-off-by: Tomasz Duszynski <tdu@semihalf.com>
7 years agomk: link the whole cfgfile library
Tomasz Duszynski [Mon, 9 Oct 2017 15:00:29 +0000 (17:00 +0200)]
mk: link the whole cfgfile library

MRVL net pmd needs rte_cfgfile to parse QoS configuration file thus
librte_pmd_mrvl.a contains undefined symbols from librte_cfgfile.a.

As a result linking applications under app/ directory will fail
because librte_cfgfile.a comes before librte_pmd_mrvl.a during
the linking stage.

Linking the whole librte_cfgfile.a solves the issue.

Signed-off-by: Jacek Siuda <jck@semihalf.com>
Signed-off-by: Tomasz Duszynski <tdu@semihalf.com>
7 years agonet/mlx5: add vectorized Rx/Tx burst for ARM
Yongseok Koh [Mon, 9 Oct 2017 18:47:00 +0000 (11:47 -0700)]
net/mlx5: add vectorized Rx/Tx burst for ARM

Brings vectorization through NEON instructions.

Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
7 years agonet/mlx5: fix configuration of Rx CQE compression
Yongseok Koh [Mon, 9 Oct 2017 18:46:59 +0000 (11:46 -0700)]
net/mlx5: fix configuration of Rx CQE compression

With the upstream rdma-core, to enable Rx CQE compression,
mlx5dv_create_cq() in Direct Verbs has to be used instead of regular
Verbs call (ibv_create_cq()). And if the size of CQE is 128 bytes,
compression is supported only by certain devices. Thus, it has to be
decided by checking the capability bits.

Fixes: 43e9d9794cde ("net/mlx5: support upstream rdma-core")
Cc: stable@dpdk.org
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
7 years agonet/mlx5: match Rx completion entry size to cacheline
Yongseok Koh [Mon, 9 Oct 2017 18:46:58 +0000 (11:46 -0700)]
net/mlx5: match Rx completion entry size to cacheline

The size of Rx completion entry should match the size of a cacheline.
This is already reflected in struct mlx5_cqe by adding 64bytes padding
if a cacheline is 128bytes. Some ARM CPUs have 128bytes cacheline.

Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
7 years agonet/mlx5: separate shareable vector functions
Yongseok Koh [Mon, 9 Oct 2017 18:46:57 +0000 (11:46 -0700)]
net/mlx5: separate shareable vector functions

Considering more architecture (e.g. ARM and PowerPC) will be added for
vectorized Rx/Tx burst, all the shareable functions which don't use any
vector intrinsics need to be separated from architecture-dependent
functions. All the vector functions for x86 SSE are moved to a new
header file - mlx5_rxtx_vec_sse.h. And shareable common functions are
now in mlx5_rxtx_vec.c.

Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
7 years agonet/mlx5: use static assert for compile-time sanity checks
Yongseok Koh [Mon, 9 Oct 2017 18:46:56 +0000 (11:46 -0700)]
net/mlx5: use static assert for compile-time sanity checks

Replace compile-time sanity check with static_assert() as c11 standard
has been set. Add mlx5_rxtx_vec.h and move the sanity checks to the file

Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>