net/mlx5: add Rx HW timestamp
authorRaslan Darawsheh <rasland@mellanox.com>
Tue, 10 Oct 2017 14:37:07 +0000 (17:37 +0300)
committerFerruh Yigit <ferruh.yigit@intel.com>
Thu, 12 Oct 2017 00:52:49 +0000 (01:52 +0100)
Expose Rx HW timestamp to packet mbufs.

Signed-off-by: Raslan Darawsheh <rasland@mellanox.com>
Acked-by: Yongseok Koh <yskoh@mellanox.com>
drivers/net/mlx5/mlx5_ethdev.c
drivers/net/mlx5/mlx5_rxq.c
drivers/net/mlx5/mlx5_rxtx.c
drivers/net/mlx5/mlx5_rxtx.h
drivers/net/mlx5/mlx5_rxtx_vec_neon.h
drivers/net/mlx5/mlx5_rxtx_vec_sse.h

index 9f5b489..e06dce3 100644 (file)
@@ -697,7 +697,9 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
                  DEV_RX_OFFLOAD_UDP_CKSUM |
                  DEV_RX_OFFLOAD_TCP_CKSUM) :
                 0) |
-               (priv->hw_vlan_strip ? DEV_RX_OFFLOAD_VLAN_STRIP : 0);
+               (priv->hw_vlan_strip ? DEV_RX_OFFLOAD_VLAN_STRIP : 0) |
+               DEV_RX_OFFLOAD_TIMESTAMP;
+
        if (!priv->mps)
                info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
        if (priv->hw_csum)
index e1867cb..632d451 100644 (file)
@@ -608,7 +608,7 @@ mlx5_priv_rxq_ibv_new(struct priv *priv, uint16_t idx)
        attr.cq.mlx5 = (struct mlx5dv_cq_init_attr){
                .comp_mask = 0,
        };
-       if (priv->cqe_comp) {
+       if (priv->cqe_comp && !rxq_data->hw_timestamp) {
                attr.cq.mlx5.comp_mask |=
                        MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
                attr.cq.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
@@ -618,6 +618,8 @@ mlx5_priv_rxq_ibv_new(struct priv *priv, uint16_t idx)
                 */
                if (rxq_check_vec_support(rxq_data) < 0)
                        cqe_n *= 2;
+       } else if (priv->cqe_comp && rxq_data->hw_timestamp) {
+               DEBUG("Rx CQE compression is disabled for HW timestamp");
        }
        tmpl->cq = ibv_cq_ex_to_cq(mlx5dv_create_cq(priv->ctx, &attr.cq.ibv,
                                                    &attr.cq.mlx5));
@@ -939,6 +941,8 @@ mlx5_priv_rxq_new(struct priv *priv, uint16_t idx, uint16_t desc,
        if (priv->hw_csum_l2tun)
                tmpl->rxq.csum_l2tun =
                        !!dev->data->dev_conf.rxmode.hw_ip_checksum;
+       tmpl->rxq.hw_timestamp =
+                       !!dev->data->dev_conf.rxmode.hw_timestamp;
        /* Configure VLAN stripping. */
        tmpl->rxq.vlan_strip = (priv->hw_vlan_strip &&
                               !!dev->data->dev_conf.rxmode.hw_vlan_strip);
index 275cd6a..961967b 100644 (file)
@@ -1887,6 +1887,11 @@ mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
                                pkt->vlan_tci =
                                        rte_be_to_cpu_16(cqe->vlan_info);
                        }
+                       if (rxq->hw_timestamp) {
+                               pkt->timestamp =
+                                       rte_be_to_cpu_64(cqe->timestamp);
+                               pkt->ol_flags |= PKT_RX_TIMESTAMP;
+                       }
                        if (rxq->crc_present)
                                len -= ETHER_CRC_LEN;
                        PKT_LEN(pkt) = len;
index 827cb3c..ea03742 100644 (file)
@@ -106,6 +106,7 @@ struct rxq_zip {
 struct mlx5_rxq_data {
        unsigned int csum:1; /* Enable checksum offloading. */
        unsigned int csum_l2tun:1; /* Same for L2 tunnels. */
+       unsigned int hw_timestamp:1; /* Enable HW timestamp. */
        unsigned int vlan_strip:1; /* Enable VLAN stripping. */
        unsigned int crc_present:1; /* CRC must be subtracted. */
        unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
@@ -114,7 +115,7 @@ struct mlx5_rxq_data {
        unsigned int rss_hash:1; /* RSS hash result is enabled. */
        unsigned int mark:1; /* Marked flow available on the queue. */
        unsigned int pending_err:1; /* CQE error needs to be handled. */
-       unsigned int :15; /* Remaining bits. */
+       unsigned int :14; /* Remaining bits. */
        volatile uint32_t *rq_db;
        volatile uint32_t *cq_db;
        uint16_t port_id;
index 86b37d5..4cb7f28 100644 (file)
@@ -566,7 +566,9 @@ rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq,
 {
        uint16x4_t ptype;
        uint32x4_t pinfo, cv_flags;
-       uint32x4_t ol_flags = vdupq_n_u32(rxq->rss_hash * PKT_RX_RSS_HASH);
+       uint32x4_t ol_flags =
+               vdupq_n_u32(rxq->rss_hash * PKT_RX_RSS_HASH |
+                           rxq->hw_timestamp * PKT_RX_TIMESTAMP);
        const uint32x4_t ptype_ol_mask = { 0x106, 0x106, 0x106, 0x106 };
        const uint8x16_t cv_flag_sel = {
                0,
@@ -973,6 +975,24 @@ rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
                /* C.4 fill in mbuf - rearm_data and packet_type. */
                rxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag,
                                         opcode, &elts[pos]);
+               if (rxq->hw_timestamp) {
+                       elts[pos]->timestamp =
+                               rte_be_to_cpu_64(
+                                       container_of(p0, struct mlx5_cqe,
+                                                    pkt_info)->timestamp);
+                       elts[pos + 1]->timestamp =
+                               rte_be_to_cpu_64(
+                                       container_of(p1, struct mlx5_cqe,
+                                                    pkt_info)->timestamp);
+                       elts[pos + 2]->timestamp =
+                               rte_be_to_cpu_64(
+                                       container_of(p2, struct mlx5_cqe,
+                                                    pkt_info)->timestamp);
+                       elts[pos + 3]->timestamp =
+                               rte_be_to_cpu_64(
+                                       container_of(p3, struct mlx5_cqe,
+                                                    pkt_info)->timestamp);
+               }
 #ifdef MLX5_PMD_SOFT_COUNTERS
                /* Add up received bytes count. */
                byte_cnt = vbic_u16(byte_cnt, invalid_mask);
index c2142d7..e9819b7 100644 (file)
@@ -545,7 +545,8 @@ rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq, __m128i cqes[4],
 {
        __m128i pinfo0, pinfo1;
        __m128i pinfo, ptype;
-       __m128i ol_flags = _mm_set1_epi32(rxq->rss_hash * PKT_RX_RSS_HASH);
+       __m128i ol_flags = _mm_set1_epi32(rxq->rss_hash * PKT_RX_RSS_HASH |
+                                         rxq->hw_timestamp * PKT_RX_TIMESTAMP);
        __m128i cv_flags;
        const __m128i zero = _mm_setzero_si128();
        const __m128i ptype_mask =
@@ -938,6 +939,16 @@ rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
                rxq->pending_err |= !!_mm_cvtsi128_si64(opcode);
                /* D.5 fill in mbuf - rearm_data and packet_type. */
                rxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]);
+               if (rxq->hw_timestamp) {
+                       pkts[pos]->timestamp =
+                               rte_be_to_cpu_64(cq[pos].timestamp);
+                       pkts[pos + 1]->timestamp =
+                               rte_be_to_cpu_64(cq[pos + p1].timestamp);
+                       pkts[pos + 2]->timestamp =
+                               rte_be_to_cpu_64(cq[pos + p2].timestamp);
+                       pkts[pos + 3]->timestamp =
+                               rte_be_to_cpu_64(cq[pos + p3].timestamp);
+               }
 #ifdef MLX5_PMD_SOFT_COUNTERS
                /* Add up received bytes count. */
                byte_cnt = _mm_shuffle_epi8(op_own, len_shuf_mask);