prog_fuse.sh: reindent file

[aversive.git] / include / aversive / parts / ATmega406.h

/*  
 *  Copyright Droids Corporation, Microb Technology, Eirbot (2009)
 * 
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 *  Revision : $Id $
 *
 */

/* WARNING : this file is automatically generated by scripts.
 * You should not edit it. If you find something wrong in it,
 * write to zer0@droids-corp.org */


/* prescalers timer 0 */
#define TIMER0_PRESCALER_DIV_0          0
#define TIMER0_PRESCALER_DIV_1          1
#define TIMER0_PRESCALER_DIV_8          2
#define TIMER0_PRESCALER_DIV_64         3
#define TIMER0_PRESCALER_DIV_256        4
#define TIMER0_PRESCALER_DIV_1024       5
#define TIMER0_PRESCALER_DIV_FALL       6
#define TIMER0_PRESCALER_DIV_RISE       7

#define TIMER0_PRESCALER_REG_0          0
#define TIMER0_PRESCALER_REG_1          1
#define TIMER0_PRESCALER_REG_2          8
#define TIMER0_PRESCALER_REG_3          64
#define TIMER0_PRESCALER_REG_4          256
#define TIMER0_PRESCALER_REG_5          1024
#define TIMER0_PRESCALER_REG_6          -1
#define TIMER0_PRESCALER_REG_7          -2

/* prescalers timer 1 */
#define TIMER1_PRESCALER_DIV_0          0
#define TIMER1_PRESCALER_DIV_1          1
#define TIMER1_PRESCALER_DIV_8          2
#define TIMER1_PRESCALER_DIV_32         3
#define TIMER1_PRESCALER_DIV_64         4
#define TIMER1_PRESCALER_DIV_128        5
#define TIMER1_PRESCALER_DIV_256        6
#define TIMER1_PRESCALER_DIV_1024       7

#define TIMER1_PRESCALER_REG_0          0
#define TIMER1_PRESCALER_REG_1          1
#define TIMER1_PRESCALER_REG_2          8
#define TIMER1_PRESCALER_REG_3          32
#define TIMER1_PRESCALER_REG_4          64
#define TIMER1_PRESCALER_REG_5          128
#define TIMER1_PRESCALER_REG_6          256
#define TIMER1_PRESCALER_REG_7          1024


/* available timers */

/* overflow interrupt number */
#define SIG_OVERFLOW_TOTAL_NUM 0

/* output compare interrupt number */
#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0

/* Pwm nums */
#define PWM_TOTAL_NUM 0

/* input capture interrupt number */
#define SIG_INPUT_CAPTURE_TOTAL_NUM 0


/* CADAC2 */
#define CADAC16_REG          CADAC2
#define CADAC17_REG          CADAC2
#define CADAC18_REG          CADAC2
#define CADAC19_REG          CADAC2
#define CADAC20_REG          CADAC2
#define CADAC21_REG          CADAC2
#define CADAC22_REG          CADAC2
#define CADAC23_REG          CADAC2

/* CADAC3 */
#define CADAC24_REG          CADAC3
#define CADAC25_REG          CADAC3
#define CADAC26_REG          CADAC3
#define CADAC27_REG          CADAC3
#define CADAC28_REG          CADAC3
#define CADAC29_REG          CADAC3
#define CADAC30_REG          CADAC3
#define CADAC31_REG          CADAC3

/* CADAC0 */
#define CADAC00_REG          CADAC0
#define CADAC01_REG          CADAC0
#define CADAC02_REG          CADAC0
#define CADAC03_REG          CADAC0
#define CADAC04_REG          CADAC0
#define CADAC05_REG          CADAC0
#define CADAC06_REG          CADAC0
#define CADAC07_REG          CADAC0

/* CADAC1 */
#define CADAC08_REG          CADAC1
#define CADAC09_REG          CADAC1
#define CADAC10_REG          CADAC1
#define CADAC11_REG          CADAC1
#define CADAC12_REG          CADAC1
#define CADAC13_REG          CADAC1
#define CADAC14_REG          CADAC1
#define CADAC15_REG          CADAC1

/* EECR */
#define EERE_REG             EECR
#define EEPE_REG             EECR
#define EEMPE_REG            EECR
#define EERIE_REG            EECR
#define EEPM0_REG            EECR
#define EEPM1_REG            EECR

/* PCIFR */
#define PCIF0_REG            PCIFR
#define PCIF1_REG            PCIFR

/* WUTCSR */
#define WUTP0_REG            WUTCSR
#define WUTP1_REG            WUTCSR
#define WUTP2_REG            WUTCSR
#define WUTE_REG             WUTCSR
#define WUTR_REG             WUTCSR
#define WUTCF_REG            WUTCSR
#define WUTIE_REG            WUTCSR
#define WUTIF_REG            WUTCSR

/* SREG */
#define C_REG                SREG
#define Z_REG                SREG
#define N_REG                SREG
#define V_REG                SREG
#define S_REG                SREG
#define H_REG                SREG
#define T_REG                SREG
#define I_REG                SREG

/* PCICR */
#define PCIE0_REG            PCICR
#define PCIE1_REG            PCICR

/* DDRB */
#define DDB0_REG             DDRB
#define DDB1_REG             DDRB
#define DDB2_REG             DDRB
#define DDB3_REG             DDRB
#define DDB4_REG             DDRB
#define DDB5_REG             DDRB
#define DDB6_REG             DDRB
#define DDB7_REG             DDRB

/* BPCR */
#define CCD_REG              BPCR
#define DCD_REG              BPCR
#define SCD_REG              BPCR
#define DUVD_REG             BPCR

/* WDTCSR */
#define WDP0_REG             WDTCSR
#define WDP1_REG             WDTCSR
#define WDP2_REG             WDTCSR
#define WDE_REG              WDTCSR
#define WDCE_REG             WDTCSR
#define WDP3_REG             WDTCSR
#define WDIE_REG             WDTCSR
#define WDIF_REG             WDTCSR

/* EEDR */
#define EEDR0_REG            EEDR
#define EEDR1_REG            EEDR
#define EEDR2_REG            EEDR
#define EEDR3_REG            EEDR
#define EEDR4_REG            EEDR
#define EEDR5_REG            EEDR
#define EEDR6_REG            EEDR
#define EEDR7_REG            EEDR

/* TWDR */
#define TWD0_REG             TWDR
#define TWD1_REG             TWDR
#define TWD2_REG             TWDR
#define TWD3_REG             TWDR
#define TWD4_REG             TWDR
#define TWD5_REG             TWDR
#define TWD6_REG             TWDR
#define TWD7_REG             TWDR

/* PIND */
#define PIND0_REG            PIND
#define PIND1_REG            PIND

/* GTCCR */
#define PSRSYNC_REG          GTCCR
#define TSM_REG              GTCCR

/* TWBR */
#define TWBR0_REG            TWBR
#define TWBR1_REG            TWBR
#define TWBR2_REG            TWBR
#define TWBR3_REG            TWBR
#define TWBR4_REG            TWBR
#define TWBR5_REG            TWBR
#define TWBR6_REG            TWBR
#define TWBR7_REG            TWBR

/* BGCRR */
#define BGCR0_REG            BGCRR
#define BGCR1_REG            BGCRR
#define BGCR2_REG            BGCRR
#define BGCR3_REG            BGCRR
#define BGCR4_REG            BGCRR
#define BGCR5_REG            BGCRR
#define BGCR6_REG            BGCRR
#define BGCR7_REG            BGCRR

/* DDRA */
#define DDA0_REG             DDRA
#define DDA1_REG             DDRA
#define DDA2_REG             DDRA
#define DDA3_REG             DDRA
#define DDA4_REG             DDRA
#define DDA5_REG             DDRA
#define DDA6_REG             DDRA
#define DDA7_REG             DDRA

/* EIMSK */
#define INT0_REG             EIMSK
#define INT1_REG             EIMSK
#define INT2_REG             EIMSK
#define INT3_REG             EIMSK

/* PRR0 */
#define PRVADC_REG           PRR0
#define PRTIM0_REG           PRR0
#define PRTIM1_REG           PRR0
#define PRTWI_REG            PRR0

/* PCMSK1 */
#define PCINT8_REG           PCMSK1
#define PCINT9_REG           PCMSK1
#define PCINT10_REG          PCMSK1
#define PCINT11_REG          PCMSK1
#define PCINT12_REG          PCMSK1
#define PCINT13_REG          PCMSK1
#define PCINT14_REG          PCMSK1
#define PCINT15_REG          PCMSK1

/* OCR0A */
#define OCR0A0_REG           OCR0A
#define OCR0A1_REG           OCR0A
#define OCR0A2_REG           OCR0A
#define OCR0A3_REG           OCR0A
#define OCR0A4_REG           OCR0A
#define OCR0A5_REG           OCR0A
#define OCR0A6_REG           OCR0A
#define OCR0A7_REG           OCR0A

/* BPOCD */
#define CCDL0_REG            BPOCD
#define CCDL1_REG            BPOCD
#define CCDL2_REG            BPOCD
#define CCDL3_REG            BPOCD
#define DCDL0_REG            BPOCD
#define DCDL1_REG            BPOCD
#define DCDL2_REG            BPOCD
#define DCDL3_REG            BPOCD

/* DDRD */
#define DDD0_REG             DDRD
#define DDD1_REG             DDRD

/* OCR0B */
#define OCR0B0_REG           OCR0B
#define OCR0B1_REG           OCR0B
#define OCR0B2_REG           OCR0B
#define OCR0B3_REG           OCR0B
#define OCR0B4_REG           OCR0B
#define OCR0B5_REG           OCR0B
#define OCR0B6_REG           OCR0B
#define OCR0B7_REG           OCR0B

/* SPH */
#define SP8_REG              SPH
#define SP9_REG              SPH
#define SP10_REG             SPH
#define SP11_REG             SPH
#define SP12_REG             SPH
#define SP13_REG             SPH
#define SP14_REG             SPH
#define SP15_REG             SPH

/* CCSR */
#define ACS_REG              CCSR
#define XOE_REG              CCSR

/* CADICH */
#define CADICH0_REG          CADICH
#define CADICH1_REG          CADICH
#define CADICH2_REG          CADICH
#define CADICH3_REG          CADICH
#define CADICH4_REG          CADICH
#define CADICH5_REG          CADICH
#define CADICH6_REG          CADICH
#define CADICH7_REG          CADICH

/* FCSR */
#define PFD_REG              FCSR
#define CFE_REG              FCSR
#define DFE_REG              FCSR
#define CPS_REG              FCSR
#define PWMOPC_REG           FCSR
#define PWMOC_REG            FCSR

/* SPL */
#define SP0_REG              SPL
#define SP1_REG              SPL
#define SP2_REG              SPL
#define SP3_REG              SPL
#define SP4_REG              SPL
#define SP5_REG              SPL
#define SP6_REG              SPL
#define SP7_REG              SPL

/* CADCSRB */
#define CADICIF_REG          CADCSRB
#define CADRCIF_REG          CADCSRB
#define CADACIF_REG          CADCSRB
#define CADICIE_REG          CADCSRB
#define CADRCIE_REG          CADCSRB
#define CADACIE_REG          CADCSRB

/* CADICL */
#define CADICL0_REG          CADICL
#define CADICL1_REG          CADICL
#define CADICL2_REG          CADICL
#define CADICL3_REG          CADICL
#define CADICL4_REG          CADICL
#define CADICL5_REG          CADICL
#define CADICL6_REG          CADICL
#define CADICL7_REG          CADICL

/* BPIR */
#define SCIE_REG             BPIR
#define DOCIE_REG            BPIR
#define COCIE_REG            BPIR
#define DUVIE_REG            BPIR
#define SCIF_REG             BPIR
#define DOCIF_REG            BPIR
#define COCIF_REG            BPIR
#define DUVIF_REG            BPIR

/* GPIOR1 */
#define GPIOR10_REG          GPIOR1
#define GPIOR11_REG          GPIOR1
#define GPIOR12_REG          GPIOR1
#define GPIOR13_REG          GPIOR1
#define GPIOR14_REG          GPIOR1
#define GPIOR15_REG          GPIOR1
#define GPIOR16_REG          GPIOR1
#define GPIOR17_REG          GPIOR1

/* BPPLR */
#define BPPL_REG             BPPLR
#define BPPLE_REG            BPPLR

/* TCCR1B */
#define CS10_REG             TCCR1B
#define CS11_REG             TCCR1B
#define CS12_REG             TCCR1B
#define CTC1_REG             TCCR1B

/* MCUSR */
#define PORF_REG             MCUSR
#define EXTRF_REG            MCUSR
#define BODRF_REG            MCUSR
#define WDRF_REG             MCUSR
#define JTRF_REG             MCUSR

/* EEARH */
#define EEAR8_REG            EEARH

/* CBPTR */
#define OCPT0_REG            CBPTR
#define OCPT1_REG            CBPTR
#define OCPT2_REG            CBPTR
#define OCPT3_REG            CBPTR
#define SCPT0_REG            CBPTR
#define SCPT1_REG            CBPTR
#define SCPT2_REG            CBPTR
#define SCPT3_REG            CBPTR

/* SPMCSR */
#define SPMEN_REG            SPMCSR
#define PGERS_REG            SPMCSR
#define PGWRT_REG            SPMCSR
#define BLBSET_REG           SPMCSR
#define RWWSRE_REG           SPMCSR
#define SIGRD_REG            SPMCSR
#define RWWSB_REG            SPMCSR
#define SPMIE_REG            SPMCSR

/* CADCSRA */
#define CADSE_REG            CADCSRA
#define CADSI0_REG           CADCSRA
#define CADSI1_REG           CADCSRA
#define CADAS0_REG           CADCSRA
#define CADAS1_REG           CADCSRA
#define CADUB_REG            CADCSRA
#define CADEN_REG            CADCSRA

/* BPDUV */
#define DUDL0_REG            BPDUV
#define DUDL1_REG            BPDUV
#define DUDL2_REG            BPDUV
#define DUDL3_REG            BPDUV
#define DUVT0_REG            BPDUV
#define DUVT1_REG            BPDUV

/* CADRDC */
#define CADRDC0_REG          CADRDC
#define CADRDC1_REG          CADRDC
#define CADRDC2_REG          CADRDC
#define CADRDC3_REG          CADRDC
#define CADRDC4_REG          CADRDC
#define CADRDC5_REG          CADRDC
#define CADRDC6_REG          CADRDC
#define CADRDC7_REG          CADRDC

/* TCNT1L */
#define TCNT1L0_REG          TCNT1L
#define TCNT1L1_REG          TCNT1L
#define TCNT1L2_REG          TCNT1L
#define TCNT1L3_REG          TCNT1L
#define TCNT1L4_REG          TCNT1L
#define TCNT1L5_REG          TCNT1L
#define TCNT1L6_REG          TCNT1L
#define TCNT1L7_REG          TCNT1L

/* PORTB */
#define PORTB0_REG           PORTB
#define PORTB1_REG           PORTB
#define PORTB2_REG           PORTB
#define PORTB3_REG           PORTB
#define PORTB4_REG           PORTB
#define PORTB5_REG           PORTB
#define PORTB6_REG           PORTB
#define PORTB7_REG           PORTB

/* PORTD */
#define PORTD0_REG           PORTD
#define PORTD1_REG           PORTD

/* SMCR */
#define SE_REG               SMCR
#define SM0_REG              SMCR
#define SM1_REG              SMCR
#define SM2_REG              SMCR

/* TCNT1H */
#define TCNT1H0_REG          TCNT1H
#define TCNT1H1_REG          TCNT1H
#define TCNT1H2_REG          TCNT1H
#define TCNT1H3_REG          TCNT1H
#define TCNT1H4_REG          TCNT1H
#define TCNT1H5_REG          TCNT1H
#define TCNT1H6_REG          TCNT1H
#define TCNT1H7_REG          TCNT1H

/* PORTC */
#define PORTC0_REG           PORTC

/* TWAMR */
#define TWAM0_REG            TWAMR
#define TWAM1_REG            TWAMR
#define TWAM2_REG            TWAMR
#define TWAM3_REG            TWAMR
#define TWAM4_REG            TWAMR
#define TWAM5_REG            TWAMR
#define TWAM6_REG            TWAMR

/* PORTA */
#define PORTA0_REG           PORTA
#define PORTA1_REG           PORTA
#define PORTA2_REG           PORTA
#define PORTA3_REG           PORTA
#define PORTA4_REG           PORTA
#define PORTA5_REG           PORTA
#define PORTA6_REG           PORTA
#define PORTA7_REG           PORTA

/* TWCR */
#define TWIE_REG             TWCR
#define TWEN_REG             TWCR
#define TWWC_REG             TWCR
#define TWSTO_REG            TWCR
#define TWSTA_REG            TWCR
#define TWEA_REG             TWCR
#define TWINT_REG            TWCR

/* BPSCD */
#define SCDL0_REG            BPSCD
#define SCDL1_REG            BPSCD
#define SCDL2_REG            BPSCD
#define SCDL3_REG            BPSCD

/* TCNT0 */
#define TCNT00_REG           TCNT0
#define TCNT01_REG           TCNT0
#define TCNT02_REG           TCNT0
#define TCNT03_REG           TCNT0
#define TCNT04_REG           TCNT0
#define TCNT05_REG           TCNT0
#define TCNT06_REG           TCNT0
#define TCNT07_REG           TCNT0

/* PINA */
#define PINA0_REG            PINA
#define PINA1_REG            PINA
#define PINA2_REG            PINA
#define PINA3_REG            PINA
#define PINA4_REG            PINA
#define PINA5_REG            PINA
#define PINA6_REG            PINA
#define PINA7_REG            PINA

/* OCR1AH */
#define OCR1AH0_REG          OCR1AH
#define OCR1AH1_REG          OCR1AH
#define OCR1AH2_REG          OCR1AH
#define OCR1AH3_REG          OCR1AH
#define OCR1AH4_REG          OCR1AH
#define OCR1AH5_REG          OCR1AH
#define OCR1AH6_REG          OCR1AH
#define OCR1AH7_REG          OCR1AH

/* TWAR */
#define TWGCE_REG            TWAR
#define TWA0_REG             TWAR
#define TWA1_REG             TWAR
#define TWA2_REG             TWAR
#define TWA3_REG             TWAR
#define TWA4_REG             TWAR
#define TWA5_REG             TWAR
#define TWA6_REG             TWAR

/* GPIOR0 */
#define GPIOR00_REG          GPIOR0
#define GPIOR01_REG          GPIOR0
#define GPIOR02_REG          GPIOR0
#define GPIOR03_REG          GPIOR0
#define GPIOR04_REG          GPIOR0
#define GPIOR05_REG          GPIOR0
#define GPIOR06_REG          GPIOR0
#define GPIOR07_REG          GPIOR0

/* EEARL */
#define EEAR0_REG            EEARL
#define EEAR1_REG            EEARL
#define EEAR2_REG            EEARL
#define EEAR3_REG            EEARL
#define EEAR4_REG            EEARL
#define EEAR5_REG            EEARL
#define EEAR6_REG            EEARL
#define EEAR7_REG            EEARL

/* TIMSK0 */
#define TOIE0_REG            TIMSK0
#define OCIE0A_REG           TIMSK0
#define OCIE0B_REG           TIMSK0

/* TIMSK1 */
#define TOIE1_REG            TIMSK1
#define OCIE1A_REG           TIMSK1

/* TCCR0B */
#define CS00_REG             TCCR0B
#define CS01_REG             TCCR0B
#define CS02_REG             TCCR0B
#define WGM02_REG            TCCR0B
#define FOC0B_REG            TCCR0B
#define FOC0A_REG            TCCR0B

/* BGCCR */
#define BGCC0_REG            BGCCR
#define BGCC1_REG            BGCCR
#define BGCC2_REG            BGCCR
#define BGCC3_REG            BGCCR
#define BGCC4_REG            BGCCR
#define BGCC5_REG            BGCCR
#define BGD_REG              BGCCR

/* VADMUX */
#define VADMUX0_REG          VADMUX
#define VADMUX1_REG          VADMUX
#define VADMUX2_REG          VADMUX
#define VADMUX3_REG          VADMUX

/* TWSR */
#define TWPS0_REG            TWSR
#define TWPS1_REG            TWSR
#define TWS3_REG             TWSR
#define TWS4_REG             TWSR
#define TWS5_REG             TWSR
#define TWS6_REG             TWSR
#define TWS7_REG             TWSR

/* VADCH */
#define VADC8_REG            VADCH
#define VADC9_REG            VADCH
#define VADC10_REG           VADCH
#define VADC11_REG           VADCH

/* GPIOR2 */
#define GPIOR20_REG          GPIOR2
#define GPIOR21_REG          GPIOR2
#define GPIOR22_REG          GPIOR2
#define GPIOR23_REG          GPIOR2
#define GPIOR24_REG          GPIOR2
#define GPIOR25_REG          GPIOR2
#define GPIOR26_REG          GPIOR2
#define GPIOR27_REG          GPIOR2

/* PCMSK0 */
#define PCINT0_REG           PCMSK0
#define PCINT1_REG           PCMSK0
#define PCINT2_REG           PCMSK0
#define PCINT3_REG           PCMSK0
#define PCINT4_REG           PCMSK0
#define PCINT5_REG           PCMSK0
#define PCINT6_REG           PCMSK0
#define PCINT7_REG           PCMSK0

/* VADCL */
#define VADC0_REG            VADCL
#define VADC1_REG            VADCL
#define VADC2_REG            VADCL
#define VADC3_REG            VADCL
#define VADC4_REG            VADCL
#define VADC5_REG            VADCL
#define VADC6_REG            VADCL
#define VADC7_REG            VADCL

/* EICRA */
#define ISC00_REG            EICRA
#define ISC01_REG            EICRA
#define ISC10_REG            EICRA
#define ISC11_REG            EICRA
#define ISC20_REG            EICRA
#define ISC21_REG            EICRA
#define ISC30_REG            EICRA
#define ISC31_REG            EICRA

/* VADCSR */
#define VADCCIE_REG          VADCSR
#define VADCCIF_REG          VADCSR
#define VADSC_REG            VADCSR
#define VADEN_REG            VADCSR

/* FOSCCAL */
#define FCAL0_REG            FOSCCAL
#define FCAL1_REG            FOSCCAL
#define FCAL2_REG            FOSCCAL
#define FCAL3_REG            FOSCCAL
#define FCAL4_REG            FOSCCAL
#define FCAL5_REG            FOSCCAL
#define FCAL6_REG            FOSCCAL
#define FCAL7_REG            FOSCCAL

/* DIDR0 */
#define VADC0D_REG           DIDR0
#define VADC1D_REG           DIDR0
#define VADC2D_REG           DIDR0
#define VADC3D_REG           DIDR0

/* TCCR0A */
#define WGM00_REG            TCCR0A
#define WGM01_REG            TCCR0A
#define COM0B0_REG           TCCR0A
#define COM0B1_REG           TCCR0A
#define COM0A0_REG           TCCR0A
#define COM0A1_REG           TCCR0A

/* MCUCR */
#define IVCE_REG             MCUCR
#define IVSEL_REG            MCUCR
#define PUD_REG              MCUCR
#define JTD_REG              MCUCR

/* CBCR */
#define CBE1_REG             CBCR
#define CBE2_REG             CBCR
#define CBE3_REG             CBCR
#define CBE4_REG             CBCR

/* TWBCSR */
#define TWBCIP_REG           TWBCSR
#define TWBDT0_REG           TWBCSR
#define TWBDT1_REG           TWBCSR
#define TWBCIE_REG           TWBCSR
#define TWBCIF_REG           TWBCSR

/* OCR1AL */
#define OCR1AL0_REG          OCR1AL
#define OCR1AL1_REG          OCR1AL
#define OCR1AL2_REG          OCR1AL
#define OCR1AL3_REG          OCR1AL
#define OCR1AL4_REG          OCR1AL
#define OCR1AL5_REG          OCR1AL
#define OCR1AL6_REG          OCR1AL
#define OCR1AL7_REG          OCR1AL

/* CADRCC */
#define CADRCC0_REG          CADRCC
#define CADRCC1_REG          CADRCC
#define CADRCC2_REG          CADRCC
#define CADRCC3_REG          CADRCC
#define CADRCC4_REG          CADRCC
#define CADRCC5_REG          CADRCC
#define CADRCC6_REG          CADRCC
#define CADRCC7_REG          CADRCC

/* PINB */
#define PINB0_REG            PINB
#define PINB1_REG            PINB
#define PINB2_REG            PINB
#define PINB3_REG            PINB
#define PINB4_REG            PINB
#define PINB5_REG            PINB
#define PINB6_REG            PINB
#define PINB7_REG            PINB

/* EIFR */
#define INTF0_REG            EIFR
#define INTF1_REG            EIFR
#define INTF2_REG            EIFR
#define INTF3_REG            EIFR

/* TIFR0 */
#define TOV0_REG             TIFR0
#define OCF0A_REG            TIFR0
#define OCF0B_REG            TIFR0

/* TIFR1 */
#define TOV1_REG             TIFR1
#define OCF1A_REG            TIFR1

/* pins mapping */
#define ADC0_PORT PORTA
#define ADC0_BIT 0
#define PCINT0_PORT PORTA
#define PCINT0_BIT 0

#define ADC1_PORT PORTA
#define ADC1_BIT 1
#define PCINT1_PORT PORTA
#define PCINT1_BIT 1

#define ADC2_PORT PORTA
#define ADC2_BIT 2
#define PCINT2_PORT PORTA
#define PCINT2_BIT 2

#define ADC3_PORT PORTA
#define ADC3_BIT 3
#define PCINT3_PORT PORTA
#define PCINT3_BIT 3

#define ADC4_PORT PORTA
#define ADC4_BIT 4
#define INT0_PORT PORTA
#define INT0_BIT 4
#define PCINT4_PORT PORTA
#define PCINT4_BIT 4

#define INT1_PORT PORTA
#define INT1_BIT 5
#define PCINT5_PORT PORTA
#define PCINT5_BIT 5

#define INT2_PORT PORTA
#define INT2_BIT 6
#define PCINT6_PORT PORTA
#define PCINT6_BIT 6

#define INT3_PORT PORTA
#define INT3_BIT 7
#define PCINT7_PORT PORTA
#define PCINT7_BIT 7

#define TDO_PORT PORTB
#define TDO_BIT 0
#define PCINT8_PORT PORTB
#define PCINT8_BIT 0

#define TDI_PORT PORTB
#define TDI_BIT 1
#define PCINT9_PORT PORTB
#define PCINT9_BIT 1

#define TMS_PORT PORTB
#define TMS_BIT 2
#define PCINT10_PORT PORTB
#define PCINT10_BIT 2

#define TCK_PORT PORTB
#define TCK_BIT 3
#define PCINT11_PORT PORTB
#define PCINT11_BIT 3

#define PCINT12_PORT PORTB
#define PCINT12_BIT 4

#define PCINT13_PORT PORTB
#define PCINT13_BIT 5

#define OC0A_PORT PORTB
#define OC0A_BIT 6
#define PCINT14_PORT PORTB
#define PCINT14_BIT 6

#define OC0B_PORT PORTB
#define OC0B_BIT 7
#define PCINT15_PORT PORTB
#define PCINT15_BIT 7


#define T0_PORT PORTD
#define T0_BIT 0