1 # SPDX-License-Identifier: BSD-3-Clause
2 # Copyright(c) 2017 Intel Corporation.
3 # Copyright(c) 2017 Cavium, Inc
5 # for checking defines we need to use the correct compiler flags
6 march_opt = '-march=@0@'.format(machine)
8 arm_force_native_march = false
10 flags_common_default = [
11 # Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
12 # to determine the best threshold in code. Refer to notes in source file
13 # (lib/librte_eal/common/include/arch/arm/rte_memcpy_64.h) for more info.
14 ['RTE_ARCH_ARM64_MEMCPY', false],
15 # ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],
16 # ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],
17 # Leave below RTE_ARM64_MEMCPY_xxx options commented out, unless there're
19 # ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],
20 # ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
21 # ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
23 ['RTE_LIBRTE_FM10K_PMD', false],
24 ['RTE_LIBRTE_SFC_EFX_PMD', false],
25 ['RTE_LIBRTE_AVP_PMD', false],
27 ['RTE_SCHED_VECTOR', false],
31 ['RTE_MACHINE', '"armv8a"'],
32 ['RTE_MAX_LCORE', 256],
33 ['RTE_USE_C11_MEM_MODEL', true],
34 ['RTE_CACHE_LINE_SIZE', 128]]
36 ['RTE_CACHE_LINE_SIZE', 128],
37 ['RTE_MAX_NUMA_NODES', 2],
38 ['RTE_MAX_LCORE', 96],
39 ['RTE_MAX_VFIO_GROUPS', 128]]
41 ['RTE_MACHINE', '"dpaa"'],
42 ['RTE_USE_C11_MEM_MODEL', true],
43 ['RTE_CACHE_LINE_SIZE', 64],
44 ['RTE_MAX_NUMA_NODES', 1],
45 ['RTE_MAX_LCORE', 16]]
47 ['RTE_MACHINE', '"dpaa2"'],
48 ['RTE_USE_C11_MEM_MODEL', true],
49 ['RTE_CACHE_LINE_SIZE', 64],
50 ['RTE_MAX_NUMA_NODES', 1],
51 ['RTE_MAX_LCORE', 16],
52 ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
53 flags_default_extra = []
54 flags_thunderx_extra = [
55 ['RTE_MACHINE', '"thunderx"'],
56 ['RTE_USE_C11_MEM_MODEL', false]]
57 flags_thunderx2_extra = [
58 ['RTE_MACHINE', '"thunderx2"'],
59 ['RTE_CACHE_LINE_SIZE', 64],
60 ['RTE_MAX_NUMA_NODES', 2],
61 ['RTE_MAX_LCORE', 256],
62 ['RTE_USE_C11_MEM_MODEL', true]]
63 flags_octeontx2_extra = [
64 ['RTE_MACHINE', '"octeontx2"'],
65 ['RTE_MAX_NUMA_NODES', 1],
66 ['RTE_MAX_LCORE', 24],
67 ['RTE_EAL_IGB_UIO', false],
68 ['RTE_USE_C11_MEM_MODEL', true]]
70 machine_args_generic = [
71 ['default', ['-march=armv8-a+crc+crypto']],
72 ['native', ['-march=native']],
73 ['0xd03', ['-mcpu=cortex-a53']],
74 ['0xd04', ['-mcpu=cortex-a35']],
75 ['0xd07', ['-mcpu=cortex-a57']],
76 ['0xd08', ['-mcpu=cortex-a72']],
77 ['0xd09', ['-mcpu=cortex-a73']],
78 ['0xd0a', ['-mcpu=cortex-a75']]]
80 machine_args_cavium = [
81 ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
82 ['native', ['-march=native']],
83 ['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
84 ['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
85 ['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
86 ['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra],
87 ['0xb2', ['-mcpu=octeontx2'], flags_octeontx2_extra]]
89 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
90 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
91 impl_0x41 = ['Arm', flags_generic, machine_args_generic]
92 impl_0x42 = ['Broadcom', flags_generic, machine_args_generic]
93 impl_0x43 = ['Cavium', flags_cavium, machine_args_cavium]
94 impl_0x44 = ['DEC', flags_generic, machine_args_generic]
95 impl_0x49 = ['Infineon', flags_generic, machine_args_generic]
96 impl_0x4d = ['Motorola', flags_generic, machine_args_generic]
97 impl_0x4e = ['NVIDIA', flags_generic, machine_args_generic]
98 impl_0x50 = ['AppliedMicro', flags_generic, machine_args_generic]
99 impl_0x51 = ['Qualcomm', flags_generic, machine_args_generic]
100 impl_0x53 = ['Samsung', flags_generic, machine_args_generic]
101 impl_0x56 = ['Marvell', flags_generic, machine_args_generic]
102 impl_0x69 = ['Intel', flags_generic, machine_args_generic]
103 impl_dpaa = ['NXP DPAA', flags_dpaa, machine_args_generic]
104 impl_dpaa2 = ['NXP DPAA2', flags_dpaa2, machine_args_generic]
106 dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
108 if not dpdk_conf.get('RTE_ARCH_64')
109 dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
110 dpdk_conf.set('RTE_ARCH_ARM', 1)
111 dpdk_conf.set('RTE_ARCH_ARMv7', 1)
112 # the minimum architecture supported, armv7-a, needs the following,
113 # mk/machine/armv7a/rte.vars.mk sets it too
114 machine_args += '-mfpu=neon'
116 dpdk_conf.set('RTE_CACHE_LINE_SIZE', 128)
117 dpdk_conf.set('RTE_ARCH_ARM64', 1)
120 cmd_generic = ['generic', '', '', 'default', '']
121 cmd_output = cmd_generic # Set generic by default
122 machine_args = [] # Clear previous machine args
123 if not meson.is_cross_build()
124 # The script returns ['Implementer', 'Variant', 'Architecture',
125 # 'Primary Part number', 'Revision']
126 detect_vendor = find_program(join_paths(
127 meson.current_source_dir(), 'armv8_machine.py'))
128 cmd = run_command(detect_vendor.path())
129 if cmd.returncode() == 0
130 cmd_output = cmd.stdout().to_lower().strip().split(' ')
132 # Set to generic if variable is not found
133 machine = get_variable('impl_' + cmd_output[0], ['generic'])
134 if machine[0] == 'generic'
135 machine = impl_generic
136 cmd_output = cmd_generic
138 impl_pn = cmd_output[3]
139 if arm_force_native_march == true
143 impl_id = meson.get_cross_property('implementor_id', 'generic')
144 impl_pn = meson.get_cross_property('implementor_pn', 'default')
145 machine = get_variable('impl_' + impl_id)
148 # Apply Common Defaults. These settings may be overwritten by machine
150 foreach flag: flags_common_default
152 dpdk_conf.set(flag[0], flag[1])
156 message('Implementer : ' + machine[0])
157 foreach flag: machine[1]
159 dpdk_conf.set(flag[0], flag[1])
163 foreach marg: machine[2]
164 if marg[0] == impl_pn
165 foreach flag: marg[1]
166 if cc.has_argument(flag)
170 # Apply any extra machine specific flags.
171 foreach flag: marg.get(2, flags_default_extra)
173 dpdk_conf.set(flag[0], flag[1])
179 message(machine_args)
181 if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
182 cc.get_define('__aarch64__', args: machine_args) != '')
183 dpdk_conf.set('RTE_MACHINE_CPUFLAG_NEON', 1)
184 compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
187 if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != ''
188 dpdk_conf.set('RTE_MACHINE_CPUFLAG_CRC32', 1)
189 compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
192 if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
193 dpdk_conf.set('RTE_MACHINE_CPUFLAG_AES', 1)
194 dpdk_conf.set('RTE_MACHINE_CPUFLAG_PMULL', 1)
195 dpdk_conf.set('RTE_MACHINE_CPUFLAG_SHA1', 1)
196 dpdk_conf.set('RTE_MACHINE_CPUFLAG_SHA2', 1)
197 compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
198 'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']