config: enable C11 memory model for armv8 with meson
[dpdk.git] / config / arm / meson.build
1 # SPDX-License-Identifier: BSD-3-Clause
2 # Copyright(c) 2017 Intel Corporation.
3 # Copyright(c) 2017 Cavium, Inc
4
5 # for checking defines we need to use the correct compiler flags
6 march_opt = '-march=@0@'.format(machine)
7
8 arm_force_native_march = false
9
10 machine_args_generic = [
11         ['default', ['-march=armv8-a+crc+crypto']],
12         ['native', ['-march=native']],
13         ['0xd03', ['-mcpu=cortex-a53']],
14         ['0xd04', ['-mcpu=cortex-a35']],
15         ['0xd07', ['-mcpu=cortex-a57']],
16         ['0xd08', ['-mcpu=cortex-a72']],
17         ['0xd09', ['-mcpu=cortex-a73']],
18         ['0xd0a', ['-mcpu=cortex-a75']],
19 ]
20 machine_args_cavium = [
21         ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
22         ['native', ['-march=native']],
23         ['0xa1', ['-mcpu=thunderxt88']],
24         ['0xa2', ['-mcpu=thunderxt81']],
25         ['0xa3', ['-mcpu=thunderxt83']]]
26
27 flags_common_default = [
28         # Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
29         # to determine the best threshold in code. Refer to notes in source file
30         # (lib/librte_eal/common/include/arch/arm/rte_memcpy_64.h) for more info.
31         ['RTE_ARCH_ARM64_MEMCPY', false],
32         #       ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],
33         #       ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],
34         # Leave below RTE_ARM64_MEMCPY_xxx options commented out, unless there're
35         # strong reasons.
36         #       ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],
37         #       ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
38         #       ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
39
40         ['RTE_LIBRTE_FM10K_PMD', false],
41         ['RTE_LIBRTE_SFC_EFX_PMD', false],
42         ['RTE_LIBRTE_AVP_PMD', false],
43
44         ['RTE_SCHED_VECTOR', false],
45 ]
46
47 flags_generic = [
48         ['RTE_MACHINE', '"armv8a"'],
49         ['RTE_MAX_LCORE', 256],
50         ['RTE_USE_C11_MEM_MODEL', true],
51         ['RTE_CACHE_LINE_SIZE', 128]]
52 flags_cavium = [
53         ['RTE_MACHINE', '"thunderx"'],
54         ['RTE_CACHE_LINE_SIZE', 128],
55         ['RTE_MAX_NUMA_NODES', 2],
56         ['RTE_MAX_LCORE', 96],
57         ['RTE_MAX_VFIO_GROUPS', 128],
58         ['RTE_USE_C11_MEM_MODEL', false]]
59 flags_dpaa = [
60         ['RTE_MACHINE', '"dpaa"'],
61         ['RTE_USE_C11_MEM_MODEL', true],
62         ['RTE_CACHE_LINE_SIZE', 64],
63         ['RTE_MAX_NUMA_NODES', 1],
64         ['RTE_MAX_LCORE', 16]]
65 flags_dpaa2 = [
66         ['RTE_MACHINE', '"dpaa2"'],
67         ['RTE_USE_C11_MEM_MODEL', true],
68         ['RTE_CACHE_LINE_SIZE', 64],
69         ['RTE_MAX_NUMA_NODES', 1],
70         ['RTE_MAX_LCORE', 16],
71         ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
72
73 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
74 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
75 impl_0x41 = ['Arm', flags_generic, machine_args_generic]
76 impl_0x42 = ['Broadcom', flags_generic, machine_args_generic]
77 impl_0x43 = ['Cavium', flags_cavium, machine_args_cavium]
78 impl_0x44 = ['DEC', flags_generic, machine_args_generic]
79 impl_0x49 = ['Infineon', flags_generic, machine_args_generic]
80 impl_0x4d = ['Motorola', flags_generic, machine_args_generic]
81 impl_0x4e = ['NVIDIA', flags_generic, machine_args_generic]
82 impl_0x50 = ['AppliedMicro', flags_generic, machine_args_generic]
83 impl_0x51 = ['Qualcomm', flags_generic, machine_args_generic]
84 impl_0x53 = ['Samsung', flags_generic, machine_args_generic]
85 impl_0x56 = ['Marvell', flags_generic, machine_args_generic]
86 impl_0x69 = ['Intel', flags_generic, machine_args_generic]
87 impl_dpaa = ['NXP DPAA', flags_dpaa, machine_args_generic]
88 impl_dpaa2 = ['NXP DPAA2', flags_dpaa2, machine_args_generic]
89
90 dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
91
92 if cc.sizeof('void *') != 8
93         dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
94         dpdk_conf.set('RTE_ARCH_ARM', 1)
95         dpdk_conf.set('RTE_ARCH_ARMv7', 1)
96         # the minimum architecture supported, armv7-a, needs the following,
97         # mk/machine/armv7a/rte.vars.mk sets it too
98         machine_args += '-mfpu=neon'
99 else
100         dpdk_conf.set('RTE_CACHE_LINE_SIZE', 128)
101         dpdk_conf.set('RTE_ARCH_ARM64', 1)
102         dpdk_conf.set('RTE_ARCH_64', 1)
103
104         machine = []
105         cmd_generic = ['generic', '', '', 'default', '']
106         cmd_output = cmd_generic # Set generic by default
107         machine_args = [] # Clear previous machine args
108         if not meson.is_cross_build()
109                 # The script returns ['Implementer', 'Variant', 'Architecture',
110                 # 'Primary Part number', 'Revision']
111                 detect_vendor = find_program(join_paths(
112                                 meson.current_source_dir(), 'armv8_machine.py'))
113                 cmd = run_command(detect_vendor.path())
114                 if cmd.returncode() == 0
115                         cmd_output = cmd.stdout().to_lower().strip().split(' ')
116                 endif
117                 # Set to generic if variable is not found
118                 machine = get_variable('impl_' + cmd_output[0], 'generic')
119                 if machine == 'generic'
120                         machine = impl_generic
121                         cmd_output = cmd_generic
122                 endif
123                 impl_pn = cmd_output[3]
124                 if arm_force_native_march == true
125                         impl_pn = 'native'
126                 endif
127         else
128                 impl_id = meson.get_cross_property('implementor_id', 'generic')
129                 impl_pn = meson.get_cross_property('implementor_pn', 'default')
130                 machine = get_variable('impl_' + impl_id)
131         endif
132
133         # Apply Common Defaults. These settings may be overwritten by machine
134         # settings later.
135         foreach flag: flags_common_default
136                 if flag.length() > 0
137                         dpdk_conf.set(flag[0], flag[1])
138                 endif
139         endforeach
140
141         message('Implementer : ' + machine[0])
142         foreach flag: machine[1]
143                 if flag.length() > 0
144                         dpdk_conf.set(flag[0], flag[1])
145                 endif
146         endforeach
147         # Primary part number based mcpu flags are supported
148         # for gcc versions > 7
149         if cc.version().version_compare(
150                         '<7.0') or cmd_output.length() == 0
151                 if not meson.is_cross_build() and arm_force_native_march == true
152                         impl_pn = 'native'
153                 else
154                         impl_pn = 'default'
155                 endif
156         endif
157         foreach marg: machine[2]
158                 if marg[0] == impl_pn
159                         foreach f: marg[1]
160                                 machine_args += f
161                         endforeach
162                 endif
163         endforeach
164 endif
165 message(machine_args)
166
167 if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
168     cc.get_define('__aarch64__', args: machine_args) != '')
169         dpdk_conf.set('RTE_MACHINE_CPUFLAG_NEON', 1)
170         compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
171 endif
172
173 if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != ''
174         dpdk_conf.set('RTE_MACHINE_CPUFLAG_CRC32', 1)
175         compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
176 endif
177
178 if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
179         dpdk_conf.set('RTE_MACHINE_CPUFLAG_AES', 1)
180         dpdk_conf.set('RTE_MACHINE_CPUFLAG_PMULL', 1)
181         dpdk_conf.set('RTE_MACHINE_CPUFLAG_SHA1', 1)
182         dpdk_conf.set('RTE_MACHINE_CPUFLAG_SHA2', 1)
183         compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
184         'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']
185 endif