1 .. SPDX-License-Identifier: BSD-3-Clause
2 Copyright(c) 2015-2019 Intel Corporation.
4 Intel(R) QuickAssist (QAT) Crypto Poll Mode Driver
5 ==================================================
7 QAT documentation consists of three parts:
9 * Details of the symmetric and asymmetric crypto services below.
10 * Details of the :doc:`compression service <../compressdevs/qat_comp>`
11 in the compressdev drivers section.
12 * Details of building the common QAT infrastructure and the PMDs to support the
13 above services. See :ref:`building_qat` below.
16 Symmetric Crypto Service on QAT
17 -------------------------------
19 The QAT symmetric crypto PMD (hereafter referred to as `QAT SYM [PMD]`) provides
20 poll mode crypto driver support for the following hardware accelerator devices:
22 * ``Intel QuickAssist Technology DH895xCC``
23 * ``Intel QuickAssist Technology C62x``
24 * ``Intel QuickAssist Technology C3xxx``
25 * ``Intel QuickAssist Technology D15xx``
26 * ``Intel QuickAssist Technology P5xxx``
32 The QAT SYM PMD has support for:
36 * ``RTE_CRYPTO_CIPHER_3DES_CBC``
37 * ``RTE_CRYPTO_CIPHER_3DES_CTR``
38 * ``RTE_CRYPTO_CIPHER_AES128_CBC``
39 * ``RTE_CRYPTO_CIPHER_AES192_CBC``
40 * ``RTE_CRYPTO_CIPHER_AES256_CBC``
41 * ``RTE_CRYPTO_CIPHER_AES128_CTR``
42 * ``RTE_CRYPTO_CIPHER_AES192_CTR``
43 * ``RTE_CRYPTO_CIPHER_AES256_CTR``
44 * ``RTE_CRYPTO_CIPHER_AES_XTS``
45 * ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``
46 * ``RTE_CRYPTO_CIPHER_NULL``
47 * ``RTE_CRYPTO_CIPHER_KASUMI_F8``
48 * ``RTE_CRYPTO_CIPHER_DES_CBC``
49 * ``RTE_CRYPTO_CIPHER_AES_DOCSISBPI``
50 * ``RTE_CRYPTO_CIPHER_DES_DOCSISBPI``
51 * ``RTE_CRYPTO_CIPHER_ZUC_EEA3``
55 * ``RTE_CRYPTO_AUTH_SHA1``
56 * ``RTE_CRYPTO_AUTH_SHA1_HMAC``
57 * ``RTE_CRYPTO_AUTH_SHA224``
58 * ``RTE_CRYPTO_AUTH_SHA224_HMAC``
59 * ``RTE_CRYPTO_AUTH_SHA256``
60 * ``RTE_CRYPTO_AUTH_SHA256_HMAC``
61 * ``RTE_CRYPTO_AUTH_SHA384``
62 * ``RTE_CRYPTO_AUTH_SHA384_HMAC``
63 * ``RTE_CRYPTO_AUTH_SHA512``
64 * ``RTE_CRYPTO_AUTH_SHA512_HMAC``
65 * ``RTE_CRYPTO_AUTH_AES_XCBC_MAC``
66 * ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
67 * ``RTE_CRYPTO_AUTH_MD5_HMAC``
68 * ``RTE_CRYPTO_AUTH_NULL``
69 * ``RTE_CRYPTO_AUTH_KASUMI_F9``
70 * ``RTE_CRYPTO_AUTH_AES_GMAC``
71 * ``RTE_CRYPTO_AUTH_ZUC_EIA3``
72 * ``RTE_CRYPTO_AUTH_AES_CMAC``
74 Supported AEAD algorithms:
76 * ``RTE_CRYPTO_AEAD_AES_GCM``
77 * ``RTE_CRYPTO_AEAD_AES_CCM``
81 * ``RTE_SECURITY_PROTOCOL_DOCSIS``
86 All the usual chains are supported and also some mixed chains:
88 .. table:: Supported hash-cipher chains for wireless digest-encrypted cases
90 +------------------+-----------+-------------+----------+----------+
91 | Cipher algorithm | NULL AUTH | SNOW3G UIA2 | ZUC EIA3 | AES CMAC |
92 +==================+===========+=============+==========+==========+
93 | NULL CIPHER | Y | 2&3 | 2&3 | Y |
94 +------------------+-----------+-------------+----------+----------+
95 | SNOW3G UEA2 | 2&3 | Y | 2&3 | 2&3 |
96 +------------------+-----------+-------------+----------+----------+
97 | ZUC EEA3 | 2&3 | 2&3 | 2&3 | 2&3 |
98 +------------------+-----------+-------------+----------+----------+
99 | AES CTR | Y | 2&3 | 2&3 | Y |
100 +------------------+-----------+-------------+----------+----------+
102 * The combinations marked as "Y" are supported on all QAT hardware versions.
103 * The combinations marked as "2&3" are supported on GEN2/GEN3 QAT hardware only.
109 * Only supports the session-oriented API implementation (session-less APIs are not supported).
110 * SNOW 3G (UEA2), KASUMI (F8) and ZUC (EEA3) supported only if cipher length and offset fields are byte-multiple.
111 * SNOW 3G (UIA2) and ZUC (EIA3) supported only if hash length and offset fields are byte-multiple.
112 * No BSD support as BSD QAT kernel driver not available.
113 * ZUC EEA3/EIA3 is not supported by dh895xcc devices
114 * Maximum additional authenticated data (AAD) for GCM is 240 bytes long and must be passed to the device in a buffer rounded up to the nearest block-size multiple (x16) and padded with zeros.
115 * Queue-pairs are thread-safe on Intel CPUs but Queues are not (that is, within a single
116 queue-pair all enqueues to the TX queue must be done from one thread and all dequeues
117 from the RX queue must be done from one thread, but enqueues and dequeues may be done
118 in different threads.)
119 * A GCM limitation exists, but only in the case where there are multiple
120 generations of QAT devices on a single platform.
121 To optimise performance, the GCM crypto session should be initialised for the
122 device generation to which the ops will be enqueued. Specifically if a GCM
123 session is initialised on a GEN2 device, but then attached to an op enqueued
124 to a GEN3 device, it will work but cannot take advantage of hardware
125 optimisations in the GEN3 device. And if a GCM session is initialised on a
126 GEN3 device, then attached to an op sent to a GEN1/GEN2 device, it will not be
127 enqueued to the device and will be marked as failed. The simplest way to
128 mitigate this is to use the bdf whitelist to avoid mixing devices of different
129 generations in the same process if planning to use for GCM.
130 * The mixed algo feature on GEN2 is not supported by all kernel drivers. Check
131 the notes under the Available Kernel Drivers table below for specific details.
132 * Out-of-place is not supported for combined Crypto-CRC DOCSIS security
134 * ``RTE_CRYPTO_CIPHER_DES_DOCSISBPI`` is not supported for combined Crypto-CRC
135 DOCSIS security protocol.
137 Extra notes on KASUMI F9
138 ~~~~~~~~~~~~~~~~~~~~~~~~
140 When using KASUMI F9 authentication algorithm, the input buffer must be
141 constructed according to the
142 `3GPP KASUMI specification <http://cryptome.org/3gpp/35201-900.pdf>`_
143 (section 4.4, page 13). The input buffer has to have COUNT (4 bytes),
144 FRESH (4 bytes), MESSAGE and DIRECTION (1 bit) concatenated. After the DIRECTION
145 bit, a single '1' bit is appended, followed by between 0 and 7 '0' bits, so that
146 the total length of the buffer is multiple of 8 bits. Note that the actual
147 message can be any length, specified in bits.
149 Once this buffer is passed this way, when creating the crypto operation,
150 length of data to authenticate "op.sym.auth.data.length" must be the length
151 of all the items described above, including the padding at the end.
152 Also, offset of data to authenticate "op.sym.auth.data.offset"
153 must be such that points at the start of the COUNT bytes.
155 Asymmetric Crypto Service on QAT
156 --------------------------------
158 The QAT asymmetric crypto PMD (hereafter referred to as `QAT ASYM [PMD]`) provides
159 poll mode crypto driver support for the following hardware accelerator devices:
161 * ``Intel QuickAssist Technology DH895xCC``
162 * ``Intel QuickAssist Technology C62x``
163 * ``Intel QuickAssist Technology C3xxx``
164 * ``Intel QuickAssist Technology D15xx``
165 * ``Intel QuickAssist Technology P5xxx``
167 The QAT ASYM PMD has support for:
169 * ``RTE_CRYPTO_ASYM_XFORM_MODEX``
170 * ``RTE_CRYPTO_ASYM_XFORM_MODINV``
175 * Big integers longer than 4096 bits are not supported.
176 * Queue-pairs are thread-safe on Intel CPUs but Queues are not (that is, within a single
177 queue-pair all enqueues to the TX queue must be done from one thread and all dequeues
178 from the RX queue must be done from one thread, but enqueues and dequeues may be done
179 in different threads.)
180 * RSA-2560, RSA-3584 are not supported
187 A QAT device can host multiple acceleration services:
189 * symmetric cryptography
191 * asymmetric cryptography
193 These services are provided to DPDK applications via PMDs which register to
194 implement the corresponding cryptodev and compressdev APIs. The PMDs use
195 common QAT driver code which manages the QAT PCI device. They also depend on a
196 QAT kernel driver being installed on the platform, see :ref:`qat_kernel` below.
199 Configuring and Building the DPDK QAT PMDs
200 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
203 Further information on configuring, building and installing DPDK is described
204 :doc:`here <../linux_gsg/build_dpdk>`.
207 Quick instructions for QAT cryptodev PMD are as follows:
209 .. code-block:: console
211 cd to the top-level DPDK directory
213 sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT_SYM\)=n,\1=y,' build/.config
215 sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT_ASYM\)=n,\1=y,' build/.config
218 Quick instructions for QAT compressdev PMD are as follows:
220 .. code-block:: console
222 cd to the top-level DPDK directory
227 .. _building_qat_config:
232 These are the build configuration options affecting QAT, and their default values:
234 .. code-block:: console
236 CONFIG_RTE_LIBRTE_PMD_QAT=y
237 CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
238 CONFIG_RTE_LIBRTE_PMD_QAT_ASYM=n
239 CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES=48
240 CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE=65536
242 CONFIG_RTE_LIBRTE_PMD_QAT must be enabled for any QAT PMD to be built.
244 Both QAT SYM PMD and QAT ASYM PMD have an external dependency on libcrypto, so are not
245 built by default. CONFIG_RTE_LIBRTE_PMD_QAT_SYM/ASYM should be enabled to build them.
247 The QAT compressdev PMD has no external dependencies, so needs no configuration
248 options and is built by default.
250 The number of VFs per PF varies - see table below. If multiple QAT packages are
251 installed on a platform then CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES should be
252 adjusted to the number of VFs which the QAT common code will need to handle.
256 There are separate config items (not QAT-specific) for max cryptodevs
257 CONFIG_RTE_CRYPTO_MAX_DEVS and max compressdevs CONFIG_RTE_COMPRESS_MAX_DEVS,
258 if necessary these should be adjusted to handle the total of QAT and other
259 devices which the process will use. In particular for crypto, where each
260 QAT VF may expose two crypto devices, sym and asym, it may happen that the
261 number of devices will be bigger than MAX_DEVS and the process will show an error
262 during PMD initialisation. To avoid this problem CONFIG_RTE_CRYPTO_MAX_DEVS may be
263 increased or -w, pci-whitelist domain:bus:devid:func option may be used.
266 QAT compression PMD needs intermediate buffers to support Deflate compression
267 with Dynamic Huffman encoding. CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE
268 specifies the size of a single buffer, the PMD will allocate a multiple of these,
269 plus some extra space for associated meta-data. For GEN2 devices, 20 buffers are
270 allocated while for GEN1 devices, 12 buffers are allocated, plus 1472 bytes overhead.
274 If the compressed output of a Deflate operation using Dynamic Huffman
275 Encoding is too big to fit in an intermediate buffer, then the
276 operation will be split into smaller operations and their results will
277 be merged afterwards.
278 This is not possible if any checksum calculation was requested - in such
279 case the code falls back to fixed compression.
280 To avoid this less performant case, applications should configure
281 the intermediate buffer size to be larger than the expected input data size
282 (compressed output size is usually unknown, so the only option is to make
283 larger than the input size).
286 Running QAT PMD with minimum threshold for burst size
287 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
289 If only a small number or packets can be enqueued. Each enqueue causes an expensive MMIO write.
290 These MMIO write occurrences can be optimised by setting any of the following parameters:
292 - qat_sym_enq_threshold
293 - qat_asym_enq_threshold
294 - qat_comp_enq_threshold
296 When any of these parameters is set rte_cryptodev_enqueue_burst function will
297 return 0 (thereby avoiding an MMIO) if the device is congested and number of packets
298 possible to enqueue is smaller.
299 To use this feature the user must set the parameter on process start as a device additional parameter::
301 -w 03:01.1,qat_sym_enq_threshold=32,qat_comp_enq_threshold=16
303 All parameters can be used with the same device regardless of order. Parameters are separated
304 by comma. When the same parameter is used more than once first occurrence of the parameter
306 Maximum threshold that can be set is 32.
309 Device and driver naming
310 ~~~~~~~~~~~~~~~~~~~~~~~~
312 * The qat cryptodev symmetric crypto driver name is "crypto_qat".
313 * The qat cryptodev asymmetric crypto driver name is "crypto_qat_asym".
315 The "rte_cryptodev_devices_get()" returns the devices exposed by either of these drivers.
317 * Each qat sym crypto device has a unique name, in format
318 "<pci bdf>_<service>", e.g. "0000:41:01.0_qat_sym".
319 * Each qat asym crypto device has a unique name, in format
320 "<pci bdf>_<service>", e.g. "0000:41:01.0_qat_asym".
321 This name can be passed to "rte_cryptodev_get_dev_id()" to get the device_id.
325 The cryptodev driver name is passed to the dpdk-test-crypto-perf tool in the "-devtype" parameter.
327 The qat crypto device name is in the format of the slave parameter passed to the crypto scheduler.
329 * The qat compressdev driver name is "compress_qat".
330 The rte_compressdev_devices_get() returns the devices exposed by this driver.
332 * Each qat compression device has a unique name, in format
333 <pci bdf>_<service>, e.g. "0000:41:01.0_qat_comp".
334 This name can be passed to rte_compressdev_get_dev_id() to get the device_id.
338 Dependency on the QAT kernel driver
339 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
341 To use QAT an SRIOV-enabled QAT kernel driver is required. The VF
342 devices created and initialised by this driver will be used by the QAT PMDs.
344 Instructions for installation are below, but first an explanation of the
345 relationships between the PF/VF devices and the PMDs visible to
348 Each QuickAssist PF device exposes a number of VF devices. Each VF device can
349 enable one symmetric cryptodev PMD and/or one asymmetric cryptodev PMD and/or
351 These QAT PMDs share the same underlying device and pci-mgmt code, but are
352 enumerated independently on their respective APIs and appear as independent
353 devices to applications.
357 Each VF can only be used by one DPDK process. It is not possible to share
358 the same VF across multiple processes, even if these processes are using
359 different acceleration services.
361 Conversely one DPDK process can use one or more QAT VFs and can expose both
362 cryptodev and compressdev instances on each of those VFs.
365 Available kernel drivers
366 ~~~~~~~~~~~~~~~~~~~~~~~~
368 Kernel drivers for each device for each service are listed in the following table. (Scroll right
369 to see the full table)
372 .. _table_qat_pmds_drivers:
374 .. table:: QAT device generations, devices and drivers
376 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
377 | S | A | C | Gen | Device | Driver/ver | Kernel Module | Pci Driver | PF Did | #PFs | VF Did | VFs/PF |
378 +=====+=====+=====+=====+==========+===============+===============+============+========+======+========+========+
379 | Yes | No | No | 1 | DH895xCC | linux/4.4+ | qat_dh895xcc | dh895xcc | 435 | 1 | 443 | 32 |
380 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
381 | Yes | Yes | No | " | " | 01.org/4.2.0+ | " | " | " | " | " | " |
382 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
383 | Yes | Yes | Yes | " | " | 01.org/4.3.0+ | " | " | " | " | " | " |
384 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
385 | Yes | No | No | 2 | C62x | linux/4.5+ | qat_c62x | c6xx | 37c8 | 3 | 37c9 | 16 |
386 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
387 | Yes | Yes | Yes | " | " | 01.org/4.2.0+ | " | " | " | " | " | " |
388 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
389 | Yes | No | No | 2 | C3xxx | linux/4.5+ | qat_c3xxx | c3xxx | 19e2 | 1 | 19e3 | 16 |
390 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
391 | Yes | Yes | Yes | " | " | 01.org/4.2.0+ | " | " | " | " | " | " |
392 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
393 | Yes | No | No | 2 | D15xx | p | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 |
394 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
395 | Yes | No | No | 3 | P5xxx | p | qat_p5xxx | p5xxx | 18a0 | 1 | 18a1 | 128 |
396 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
398 * Note: Symmetric mixed crypto algorithms feature on Gen 2 works only with 01.org driver version 4.9.0+
400 The first 3 columns indicate the service:
402 * S = Symmetric crypto service (via cryptodev API)
403 * A = Asymmetric crypto service (via cryptodev API)
404 * C = Compression service (via compressdev API)
406 The ``Driver`` column indicates either the Linux kernel version in which
407 support for this device was introduced or a driver available on Intel's 01.org
408 website. There are both linux in-tree and 01.org kernel drivers available for some
409 devices. p = release pending.
411 If you are running on a kernel which includes a driver for your device, see
412 `Installation using kernel.org driver`_ below. Otherwise see
413 `Installation using 01.org QAT driver`_.
416 Installation using kernel.org driver
417 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
419 The examples below are based on the C62x device, if you have a different device
420 use the corresponding values in the above table.
422 In BIOS ensure that SRIOV is enabled and either:
425 * Enable VT-d and set ``"intel_iommu=on iommu=pt"`` in the grub file.
427 Check that the QAT driver is loaded on your system, by executing::
431 You should see the kernel module for your device listed, e.g.::
434 intel_qat 82336 1 qat_c62x
436 Next, you need to expose the Virtual Functions (VFs) using the sysfs file system.
438 First find the BDFs (Bus-Device-Function) of the physical functions (PFs) of
443 You should see output similar to::
445 1a:00.0 Co-processor: Intel Corporation Device 37c8
446 3d:00.0 Co-processor: Intel Corporation Device 37c8
447 3f:00.0 Co-processor: Intel Corporation Device 37c8
449 Enable the VFs for each PF by echoing the number of VFs per PF to the pci driver::
451 echo 16 > /sys/bus/pci/drivers/c6xx/0000:1a:00.0/sriov_numvfs
452 echo 16 > /sys/bus/pci/drivers/c6xx/0000:3d:00.0/sriov_numvfs
453 echo 16 > /sys/bus/pci/drivers/c6xx/0000:3f:00.0/sriov_numvfs
455 Check that the VFs are available for use. For example ``lspci -d:37c9`` should
456 list 48 VF devices available for a ``C62x`` device.
458 To complete the installation follow the instructions in
459 `Binding the available VFs to the DPDK UIO driver`_.
463 If the QAT kernel modules are not loaded and you see an error like ``Failed
464 to load MMP firmware qat_895xcc_mmp.bin`` in kernel logs, this may be as a
465 result of not using a distribution, but just updating the kernel directly.
467 Download firmware from the `kernel firmware repo
468 <http://git.kernel.org/cgit/linux/kernel/git/firmware/linux-firmware.git/tree/>`_.
470 Copy qat binaries to ``/lib/firmware``::
472 cp qat_895xcc.bin /lib/firmware
473 cp qat_895xcc_mmp.bin /lib/firmware
475 Change to your linux source root directory and start the qat kernel modules::
477 insmod ./drivers/crypto/qat/qat_common/intel_qat.ko
478 insmod ./drivers/crypto/qat/qat_dh895xcc/qat_dh895xcc.ko
483 If you see the following warning in ``/var/log/messages`` it can be ignored:
484 ``IOMMU should be enabled for SR-IOV to work correctly``.
487 Installation using 01.org QAT driver
488 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
490 Download the latest QuickAssist Technology Driver from `01.org
491 <https://01.org/packet-processing/intel%C2%AE-quickassist-technology-drivers-and-patches>`_.
492 Consult the *Getting Started Guide* at the same URL for further information.
494 The steps below assume you are:
496 * Building on a platform with one ``C62x`` device.
497 * Using package ``qat1.7.l.4.2.0-000xx.tar.gz``.
498 * On Fedora26 kernel ``4.11.11-300.fc26.x86_64``.
500 In the BIOS ensure that SRIOV is enabled and VT-d is disabled.
502 Uninstall any existing QAT driver, for example by running:
504 * ``./installer.sh uninstall`` in the directory where originally installed.
507 Build and install the SRIOV-enabled QAT driver::
512 # Copy the package to this location and unpack
513 tar zxof qat1.7.l.4.2.0-000xx.tar.gz
515 ./configure --enable-icp-sriov=host
518 You can use ``cat /sys/kernel/debug/qat<your device type and bdf>/version/fw`` to confirm the driver is correctly installed and is using firmware version 4.2.0.
519 You can use ``lspci -d:37c9`` to confirm the presence of the 16 VF devices available per ``C62x`` PF.
521 Confirm the driver is correctly installed and is using firmware version 4.2.0::
523 cat /sys/kernel/debug/qat<your device type and bdf>/version/fw
526 Confirm the presence of 48 VF devices - 16 per PF::
531 To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_.
535 If using a later kernel and the build fails with an error relating to
536 ``strict_stroul`` not being available apply the following patch:
540 /QAT/QAT1.6/quickassist/utilities/downloader/Target_CoreLibs/uclo/include/linux/uclo_platform.h
541 + #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,18,5)
542 + #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; if (kstrtoul((str), (base), (num))) printk("Error strtoull convert %s\n", str); }
544 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)
545 #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; if (strict_strtoull((str), (base), (num))) printk("Error strtoull convert %s\n", str); }
547 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,25)
548 #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; strict_strtoll((str), (base), (num));}
550 #define STR_TO_64(str, base, num, endPtr) \
554 *(num) = -(simple_strtoull((str+1), &(endPtr), (base))); \
556 *(num) = simple_strtoull((str), &(endPtr), (base)); \
566 If the build fails due to missing header files you may need to do following::
568 sudo yum install zlib-devel
569 sudo yum install openssl-devel
570 sudo yum install libudev-devel
574 If the build or install fails due to mismatching kernel sources you may need to do the following::
576 sudo yum install kernel-headers-`uname -r`
577 sudo yum install kernel-src-`uname -r`
578 sudo yum install kernel-devel-`uname -r`
581 Binding the available VFs to the DPDK UIO driver
582 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
584 Unbind the VFs from the stock driver so they can be bound to the uio driver.
586 For an Intel(R) QuickAssist Technology DH895xCC device
587 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
589 The unbind command below assumes ``BDFs`` of ``03:01.00-03:04.07``, if your
590 VFs are different adjust the unbind command below::
592 for device in $(seq 1 4); do \
593 for fn in $(seq 0 7); do \
594 echo -n 0000:03:0${device}.${fn} > \
595 /sys/bus/pci/devices/0000\:03\:0${device}.${fn}/driver/unbind; \
599 For an Intel(R) QuickAssist Technology C62x device
600 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
602 The unbind command below assumes ``BDFs`` of ``1a:01.00-1a:02.07``,
603 ``3d:01.00-3d:02.07`` and ``3f:01.00-3f:02.07``, if your VFs are different
604 adjust the unbind command below::
606 for device in $(seq 1 2); do \
607 for fn in $(seq 0 7); do \
608 echo -n 0000:1a:0${device}.${fn} > \
609 /sys/bus/pci/devices/0000\:1a\:0${device}.${fn}/driver/unbind; \
611 echo -n 0000:3d:0${device}.${fn} > \
612 /sys/bus/pci/devices/0000\:3d\:0${device}.${fn}/driver/unbind; \
614 echo -n 0000:3f:0${device}.${fn} > \
615 /sys/bus/pci/devices/0000\:3f\:0${device}.${fn}/driver/unbind; \
619 For Intel(R) QuickAssist Technology C3xxx or D15xx device
620 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
622 The unbind command below assumes ``BDFs`` of ``01:01.00-01:02.07``, if your
623 VFs are different adjust the unbind command below::
625 for device in $(seq 1 2); do \
626 for fn in $(seq 0 7); do \
627 echo -n 0000:01:0${device}.${fn} > \
628 /sys/bus/pci/devices/0000\:01\:0${device}.${fn}/driver/unbind; \
632 Bind to the DPDK uio driver
633 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
635 Install the DPDK igb_uio driver, bind the VF PCI Device id to it and use lspci
636 to confirm the VF devices are now in use by igb_uio kernel driver,
637 e.g. for the C62x device::
639 cd to the top-level DPDK directory
641 insmod ./build/kmod/igb_uio.ko
642 echo "8086 37c9" > /sys/bus/pci/drivers/igb_uio/new_id
646 Another way to bind the VFs to the DPDK UIO driver is by using the
647 ``dpdk-devbind.py`` script::
649 cd to the top-level DPDK directory
650 ./usertools/dpdk-devbind.py -b igb_uio 0000:03:01.1
655 QAT SYM crypto PMD can be tested by running the test application::
660 ./test -l1 -n1 -w <your qat bdf>
661 RTE>>cryptodev_qat_autotest
663 QAT ASYM crypto PMD can be tested by running the test application::
668 ./test -l1 -n1 -w <your qat bdf>
669 RTE>>cryptodev_qat_asym_autotest
671 QAT compression PMD can be tested by running the test application::
674 sed -i 's,\(CONFIG_RTE_COMPRESSDEV_TEST\)=n,\1=y,' build/.config
677 ./test -l1 -n1 -w <your qat bdf>
678 RTE>>compressdev_autotest
684 There are 2 sets of trace available via the dynamic logging feature:
686 * pmd.qat_dp exposes trace on the data-path.
687 * pmd.qat_general exposes all other trace.
689 pmd.qat exposes both sets of traces.
690 They can be enabled using the log-level option (where 8=maximum log level) on
691 the process cmdline, e.g. using any of the following::
693 --log-level="pmd.qat_general,8"
694 --log-level="pmd.qat_dp,8"
695 --log-level="pmd.qat,8"
699 The global RTE_LOG_DP_LEVEL overrides data-path trace so must be set to
700 RTE_LOG_DEBUG to see all the trace. This variable is in config/rte_config.h
701 for meson build and config/common_base for gnu make.
702 Also the dynamic global log level overrides both sets of trace, so e.g. no
703 QAT trace would display in this case::
705 --log-level="7" --log-level="pmd.qat_general,8"