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3 Copyright 2015 Mellanox
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34 The MLX5 poll mode driver library (**librte_pmd_mlx5**) provides support
35 for **Mellanox ConnectX-4**, **Mellanox ConnectX-4 Lx** and **Mellanox
36 ConnectX-5** families of 10/25/40/50/100 Gb/s adapters as well as their
37 virtual functions (VF) in SR-IOV context.
39 Information and documentation about these adapters can be found on the
40 `Mellanox website <http://www.mellanox.com>`__. Help is also provided by the
41 `Mellanox community <http://community.mellanox.com/welcome>`__.
43 There is also a `section dedicated to this poll mode driver
44 <http://www.mellanox.com/page/products_dyn?product_family=209&mtag=pmd_for_dpdk>`__.
48 Due to external dependencies, this driver is disabled by default. It must
49 be enabled manually by setting ``CONFIG_RTE_LIBRTE_MLX5_PMD=y`` and
52 Implementation details
53 ----------------------
55 Besides its dependency on libibverbs (that implies libmlx5 and associated
56 kernel support), librte_pmd_mlx5 relies heavily on system calls for control
57 operations such as querying/updating the MTU and flow control parameters.
59 For security reasons and robustness, this driver only deals with virtual
60 memory addresses. The way resources allocations are handled by the kernel
61 combined with hardware specifications that allow it to handle virtual memory
62 addresses directly ensure that DPDK applications cannot access random
63 physical memory (or memory that does not belong to the current process).
65 This capability allows the PMD to coexist with kernel network interfaces
66 which remain functional, although they stop receiving unicast packets as
67 long as they share the same MAC address.
68 This means legacy linux control tools (for example: ethtool, ifconfig and
69 more) can operate on the same network interfaces that owned by the DPDK
72 Enabling librte_pmd_mlx5 causes DPDK applications to be linked against
78 - Multi arch support: x86_64, POWER8, ARMv8.
79 - Multiple TX and RX queues.
80 - Support for scattered TX and RX frames.
81 - IPv4, IPv6, TCPv4, TCPv6, UDPv4 and UDPv6 RSS on any number of queues.
82 - Several RSS hash keys, one for each flow type.
83 - Configurable RETA table.
84 - Support for multiple MAC addresses.
88 - RX CRC stripping configuration.
90 - Multicast promiscuous mode.
91 - Hardware checksum offloads.
94 - KVM and VMware ESX SR-IOV modes are supported.
95 - RSS hash result is supported.
97 - Hardware checksum TX offload for VXLAN and GRE.
99 - Statistics query including Basic, Extended and per queue.
104 - Inner RSS for VXLAN frames is not supported yet.
105 - Port statistics through software counters only.
106 - Hardware checksum RX offloads for VXLAN inner header are not supported yet.
107 - Forked secondary process not supported.
108 - Flow pattern without any specific vlan will match for vlan packets as well:
110 When VLAN spec is not specified in the pattern, the matching rule will be created with VLAN as a wild card.
111 Meaning, the flow rule::
113 flow create 0 ingress pattern eth / vlan vid is 3 / ipv4 / end ...
115 Will only match vlan packets with vid=3. and the flow rules::
117 flow create 0 ingress pattern eth / ipv4 / end ...
121 flow create 0 ingress pattern eth / vlan / ipv4 / end ...
123 Will match any ipv4 packet (VLAN included).
125 - A multi segment packet must have less than 6 segments in case the Tx burst function
126 is set to multi-packet send or Enhanced multi-packet send. Otherwise it must have
127 less than 50 segments.
135 These options can be modified in the ``.config`` file.
137 - ``CONFIG_RTE_LIBRTE_MLX5_PMD`` (default **n**)
139 Toggle compilation of librte_pmd_mlx5 itself.
141 - ``CONFIG_RTE_LIBRTE_MLX5_DEBUG`` (default **n**)
143 Toggle debugging code and stricter compilation flags. Enabling this option
144 adds additional run-time checks and debugging messages at the cost of
147 - ``CONFIG_RTE_LIBRTE_MLX5_TX_MP_CACHE`` (default **8**)
149 Maximum number of cached memory pools (MPs) per TX queue. Each MP from
150 which buffers are to be transmitted must be associated to memory regions
151 (MRs). This is a slow operation that must be cached.
153 This value is always 1 for RX queues since they use a single MP.
155 Environment variables
156 ~~~~~~~~~~~~~~~~~~~~~
158 - ``MLX5_PMD_ENABLE_PADDING``
160 Enables HW packet padding in PCI bus transactions.
162 When packet size is cache aligned and CRC stripping is enabled, 4 fewer
163 bytes are written to the PCI bus. Enabling padding makes such packets
166 In cases where PCI bandwidth is the bottleneck, padding can improve
169 This is disabled by default since this can also decrease performance for
170 unaligned packet sizes.
172 Run-time configuration
173 ~~~~~~~~~~~~~~~~~~~~~~
175 - librte_pmd_mlx5 brings kernel network interfaces up during initialization
176 because it is affected by their state. Forcing them down prevents packets
179 - **ethtool** operations on related kernel interfaces also affect the PMD.
181 - ``rxq_cqe_comp_en`` parameter [int]
183 A nonzero value enables the compression of CQE on RX side. This feature
184 allows to save PCI bandwidth and improve performance. Enabled by default.
188 - x86_64 with ConnectX-4, ConnectX-4 LX and ConnectX-5.
189 - POWER8 and ARMv8 with ConnectX-4 LX and ConnectX-5.
191 - ``txq_inline`` parameter [int]
193 Amount of data to be inlined during TX operations. Improves latency.
194 Can improve PPS performance when PCI back pressure is detected and may be
195 useful for scenarios involving heavy traffic on many queues.
197 Because additional software logic is necessary to handle this mode, this
198 option should be used with care, as it can lower performance when back
199 pressure is not expected.
201 - ``txqs_min_inline`` parameter [int]
203 Enable inline send only when the number of TX queues is greater or equal
206 This option should be used in combination with ``txq_inline`` above.
208 On ConnectX-4, ConnectX-4 LX and ConnectX-5 without Enhanced MPW:
210 - Disabled by default.
211 - In case ``txq_inline`` is set recommendation is 4.
213 On ConnectX-5 with Enhanced MPW:
215 - Set to 8 by default.
217 - ``txq_mpw_en`` parameter [int]
219 A nonzero value enables multi-packet send (MPS) for ConnectX-4 Lx and
220 enhanced multi-packet send (Enhanced MPS) for ConnectX-5. MPS allows the
221 TX burst function to pack up multiple packets in a single descriptor
222 session in order to save PCI bandwidth and improve performance at the
223 cost of a slightly higher CPU usage. When ``txq_inline`` is set along
224 with ``txq_mpw_en``, TX burst function tries to copy entire packet data
225 on to TX descriptor instead of including pointer of packet only if there
226 is enough room remained in the descriptor. ``txq_inline`` sets
227 per-descriptor space for either pointers or inlined packets. In addition,
228 Enhanced MPS supports hybrid mode - mixing inlined packets and pointers
229 in the same descriptor.
231 This option cannot be used in conjunction with ``tso`` below. When ``tso``
232 is set, ``txq_mpw_en`` is disabled.
234 It is currently only supported on the ConnectX-4 Lx and ConnectX-5
235 families of adapters. Enabled by default.
237 - ``txq_mpw_hdr_dseg_en`` parameter [int]
239 A nonzero value enables including two pointers in the first block of TX
240 descriptor. This can be used to lessen CPU load for memory copy.
242 Effective only when Enhanced MPS is supported. Disabled by default.
244 - ``txq_max_inline_len`` parameter [int]
246 Maximum size of packet to be inlined. This limits the size of packet to
247 be inlined. If the size of a packet is larger than configured value, the
248 packet isn't inlined even though there's enough space remained in the
249 descriptor. Instead, the packet is included with pointer.
251 Effective only when Enhanced MPS is supported. The default value is 256.
253 - ``tso`` parameter [int]
255 A nonzero value enables hardware TSO.
256 When hardware TSO is enabled, packets marked with TCP segmentation
257 offload will be divided into segments by the hardware. Disabled by default.
259 - ``tx_vec_en`` parameter [int]
261 A nonzero value enables Tx vector on ConnectX-5 only NIC if the number of
262 global Tx queues on the port is lesser than MLX5_VPMD_MIN_TXQS.
264 Enabled by default on ConnectX-5.
266 - ``rx_vec_en`` parameter [int]
268 A nonzero value enables Rx vector if the port is not configured in
269 multi-segment otherwise this parameter is ignored.
276 This driver relies on external libraries and kernel drivers for resources
277 allocations and initialization. The following dependencies are not part of
278 DPDK and must be installed separately:
282 User space Verbs framework used by librte_pmd_mlx5. This library provides
283 a generic interface between the kernel and low-level user space drivers
286 It allows slow and privileged operations (context initialization, hardware
287 resources allocations) to be managed by the kernel and fast operations to
288 never leave user space.
292 Low-level user space driver library for Mellanox ConnectX-4/ConnectX-5
293 devices, it is automatically loaded by libibverbs.
295 This library basically implements send/receive calls to the hardware
300 They provide the kernel-side Verbs API and low level device drivers that
301 manage actual hardware initialization and resources sharing with user
304 Unlike most other PMDs, these modules must remain loaded and bound to
307 - mlx5_core: hardware driver managing Mellanox ConnectX-4/ConnectX-5
308 devices and related Ethernet kernel network devices.
309 - mlx5_ib: InifiniBand device driver.
310 - ib_uverbs: user space driver for Verbs (entry point for libibverbs).
312 - **Firmware update**
314 Mellanox OFED releases include firmware updates for ConnectX-4/ConnectX-5
317 Because each release provides new features, these updates must be applied to
318 match the kernel modules and libraries they come with.
322 Both libraries are BSD and GPL licensed. Linux kernel modules are GPL
328 Either RDMA Core library with a recent enough Linux kernel release
329 (recommended) or Mellanox OFED, which provides compatibility with older
332 RMDA Core with Linux Kernel
333 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
335 - Minimal kernel version : 4.13-rc4 (see `Linux installation documentation`_)
336 - Minimal rdma-core version: v15 (see `RDMA Core installation documentation`_)
338 .. _`Linux installation documentation`: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git/plain/Documentation/admin-guide/README.rst
339 .. _`RDMA Core installation documentation`: https://raw.githubusercontent.com/linux-rdma/rdma-core/master/README.md
344 - Mellanox OFED version: **4.2**.
347 - ConnectX-4: **12.20.1010** and above.
348 - ConnectX-4 Lx: **14.20.1010** and above.
349 - ConnectX-5: **16.20.1010** and above.
350 - ConnectX-5 Ex: **16.20.1010** and above.
352 While these libraries and kernel modules are available on OpenFabrics
353 Alliance's `website <https://www.openfabrics.org/>`__ and provided by package
354 managers on most distributions, this PMD requires Ethernet extensions that
355 may not be supported at the moment (this is a work in progress).
358 <http://www.mellanox.com/page/products_dyn?product_family=26&mtag=linux>`__
359 includes the necessary support and should be used in the meantime. For DPDK,
360 only libibverbs, libmlx5, mlnx-ofed-kernel packages and firmware updates are
361 required from that distribution.
365 Several versions of Mellanox OFED are available. Installing the version
366 this DPDK release was developed and tested against is strongly
367 recommended. Please check the `prerequisites`_.
372 * Mellanox(R) ConnectX(R)-4 10G MCX4111A-XCAT (1x10G)
373 * Mellanox(R) ConnectX(R)-4 10G MCX4121A-XCAT (2x10G)
374 * Mellanox(R) ConnectX(R)-4 25G MCX4111A-ACAT (1x25G)
375 * Mellanox(R) ConnectX(R)-4 25G MCX4121A-ACAT (2x25G)
376 * Mellanox(R) ConnectX(R)-4 40G MCX4131A-BCAT (1x40G)
377 * Mellanox(R) ConnectX(R)-4 40G MCX413A-BCAT (1x40G)
378 * Mellanox(R) ConnectX(R)-4 40G MCX415A-BCAT (1x40G)
379 * Mellanox(R) ConnectX(R)-4 50G MCX4131A-GCAT (1x50G)
380 * Mellanox(R) ConnectX(R)-4 50G MCX413A-GCAT (1x50G)
381 * Mellanox(R) ConnectX(R)-4 50G MCX414A-BCAT (2x50G)
382 * Mellanox(R) ConnectX(R)-4 50G MCX415A-GCAT (2x50G)
383 * Mellanox(R) ConnectX(R)-4 50G MCX416A-BCAT (2x50G)
384 * Mellanox(R) ConnectX(R)-4 50G MCX416A-GCAT (2x50G)
385 * Mellanox(R) ConnectX(R)-4 50G MCX415A-CCAT (1x100G)
386 * Mellanox(R) ConnectX(R)-4 100G MCX416A-CCAT (2x100G)
387 * Mellanox(R) ConnectX(R)-4 Lx 10G MCX4121A-XCAT (2x10G)
388 * Mellanox(R) ConnectX(R)-4 Lx 25G MCX4121A-ACAT (2x25G)
389 * Mellanox(R) ConnectX(R)-5 100G MCX556A-ECAT (2x100G)
390 * Mellanox(R) ConnectX(R)-5 Ex EN 100G MCX516A-CDAT (2x100G)
392 Quick Start Guide on OFED
393 -------------------------
395 1. Download latest Mellanox OFED. For more info check the `prerequisites`_.
398 2. Install the required libraries and kernel modules either by installing
399 only the required set, or by installing the entire Mellanox OFED:
401 .. code-block:: console
405 3. Verify the firmware is the correct one:
407 .. code-block:: console
411 4. Verify all ports links are set to Ethernet:
413 .. code-block:: console
415 mlxconfig -d <mst device> query | grep LINK_TYPE
419 Link types may have to be configured to Ethernet:
421 .. code-block:: console
423 mlxconfig -d <mst device> set LINK_TYPE_P1/2=1/2/3
425 * LINK_TYPE_P1=<1|2|3> , 1=Infiniband 2=Ethernet 3=VPI(auto-sense)
427 For hypervisors verify SR-IOV is enabled on the NIC:
429 .. code-block:: console
431 mlxconfig -d <mst device> query | grep SRIOV_EN
434 If needed, set enable the set the relevant fields:
436 .. code-block:: console
438 mlxconfig -d <mst device> set SRIOV_EN=1 NUM_OF_VFS=16
439 mlxfwreset -d <mst device> reset
441 5. Restart the driver:
443 .. code-block:: console
445 /etc/init.d/openibd restart
449 .. code-block:: console
451 service openibd restart
453 If link type was changed, firmware must be reset as well:
455 .. code-block:: console
457 mlxfwreset -d <mst device> reset
459 For hypervisors, after reset write the sysfs number of virtual functions
462 To dynamically instantiate a given number of virtual functions (VFs):
464 .. code-block:: console
466 echo [num_vfs] > /sys/class/infiniband/mlx5_0/device/sriov_numvfs
468 6. Compile DPDK and you are ready to go. See instructions on
469 :ref:`Development Kit Build System <Development_Kit_Build_System>`
474 1. Configure aggressive CQE Zipping for maximum performance:
476 .. code-block:: console
478 mlxconfig -d <mst device> s CQE_COMPRESSION=1
480 To set it back to the default CQE Zipping mode use:
482 .. code-block:: console
484 mlxconfig -d <mst device> s CQE_COMPRESSION=0
486 2. In case of virtualization:
488 - Make sure that hypervisor kernel is 3.16 or newer.
489 - Configure boot with ``iommu=pt``.
491 - Make sure to allocate a VM on huge pages.
492 - Make sure to set CPU pinning.
494 3. Use the CPU near local NUMA node to which the PCIe adapter is connected,
495 for better performance. For VMs, verify that the right CPU
496 and NUMA node are pinned according to the above. Run:
498 .. code-block:: console
502 to identify the NUMA node to which the PCIe adapter is connected.
504 4. If more than one adapter is used, and root complex capabilities allow
505 to put both adapters on the same NUMA node without PCI bandwidth degradation,
506 it is recommended to locate both adapters on the same NUMA node.
507 This in order to forward packets from one to the other without
508 NUMA performance penalty.
510 5. Disable pause frames:
512 .. code-block:: console
514 ethtool -A <netdev> rx off tx off
516 6. Verify IO non-posted prefetch is disabled by default. This can be checked
517 via the BIOS configuration. Please contact you server provider for more
518 information about the settings.
522 On some machines, depends on the machine integrator, it is beneficial
523 to set the PCI max read request parameter to 1K. This can be
524 done in the following way:
526 To query the read request size use:
528 .. code-block:: console
530 setpci -s <NIC PCI address> 68.w
532 If the output is different than 3XXX, set it by:
534 .. code-block:: console
536 setpci -s <NIC PCI address> 68.w=3XXX
538 The XXX can be different on different systems. Make sure to configure
539 according to the setpci output.
544 Compared to librte_pmd_mlx4 that implements a single RSS configuration per
545 port, librte_pmd_mlx5 supports per-protocol RSS configuration.
547 Since ``testpmd`` defaults to IP RSS mode and there is currently no
548 command-line parameter to enable additional protocols (UDP and TCP as well
549 as IP), the following commands must be entered from its CLI to get the same
550 behavior as librte_pmd_mlx4:
552 .. code-block:: console
555 > port config all rss all
561 This section demonstrates how to launch **testpmd** with Mellanox
562 ConnectX-4/ConnectX-5 devices managed by librte_pmd_mlx5.
564 #. Load the kernel modules:
566 .. code-block:: console
568 modprobe -a ib_uverbs mlx5_core mlx5_ib
570 Alternatively if MLNX_OFED is fully installed, the following script can
573 .. code-block:: console
575 /etc/init.d/openibd restart
579 User space I/O kernel modules (uio and igb_uio) are not used and do
580 not have to be loaded.
582 #. Make sure Ethernet interfaces are in working order and linked to kernel
583 verbs. Related sysfs entries should be present:
585 .. code-block:: console
587 ls -d /sys/class/net/*/device/infiniband_verbs/uverbs* | cut -d / -f 5
591 .. code-block:: console
598 #. Optionally, retrieve their PCI bus addresses for whitelisting:
600 .. code-block:: console
603 for intf in eth2 eth3 eth4 eth5;
605 (cd "/sys/class/net/${intf}/device/" && pwd -P);
608 sed -n 's,.*/\(.*\),-w \1,p'
612 .. code-block:: console
619 #. Request huge pages:
621 .. code-block:: console
623 echo 1024 > /sys/kernel/mm/hugepages/hugepages-2048kB/nr_hugepages/nr_hugepages
625 #. Start testpmd with basic parameters:
627 .. code-block:: console
629 testpmd -l 8-15 -n 4 -w 05:00.0 -w 05:00.1 -w 06:00.0 -w 06:00.1 -- --rxq=2 --txq=2 -i
633 .. code-block:: console
636 EAL: PCI device 0000:05:00.0 on NUMA socket 0
637 EAL: probe driver: 15b3:1013 librte_pmd_mlx5
638 PMD: librte_pmd_mlx5: PCI information matches, using device "mlx5_0" (VF: false)
639 PMD: librte_pmd_mlx5: 1 port(s) detected
640 PMD: librte_pmd_mlx5: port 1 MAC address is e4:1d:2d:e7:0c:fe
641 EAL: PCI device 0000:05:00.1 on NUMA socket 0
642 EAL: probe driver: 15b3:1013 librte_pmd_mlx5
643 PMD: librte_pmd_mlx5: PCI information matches, using device "mlx5_1" (VF: false)
644 PMD: librte_pmd_mlx5: 1 port(s) detected
645 PMD: librte_pmd_mlx5: port 1 MAC address is e4:1d:2d:e7:0c:ff
646 EAL: PCI device 0000:06:00.0 on NUMA socket 0
647 EAL: probe driver: 15b3:1013 librte_pmd_mlx5
648 PMD: librte_pmd_mlx5: PCI information matches, using device "mlx5_2" (VF: false)
649 PMD: librte_pmd_mlx5: 1 port(s) detected
650 PMD: librte_pmd_mlx5: port 1 MAC address is e4:1d:2d:e7:0c:fa
651 EAL: PCI device 0000:06:00.1 on NUMA socket 0
652 EAL: probe driver: 15b3:1013 librte_pmd_mlx5
653 PMD: librte_pmd_mlx5: PCI information matches, using device "mlx5_3" (VF: false)
654 PMD: librte_pmd_mlx5: 1 port(s) detected
655 PMD: librte_pmd_mlx5: port 1 MAC address is e4:1d:2d:e7:0c:fb
656 Interactive-mode selected
657 Configuring Port 0 (socket 0)
658 PMD: librte_pmd_mlx5: 0x8cba80: TX queues number update: 0 -> 2
659 PMD: librte_pmd_mlx5: 0x8cba80: RX queues number update: 0 -> 2
660 Port 0: E4:1D:2D:E7:0C:FE
661 Configuring Port 1 (socket 0)
662 PMD: librte_pmd_mlx5: 0x8ccac8: TX queues number update: 0 -> 2
663 PMD: librte_pmd_mlx5: 0x8ccac8: RX queues number update: 0 -> 2
664 Port 1: E4:1D:2D:E7:0C:FF
665 Configuring Port 2 (socket 0)
666 PMD: librte_pmd_mlx5: 0x8cdb10: TX queues number update: 0 -> 2
667 PMD: librte_pmd_mlx5: 0x8cdb10: RX queues number update: 0 -> 2
668 Port 2: E4:1D:2D:E7:0C:FA
669 Configuring Port 3 (socket 0)
670 PMD: librte_pmd_mlx5: 0x8ceb58: TX queues number update: 0 -> 2
671 PMD: librte_pmd_mlx5: 0x8ceb58: RX queues number update: 0 -> 2
672 Port 3: E4:1D:2D:E7:0C:FB
673 Checking link statuses...
674 Port 0 Link Up - speed 40000 Mbps - full-duplex
675 Port 1 Link Up - speed 40000 Mbps - full-duplex
676 Port 2 Link Up - speed 10000 Mbps - full-duplex
677 Port 3 Link Up - speed 10000 Mbps - full-duplex