drivers/bus/dpaa/base/qbman/qman.c

   1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
   2  *
   3  * Copyright 2008-2016 Freescale Semiconductor Inc.
   4  * Copyright 2017 NXP
   5  *
   6  */
   7
   8 #include "qman.h"
   9 #include <rte_branch_prediction.h>
  10 #include <rte_dpaa_bus.h>
  11 #include <rte_eventdev.h>
  12 #include <rte_byteorder.h>
  13
  14 /* Compilation constants */
  15 #define DQRR_MAXFILL    15
  16 #define EQCR_ITHRESH    4       /* if EQCR congests, interrupt threshold */
  17 #define IRQNAME         "QMan portal %d"
  18 #define MAX_IRQNAME     16      /* big enough for "QMan portal %d" */
  19 /* maximum number of DQRR entries to process in qman_poll() */
  20 #define FSL_QMAN_POLL_LIMIT 8
  21
  22 /* Lock/unlock frame queues, subject to the "LOCKED" flag. This is about
  23  * inter-processor locking only. Note, FQLOCK() is always called either under a
  24  * local_irq_save() or from interrupt context - hence there's no need for irq
  25  * protection (and indeed, attempting to nest irq-protection doesn't work, as
  26  * the "irq en/disable" machinery isn't recursive...).
  27  */
  28 #define FQLOCK(fq) \
  29         do { \
  30                 struct qman_fq *__fq478 = (fq); \
  31                 if (fq_isset(__fq478, QMAN_FQ_FLAG_LOCKED)) \
  32                         spin_lock(&__fq478->fqlock); \
  33         } while (0)
  34 #define FQUNLOCK(fq) \
  35         do { \
  36                 struct qman_fq *__fq478 = (fq); \
  37                 if (fq_isset(__fq478, QMAN_FQ_FLAG_LOCKED)) \
  38                         spin_unlock(&__fq478->fqlock); \
  39         } while (0)
  40
  41 static inline void fq_set(struct qman_fq *fq, u32 mask)
  42 {
  43         dpaa_set_bits(mask, &fq->flags);
  44 }
  45
  46 static inline void fq_clear(struct qman_fq *fq, u32 mask)
  47 {
  48         dpaa_clear_bits(mask, &fq->flags);
  49 }
  50
  51 static inline int fq_isset(struct qman_fq *fq, u32 mask)
  52 {
  53         return fq->flags & mask;
  54 }
  55
  56 static inline int fq_isclear(struct qman_fq *fq, u32 mask)
  57 {
  58         return !(fq->flags & mask);
  59 }
  60
  61 struct qman_portal {
  62         struct qm_portal p;
  63         /* PORTAL_BITS_*** - dynamic, strictly internal */
  64         unsigned long bits;
  65         /* interrupt sources processed by portal_isr(), configurable */
  66         unsigned long irq_sources;
  67         u32 use_eqcr_ci_stashing;
  68         u32 slowpoll;   /* only used when interrupts are off */
  69         /* only 1 volatile dequeue at a time */
  70         struct qman_fq *vdqcr_owned;
  71         u32 sdqcr;
  72         int dqrr_disable_ref;
  73         /* A portal-specific handler for DCP ERNs. If this is NULL, the global
  74          * handler is called instead.
  75          */
  76         qman_cb_dc_ern cb_dc_ern;
  77         /* When the cpu-affine portal is activated, this is non-NULL */
  78         const struct qm_portal_config *config;
  79         struct dpa_rbtree retire_table;
  80         char irqname[MAX_IRQNAME];
  81         /* 2-element array. cgrs[0] is mask, cgrs[1] is snapshot. */
  82         struct qman_cgrs *cgrs;
  83         /* linked-list of CSCN handlers. */
  84         struct list_head cgr_cbs;
  85         /* list lock */
  86         spinlock_t cgr_lock;
  87         /* track if memory was allocated by the driver */
  88 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
  89         /* Keep a shadow copy of the DQRR on LE systems as the SW needs to
  90          * do byte swaps of DQRR read only memory.  First entry must be aligned
  91          * to 2 ** 10 to ensure DQRR index calculations based shadow copy
  92          * address (6 bits for address shift + 4 bits for the DQRR size).
  93          */
  94         struct qm_dqrr_entry shadow_dqrr[QM_DQRR_SIZE]
  95                     __attribute__((aligned(1024)));
  96 #endif
  97 };
  98
  99 /* Global handler for DCP ERNs. Used when the portal receiving the message does
 100  * not have a portal-specific handler.
 101  */
 102 static qman_cb_dc_ern cb_dc_ern;
 103
 104 static cpumask_t affine_mask;
 105 static DEFINE_SPINLOCK(affine_mask_lock);
 106 static u16 affine_channels[NR_CPUS];
 107 static RTE_DEFINE_PER_LCORE(struct qman_portal, qman_affine_portal);
 108
 109 static inline struct qman_portal *get_affine_portal(void)
 110 {
 111         return &RTE_PER_LCORE(qman_affine_portal);
 112 }
 113
 114 /* This gives a FQID->FQ lookup to cover the fact that we can't directly demux
 115  * retirement notifications (the fact they are sometimes h/w-consumed means that
 116  * contextB isn't always a s/w demux - and as we can't know which case it is
 117  * when looking at the notification, we have to use the slow lookup for all of
 118  * them). NB, it's possible to have multiple FQ objects refer to the same FQID
 119  * (though at most one of them should be the consumer), so this table isn't for
 120  * all FQs - FQs are added when retirement commands are issued, and removed when
 121  * they complete, which also massively reduces the size of this table.
 122  */
 123 IMPLEMENT_DPAA_RBTREE(fqtree, struct qman_fq, node, fqid);
 124 /*
 125  * This is what everything can wait on, even if it migrates to a different cpu
 126  * to the one whose affine portal it is waiting on.
 127  */
 128 static DECLARE_WAIT_QUEUE_HEAD(affine_queue);
 129
 130 static inline int table_push_fq(struct qman_portal *p, struct qman_fq *fq)
 131 {
 132         int ret = fqtree_push(&p->retire_table, fq);
 133
 134         if (ret)
 135                 pr_err("ERROR: double FQ-retirement %d\n", fq->fqid);
 136         return ret;
 137 }
 138
 139 static inline void table_del_fq(struct qman_portal *p, struct qman_fq *fq)
 140 {
 141         fqtree_del(&p->retire_table, fq);
 142 }
 143
 144 static inline struct qman_fq *table_find_fq(struct qman_portal *p, u32 fqid)
 145 {
 146         return fqtree_find(&p->retire_table, fqid);
 147 }
 148
 149 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
 150 static void **qman_fq_lookup_table;
 151 static size_t qman_fq_lookup_table_size;
 152
 153 int qman_setup_fq_lookup_table(size_t num_entries)
 154 {
 155         num_entries++;
 156         /* Allocate 1 more entry since the first entry is not used */
 157         qman_fq_lookup_table = vmalloc((num_entries * sizeof(void *)));
 158         if (!qman_fq_lookup_table) {
 159                 pr_err("QMan: Could not allocate fq lookup table\n");
 160                 return -ENOMEM;
 161         }
 162         memset(qman_fq_lookup_table, 0, num_entries * sizeof(void *));
 163         qman_fq_lookup_table_size = num_entries;
 164         pr_debug("QMan: Allocated lookup table at %p, entry count %lu\n",
 165                 qman_fq_lookup_table,
 166                         (unsigned long)qman_fq_lookup_table_size);
 167         return 0;
 168 }
 169
 170 /* global structure that maintains fq object mapping */
 171 static DEFINE_SPINLOCK(fq_hash_table_lock);
 172
 173 static int find_empty_fq_table_entry(u32 *entry, struct qman_fq *fq)
 174 {
 175         u32 i;
 176
 177         spin_lock(&fq_hash_table_lock);
 178         /* Can't use index zero because this has special meaning
 179          * in context_b field.
 180          */
 181         for (i = 1; i < qman_fq_lookup_table_size; i++) {
 182                 if (qman_fq_lookup_table[i] == NULL) {
 183                         *entry = i;
 184                         qman_fq_lookup_table[i] = fq;
 185                         spin_unlock(&fq_hash_table_lock);
 186                         return 0;
 187                 }
 188         }
 189         spin_unlock(&fq_hash_table_lock);
 190         return -ENOMEM;
 191 }
 192
 193 static void clear_fq_table_entry(u32 entry)
 194 {
 195         spin_lock(&fq_hash_table_lock);
 196         DPAA_BUG_ON(entry >= qman_fq_lookup_table_size);
 197         qman_fq_lookup_table[entry] = NULL;
 198         spin_unlock(&fq_hash_table_lock);
 199 }
 200
 201 static inline struct qman_fq *get_fq_table_entry(u32 entry)
 202 {
 203         DPAA_BUG_ON(entry >= qman_fq_lookup_table_size);
 204         return qman_fq_lookup_table[entry];
 205 }
 206 #endif
 207
 208 static inline void cpu_to_hw_fqd(struct qm_fqd *fqd)
 209 {
 210         /* Byteswap the FQD to HW format */
 211         fqd->fq_ctrl = cpu_to_be16(fqd->fq_ctrl);
 212         fqd->dest_wq = cpu_to_be16(fqd->dest_wq);
 213         fqd->ics_cred = cpu_to_be16(fqd->ics_cred);
 214         fqd->context_b = cpu_to_be32(fqd->context_b);
 215         fqd->context_a.opaque = cpu_to_be64(fqd->context_a.opaque);
 216         fqd->opaque_td = cpu_to_be16(fqd->opaque_td);
 217 }
 218
 219 static inline void hw_fqd_to_cpu(struct qm_fqd *fqd)
 220 {
 221         /* Byteswap the FQD to CPU format */
 222         fqd->fq_ctrl = be16_to_cpu(fqd->fq_ctrl);
 223         fqd->dest_wq = be16_to_cpu(fqd->dest_wq);
 224         fqd->ics_cred = be16_to_cpu(fqd->ics_cred);
 225         fqd->context_b = be32_to_cpu(fqd->context_b);
 226         fqd->context_a.opaque = be64_to_cpu(fqd->context_a.opaque);
 227 }
 228
 229 static inline void cpu_to_hw_fd(struct qm_fd *fd)
 230 {
 231         fd->addr = cpu_to_be40(fd->addr);
 232         fd->status = cpu_to_be32(fd->status);
 233         fd->opaque = cpu_to_be32(fd->opaque);
 234 }
 235
 236 static inline void hw_fd_to_cpu(struct qm_fd *fd)
 237 {
 238         fd->addr = be40_to_cpu(fd->addr);
 239         fd->status = be32_to_cpu(fd->status);
 240         fd->opaque = be32_to_cpu(fd->opaque);
 241 }
 242
 243 /* In the case that slow- and fast-path handling are both done by qman_poll()
 244  * (ie. because there is no interrupt handling), we ought to balance how often
 245  * we do the fast-path poll versus the slow-path poll. We'll use two decrementer
 246  * sources, so we call the fast poll 'n' times before calling the slow poll
 247  * once. The idle decrementer constant is used when the last slow-poll detected
 248  * no work to do, and the busy decrementer constant when the last slow-poll had
 249  * work to do.
 250  */
 251 #define SLOW_POLL_IDLE   1000
 252 #define SLOW_POLL_BUSY   10
 253 static u32 __poll_portal_slow(struct qman_portal *p, u32 is);
 254 static inline unsigned int __poll_portal_fast(struct qman_portal *p,
 255                                               unsigned int poll_limit);
 256
 257 /* Portal interrupt handler */
 258 static irqreturn_t portal_isr(__always_unused int irq, void *ptr)
 259 {
 260         struct qman_portal *p = ptr;
 261         /*
 262          * The CSCI/CCSCI source is cleared inside __poll_portal_slow(), because
 263          * it could race against a Query Congestion State command also given
 264          * as part of the handling of this interrupt source. We mustn't
 265          * clear it a second time in this top-level function.
 266          */
 267         u32 clear = QM_DQAVAIL_MASK | (p->irq_sources &
 268                 ~(QM_PIRQ_CSCI | QM_PIRQ_CCSCI));
 269         u32 is = qm_isr_status_read(&p->p) & p->irq_sources;
 270         /* DQRR-handling if it's interrupt-driven */
 271         if (is & QM_PIRQ_DQRI)
 272                 __poll_portal_fast(p, FSL_QMAN_POLL_LIMIT);
 273         /* Handling of anything else that's interrupt-driven */
 274         clear |= __poll_portal_slow(p, is);
 275         qm_isr_status_clear(&p->p, clear);
 276         return IRQ_HANDLED;
 277 }
 278
 279 /* This inner version is used privately by qman_create_affine_portal(), as well
 280  * as by the exported qman_stop_dequeues().
 281  */
 282 static inline void qman_stop_dequeues_ex(struct qman_portal *p)
 283 {
 284         if (!(p->dqrr_disable_ref++))
 285                 qm_dqrr_set_maxfill(&p->p, 0);
 286 }
 287
 288 static int drain_mr_fqrni(struct qm_portal *p)
 289 {
 290         const struct qm_mr_entry *msg;
 291 loop:
 292         msg = qm_mr_current(p);
 293         if (!msg) {
 294                 /*
 295                  * if MR was full and h/w had other FQRNI entries to produce, we
 296                  * need to allow it time to produce those entries once the
 297                  * existing entries are consumed. A worst-case situation
 298                  * (fully-loaded system) means h/w sequencers may have to do 3-4
 299                  * other things before servicing the portal's MR pump, each of
 300                  * which (if slow) may take ~50 qman cycles (which is ~200
 301                  * processor cycles). So rounding up and then multiplying this
 302                  * worst-case estimate by a factor of 10, just to be
 303                  * ultra-paranoid, goes as high as 10,000 cycles. NB, we consume
 304                  * one entry at a time, so h/w has an opportunity to produce new
 305                  * entries well before the ring has been fully consumed, so
 306                  * we're being *really* paranoid here.
 307                  */
 308                 u64 now, then = mfatb();
 309
 310                 do {
 311                         now = mfatb();
 312                 } while ((then + 10000) > now);
 313                 msg = qm_mr_current(p);
 314                 if (!msg)
 315                         return 0;
 316         }
 317         if ((msg->verb & QM_MR_VERB_TYPE_MASK) != QM_MR_VERB_FQRNI) {
 318                 /* We aren't draining anything but FQRNIs */
 319                 pr_err("Found verb 0x%x in MR\n", msg->verb);
 320                 return -1;
 321         }
 322         qm_mr_next(p);
 323         qm_mr_cci_consume(p, 1);
 324         goto loop;
 325 }
 326
 327 static inline int qm_eqcr_init(struct qm_portal *portal,
 328                                enum qm_eqcr_pmode pmode,
 329                                unsigned int eq_stash_thresh,
 330                                int eq_stash_prio)
 331 {
 332         /* This use of 'register', as well as all other occurrences, is because
 333          * it has been observed to generate much faster code with gcc than is
 334          * otherwise the case.
 335          */
 336         register struct qm_eqcr *eqcr = &portal->eqcr;
 337         u32 cfg;
 338         u8 pi;
 339
 340         eqcr->ring = portal->addr.ce + QM_CL_EQCR;
 341         eqcr->ci = qm_in(EQCR_CI_CINH) & (QM_EQCR_SIZE - 1);
 342         qm_cl_invalidate(EQCR_CI);
 343         pi = qm_in(EQCR_PI_CINH) & (QM_EQCR_SIZE - 1);
 344         eqcr->cursor = eqcr->ring + pi;
 345         eqcr->vbit = (qm_in(EQCR_PI_CINH) & QM_EQCR_SIZE) ?
 346                         QM_EQCR_VERB_VBIT : 0;
 347         eqcr->available = QM_EQCR_SIZE - 1 -
 348                         qm_cyc_diff(QM_EQCR_SIZE, eqcr->ci, pi);
 349         eqcr->ithresh = qm_in(EQCR_ITR);
 350 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
 351         eqcr->busy = 0;
 352         eqcr->pmode = pmode;
 353 #endif
 354         cfg = (qm_in(CFG) & 0x00ffffff) |
 355                 (eq_stash_thresh << 28) | /* QCSP_CFG: EST */
 356                 (eq_stash_prio << 26)   | /* QCSP_CFG: EP */
 357                 ((pmode & 0x3) << 24);  /* QCSP_CFG::EPM */
 358         qm_out(CFG, cfg);
 359         return 0;
 360 }
 361
 362 static inline void qm_eqcr_finish(struct qm_portal *portal)
 363 {
 364         register struct qm_eqcr *eqcr = &portal->eqcr;
 365         u8 pi, ci;
 366         u32 cfg;
 367
 368         /*
 369          * Disable EQCI stashing because the QMan only
 370          * presents the value it previously stashed to
 371          * maintain coherency.  Setting the stash threshold
 372          * to 1 then 0 ensures that QMan has resyncronized
 373          * its internal copy so that the portal is clean
 374          * when it is reinitialized in the future
 375          */
 376         cfg = (qm_in(CFG) & 0x0fffffff) |
 377                 (1 << 28); /* QCSP_CFG: EST */
 378         qm_out(CFG, cfg);
 379         cfg &= 0x0fffffff; /* stash threshold = 0 */
 380         qm_out(CFG, cfg);
 381
 382         pi = qm_in(EQCR_PI_CINH) & (QM_EQCR_SIZE - 1);
 383         ci = qm_in(EQCR_CI_CINH) & (QM_EQCR_SIZE - 1);
 384
 385         /* Refresh EQCR CI cache value */
 386         qm_cl_invalidate(EQCR_CI);
 387         eqcr->ci = qm_cl_in(EQCR_CI) & (QM_EQCR_SIZE - 1);
 388
 389 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
 390         DPAA_ASSERT(!eqcr->busy);
 391 #endif
 392         if (pi != EQCR_PTR2IDX(eqcr->cursor))
 393                 pr_crit("losing uncommitted EQCR entries\n");
 394         if (ci != eqcr->ci)
 395                 pr_crit("missing existing EQCR completions\n");
 396         if (eqcr->ci != EQCR_PTR2IDX(eqcr->cursor))
 397                 pr_crit("EQCR destroyed unquiesced\n");
 398 }
 399
 400 static inline int qm_dqrr_init(struct qm_portal *portal,
 401                         __maybe_unused const struct qm_portal_config *config,
 402                         enum qm_dqrr_dmode dmode,
 403                         __maybe_unused enum qm_dqrr_pmode pmode,
 404                         enum qm_dqrr_cmode cmode, u8 max_fill)
 405 {
 406         register struct qm_dqrr *dqrr = &portal->dqrr;
 407         u32 cfg;
 408
 409         /* Make sure the DQRR will be idle when we enable */
 410         qm_out(DQRR_SDQCR, 0);
 411         qm_out(DQRR_VDQCR, 0);
 412         qm_out(DQRR_PDQCR, 0);
 413         dqrr->ring = portal->addr.ce + QM_CL_DQRR;
 414         dqrr->pi = qm_in(DQRR_PI_CINH) & (QM_DQRR_SIZE - 1);
 415         dqrr->ci = qm_in(DQRR_CI_CINH) & (QM_DQRR_SIZE - 1);
 416         dqrr->cursor = dqrr->ring + dqrr->ci;
 417         dqrr->fill = qm_cyc_diff(QM_DQRR_SIZE, dqrr->ci, dqrr->pi);
 418         dqrr->vbit = (qm_in(DQRR_PI_CINH) & QM_DQRR_SIZE) ?
 419                         QM_DQRR_VERB_VBIT : 0;
 420         dqrr->ithresh = qm_in(DQRR_ITR);
 421 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
 422         dqrr->dmode = dmode;
 423         dqrr->pmode = pmode;
 424         dqrr->cmode = cmode;
 425 #endif
 426         /* Invalidate every ring entry before beginning */
 427         for (cfg = 0; cfg < QM_DQRR_SIZE; cfg++)
 428                 dccivac(qm_cl(dqrr->ring, cfg));
 429         cfg = (qm_in(CFG) & 0xff000f00) |
 430                 ((max_fill & (QM_DQRR_SIZE - 1)) << 20) | /* DQRR_MF */
 431                 ((dmode & 1) << 18) |                   /* DP */
 432                 ((cmode & 3) << 16) |                   /* DCM */
 433                 0xa0 |                                  /* RE+SE */
 434                 (0 ? 0x40 : 0) |                        /* Ignore RP */
 435                 (0 ? 0x10 : 0);                         /* Ignore SP */
 436         qm_out(CFG, cfg);
 437         qm_dqrr_set_maxfill(portal, max_fill);
 438         return 0;
 439 }
 440
 441 static inline void qm_dqrr_finish(struct qm_portal *portal)
 442 {
 443         __maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
 444 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
 445         if ((dqrr->cmode != qm_dqrr_cdc) &&
 446             (dqrr->ci != DQRR_PTR2IDX(dqrr->cursor)))
 447                 pr_crit("Ignoring completed DQRR entries\n");
 448 #endif
 449 }
 450
 451 static inline int qm_mr_init(struct qm_portal *portal,
 452                              __maybe_unused enum qm_mr_pmode pmode,
 453                              enum qm_mr_cmode cmode)
 454 {
 455         register struct qm_mr *mr = &portal->mr;
 456         u32 cfg;
 457
 458         mr->ring = portal->addr.ce + QM_CL_MR;
 459         mr->pi = qm_in(MR_PI_CINH) & (QM_MR_SIZE - 1);
 460         mr->ci = qm_in(MR_CI_CINH) & (QM_MR_SIZE - 1);
 461         mr->cursor = mr->ring + mr->ci;
 462         mr->fill = qm_cyc_diff(QM_MR_SIZE, mr->ci, mr->pi);
 463         mr->vbit = (qm_in(MR_PI_CINH) & QM_MR_SIZE) ? QM_MR_VERB_VBIT : 0;
 464         mr->ithresh = qm_in(MR_ITR);
 465 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
 466         mr->pmode = pmode;
 467         mr->cmode = cmode;
 468 #endif
 469         cfg = (qm_in(CFG) & 0xfffff0ff) |
 470                 ((cmode & 1) << 8);             /* QCSP_CFG:MM */
 471         qm_out(CFG, cfg);
 472         return 0;
 473 }
 474
 475 static inline void qm_mr_pvb_update(struct qm_portal *portal)
 476 {
 477         register struct qm_mr *mr = &portal->mr;
 478         const struct qm_mr_entry *res = qm_cl(mr->ring, mr->pi);
 479
 480 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
 481         DPAA_ASSERT(mr->pmode == qm_mr_pvb);
 482 #endif
 483         /* when accessing 'verb', use __raw_readb() to ensure that compiler
 484          * inlining doesn't try to optimise out "excess reads".
 485          */
 486         if ((__raw_readb(&res->verb) & QM_MR_VERB_VBIT) == mr->vbit) {
 487                 mr->pi = (mr->pi + 1) & (QM_MR_SIZE - 1);
 488                 if (!mr->pi)
 489                         mr->vbit ^= QM_MR_VERB_VBIT;
 490                 mr->fill++;
 491                 res = MR_INC(res);
 492         }
 493         dcbit_ro(res);
 494 }
 495
 496 static inline
 497 struct qman_portal *qman_create_portal(
 498                         struct qman_portal *portal,
 499                               const struct qm_portal_config *c,
 500                               const struct qman_cgrs *cgrs)
 501 {
 502         struct qm_portal *p;
 503         char buf[16];
 504         int ret;
 505         u32 isdr;
 506
 507         p = &portal->p;
 508
 509         if (dpaa_svr_family == SVR_LS1043A_FAMILY)
 510                 portal->use_eqcr_ci_stashing = 3;
 511         else
 512                 portal->use_eqcr_ci_stashing =
 513                                         ((qman_ip_rev >= QMAN_REV30) ? 1 : 0);
 514
 515         /*
 516          * prep the low-level portal struct with the mapped addresses from the
 517          * config, everything that follows depends on it and "config" is more
 518          * for (de)reference
 519          */
 520         p->addr.ce = c->addr_virt[DPAA_PORTAL_CE];
 521         p->addr.ci = c->addr_virt[DPAA_PORTAL_CI];
 522         /*
 523          * If CI-stashing is used, the current defaults use a threshold of 3,
 524          * and stash with high-than-DQRR priority.
 525          */
 526         if (qm_eqcr_init(p, qm_eqcr_pvb,
 527                          portal->use_eqcr_ci_stashing, 1)) {
 528                 pr_err("Qman EQCR initialisation failed\n");
 529                 goto fail_eqcr;
 530         }
 531         if (qm_dqrr_init(p, c, qm_dqrr_dpush, qm_dqrr_pvb,
 532                          qm_dqrr_cdc, DQRR_MAXFILL)) {
 533                 pr_err("Qman DQRR initialisation failed\n");
 534                 goto fail_dqrr;
 535         }
 536         if (qm_mr_init(p, qm_mr_pvb, qm_mr_cci)) {
 537                 pr_err("Qman MR initialisation failed\n");
 538                 goto fail_mr;
 539         }
 540         if (qm_mc_init(p)) {
 541                 pr_err("Qman MC initialisation failed\n");
 542                 goto fail_mc;
 543         }
 544
 545         /* static interrupt-gating controls */
 546         qm_dqrr_set_ithresh(p, 0);
 547         qm_mr_set_ithresh(p, 0);
 548         qm_isr_set_iperiod(p, 0);
 549         portal->cgrs = kmalloc(2 * sizeof(*cgrs), GFP_KERNEL);
 550         if (!portal->cgrs)
 551                 goto fail_cgrs;
 552         /* initial snapshot is no-depletion */
 553         qman_cgrs_init(&portal->cgrs[1]);
 554         if (cgrs)
 555                 portal->cgrs[0] = *cgrs;
 556         else
 557                 /* if the given mask is NULL, assume all CGRs can be seen */
 558                 qman_cgrs_fill(&portal->cgrs[0]);
 559         INIT_LIST_HEAD(&portal->cgr_cbs);
 560         spin_lock_init(&portal->cgr_lock);
 561         portal->bits = 0;
 562         portal->slowpoll = 0;
 563         portal->sdqcr = QM_SDQCR_SOURCE_CHANNELS | QM_SDQCR_COUNT_UPTO3 |
 564                         QM_SDQCR_DEDICATED_PRECEDENCE | QM_SDQCR_TYPE_PRIO_QOS |
 565                         QM_SDQCR_TOKEN_SET(0xab) | QM_SDQCR_CHANNELS_DEDICATED;
 566         portal->dqrr_disable_ref = 0;
 567         portal->cb_dc_ern = NULL;
 568         sprintf(buf, "qportal-%d", c->channel);
 569         dpa_rbtree_init(&portal->retire_table);
 570         isdr = 0xffffffff;
 571         qm_isr_disable_write(p, isdr);
 572         portal->irq_sources = 0;
 573         qm_isr_enable_write(p, portal->irq_sources);
 574         qm_isr_status_clear(p, 0xffffffff);
 575         snprintf(portal->irqname, MAX_IRQNAME, IRQNAME, c->cpu);
 576         if (request_irq(c->irq, portal_isr, 0, portal->irqname,
 577                         portal)) {
 578                 pr_err("request_irq() failed\n");
 579                 goto fail_irq;
 580         }
 581
 582         /* Need EQCR to be empty before continuing */
 583         isdr &= ~QM_PIRQ_EQCI;
 584         qm_isr_disable_write(p, isdr);
 585         ret = qm_eqcr_get_fill(p);
 586         if (ret) {
 587                 pr_err("Qman EQCR unclean\n");
 588                 goto fail_eqcr_empty;
 589         }
 590         isdr &= ~(QM_PIRQ_DQRI | QM_PIRQ_MRI);
 591         qm_isr_disable_write(p, isdr);
 592         if (qm_dqrr_current(p)) {
 593                 pr_err("Qman DQRR unclean\n");
 594                 qm_dqrr_cdc_consume_n(p, 0xffff);
 595         }
 596         if (qm_mr_current(p) && drain_mr_fqrni(p)) {
 597                 /* special handling, drain just in case it's a few FQRNIs */
 598                 if (drain_mr_fqrni(p))
 599                         goto fail_dqrr_mr_empty;
 600         }
 601         /* Success */
 602         portal->config = c;
 603         qm_isr_disable_write(p, 0);
 604         qm_isr_uninhibit(p);
 605         /* Write a sane SDQCR */
 606         qm_dqrr_sdqcr_set(p, portal->sdqcr);
 607         return portal;
 608 fail_dqrr_mr_empty:
 609 fail_eqcr_empty:
 610         free_irq(c->irq, portal);
 611 fail_irq:
 612         kfree(portal->cgrs);
 613         spin_lock_destroy(&portal->cgr_lock);
 614 fail_cgrs:
 615         qm_mc_finish(p);
 616 fail_mc:
 617         qm_mr_finish(p);
 618 fail_mr:
 619         qm_dqrr_finish(p);
 620 fail_dqrr:
 621         qm_eqcr_finish(p);
 622 fail_eqcr:
 623         return NULL;
 624 }
 625
 626 #define MAX_GLOBAL_PORTALS 8
 627 static struct qman_portal global_portals[MAX_GLOBAL_PORTALS];
 628 rte_atomic16_t global_portals_used[MAX_GLOBAL_PORTALS];
 629
 630 static struct qman_portal *
 631 qman_alloc_global_portal(void)
 632 {
 633         unsigned int i;
 634
 635         for (i = 0; i < MAX_GLOBAL_PORTALS; i++) {
 636                 if (rte_atomic16_test_and_set(&global_portals_used[i]))
 637                         return &global_portals[i];
 638         }
 639         pr_err("No portal available (%x)\n", MAX_GLOBAL_PORTALS);
 640
 641         return NULL;
 642 }
 643
 644 static int
 645 qman_free_global_portal(struct qman_portal *portal)
 646 {
 647         unsigned int i;
 648
 649         for (i = 0; i < MAX_GLOBAL_PORTALS; i++) {
 650                 if (&global_portals[i] == portal) {
 651                         rte_atomic16_clear(&global_portals_used[i]);
 652                         return 0;
 653                 }
 654         }
 655         return -1;
 656 }
 657
 658 struct qman_portal *qman_create_affine_portal(const struct qm_portal_config *c,
 659                                               const struct qman_cgrs *cgrs,
 660                                               int alloc)
 661 {
 662         struct qman_portal *res;
 663         struct qman_portal *portal;
 664
 665         if (alloc)
 666                 portal = qman_alloc_global_portal();
 667         else
 668                 portal = get_affine_portal();
 669
 670         /* A criteria for calling this function (from qman_driver.c) is that
 671          * we're already affine to the cpu and won't schedule onto another cpu.
 672          */
 673
 674         res = qman_create_portal(portal, c, cgrs);
 675         if (res) {
 676                 spin_lock(&affine_mask_lock);
 677                 CPU_SET(c->cpu, &affine_mask);
 678                 affine_channels[c->cpu] =
 679                         c->channel;
 680                 spin_unlock(&affine_mask_lock);
 681         }
 682         return res;
 683 }
 684
 685 static inline
 686 void qman_destroy_portal(struct qman_portal *qm)
 687 {
 688         const struct qm_portal_config *pcfg;
 689
 690         /* Stop dequeues on the portal */
 691         qm_dqrr_sdqcr_set(&qm->p, 0);
 692
 693         /*
 694          * NB we do this to "quiesce" EQCR. If we add enqueue-completions or
 695          * something related to QM_PIRQ_EQCI, this may need fixing.
 696          * Also, due to the prefetching model used for CI updates in the enqueue
 697          * path, this update will only invalidate the CI cacheline *after*
 698          * working on it, so we need to call this twice to ensure a full update
 699          * irrespective of where the enqueue processing was at when the teardown
 700          * began.
 701          */
 702         qm_eqcr_cce_update(&qm->p);
 703         qm_eqcr_cce_update(&qm->p);
 704         pcfg = qm->config;
 705
 706         free_irq(pcfg->irq, qm);
 707
 708         kfree(qm->cgrs);
 709         qm_mc_finish(&qm->p);
 710         qm_mr_finish(&qm->p);
 711         qm_dqrr_finish(&qm->p);
 712         qm_eqcr_finish(&qm->p);
 713
 714         qm->config = NULL;
 715
 716         spin_lock_destroy(&qm->cgr_lock);
 717 }
 718
 719 const struct qm_portal_config *
 720 qman_destroy_affine_portal(struct qman_portal *qp)
 721 {
 722         /* We don't want to redirect if we're a slave, use "raw" */
 723         struct qman_portal *qm;
 724         const struct qm_portal_config *pcfg;
 725         int cpu;
 726
 727         if (qp == NULL)
 728                 qm = get_affine_portal();
 729         else
 730                 qm = qp;
 731         pcfg = qm->config;
 732         cpu = pcfg->cpu;
 733
 734         qman_destroy_portal(qm);
 735
 736         spin_lock(&affine_mask_lock);
 737         CPU_CLR(cpu, &affine_mask);
 738         spin_unlock(&affine_mask_lock);
 739
 740         qman_free_global_portal(qm);
 741
 742         return pcfg;
 743 }
 744
 745 int qman_get_portal_index(void)
 746 {
 747         struct qman_portal *p = get_affine_portal();
 748         return p->config->index;
 749 }
 750
 751 /* Inline helper to reduce nesting in __poll_portal_slow() */
 752 static inline void fq_state_change(struct qman_portal *p, struct qman_fq *fq,
 753                                    const struct qm_mr_entry *msg, u8 verb)
 754 {
 755         FQLOCK(fq);
 756         switch (verb) {
 757         case QM_MR_VERB_FQRL:
 758                 DPAA_ASSERT(fq_isset(fq, QMAN_FQ_STATE_ORL));
 759                 fq_clear(fq, QMAN_FQ_STATE_ORL);
 760                 table_del_fq(p, fq);
 761                 break;
 762         case QM_MR_VERB_FQRN:
 763                 DPAA_ASSERT((fq->state == qman_fq_state_parked) ||
 764                             (fq->state == qman_fq_state_sched));
 765                 DPAA_ASSERT(fq_isset(fq, QMAN_FQ_STATE_CHANGING));
 766                 fq_clear(fq, QMAN_FQ_STATE_CHANGING);
 767                 if (msg->fq.fqs & QM_MR_FQS_NOTEMPTY)
 768                         fq_set(fq, QMAN_FQ_STATE_NE);
 769                 if (msg->fq.fqs & QM_MR_FQS_ORLPRESENT)
 770                         fq_set(fq, QMAN_FQ_STATE_ORL);
 771                 else
 772                         table_del_fq(p, fq);
 773                 fq->state = qman_fq_state_retired;
 774                 break;
 775         case QM_MR_VERB_FQPN:
 776                 DPAA_ASSERT(fq->state == qman_fq_state_sched);
 777                 DPAA_ASSERT(fq_isclear(fq, QMAN_FQ_STATE_CHANGING));
 778                 fq->state = qman_fq_state_parked;
 779         }
 780         FQUNLOCK(fq);
 781 }
 782
 783 static u32 __poll_portal_slow(struct qman_portal *p, u32 is)
 784 {
 785         const struct qm_mr_entry *msg;
 786         struct qm_mr_entry swapped_msg;
 787
 788         if (is & QM_PIRQ_CSCI) {
 789                 struct qman_cgrs rr, c;
 790                 struct qm_mc_result *mcr;
 791                 struct qman_cgr *cgr;
 792
 793                 spin_lock(&p->cgr_lock);
 794                 /*
 795                  * The CSCI bit must be cleared _before_ issuing the
 796                  * Query Congestion State command, to ensure that a long
 797                  * CGR State Change callback cannot miss an intervening
 798                  * state change.
 799                  */
 800                 qm_isr_status_clear(&p->p, QM_PIRQ_CSCI);
 801                 qm_mc_start(&p->p);
 802                 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCONGESTION);
 803                 while (!(mcr = qm_mc_result(&p->p)))
 804                         cpu_relax();
 805                 /* mask out the ones I'm not interested in */
 806                 qman_cgrs_and(&rr, (const struct qman_cgrs *)
 807                         &mcr->querycongestion.state, &p->cgrs[0]);
 808                 /* check previous snapshot for delta, enter/exit congestion */
 809                 qman_cgrs_xor(&c, &rr, &p->cgrs[1]);
 810                 /* update snapshot */
 811                 qman_cgrs_cp(&p->cgrs[1], &rr);
 812                 /* Invoke callback */
 813                 list_for_each_entry(cgr, &p->cgr_cbs, node)
 814                         if (cgr->cb && qman_cgrs_get(&c, cgr->cgrid))
 815                                 cgr->cb(p, cgr, qman_cgrs_get(&rr, cgr->cgrid));
 816                 spin_unlock(&p->cgr_lock);
 817         }
 818
 819         if (is & QM_PIRQ_EQRI) {
 820                 qm_eqcr_cce_update(&p->p);
 821                 qm_eqcr_set_ithresh(&p->p, 0);
 822                 wake_up(&affine_queue);
 823         }
 824
 825         if (is & QM_PIRQ_MRI) {
 826                 struct qman_fq *fq;
 827                 u8 verb, num = 0;
 828 mr_loop:
 829                 qm_mr_pvb_update(&p->p);
 830                 msg = qm_mr_current(&p->p);
 831                 if (!msg)
 832                         goto mr_done;
 833                 swapped_msg = *msg;
 834                 hw_fd_to_cpu(&swapped_msg.ern.fd);
 835                 verb = msg->verb & QM_MR_VERB_TYPE_MASK;
 836                 /* The message is a software ERN iff the 0x20 bit is set */
 837                 if (verb & 0x20) {
 838                         switch (verb) {
 839                         case QM_MR_VERB_FQRNI:
 840                                 /* nada, we drop FQRNIs on the floor */
 841                                 break;
 842                         case QM_MR_VERB_FQRN:
 843                         case QM_MR_VERB_FQRL:
 844                                 /* Lookup in the retirement table */
 845                                 fq = table_find_fq(p,
 846                                                    be32_to_cpu(msg->fq.fqid));
 847                                 DPAA_BUG_ON(!fq);
 848                                 fq_state_change(p, fq, &swapped_msg, verb);
 849                                 if (fq->cb.fqs)
 850                                         fq->cb.fqs(p, fq, &swapped_msg);
 851                                 break;
 852                         case QM_MR_VERB_FQPN:
 853                                 /* Parked */
 854 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
 855                                 fq = get_fq_table_entry(
 856                                         be32_to_cpu(msg->fq.contextB));
 857 #else
 858                                 fq = (void *)(uintptr_t)
 859                                         be32_to_cpu(msg->fq.contextB);
 860 #endif
 861                                 fq_state_change(p, fq, msg, verb);
 862                                 if (fq->cb.fqs)
 863                                         fq->cb.fqs(p, fq, &swapped_msg);
 864                                 break;
 865                         case QM_MR_VERB_DC_ERN:
 866                                 /* DCP ERN */
 867                                 if (p->cb_dc_ern)
 868                                         p->cb_dc_ern(p, msg);
 869                                 else if (cb_dc_ern)
 870                                         cb_dc_ern(p, msg);
 871                                 else {
 872                                         static int warn_once;
 873
 874                                         if (!warn_once) {
 875                                                 pr_crit("Leaking DCP ERNs!\n");
 876                                                 warn_once = 1;
 877                                         }
 878                                 }
 879                                 break;
 880                         default:
 881                                 pr_crit("Invalid MR verb 0x%02x\n", verb);
 882                         }
 883                 } else {
 884                         /* Its a software ERN */
 885 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
 886                         fq = get_fq_table_entry(be32_to_cpu(msg->ern.tag));
 887 #else
 888                         fq = (void *)(uintptr_t)be32_to_cpu(msg->ern.tag);
 889 #endif
 890                         fq->cb.ern(p, fq, &swapped_msg);
 891                 }
 892                 num++;
 893                 qm_mr_next(&p->p);
 894                 goto mr_loop;
 895 mr_done:
 896                 qm_mr_cci_consume(&p->p, num);
 897         }
 898         /*
 899          * QM_PIRQ_CSCI/CCSCI has already been cleared, as part of its specific
 900          * processing. If that interrupt source has meanwhile been re-asserted,
 901          * we mustn't clear it here (or in the top-level interrupt handler).
 902          */
 903         return is & (QM_PIRQ_EQCI | QM_PIRQ_EQRI | QM_PIRQ_MRI);
 904 }
 905
 906 /*
 907  * remove some slowish-path stuff from the "fast path" and make sure it isn't
 908  * inlined.
 909  */
 910 static noinline void clear_vdqcr(struct qman_portal *p, struct qman_fq *fq)
 911 {
 912         p->vdqcr_owned = NULL;
 913         FQLOCK(fq);
 914         fq_clear(fq, QMAN_FQ_STATE_VDQCR);
 915         FQUNLOCK(fq);
 916         wake_up(&affine_queue);
 917 }
 918
 919 /*
 920  * The only states that would conflict with other things if they ran at the
 921  * same time on the same cpu are:
 922  *
 923  *   (i) setting/clearing vdqcr_owned, and
 924  *  (ii) clearing the NE (Not Empty) flag.
 925  *
 926  * Both are safe. Because;
 927  *
 928  *   (i) this clearing can only occur after qman_set_vdq() has set the
 929  *       vdqcr_owned field (which it does before setting VDQCR), and
 930  *       qman_volatile_dequeue() blocks interrupts and preemption while this is
 931  *       done so that we can't interfere.
 932  *  (ii) the NE flag is only cleared after qman_retire_fq() has set it, and as
 933  *       with (i) that API prevents us from interfering until it's safe.
 934  *
 935  * The good thing is that qman_set_vdq() and qman_retire_fq() run far
 936  * less frequently (ie. per-FQ) than __poll_portal_fast() does, so the nett
 937  * advantage comes from this function not having to "lock" anything at all.
 938  *
 939  * Note also that the callbacks are invoked at points which are safe against the
 940  * above potential conflicts, but that this function itself is not re-entrant
 941  * (this is because the function tracks one end of each FIFO in the portal and
 942  * we do *not* want to lock that). So the consequence is that it is safe for
 943  * user callbacks to call into any QMan API.
 944  */
 945 static inline unsigned int __poll_portal_fast(struct qman_portal *p,
 946                                               unsigned int poll_limit)
 947 {
 948         const struct qm_dqrr_entry *dq;
 949         struct qman_fq *fq;
 950         enum qman_cb_dqrr_result res;
 951         unsigned int limit = 0;
 952 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
 953         struct qm_dqrr_entry *shadow;
 954 #endif
 955         do {
 956                 qm_dqrr_pvb_update(&p->p);
 957                 dq = qm_dqrr_current(&p->p);
 958                 if (unlikely(!dq))
 959                         break;
 960 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
 961         /* If running on an LE system the fields of the
 962          * dequeue entry must be swapper.  Because the
 963          * QMan HW will ignore writes the DQRR entry is
 964          * copied and the index stored within the copy
 965          */
 966                 shadow = &p->shadow_dqrr[DQRR_PTR2IDX(dq)];
 967                 *shadow = *dq;
 968                 dq = shadow;
 969                 shadow->fqid = be32_to_cpu(shadow->fqid);
 970                 shadow->contextB = be32_to_cpu(shadow->contextB);
 971                 shadow->seqnum = be16_to_cpu(shadow->seqnum);
 972                 hw_fd_to_cpu(&shadow->fd);
 973 #endif
 974
 975                 if (dq->stat & QM_DQRR_STAT_UNSCHEDULED) {
 976                         /*
 977                          * VDQCR: don't trust context_b as the FQ may have
 978                          * been configured for h/w consumption and we're
 979                          * draining it post-retirement.
 980                          */
 981                         fq = p->vdqcr_owned;
 982                         /*
 983                          * We only set QMAN_FQ_STATE_NE when retiring, so we
 984                          * only need to check for clearing it when doing
 985                          * volatile dequeues.  It's one less thing to check
 986                          * in the critical path (SDQCR).
 987                          */
 988                         if (dq->stat & QM_DQRR_STAT_FQ_EMPTY)
 989                                 fq_clear(fq, QMAN_FQ_STATE_NE);
 990                         /*
 991                          * This is duplicated from the SDQCR code, but we
 992                          * have stuff to do before *and* after this callback,
 993                          * and we don't want multiple if()s in the critical
 994                          * path (SDQCR).
 995                          */
 996                         res = fq->cb.dqrr(p, fq, dq);
 997                         if (res == qman_cb_dqrr_stop)
 998                                 break;
 999                         /* Check for VDQCR completion */
1000                         if (dq->stat & QM_DQRR_STAT_DQCR_EXPIRED)
1001                                 clear_vdqcr(p, fq);
1002                 } else {
1003                         /* SDQCR: context_b points to the FQ */
1004 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1005                         fq = get_fq_table_entry(dq->contextB);
1006 #else
1007                         fq = (void *)(uintptr_t)dq->contextB;
1008 #endif
1009                         /* Now let the callback do its stuff */
1010                         res = fq->cb.dqrr(p, fq, dq);
1011                         /*
1012                          * The callback can request that we exit without
1013                          * consuming this entry nor advancing;
1014                          */
1015                         if (res == qman_cb_dqrr_stop)
1016                                 break;
1017                 }
1018                 /* Interpret 'dq' from a driver perspective. */
1019                 /*
1020                  * Parking isn't possible unless HELDACTIVE was set. NB,
1021                  * FORCEELIGIBLE implies HELDACTIVE, so we only need to
1022                  * check for HELDACTIVE to cover both.
1023                  */
1024                 DPAA_ASSERT((dq->stat & QM_DQRR_STAT_FQ_HELDACTIVE) ||
1025                             (res != qman_cb_dqrr_park));
1026                 /* just means "skip it, I'll consume it myself later on" */
1027                 if (res != qman_cb_dqrr_defer)
1028                         qm_dqrr_cdc_consume_1ptr(&p->p, dq,
1029                                                  res == qman_cb_dqrr_park);
1030                 /* Move forward */
1031                 qm_dqrr_next(&p->p);
1032                 /*
1033                  * Entry processed and consumed, increment our counter.  The
1034                  * callback can request that we exit after consuming the
1035                  * entry, and we also exit if we reach our processing limit,
1036                  * so loop back only if neither of these conditions is met.
1037                  */
1038         } while (++limit < poll_limit && res != qman_cb_dqrr_consume_stop);
1039
1040         return limit;
1041 }
1042
1043 u16 qman_affine_channel(int cpu)
1044 {
1045         if (cpu < 0) {
1046                 struct qman_portal *portal = get_affine_portal();
1047
1048                 cpu = portal->config->cpu;
1049         }
1050         DPAA_BUG_ON(!CPU_ISSET(cpu, &affine_mask));
1051         return affine_channels[cpu];
1052 }
1053
1054 unsigned int qman_portal_poll_rx(unsigned int poll_limit,
1055                                  void **bufs,
1056                                  struct qman_portal *p)
1057 {
1058         const struct qm_dqrr_entry *dq;
1059         struct qman_fq *fq;
1060         enum qman_cb_dqrr_result res;
1061         unsigned int limit = 0;
1062 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
1063         struct qm_dqrr_entry *shadow;
1064 #endif
1065         unsigned int rx_number = 0;
1066
1067         do {
1068                 qm_dqrr_pvb_update(&p->p);
1069                 dq = qm_dqrr_current(&p->p);
1070                 if (unlikely(!dq))
1071                         break;
1072 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
1073         /* If running on an LE system the fields of the
1074          * dequeue entry must be swapper.  Because the
1075          * QMan HW will ignore writes the DQRR entry is
1076          * copied and the index stored within the copy
1077          */
1078                 shadow = &p->shadow_dqrr[DQRR_PTR2IDX(dq)];
1079                 *shadow = *dq;
1080                 dq = shadow;
1081                 shadow->fqid = be32_to_cpu(shadow->fqid);
1082                 shadow->contextB = be32_to_cpu(shadow->contextB);
1083                 shadow->seqnum = be16_to_cpu(shadow->seqnum);
1084                 hw_fd_to_cpu(&shadow->fd);
1085 #endif
1086
1087                 /* SDQCR: context_b points to the FQ */
1088 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1089                 fq = get_fq_table_entry(dq->contextB);
1090 #else
1091                 fq = (void *)(uintptr_t)dq->contextB;
1092 #endif
1093                 /* Now let the callback do its stuff */
1094                 res = fq->cb.dqrr_dpdk_cb(NULL, p, fq, dq, &bufs[rx_number]);
1095                 rx_number++;
1096                 /* Interpret 'dq' from a driver perspective. */
1097                 /*
1098                  * Parking isn't possible unless HELDACTIVE was set. NB,
1099                  * FORCEELIGIBLE implies HELDACTIVE, so we only need to
1100                  * check for HELDACTIVE to cover both.
1101                  */
1102                 DPAA_ASSERT((dq->stat & QM_DQRR_STAT_FQ_HELDACTIVE) ||
1103                             (res != qman_cb_dqrr_park));
1104                 qm_dqrr_cdc_consume_1ptr(&p->p, dq, res == qman_cb_dqrr_park);
1105                 /* Move forward */
1106                 qm_dqrr_next(&p->p);
1107                 /*
1108                  * Entry processed and consumed, increment our counter.  The
1109                  * callback can request that we exit after consuming the
1110                  * entry, and we also exit if we reach our processing limit,
1111                  * so loop back only if neither of these conditions is met.
1112                  */
1113         } while (likely(++limit < poll_limit));
1114
1115         return limit;
1116 }
1117
1118 u32 qman_portal_dequeue(struct rte_event ev[], unsigned int poll_limit,
1119                         void **bufs)
1120 {
1121         const struct qm_dqrr_entry *dq;
1122         struct qman_fq *fq;
1123         enum qman_cb_dqrr_result res;
1124         unsigned int limit = 0;
1125         struct qman_portal *p = get_affine_portal();
1126 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1127         struct qm_dqrr_entry *shadow;
1128 #endif
1129         unsigned int rx_number = 0;
1130
1131         do {
1132                 qm_dqrr_pvb_update(&p->p);
1133                 dq = qm_dqrr_current(&p->p);
1134                 if (!dq)
1135                         break;
1136 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1137                 /*
1138                  * If running on an LE system the fields of the
1139                  * dequeue entry must be swapper.  Because the
1140                  * QMan HW will ignore writes the DQRR entry is
1141                  * copied and the index stored within the copy
1142                  */
1143                 shadow = &p->shadow_dqrr[DQRR_PTR2IDX(dq)];
1144                 *shadow = *dq;
1145                 dq = shadow;
1146                 shadow->fqid = be32_to_cpu(shadow->fqid);
1147                 shadow->contextB = be32_to_cpu(shadow->contextB);
1148                 shadow->seqnum = be16_to_cpu(shadow->seqnum);
1149                 hw_fd_to_cpu(&shadow->fd);
1150 #endif
1151
1152                /* SDQCR: context_b points to the FQ */
1153 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1154                 fq = get_fq_table_entry(dq->contextB);
1155 #else
1156                 fq = (void *)(uintptr_t)dq->contextB;
1157 #endif
1158                 /* Now let the callback do its stuff */
1159                 res = fq->cb.dqrr_dpdk_cb(&ev[rx_number], p, fq,
1160                                          dq, &bufs[rx_number]);
1161                 rx_number++;
1162                 /* Interpret 'dq' from a driver perspective. */
1163                 /*
1164                  * Parking isn't possible unless HELDACTIVE was set. NB,
1165                  * FORCEELIGIBLE implies HELDACTIVE, so we only need to
1166                  * check for HELDACTIVE to cover both.
1167                  */
1168                 DPAA_ASSERT((dq->stat & QM_DQRR_STAT_FQ_HELDACTIVE) ||
1169                             (res != qman_cb_dqrr_park));
1170                 if (res != qman_cb_dqrr_defer)
1171                         qm_dqrr_cdc_consume_1ptr(&p->p, dq,
1172                                                  res == qman_cb_dqrr_park);
1173                 /* Move forward */
1174                 qm_dqrr_next(&p->p);
1175                 /*
1176                  * Entry processed and consumed, increment our counter.  The
1177                  * callback can request that we exit after consuming the
1178                  * entry, and we also exit if we reach our processing limit,
1179                  * so loop back only if neither of these conditions is met.
1180                  */
1181         } while (++limit < poll_limit);
1182
1183         return limit;
1184 }
1185
1186 struct qm_dqrr_entry *qman_dequeue(struct qman_fq *fq)
1187 {
1188         struct qman_portal *p = get_affine_portal();
1189         const struct qm_dqrr_entry *dq;
1190 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
1191         struct qm_dqrr_entry *shadow;
1192 #endif
1193
1194         qm_dqrr_pvb_update(&p->p);
1195         dq = qm_dqrr_current(&p->p);
1196         if (!dq)
1197                 return NULL;
1198
1199         if (!(dq->stat & QM_DQRR_STAT_FD_VALID)) {
1200                 /* Invalid DQRR - put the portal and consume the DQRR.
1201                  * Return NULL to user as no packet is seen.
1202                  */
1203                 qman_dqrr_consume(fq, (struct qm_dqrr_entry *)dq);
1204                 return NULL;
1205         }
1206
1207 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
1208         shadow = &p->shadow_dqrr[DQRR_PTR2IDX(dq)];
1209         *shadow = *dq;
1210         dq = shadow;
1211         shadow->fqid = be32_to_cpu(shadow->fqid);
1212         shadow->contextB = be32_to_cpu(shadow->contextB);
1213         shadow->seqnum = be16_to_cpu(shadow->seqnum);
1214         hw_fd_to_cpu(&shadow->fd);
1215 #endif
1216
1217         if (dq->stat & QM_DQRR_STAT_FQ_EMPTY)
1218                 fq_clear(fq, QMAN_FQ_STATE_NE);
1219
1220         return (struct qm_dqrr_entry *)dq;
1221 }
1222
1223 void qman_dqrr_consume(struct qman_fq *fq,
1224                        struct qm_dqrr_entry *dq)
1225 {
1226         struct qman_portal *p = get_affine_portal();
1227
1228         if (dq->stat & QM_DQRR_STAT_DQCR_EXPIRED)
1229                 clear_vdqcr(p, fq);
1230
1231         qm_dqrr_cdc_consume_1ptr(&p->p, dq, 0);
1232         qm_dqrr_next(&p->p);
1233 }
1234
1235 int qman_poll_dqrr(unsigned int limit)
1236 {
1237         struct qman_portal *p = get_affine_portal();
1238         int ret;
1239
1240         ret = __poll_portal_fast(p, limit);
1241         return ret;
1242 }
1243
1244 void qman_poll(void)
1245 {
1246         struct qman_portal *p = get_affine_portal();
1247
1248         if ((~p->irq_sources) & QM_PIRQ_SLOW) {
1249                 if (!(p->slowpoll--)) {
1250                         u32 is = qm_isr_status_read(&p->p) & ~p->irq_sources;
1251                         u32 active = __poll_portal_slow(p, is);
1252
1253                         if (active) {
1254                                 qm_isr_status_clear(&p->p, active);
1255                                 p->slowpoll = SLOW_POLL_BUSY;
1256                         } else
1257                                 p->slowpoll = SLOW_POLL_IDLE;
1258                 }
1259         }
1260         if ((~p->irq_sources) & QM_PIRQ_DQRI)
1261                 __poll_portal_fast(p, FSL_QMAN_POLL_LIMIT);
1262 }
1263
1264 void qman_stop_dequeues(void)
1265 {
1266         struct qman_portal *p = get_affine_portal();
1267
1268         qman_stop_dequeues_ex(p);
1269 }
1270
1271 void qman_start_dequeues(void)
1272 {
1273         struct qman_portal *p = get_affine_portal();
1274
1275         DPAA_ASSERT(p->dqrr_disable_ref > 0);
1276         if (!(--p->dqrr_disable_ref))
1277                 qm_dqrr_set_maxfill(&p->p, DQRR_MAXFILL);
1278 }
1279
1280 void qman_static_dequeue_add(u32 pools, struct qman_portal *qp)
1281 {
1282         struct qman_portal *p = qp ? qp : get_affine_portal();
1283
1284         pools &= p->config->pools;
1285         p->sdqcr |= pools;
1286         qm_dqrr_sdqcr_set(&p->p, p->sdqcr);
1287 }
1288
1289 void qman_static_dequeue_del(u32 pools, struct qman_portal *qp)
1290 {
1291         struct qman_portal *p = qp ? qp : get_affine_portal();
1292
1293         pools &= p->config->pools;
1294         p->sdqcr &= ~pools;
1295         qm_dqrr_sdqcr_set(&p->p, p->sdqcr);
1296 }
1297
1298 u32 qman_static_dequeue_get(struct qman_portal *qp)
1299 {
1300         struct qman_portal *p = qp ? qp : get_affine_portal();
1301         return p->sdqcr;
1302 }
1303
1304 void qman_dca(const struct qm_dqrr_entry *dq, int park_request)
1305 {
1306         struct qman_portal *p = get_affine_portal();
1307
1308         qm_dqrr_cdc_consume_1ptr(&p->p, dq, park_request);
1309 }
1310
1311 void qman_dca_index(u8 index, int park_request)
1312 {
1313         struct qman_portal *p = get_affine_portal();
1314
1315         qm_dqrr_cdc_consume_1(&p->p, index, park_request);
1316 }
1317
1318 /* Frame queue API */
1319 static const char *mcr_result_str(u8 result)
1320 {
1321         switch (result) {
1322         case QM_MCR_RESULT_NULL:
1323                 return "QM_MCR_RESULT_NULL";
1324         case QM_MCR_RESULT_OK:
1325                 return "QM_MCR_RESULT_OK";
1326         case QM_MCR_RESULT_ERR_FQID:
1327                 return "QM_MCR_RESULT_ERR_FQID";
1328         case QM_MCR_RESULT_ERR_FQSTATE:
1329                 return "QM_MCR_RESULT_ERR_FQSTATE";
1330         case QM_MCR_RESULT_ERR_NOTEMPTY:
1331                 return "QM_MCR_RESULT_ERR_NOTEMPTY";
1332         case QM_MCR_RESULT_PENDING:
1333                 return "QM_MCR_RESULT_PENDING";
1334         case QM_MCR_RESULT_ERR_BADCOMMAND:
1335                 return "QM_MCR_RESULT_ERR_BADCOMMAND";
1336         }
1337         return "<unknown MCR result>";
1338 }
1339
1340 int qman_create_fq(u32 fqid, u32 flags, struct qman_fq *fq)
1341 {
1342         struct qm_fqd fqd;
1343         struct qm_mcr_queryfq_np np;
1344         struct qm_mc_command *mcc;
1345         struct qm_mc_result *mcr;
1346         struct qman_portal *p;
1347
1348         if (flags & QMAN_FQ_FLAG_DYNAMIC_FQID) {
1349                 int ret = qman_alloc_fqid(&fqid);
1350
1351                 if (ret)
1352                         return ret;
1353         }
1354         spin_lock_init(&fq->fqlock);
1355         fq->fqid = fqid;
1356         fq->fqid_le = cpu_to_be32(fqid);
1357         fq->flags = flags;
1358         fq->state = qman_fq_state_oos;
1359         fq->cgr_groupid = 0;
1360 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1361         if (unlikely(find_empty_fq_table_entry(&fq->key, fq))) {
1362                 pr_info("Find empty table entry failed\n");
1363                 return -ENOMEM;
1364         }
1365 #endif
1366         if (!(flags & QMAN_FQ_FLAG_AS_IS) || (flags & QMAN_FQ_FLAG_NO_MODIFY))
1367                 return 0;
1368         /* Everything else is AS_IS support */
1369         p = get_affine_portal();
1370         mcc = qm_mc_start(&p->p);
1371         mcc->queryfq.fqid = cpu_to_be32(fqid);
1372         qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ);
1373         while (!(mcr = qm_mc_result(&p->p)))
1374                 cpu_relax();
1375         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCC_VERB_QUERYFQ);
1376         if (mcr->result != QM_MCR_RESULT_OK) {
1377                 pr_err("QUERYFQ failed: %s\n", mcr_result_str(mcr->result));
1378                 goto err;
1379         }
1380         fqd = mcr->queryfq.fqd;
1381         hw_fqd_to_cpu(&fqd);
1382         mcc = qm_mc_start(&p->p);
1383         mcc->queryfq_np.fqid = cpu_to_be32(fqid);
1384         qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP);
1385         while (!(mcr = qm_mc_result(&p->p)))
1386                 cpu_relax();
1387         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCC_VERB_QUERYFQ_NP);
1388         if (mcr->result != QM_MCR_RESULT_OK) {
1389                 pr_err("QUERYFQ_NP failed: %s\n", mcr_result_str(mcr->result));
1390                 goto err;
1391         }
1392         np = mcr->queryfq_np;
1393         /* Phew, have queryfq and queryfq_np results, stitch together
1394          * the FQ object from those.
1395          */
1396         fq->cgr_groupid = fqd.cgid;
1397         switch (np.state & QM_MCR_NP_STATE_MASK) {
1398         case QM_MCR_NP_STATE_OOS:
1399                 break;
1400         case QM_MCR_NP_STATE_RETIRED:
1401                 fq->state = qman_fq_state_retired;
1402                 if (np.frm_cnt)
1403                         fq_set(fq, QMAN_FQ_STATE_NE);
1404                 break;
1405         case QM_MCR_NP_STATE_TEN_SCHED:
1406         case QM_MCR_NP_STATE_TRU_SCHED:
1407         case QM_MCR_NP_STATE_ACTIVE:
1408                 fq->state = qman_fq_state_sched;
1409                 if (np.state & QM_MCR_NP_STATE_R)
1410                         fq_set(fq, QMAN_FQ_STATE_CHANGING);
1411                 break;
1412         case QM_MCR_NP_STATE_PARKED:
1413                 fq->state = qman_fq_state_parked;
1414                 break;
1415         default:
1416                 DPAA_ASSERT(NULL == "invalid FQ state");
1417         }
1418         if (fqd.fq_ctrl & QM_FQCTRL_CGE)
1419                 fq->state |= QMAN_FQ_STATE_CGR_EN;
1420         return 0;
1421 err:
1422         if (flags & QMAN_FQ_FLAG_DYNAMIC_FQID)
1423                 qman_release_fqid(fqid);
1424         return -EIO;
1425 }
1426
1427 void qman_destroy_fq(struct qman_fq *fq, u32 flags __maybe_unused)
1428 {
1429         /*
1430          * We don't need to lock the FQ as it is a pre-condition that the FQ be
1431          * quiesced. Instead, run some checks.
1432          */
1433         switch (fq->state) {
1434         case qman_fq_state_parked:
1435                 DPAA_ASSERT(flags & QMAN_FQ_DESTROY_PARKED);
1436                 /* Fallthrough */
1437         case qman_fq_state_oos:
1438                 if (fq_isset(fq, QMAN_FQ_FLAG_DYNAMIC_FQID))
1439                         qman_release_fqid(fq->fqid);
1440 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1441                 clear_fq_table_entry(fq->key);
1442 #endif
1443                 return;
1444         default:
1445                 break;
1446         }
1447         DPAA_ASSERT(NULL == "qman_free_fq() on unquiesced FQ!");
1448 }
1449
1450 u32 qman_fq_fqid(struct qman_fq *fq)
1451 {
1452         return fq->fqid;
1453 }
1454
1455 void qman_fq_state(struct qman_fq *fq, enum qman_fq_state *state, u32 *flags)
1456 {
1457         if (state)
1458                 *state = fq->state;
1459         if (flags)
1460                 *flags = fq->flags;
1461 }
1462
1463 int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts)
1464 {
1465         struct qm_mc_command *mcc;
1466         struct qm_mc_result *mcr;
1467         struct qman_portal *p;
1468
1469         u8 res, myverb = (flags & QMAN_INITFQ_FLAG_SCHED) ?
1470                 QM_MCC_VERB_INITFQ_SCHED : QM_MCC_VERB_INITFQ_PARKED;
1471
1472         if ((fq->state != qman_fq_state_oos) &&
1473             (fq->state != qman_fq_state_parked))
1474                 return -EINVAL;
1475 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
1476         if (unlikely(fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY)))
1477                 return -EINVAL;
1478 #endif
1479         if (opts && (opts->we_mask & QM_INITFQ_WE_OAC)) {
1480                 /* And can't be set at the same time as TDTHRESH */
1481                 if (opts->we_mask & QM_INITFQ_WE_TDTHRESH)
1482                         return -EINVAL;
1483         }
1484         /* Issue an INITFQ_[PARKED|SCHED] management command */
1485         p = get_affine_portal();
1486         FQLOCK(fq);
1487         if (unlikely((fq_isset(fq, QMAN_FQ_STATE_CHANGING)) ||
1488                      ((fq->state != qman_fq_state_oos) &&
1489                                 (fq->state != qman_fq_state_parked)))) {
1490                 FQUNLOCK(fq);
1491                 return -EBUSY;
1492         }
1493         mcc = qm_mc_start(&p->p);
1494         if (opts)
1495                 mcc->initfq = *opts;
1496         mcc->initfq.fqid = cpu_to_be32(fq->fqid);
1497         mcc->initfq.count = 0;
1498         /*
1499          * If the FQ does *not* have the TO_DCPORTAL flag, context_b is set as a
1500          * demux pointer. Otherwise, the caller-provided value is allowed to
1501          * stand, don't overwrite it.
1502          */
1503         if (fq_isclear(fq, QMAN_FQ_FLAG_TO_DCPORTAL)) {
1504                 dma_addr_t phys_fq;
1505
1506                 mcc->initfq.we_mask |= QM_INITFQ_WE_CONTEXTB;
1507 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1508                 mcc->initfq.fqd.context_b = fq->key;
1509 #else
1510                 mcc->initfq.fqd.context_b = (u32)(uintptr_t)fq;
1511 #endif
1512                 /*
1513                  *  and the physical address - NB, if the user wasn't trying to
1514                  * set CONTEXTA, clear the stashing settings.
1515                  */
1516                 if (!(mcc->initfq.we_mask & QM_INITFQ_WE_CONTEXTA)) {
1517                         mcc->initfq.we_mask |= QM_INITFQ_WE_CONTEXTA;
1518                         memset(&mcc->initfq.fqd.context_a, 0,
1519                                sizeof(mcc->initfq.fqd.context_a));
1520                 } else {
1521                         phys_fq = rte_mem_virt2iova(fq);
1522                         qm_fqd_stashing_set64(&mcc->initfq.fqd, phys_fq);
1523                 }
1524         }
1525         if (flags & QMAN_INITFQ_FLAG_LOCAL) {
1526                 mcc->initfq.fqd.dest.channel = p->config->channel;
1527                 if (!(mcc->initfq.we_mask & QM_INITFQ_WE_DESTWQ)) {
1528                         mcc->initfq.we_mask |= QM_INITFQ_WE_DESTWQ;
1529                         mcc->initfq.fqd.dest.wq = 4;
1530                 }
1531         }
1532         mcc->initfq.we_mask = cpu_to_be16(mcc->initfq.we_mask);
1533         cpu_to_hw_fqd(&mcc->initfq.fqd);
1534         qm_mc_commit(&p->p, myverb);
1535         while (!(mcr = qm_mc_result(&p->p)))
1536                 cpu_relax();
1537         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == myverb);
1538         res = mcr->result;
1539         if (res != QM_MCR_RESULT_OK) {
1540                 FQUNLOCK(fq);
1541                 return -EIO;
1542         }
1543         if (opts) {
1544                 if (opts->we_mask & QM_INITFQ_WE_FQCTRL) {
1545                         if (opts->fqd.fq_ctrl & QM_FQCTRL_CGE)
1546                                 fq_set(fq, QMAN_FQ_STATE_CGR_EN);
1547                         else
1548                                 fq_clear(fq, QMAN_FQ_STATE_CGR_EN);
1549                 }
1550                 if (opts->we_mask & QM_INITFQ_WE_CGID)
1551                         fq->cgr_groupid = opts->fqd.cgid;
1552         }
1553         fq->state = (flags & QMAN_INITFQ_FLAG_SCHED) ?
1554                 qman_fq_state_sched : qman_fq_state_parked;
1555         FQUNLOCK(fq);
1556         return 0;
1557 }
1558
1559 int qman_schedule_fq(struct qman_fq *fq)
1560 {
1561         struct qm_mc_command *mcc;
1562         struct qm_mc_result *mcr;
1563         struct qman_portal *p;
1564
1565         int ret = 0;
1566         u8 res;
1567
1568         if (fq->state != qman_fq_state_parked)
1569                 return -EINVAL;
1570 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
1571         if (unlikely(fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY)))
1572                 return -EINVAL;
1573 #endif
1574         /* Issue a ALTERFQ_SCHED management command */
1575         p = get_affine_portal();
1576
1577         FQLOCK(fq);
1578         if (unlikely((fq_isset(fq, QMAN_FQ_STATE_CHANGING)) ||
1579                      (fq->state != qman_fq_state_parked))) {
1580                 ret = -EBUSY;
1581                 goto out;
1582         }
1583         mcc = qm_mc_start(&p->p);
1584         mcc->alterfq.fqid = cpu_to_be32(fq->fqid);
1585         qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_SCHED);
1586         while (!(mcr = qm_mc_result(&p->p)))
1587                 cpu_relax();
1588         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_SCHED);
1589         res = mcr->result;
1590         if (res != QM_MCR_RESULT_OK) {
1591                 ret = -EIO;
1592                 goto out;
1593         }
1594         fq->state = qman_fq_state_sched;
1595 out:
1596         FQUNLOCK(fq);
1597
1598         return ret;
1599 }
1600
1601 int qman_retire_fq(struct qman_fq *fq, u32 *flags)
1602 {
1603         struct qm_mc_command *mcc;
1604         struct qm_mc_result *mcr;
1605         struct qman_portal *p;
1606
1607         int rval;
1608         u8 res;
1609
1610         if ((fq->state != qman_fq_state_parked) &&
1611             (fq->state != qman_fq_state_sched))
1612                 return -EINVAL;
1613 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
1614         if (unlikely(fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY)))
1615                 return -EINVAL;
1616 #endif
1617         p = get_affine_portal();
1618
1619         FQLOCK(fq);
1620         if (unlikely((fq_isset(fq, QMAN_FQ_STATE_CHANGING)) ||
1621                      (fq->state == qman_fq_state_retired) ||
1622                                 (fq->state == qman_fq_state_oos))) {
1623                 rval = -EBUSY;
1624                 goto out;
1625         }
1626         rval = table_push_fq(p, fq);
1627         if (rval)
1628                 goto out;
1629         mcc = qm_mc_start(&p->p);
1630         mcc->alterfq.fqid = cpu_to_be32(fq->fqid);
1631         qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_RETIRE);
1632         while (!(mcr = qm_mc_result(&p->p)))
1633                 cpu_relax();
1634         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_RETIRE);
1635         res = mcr->result;
1636         /*
1637          * "Elegant" would be to treat OK/PENDING the same way; set CHANGING,
1638          * and defer the flags until FQRNI or FQRN (respectively) show up. But
1639          * "Friendly" is to process OK immediately, and not set CHANGING. We do
1640          * friendly, otherwise the caller doesn't necessarily have a fully
1641          * "retired" FQ on return even if the retirement was immediate. However
1642          * this does mean some code duplication between here and
1643          * fq_state_change().
1644          */
1645         if (likely(res == QM_MCR_RESULT_OK)) {
1646                 rval = 0;
1647                 /* Process 'fq' right away, we'll ignore FQRNI */
1648                 if (mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY)
1649                         fq_set(fq, QMAN_FQ_STATE_NE);
1650                 if (mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT)
1651                         fq_set(fq, QMAN_FQ_STATE_ORL);
1652                 else
1653                         table_del_fq(p, fq);
1654                 if (flags)
1655                         *flags = fq->flags;
1656                 fq->state = qman_fq_state_retired;
1657                 if (fq->cb.fqs) {
1658                         /*
1659                          * Another issue with supporting "immediate" retirement
1660                          * is that we're forced to drop FQRNIs, because by the
1661                          * time they're seen it may already be "too late" (the
1662                          * fq may have been OOS'd and free()'d already). But if
1663                          * the upper layer wants a callback whether it's
1664                          * immediate or not, we have to fake a "MR" entry to
1665                          * look like an FQRNI...
1666                          */
1667                         struct qm_mr_entry msg;
1668
1669                         msg.verb = QM_MR_VERB_FQRNI;
1670                         msg.fq.fqs = mcr->alterfq.fqs;
1671                         msg.fq.fqid = fq->fqid;
1672 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1673                         msg.fq.contextB = fq->key;
1674 #else
1675                         msg.fq.contextB = (u32)(uintptr_t)fq;
1676 #endif
1677                         fq->cb.fqs(p, fq, &msg);
1678                 }
1679         } else if (res == QM_MCR_RESULT_PENDING) {
1680                 rval = 1;
1681                 fq_set(fq, QMAN_FQ_STATE_CHANGING);
1682         } else {
1683                 rval = -EIO;
1684                 table_del_fq(p, fq);
1685         }
1686 out:
1687         FQUNLOCK(fq);
1688         return rval;
1689 }
1690
1691 int qman_oos_fq(struct qman_fq *fq)
1692 {
1693         struct qm_mc_command *mcc;
1694         struct qm_mc_result *mcr;
1695         struct qman_portal *p;
1696
1697         int ret = 0;
1698         u8 res;
1699
1700         if (fq->state != qman_fq_state_retired)
1701                 return -EINVAL;
1702 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
1703         if (unlikely(fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY)))
1704                 return -EINVAL;
1705 #endif
1706         p = get_affine_portal();
1707         FQLOCK(fq);
1708         if (unlikely((fq_isset(fq, QMAN_FQ_STATE_BLOCKOOS)) ||
1709                      (fq->state != qman_fq_state_retired))) {
1710                 ret = -EBUSY;
1711                 goto out;
1712         }
1713         mcc = qm_mc_start(&p->p);
1714         mcc->alterfq.fqid = cpu_to_be32(fq->fqid);
1715         qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
1716         while (!(mcr = qm_mc_result(&p->p)))
1717                 cpu_relax();
1718         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_OOS);
1719         res = mcr->result;
1720         if (res != QM_MCR_RESULT_OK) {
1721                 ret = -EIO;
1722                 goto out;
1723         }
1724         fq->state = qman_fq_state_oos;
1725 out:
1726         FQUNLOCK(fq);
1727         return ret;
1728 }
1729
1730 int qman_fq_flow_control(struct qman_fq *fq, int xon)
1731 {
1732         struct qm_mc_command *mcc;
1733         struct qm_mc_result *mcr;
1734         struct qman_portal *p;
1735
1736         int ret = 0;
1737         u8 res;
1738         u8 myverb;
1739
1740         if ((fq->state == qman_fq_state_oos) ||
1741             (fq->state == qman_fq_state_retired) ||
1742                 (fq->state == qman_fq_state_parked))
1743                 return -EINVAL;
1744
1745 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
1746         if (unlikely(fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY)))
1747                 return -EINVAL;
1748 #endif
1749         /* Issue a ALTER_FQXON or ALTER_FQXOFF management command */
1750         p = get_affine_portal();
1751         FQLOCK(fq);
1752         if (unlikely((fq_isset(fq, QMAN_FQ_STATE_CHANGING)) ||
1753                      (fq->state == qman_fq_state_parked) ||
1754                         (fq->state == qman_fq_state_oos) ||
1755                         (fq->state == qman_fq_state_retired))) {
1756                 ret = -EBUSY;
1757                 goto out;
1758         }
1759         mcc = qm_mc_start(&p->p);
1760         mcc->alterfq.fqid = fq->fqid;
1761         mcc->alterfq.count = 0;
1762         myverb = xon ? QM_MCC_VERB_ALTER_FQXON : QM_MCC_VERB_ALTER_FQXOFF;
1763
1764         qm_mc_commit(&p->p, myverb);
1765         while (!(mcr = qm_mc_result(&p->p)))
1766                 cpu_relax();
1767         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == myverb);
1768
1769         res = mcr->result;
1770         if (res != QM_MCR_RESULT_OK) {
1771                 ret = -EIO;
1772                 goto out;
1773         }
1774 out:
1775         FQUNLOCK(fq);
1776         return ret;
1777 }
1778
1779 int qman_query_fq(struct qman_fq *fq, struct qm_fqd *fqd)
1780 {
1781         struct qm_mc_command *mcc;
1782         struct qm_mc_result *mcr;
1783         struct qman_portal *p = get_affine_portal();
1784
1785         u8 res;
1786
1787         mcc = qm_mc_start(&p->p);
1788         mcc->queryfq.fqid = cpu_to_be32(fq->fqid);
1789         qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ);
1790         while (!(mcr = qm_mc_result(&p->p)))
1791                 cpu_relax();
1792         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ);
1793         res = mcr->result;
1794         if (res == QM_MCR_RESULT_OK)
1795                 *fqd = mcr->queryfq.fqd;
1796         hw_fqd_to_cpu(fqd);
1797         if (res != QM_MCR_RESULT_OK)
1798                 return -EIO;
1799         return 0;
1800 }
1801
1802 int qman_query_fq_has_pkts(struct qman_fq *fq)
1803 {
1804         struct qm_mc_command *mcc;
1805         struct qm_mc_result *mcr;
1806         struct qman_portal *p = get_affine_portal();
1807
1808         int ret = 0;
1809         u8 res;
1810
1811         mcc = qm_mc_start(&p->p);
1812         mcc->queryfq.fqid = cpu_to_be32(fq->fqid);
1813         qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP);
1814         while (!(mcr = qm_mc_result(&p->p)))
1815                 cpu_relax();
1816         res = mcr->result;
1817         if (res == QM_MCR_RESULT_OK)
1818                 ret = !!mcr->queryfq_np.frm_cnt;
1819         return ret;
1820 }
1821
1822 int qman_query_fq_np(struct qman_fq *fq, struct qm_mcr_queryfq_np *np)
1823 {
1824         struct qm_mc_command *mcc;
1825         struct qm_mc_result *mcr;
1826         struct qman_portal *p = get_affine_portal();
1827
1828         u8 res;
1829
1830         mcc = qm_mc_start(&p->p);
1831         mcc->queryfq.fqid = cpu_to_be32(fq->fqid);
1832         qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP);
1833         while (!(mcr = qm_mc_result(&p->p)))
1834                 cpu_relax();
1835         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP);
1836         res = mcr->result;
1837         if (res == QM_MCR_RESULT_OK) {
1838                 *np = mcr->queryfq_np;
1839                 np->fqd_link = be24_to_cpu(np->fqd_link);
1840                 np->odp_seq = be16_to_cpu(np->odp_seq);
1841                 np->orp_nesn = be16_to_cpu(np->orp_nesn);
1842                 np->orp_ea_hseq  = be16_to_cpu(np->orp_ea_hseq);
1843                 np->orp_ea_tseq  = be16_to_cpu(np->orp_ea_tseq);
1844                 np->orp_ea_hptr = be24_to_cpu(np->orp_ea_hptr);
1845                 np->orp_ea_tptr = be24_to_cpu(np->orp_ea_tptr);
1846                 np->pfdr_hptr = be24_to_cpu(np->pfdr_hptr);
1847                 np->pfdr_tptr = be24_to_cpu(np->pfdr_tptr);
1848                 np->ics_surp = be16_to_cpu(np->ics_surp);
1849                 np->byte_cnt = be32_to_cpu(np->byte_cnt);
1850                 np->frm_cnt = be24_to_cpu(np->frm_cnt);
1851                 np->ra1_sfdr = be16_to_cpu(np->ra1_sfdr);
1852                 np->ra2_sfdr = be16_to_cpu(np->ra2_sfdr);
1853                 np->od1_sfdr = be16_to_cpu(np->od1_sfdr);
1854                 np->od2_sfdr = be16_to_cpu(np->od2_sfdr);
1855                 np->od3_sfdr = be16_to_cpu(np->od3_sfdr);
1856         }
1857         if (res == QM_MCR_RESULT_ERR_FQID)
1858                 return -ERANGE;
1859         else if (res != QM_MCR_RESULT_OK)
1860                 return -EIO;
1861         return 0;
1862 }
1863
1864 int qman_query_fq_frm_cnt(struct qman_fq *fq, u32 *frm_cnt)
1865 {
1866         struct qm_mc_command *mcc;
1867         struct qm_mc_result *mcr;
1868         struct qman_portal *p = get_affine_portal();
1869
1870         mcc = qm_mc_start(&p->p);
1871         mcc->queryfq.fqid = cpu_to_be32(fq->fqid);
1872         qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP);
1873         while (!(mcr = qm_mc_result(&p->p)))
1874                 cpu_relax();
1875         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP);
1876
1877         if (mcr->result == QM_MCR_RESULT_OK)
1878                 *frm_cnt = be24_to_cpu(mcr->queryfq_np.frm_cnt);
1879         else if (mcr->result == QM_MCR_RESULT_ERR_FQID)
1880                 return -ERANGE;
1881         else if (mcr->result != QM_MCR_RESULT_OK)
1882                 return -EIO;
1883         return 0;
1884 }
1885
1886 int qman_query_wq(u8 query_dedicated, struct qm_mcr_querywq *wq)
1887 {
1888         struct qm_mc_command *mcc;
1889         struct qm_mc_result *mcr;
1890         struct qman_portal *p = get_affine_portal();
1891
1892         u8 res, myverb;
1893
1894         myverb = (query_dedicated) ? QM_MCR_VERB_QUERYWQ_DEDICATED :
1895                                  QM_MCR_VERB_QUERYWQ;
1896         mcc = qm_mc_start(&p->p);
1897         mcc->querywq.channel.id = cpu_to_be16(wq->channel.id);
1898         qm_mc_commit(&p->p, myverb);
1899         while (!(mcr = qm_mc_result(&p->p)))
1900                 cpu_relax();
1901         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == myverb);
1902         res = mcr->result;
1903         if (res == QM_MCR_RESULT_OK) {
1904                 int i, array_len;
1905
1906                 wq->channel.id = be16_to_cpu(mcr->querywq.channel.id);
1907                 array_len = ARRAY_SIZE(mcr->querywq.wq_len);
1908                 for (i = 0; i < array_len; i++)
1909                         wq->wq_len[i] = be32_to_cpu(mcr->querywq.wq_len[i]);
1910         }
1911         if (res != QM_MCR_RESULT_OK) {
1912                 pr_err("QUERYWQ failed: %s\n", mcr_result_str(res));
1913                 return -EIO;
1914         }
1915         return 0;
1916 }
1917
1918 int qman_testwrite_cgr(struct qman_cgr *cgr, u64 i_bcnt,
1919                        struct qm_mcr_cgrtestwrite *result)
1920 {
1921         struct qm_mc_command *mcc;
1922         struct qm_mc_result *mcr;
1923         struct qman_portal *p = get_affine_portal();
1924
1925         u8 res;
1926
1927         mcc = qm_mc_start(&p->p);
1928         mcc->cgrtestwrite.cgid = cgr->cgrid;
1929         mcc->cgrtestwrite.i_bcnt_hi = (u8)(i_bcnt >> 32);
1930         mcc->cgrtestwrite.i_bcnt_lo = (u32)i_bcnt;
1931         qm_mc_commit(&p->p, QM_MCC_VERB_CGRTESTWRITE);
1932         while (!(mcr = qm_mc_result(&p->p)))
1933                 cpu_relax();
1934         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCC_VERB_CGRTESTWRITE);
1935         res = mcr->result;
1936         if (res == QM_MCR_RESULT_OK)
1937                 *result = mcr->cgrtestwrite;
1938         if (res != QM_MCR_RESULT_OK) {
1939                 pr_err("CGR TEST WRITE failed: %s\n", mcr_result_str(res));
1940                 return -EIO;
1941         }
1942         return 0;
1943 }
1944
1945 int qman_query_cgr(struct qman_cgr *cgr, struct qm_mcr_querycgr *cgrd)
1946 {
1947         struct qm_mc_command *mcc;
1948         struct qm_mc_result *mcr;
1949         struct qman_portal *p = get_affine_portal();
1950         u8 res;
1951         unsigned int i;
1952
1953         mcc = qm_mc_start(&p->p);
1954         mcc->querycgr.cgid = cgr->cgrid;
1955         qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCGR);
1956         while (!(mcr = qm_mc_result(&p->p)))
1957                 cpu_relax();
1958         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCC_VERB_QUERYCGR);
1959         res = mcr->result;
1960         if (res == QM_MCR_RESULT_OK)
1961                 *cgrd = mcr->querycgr;
1962         if (res != QM_MCR_RESULT_OK) {
1963                 pr_err("QUERY_CGR failed: %s\n", mcr_result_str(res));
1964                 return -EIO;
1965         }
1966         cgrd->cgr.wr_parm_g.word =
1967                 be32_to_cpu(cgrd->cgr.wr_parm_g.word);
1968         cgrd->cgr.wr_parm_y.word =
1969                 be32_to_cpu(cgrd->cgr.wr_parm_y.word);
1970         cgrd->cgr.wr_parm_r.word =
1971                 be32_to_cpu(cgrd->cgr.wr_parm_r.word);
1972         cgrd->cgr.cscn_targ =  be32_to_cpu(cgrd->cgr.cscn_targ);
1973         cgrd->cgr.__cs_thres = be16_to_cpu(cgrd->cgr.__cs_thres);
1974         for (i = 0; i < ARRAY_SIZE(cgrd->cscn_targ_swp); i++)
1975                 cgrd->cscn_targ_swp[i] =
1976                         be32_to_cpu(cgrd->cscn_targ_swp[i]);
1977         return 0;
1978 }
1979
1980 int qman_query_congestion(struct qm_mcr_querycongestion *congestion)
1981 {
1982         struct qm_mc_result *mcr;
1983         struct qman_portal *p = get_affine_portal();
1984         u8 res;
1985         unsigned int i;
1986
1987         qm_mc_start(&p->p);
1988         qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCONGESTION);
1989         while (!(mcr = qm_mc_result(&p->p)))
1990                 cpu_relax();
1991         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
1992                         QM_MCC_VERB_QUERYCONGESTION);
1993         res = mcr->result;
1994         if (res == QM_MCR_RESULT_OK)
1995                 *congestion = mcr->querycongestion;
1996         if (res != QM_MCR_RESULT_OK) {
1997                 pr_err("QUERY_CONGESTION failed: %s\n", mcr_result_str(res));
1998                 return -EIO;
1999         }
2000         for (i = 0; i < ARRAY_SIZE(congestion->state.state); i++)
2001                 congestion->state.state[i] =
2002                         be32_to_cpu(congestion->state.state[i]);
2003         return 0;
2004 }
2005
2006 int qman_set_vdq(struct qman_fq *fq, u16 num)
2007 {
2008         struct qman_portal *p = get_affine_portal();
2009         uint32_t vdqcr;
2010         int ret = -EBUSY;
2011
2012         vdqcr = QM_VDQCR_EXACT;
2013         vdqcr |= QM_VDQCR_NUMFRAMES_SET(num);
2014
2015         if ((fq->state != qman_fq_state_parked) &&
2016             (fq->state != qman_fq_state_retired)) {
2017                 ret = -EINVAL;
2018                 goto out;
2019         }
2020         if (fq_isset(fq, QMAN_FQ_STATE_VDQCR)) {
2021                 ret = -EBUSY;
2022                 goto out;
2023         }
2024         vdqcr = (vdqcr & ~QM_VDQCR_FQID_MASK) | fq->fqid;
2025
2026         if (!p->vdqcr_owned) {
2027                 FQLOCK(fq);
2028                 if (fq_isset(fq, QMAN_FQ_STATE_VDQCR))
2029                         goto escape;
2030                 fq_set(fq, QMAN_FQ_STATE_VDQCR);
2031                 FQUNLOCK(fq);
2032                 p->vdqcr_owned = fq;
2033                 ret = 0;
2034         }
2035 escape:
2036         if (!ret)
2037                 qm_dqrr_vdqcr_set(&p->p, vdqcr);
2038
2039 out:
2040         return ret;
2041 }
2042
2043 int qman_volatile_dequeue(struct qman_fq *fq, u32 flags __maybe_unused,
2044                           u32 vdqcr)
2045 {
2046         struct qman_portal *p;
2047         int ret = -EBUSY;
2048
2049         if ((fq->state != qman_fq_state_parked) &&
2050             (fq->state != qman_fq_state_retired))
2051                 return -EINVAL;
2052         if (vdqcr & QM_VDQCR_FQID_MASK)
2053                 return -EINVAL;
2054         if (fq_isset(fq, QMAN_FQ_STATE_VDQCR))
2055                 return -EBUSY;
2056         vdqcr = (vdqcr & ~QM_VDQCR_FQID_MASK) | fq->fqid;
2057
2058         p = get_affine_portal();
2059
2060         if (!p->vdqcr_owned) {
2061                 FQLOCK(fq);
2062                 if (fq_isset(fq, QMAN_FQ_STATE_VDQCR))
2063                         goto escape;
2064                 fq_set(fq, QMAN_FQ_STATE_VDQCR);
2065                 FQUNLOCK(fq);
2066                 p->vdqcr_owned = fq;
2067                 ret = 0;
2068         }
2069 escape:
2070         if (ret)
2071                 return ret;
2072
2073         /* VDQCR is set */
2074         qm_dqrr_vdqcr_set(&p->p, vdqcr);
2075         return 0;
2076 }
2077
2078 static noinline void update_eqcr_ci(struct qman_portal *p, u8 avail)
2079 {
2080         if (avail)
2081                 qm_eqcr_cce_prefetch(&p->p);
2082         else
2083                 qm_eqcr_cce_update(&p->p);
2084 }
2085
2086 int qman_eqcr_is_empty(void)
2087 {
2088         struct qman_portal *p = get_affine_portal();
2089         u8 avail;
2090
2091         update_eqcr_ci(p, 0);
2092         avail = qm_eqcr_get_fill(&p->p);
2093         return (avail == 0);
2094 }
2095
2096 void qman_set_dc_ern(qman_cb_dc_ern handler, int affine)
2097 {
2098         if (affine) {
2099                 struct qman_portal *p = get_affine_portal();
2100
2101                 p->cb_dc_ern = handler;
2102         } else
2103                 cb_dc_ern = handler;
2104 }
2105
2106 static inline struct qm_eqcr_entry *try_p_eq_start(struct qman_portal *p,
2107                                         struct qman_fq *fq,
2108                                         const struct qm_fd *fd,
2109                                         u32 flags)
2110 {
2111         struct qm_eqcr_entry *eq;
2112         u8 avail;
2113
2114         if (p->use_eqcr_ci_stashing) {
2115                 /*
2116                  * The stashing case is easy, only update if we need to in
2117                  * order to try and liberate ring entries.
2118                  */
2119                 eq = qm_eqcr_start_stash(&p->p);
2120         } else {
2121                 /*
2122                  * The non-stashing case is harder, need to prefetch ahead of
2123                  * time.
2124                  */
2125                 avail = qm_eqcr_get_avail(&p->p);
2126                 if (avail < 2)
2127                         update_eqcr_ci(p, avail);
2128                 eq = qm_eqcr_start_no_stash(&p->p);
2129         }
2130
2131         if (unlikely(!eq))
2132                 return NULL;
2133
2134         if (flags & QMAN_ENQUEUE_FLAG_DCA)
2135                 eq->dca = QM_EQCR_DCA_ENABLE |
2136                         ((flags & QMAN_ENQUEUE_FLAG_DCA_PARK) ?
2137                                         QM_EQCR_DCA_PARK : 0) |
2138                         ((flags >> 8) & QM_EQCR_DCA_IDXMASK);
2139         eq->fqid = cpu_to_be32(fq->fqid);
2140 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
2141         eq->tag = cpu_to_be32(fq->key);
2142 #else
2143         eq->tag = cpu_to_be32((u32)(uintptr_t)fq);
2144 #endif
2145         eq->fd = *fd;
2146         cpu_to_hw_fd(&eq->fd);
2147         return eq;
2148 }
2149
2150 int qman_enqueue(struct qman_fq *fq, const struct qm_fd *fd, u32 flags)
2151 {
2152         struct qman_portal *p = get_affine_portal();
2153         struct qm_eqcr_entry *eq;
2154
2155         eq = try_p_eq_start(p, fq, fd, flags);
2156         if (!eq)
2157                 return -EBUSY;
2158         /* Note: QM_EQCR_VERB_INTERRUPT == QMAN_ENQUEUE_FLAG_WAIT_SYNC */
2159         qm_eqcr_pvb_commit(&p->p, QM_EQCR_VERB_CMD_ENQUEUE |
2160                 (flags & (QM_EQCR_VERB_COLOUR_MASK | QM_EQCR_VERB_INTERRUPT)));
2161         /* Factor the below out, it's used from qman_enqueue_orp() too */
2162         return 0;
2163 }
2164
2165 int qman_enqueue_multi(struct qman_fq *fq,
2166                        const struct qm_fd *fd, u32 *flags,
2167                 int frames_to_send)
2168 {
2169         struct qman_portal *p = get_affine_portal();
2170         struct qm_portal *portal = &p->p;
2171
2172         register struct qm_eqcr *eqcr = &portal->eqcr;
2173         struct qm_eqcr_entry *eq = eqcr->cursor, *prev_eq;
2174
2175         u8 i = 0, diff, old_ci, sent = 0;
2176
2177         /* Update the available entries if no entry is free */
2178         if (!eqcr->available) {
2179                 old_ci = eqcr->ci;
2180                 eqcr->ci = qm_cl_in(EQCR_CI) & (QM_EQCR_SIZE - 1);
2181                 diff = qm_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci);
2182                 eqcr->available += diff;
2183                 if (!diff)
2184                         return 0;
2185         }
2186
2187         /* try to send as many frames as possible */
2188         while (eqcr->available && frames_to_send--) {
2189                 eq->fqid = fq->fqid_le;
2190 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
2191                 eq->tag = cpu_to_be32(fq->key);
2192 #else
2193                 eq->tag = cpu_to_be32((u32)(uintptr_t)fq);
2194 #endif
2195                 eq->fd.opaque_addr = fd->opaque_addr;
2196                 eq->fd.addr = cpu_to_be40(fd->addr);
2197                 eq->fd.status = cpu_to_be32(fd->status);
2198                 eq->fd.opaque = cpu_to_be32(fd->opaque);
2199                 if (flags && (flags[i] & QMAN_ENQUEUE_FLAG_DCA)) {
2200                         eq->dca = QM_EQCR_DCA_ENABLE |
2201                                 ((flags[i] >> 8) & QM_EQCR_DCA_IDXMASK);
2202                 }
2203                 i++;
2204                 eq = (void *)((unsigned long)(eq + 1) &
2205                         (~(unsigned long)(QM_EQCR_SIZE << 6)));
2206                 eqcr->available--;
2207                 sent++;
2208                 fd++;
2209         }
2210         lwsync();
2211
2212         /* In order for flushes to complete faster, all lines are recorded in
2213          * 32 bit word.
2214          */
2215         eq = eqcr->cursor;
2216         for (i = 0; i < sent; i++) {
2217                 eq->__dont_write_directly__verb =
2218                         QM_EQCR_VERB_CMD_ENQUEUE | eqcr->vbit;
2219                 prev_eq = eq;
2220                 eq = (void *)((unsigned long)(eq + 1) &
2221                         (~(unsigned long)(QM_EQCR_SIZE << 6)));
2222                 if (unlikely((prev_eq + 1) != eq))
2223                         eqcr->vbit ^= QM_EQCR_VERB_VBIT;
2224         }
2225
2226         /* We need  to flush all the lines but without load/store operations
2227          * between them
2228          */
2229         eq = eqcr->cursor;
2230         for (i = 0; i < sent; i++) {
2231                 dcbf(eq);
2232                 eq = (void *)((unsigned long)(eq + 1) &
2233                         (~(unsigned long)(QM_EQCR_SIZE << 6)));
2234         }
2235         /* Update cursor for the next call */
2236         eqcr->cursor = eq;
2237         return sent;
2238 }
2239
2240 int
2241 qman_enqueue_multi_fq(struct qman_fq *fq[], const struct qm_fd *fd,
2242                       int frames_to_send)
2243 {
2244         struct qman_portal *p = get_affine_portal();
2245         struct qm_portal *portal = &p->p;
2246
2247         register struct qm_eqcr *eqcr = &portal->eqcr;
2248         struct qm_eqcr_entry *eq = eqcr->cursor, *prev_eq;
2249
2250         u8 i, diff, old_ci, sent = 0;
2251
2252         /* Update the available entries if no entry is free */
2253         if (!eqcr->available) {
2254                 old_ci = eqcr->ci;
2255                 eqcr->ci = qm_cl_in(EQCR_CI) & (QM_EQCR_SIZE - 1);
2256                 diff = qm_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci);
2257                 eqcr->available += diff;
2258                 if (!diff)
2259                         return 0;
2260         }
2261
2262         /* try to send as many frames as possible */
2263         while (eqcr->available && frames_to_send--) {
2264                 eq->fqid = fq[sent]->fqid_le;
2265                 eq->fd.opaque_addr = fd->opaque_addr;
2266                 eq->fd.addr = cpu_to_be40(fd->addr);
2267                 eq->fd.status = cpu_to_be32(fd->status);
2268                 eq->fd.opaque = cpu_to_be32(fd->opaque);
2269
2270                 eq = (void *)((unsigned long)(eq + 1) &
2271                         (~(unsigned long)(QM_EQCR_SIZE << 6)));
2272                 eqcr->available--;
2273                 sent++;
2274                 fd++;
2275         }
2276         lwsync();
2277
2278         /* In order for flushes to complete faster, all lines are recorded in
2279          * 32 bit word.
2280          */
2281         eq = eqcr->cursor;
2282         for (i = 0; i < sent; i++) {
2283                 eq->__dont_write_directly__verb =
2284                         QM_EQCR_VERB_CMD_ENQUEUE | eqcr->vbit;
2285                 prev_eq = eq;
2286                 eq = (void *)((unsigned long)(eq + 1) &
2287                         (~(unsigned long)(QM_EQCR_SIZE << 6)));
2288                 if (unlikely((prev_eq + 1) != eq))
2289                         eqcr->vbit ^= QM_EQCR_VERB_VBIT;
2290         }
2291
2292         /* We need  to flush all the lines but without load/store operations
2293          * between them
2294          */
2295         eq = eqcr->cursor;
2296         for (i = 0; i < sent; i++) {
2297                 dcbf(eq);
2298                 eq = (void *)((unsigned long)(eq + 1) &
2299                         (~(unsigned long)(QM_EQCR_SIZE << 6)));
2300         }
2301         /* Update cursor for the next call */
2302         eqcr->cursor = eq;
2303         return sent;
2304 }
2305
2306 int qman_enqueue_orp(struct qman_fq *fq, const struct qm_fd *fd, u32 flags,
2307                      struct qman_fq *orp, u16 orp_seqnum)
2308 {
2309         struct qman_portal *p  = get_affine_portal();
2310         struct qm_eqcr_entry *eq;
2311
2312         eq = try_p_eq_start(p, fq, fd, flags);
2313         if (!eq)
2314                 return -EBUSY;
2315         /* Process ORP-specifics here */
2316         if (flags & QMAN_ENQUEUE_FLAG_NLIS)
2317                 orp_seqnum |= QM_EQCR_SEQNUM_NLIS;
2318         else {
2319                 orp_seqnum &= ~QM_EQCR_SEQNUM_NLIS;
2320                 if (flags & QMAN_ENQUEUE_FLAG_NESN)
2321                         orp_seqnum |= QM_EQCR_SEQNUM_NESN;
2322                 else
2323                         /* No need to check 4 QMAN_ENQUEUE_FLAG_HOLE */
2324                         orp_seqnum &= ~QM_EQCR_SEQNUM_NESN;
2325         }
2326         eq->seqnum = cpu_to_be16(orp_seqnum);
2327         eq->orp = cpu_to_be32(orp->fqid);
2328         /* Note: QM_EQCR_VERB_INTERRUPT == QMAN_ENQUEUE_FLAG_WAIT_SYNC */
2329         qm_eqcr_pvb_commit(&p->p, QM_EQCR_VERB_ORP |
2330                 ((flags & (QMAN_ENQUEUE_FLAG_HOLE | QMAN_ENQUEUE_FLAG_NESN)) ?
2331                                 0 : QM_EQCR_VERB_CMD_ENQUEUE) |
2332                 (flags & (QM_EQCR_VERB_COLOUR_MASK | QM_EQCR_VERB_INTERRUPT)));
2333
2334         return 0;
2335 }
2336
2337 int qman_modify_cgr(struct qman_cgr *cgr, u32 flags,
2338                     struct qm_mcc_initcgr *opts)
2339 {
2340         struct qm_mc_command *mcc;
2341         struct qm_mc_result *mcr;
2342         struct qman_portal *p = get_affine_portal();
2343
2344         u8 res;
2345         u8 verb = QM_MCC_VERB_MODIFYCGR;
2346
2347         mcc = qm_mc_start(&p->p);
2348         if (opts)
2349                 mcc->initcgr = *opts;
2350         mcc->initcgr.we_mask = cpu_to_be16(mcc->initcgr.we_mask);
2351         mcc->initcgr.cgr.wr_parm_g.word =
2352                 cpu_to_be32(mcc->initcgr.cgr.wr_parm_g.word);
2353         mcc->initcgr.cgr.wr_parm_y.word =
2354                 cpu_to_be32(mcc->initcgr.cgr.wr_parm_y.word);
2355         mcc->initcgr.cgr.wr_parm_r.word =
2356                 cpu_to_be32(mcc->initcgr.cgr.wr_parm_r.word);
2357         mcc->initcgr.cgr.cscn_targ =  cpu_to_be32(mcc->initcgr.cgr.cscn_targ);
2358         mcc->initcgr.cgr.__cs_thres = cpu_to_be16(mcc->initcgr.cgr.__cs_thres);
2359
2360         mcc->initcgr.cgid = cgr->cgrid;
2361         if (flags & QMAN_CGR_FLAG_USE_INIT)
2362                 verb = QM_MCC_VERB_INITCGR;
2363         qm_mc_commit(&p->p, verb);
2364         while (!(mcr = qm_mc_result(&p->p)))
2365                 cpu_relax();
2366
2367         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == verb);
2368         res = mcr->result;
2369         return (res == QM_MCR_RESULT_OK) ? 0 : -EIO;
2370 }
2371
2372 #define TARG_MASK(n) (0x80000000 >> (n->config->channel - \
2373                                         QM_CHANNEL_SWPORTAL0))
2374 #define TARG_DCP_MASK(n) (0x80000000 >> (10 + n))
2375 #define PORTAL_IDX(n) (n->config->channel - QM_CHANNEL_SWPORTAL0)
2376
2377 int qman_create_cgr(struct qman_cgr *cgr, u32 flags,
2378                     struct qm_mcc_initcgr *opts)
2379 {
2380         struct qm_mcr_querycgr cgr_state;
2381         struct qm_mcc_initcgr local_opts;
2382         int ret;
2383         struct qman_portal *p;
2384
2385         /* We have to check that the provided CGRID is within the limits of the
2386          * data-structures, for obvious reasons. However we'll let h/w take
2387          * care of determining whether it's within the limits of what exists on
2388          * the SoC.
2389          */
2390         if (cgr->cgrid >= __CGR_NUM)
2391                 return -EINVAL;
2392
2393         p = get_affine_portal();
2394
2395         memset(&local_opts, 0, sizeof(struct qm_mcc_initcgr));
2396         cgr->chan = p->config->channel;
2397         spin_lock(&p->cgr_lock);
2398
2399         /* if no opts specified, just add it to the list */
2400         if (!opts)
2401                 goto add_list;
2402
2403         ret = qman_query_cgr(cgr, &cgr_state);
2404         if (ret)
2405                 goto release_lock;
2406         if (opts)
2407                 local_opts = *opts;
2408         if ((qman_ip_rev & 0xFF00) >= QMAN_REV30)
2409                 local_opts.cgr.cscn_targ_upd_ctrl =
2410                         QM_CGR_TARG_UDP_CTRL_WRITE_BIT | PORTAL_IDX(p);
2411         else
2412                 /* Overwrite TARG */
2413                 local_opts.cgr.cscn_targ = cgr_state.cgr.cscn_targ |
2414                                                         TARG_MASK(p);
2415         local_opts.we_mask |= QM_CGR_WE_CSCN_TARG;
2416
2417         /* send init if flags indicate so */
2418         if (opts && (flags & QMAN_CGR_FLAG_USE_INIT))
2419                 ret = qman_modify_cgr(cgr, QMAN_CGR_FLAG_USE_INIT, &local_opts);
2420         else
2421                 ret = qman_modify_cgr(cgr, 0, &local_opts);
2422         if (ret)
2423                 goto release_lock;
2424 add_list:
2425         list_add(&cgr->node, &p->cgr_cbs);
2426
2427         /* Determine if newly added object requires its callback to be called */
2428         ret = qman_query_cgr(cgr, &cgr_state);
2429         if (ret) {
2430                 /* we can't go back, so proceed and return success, but screen
2431                  * and wail to the log file.
2432                  */
2433                 pr_crit("CGR HW state partially modified\n");
2434                 ret = 0;
2435                 goto release_lock;
2436         }
2437         if (cgr->cb && cgr_state.cgr.cscn_en && qman_cgrs_get(&p->cgrs[1],
2438                                                               cgr->cgrid))
2439                 cgr->cb(p, cgr, 1);
2440 release_lock:
2441         spin_unlock(&p->cgr_lock);
2442         return ret;
2443 }
2444
2445 int qman_create_cgr_to_dcp(struct qman_cgr *cgr, u32 flags, u16 dcp_portal,
2446                            struct qm_mcc_initcgr *opts)
2447 {
2448         struct qm_mcc_initcgr local_opts;
2449         struct qm_mcr_querycgr cgr_state;
2450         int ret;
2451
2452         if ((qman_ip_rev & 0xFF00) < QMAN_REV30) {
2453                 pr_warn("QMan version doesn't support CSCN => DCP portal\n");
2454                 return -EINVAL;
2455         }
2456         /* We have to check that the provided CGRID is within the limits of the
2457          * data-structures, for obvious reasons. However we'll let h/w take
2458          * care of determining whether it's within the limits of what exists on
2459          * the SoC.
2460          */
2461         if (cgr->cgrid >= __CGR_NUM)
2462                 return -EINVAL;
2463
2464         ret = qman_query_cgr(cgr, &cgr_state);
2465         if (ret)
2466                 return ret;
2467
2468         memset(&local_opts, 0, sizeof(struct qm_mcc_initcgr));
2469         if (opts)
2470                 local_opts = *opts;
2471
2472         if ((qman_ip_rev & 0xFF00) >= QMAN_REV30)
2473                 local_opts.cgr.cscn_targ_upd_ctrl =
2474                                 QM_CGR_TARG_UDP_CTRL_WRITE_BIT |
2475                                 QM_CGR_TARG_UDP_CTRL_DCP | dcp_portal;
2476         else
2477                 local_opts.cgr.cscn_targ = cgr_state.cgr.cscn_targ |
2478                                         TARG_DCP_MASK(dcp_portal);
2479         local_opts.we_mask |= QM_CGR_WE_CSCN_TARG;
2480
2481         /* send init if flags indicate so */
2482         if (opts && (flags & QMAN_CGR_FLAG_USE_INIT))
2483                 ret = qman_modify_cgr(cgr, QMAN_CGR_FLAG_USE_INIT,
2484                                       &local_opts);
2485         else
2486                 ret = qman_modify_cgr(cgr, 0, &local_opts);
2487
2488         return ret;
2489 }
2490
2491 int qman_delete_cgr(struct qman_cgr *cgr)
2492 {
2493         struct qm_mcr_querycgr cgr_state;
2494         struct qm_mcc_initcgr local_opts;
2495         int ret = 0;
2496         struct qman_cgr *i;
2497         struct qman_portal *p = get_affine_portal();
2498
2499         if (cgr->chan != p->config->channel) {
2500                 pr_crit("Attempting to delete cgr from different portal than"
2501                         " it was create: create 0x%x, delete 0x%x\n",
2502                         cgr->chan, p->config->channel);
2503                 ret = -EINVAL;
2504                 goto put_portal;
2505         }
2506         memset(&local_opts, 0, sizeof(struct qm_mcc_initcgr));
2507         spin_lock(&p->cgr_lock);
2508         list_del(&cgr->node);
2509         /*
2510          * If there are no other CGR objects for this CGRID in the list,
2511          * update CSCN_TARG accordingly
2512          */
2513         list_for_each_entry(i, &p->cgr_cbs, node)
2514                 if ((i->cgrid == cgr->cgrid) && i->cb)
2515                         goto release_lock;
2516         ret = qman_query_cgr(cgr, &cgr_state);
2517         if (ret)  {
2518                 /* add back to the list */
2519                 list_add(&cgr->node, &p->cgr_cbs);
2520                 goto release_lock;
2521         }
2522         /* Overwrite TARG */
2523         local_opts.we_mask = QM_CGR_WE_CSCN_TARG;
2524         if ((qman_ip_rev & 0xFF00) >= QMAN_REV30)
2525                 local_opts.cgr.cscn_targ_upd_ctrl = PORTAL_IDX(p);
2526         else
2527                 local_opts.cgr.cscn_targ = cgr_state.cgr.cscn_targ &
2528                                                          ~(TARG_MASK(p));
2529         ret = qman_modify_cgr(cgr, 0, &local_opts);
2530         if (ret)
2531                 /* add back to the list */
2532                 list_add(&cgr->node, &p->cgr_cbs);
2533 release_lock:
2534         spin_unlock(&p->cgr_lock);
2535 put_portal:
2536         return ret;
2537 }
2538
2539 int qman_shutdown_fq(u32 fqid)
2540 {
2541         struct qman_portal *p;
2542         struct qm_portal *low_p;
2543         struct qm_mc_command *mcc;
2544         struct qm_mc_result *mcr;
2545         u8 state;
2546         int orl_empty, fq_empty, drain = 0;
2547         u32 result;
2548         u32 channel, wq;
2549         u16 dest_wq;
2550
2551         p = get_affine_portal();
2552         low_p = &p->p;
2553
2554         /* Determine the state of the FQID */
2555         mcc = qm_mc_start(low_p);
2556         mcc->queryfq_np.fqid = cpu_to_be32(fqid);
2557         qm_mc_commit(low_p, QM_MCC_VERB_QUERYFQ_NP);
2558         while (!(mcr = qm_mc_result(low_p)))
2559                 cpu_relax();
2560         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP);
2561         state = mcr->queryfq_np.state & QM_MCR_NP_STATE_MASK;
2562         if (state == QM_MCR_NP_STATE_OOS)
2563                 return 0; /* Already OOS, no need to do anymore checks */
2564
2565         /* Query which channel the FQ is using */
2566         mcc = qm_mc_start(low_p);
2567         mcc->queryfq.fqid = cpu_to_be32(fqid);
2568         qm_mc_commit(low_p, QM_MCC_VERB_QUERYFQ);
2569         while (!(mcr = qm_mc_result(low_p)))
2570                 cpu_relax();
2571         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ);
2572
2573         /* Need to store these since the MCR gets reused */
2574         dest_wq = be16_to_cpu(mcr->queryfq.fqd.dest_wq);
2575         channel = dest_wq & 0x7;
2576         wq = dest_wq >> 3;
2577
2578         switch (state) {
2579         case QM_MCR_NP_STATE_TEN_SCHED:
2580         case QM_MCR_NP_STATE_TRU_SCHED:
2581         case QM_MCR_NP_STATE_ACTIVE:
2582         case QM_MCR_NP_STATE_PARKED:
2583                 orl_empty = 0;
2584                 mcc = qm_mc_start(low_p);
2585                 mcc->alterfq.fqid = cpu_to_be32(fqid);
2586                 qm_mc_commit(low_p, QM_MCC_VERB_ALTER_RETIRE);
2587                 while (!(mcr = qm_mc_result(low_p)))
2588                         cpu_relax();
2589                 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2590                            QM_MCR_VERB_ALTER_RETIRE);
2591                 result = mcr->result; /* Make a copy as we reuse MCR below */
2592
2593                 if (result == QM_MCR_RESULT_PENDING) {
2594                         /* Need to wait for the FQRN in the message ring, which
2595                          * will only occur once the FQ has been drained.  In
2596                          * order for the FQ to drain the portal needs to be set
2597                          * to dequeue from the channel the FQ is scheduled on
2598                          */
2599                         const struct qm_mr_entry *msg;
2600                         const struct qm_dqrr_entry *dqrr = NULL;
2601                         int found_fqrn = 0;
2602                         __maybe_unused u16 dequeue_wq = 0;
2603
2604                         /* Flag that we need to drain FQ */
2605                         drain = 1;
2606
2607                         if (channel >= qm_channel_pool1 &&
2608                             channel < (u16)(qm_channel_pool1 + 15)) {
2609                                 /* Pool channel, enable the bit in the portal */
2610                                 dequeue_wq = (channel -
2611                                               qm_channel_pool1 + 1) << 4 | wq;
2612                         } else if (channel < qm_channel_pool1) {
2613                                 /* Dedicated channel */
2614                                 dequeue_wq = wq;
2615                         } else {
2616                                 pr_info("Cannot recover FQ 0x%x,"
2617                                         " it is scheduled on channel 0x%x",
2618                                         fqid, channel);
2619                                 return -EBUSY;
2620                         }
2621                         /* Set the sdqcr to drain this channel */
2622                         if (channel < qm_channel_pool1)
2623                                 qm_dqrr_sdqcr_set(low_p,
2624                                                   QM_SDQCR_TYPE_ACTIVE |
2625                                           QM_SDQCR_CHANNELS_DEDICATED);
2626                         else
2627                                 qm_dqrr_sdqcr_set(low_p,
2628                                                   QM_SDQCR_TYPE_ACTIVE |
2629                                                   QM_SDQCR_CHANNELS_POOL_CONV
2630                                                   (channel));
2631                         while (!found_fqrn) {
2632                                 /* Keep draining DQRR while checking the MR*/
2633                                 qm_dqrr_pvb_update(low_p);
2634                                 dqrr = qm_dqrr_current(low_p);
2635                                 while (dqrr) {
2636                                         qm_dqrr_cdc_consume_1ptr(
2637                                                 low_p, dqrr, 0);
2638                                         qm_dqrr_pvb_update(low_p);
2639                                         qm_dqrr_next(low_p);
2640                                         dqrr = qm_dqrr_current(low_p);
2641                                 }
2642                                 /* Process message ring too */
2643                                 qm_mr_pvb_update(low_p);
2644                                 msg = qm_mr_current(low_p);
2645                                 while (msg) {
2646                                         if ((msg->verb &
2647                                              QM_MR_VERB_TYPE_MASK)
2648                                             == QM_MR_VERB_FQRN)
2649                                                 found_fqrn = 1;
2650                                         qm_mr_next(low_p);
2651                                         qm_mr_cci_consume_to_current(low_p);
2652                                         qm_mr_pvb_update(low_p);
2653                                         msg = qm_mr_current(low_p);
2654                                 }
2655                                 cpu_relax();
2656                         }
2657                 }
2658                 if (result != QM_MCR_RESULT_OK &&
2659                     result !=  QM_MCR_RESULT_PENDING) {
2660                         /* error */
2661                         pr_err("qman_retire_fq failed on FQ 0x%x,"
2662                                " result=0x%x\n", fqid, result);
2663                         return -1;
2664                 }
2665                 if (!(mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT)) {
2666                         /* ORL had no entries, no need to wait until the
2667                          * ERNs come in.
2668                          */
2669                         orl_empty = 1;
2670                 }
2671                 /* Retirement succeeded, check to see if FQ needs
2672                  * to be drained.
2673                  */
2674                 if (drain || mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY) {
2675                         /* FQ is Not Empty, drain using volatile DQ commands */
2676                         fq_empty = 0;
2677                         do {
2678                                 const struct qm_dqrr_entry *dqrr = NULL;
2679                                 u32 vdqcr = fqid | QM_VDQCR_NUMFRAMES_SET(3);
2680
2681                                 qm_dqrr_vdqcr_set(low_p, vdqcr);
2682
2683                                 /* Wait for a dequeue to occur */
2684                                 while (dqrr == NULL) {
2685                                         qm_dqrr_pvb_update(low_p);
2686                                         dqrr = qm_dqrr_current(low_p);
2687                                         if (!dqrr)
2688                                                 cpu_relax();
2689                                 }
2690                                 /* Process the dequeues, making sure to
2691                                  * empty the ring completely.
2692                                  */
2693                                 while (dqrr) {
2694                                         if (dqrr->fqid == fqid &&
2695                                             dqrr->stat & QM_DQRR_STAT_FQ_EMPTY)
2696                                                 fq_empty = 1;
2697                                         qm_dqrr_cdc_consume_1ptr(low_p,
2698                                                                  dqrr, 0);
2699                                         qm_dqrr_pvb_update(low_p);
2700                                         qm_dqrr_next(low_p);
2701                                         dqrr = qm_dqrr_current(low_p);
2702                                 }
2703                         } while (fq_empty == 0);
2704                 }
2705                 qm_dqrr_sdqcr_set(low_p, 0);
2706
2707                 /* Wait for the ORL to have been completely drained */
2708                 while (orl_empty == 0) {
2709                         const struct qm_mr_entry *msg;
2710
2711                         qm_mr_pvb_update(low_p);
2712                         msg = qm_mr_current(low_p);
2713                         while (msg) {
2714                                 if ((msg->verb & QM_MR_VERB_TYPE_MASK) ==
2715                                     QM_MR_VERB_FQRL)
2716                                         orl_empty = 1;
2717                                 qm_mr_next(low_p);
2718                                 qm_mr_cci_consume_to_current(low_p);
2719                                 qm_mr_pvb_update(low_p);
2720                                 msg = qm_mr_current(low_p);
2721                         }
2722                         cpu_relax();
2723                 }
2724                 mcc = qm_mc_start(low_p);
2725                 mcc->alterfq.fqid = cpu_to_be32(fqid);
2726                 qm_mc_commit(low_p, QM_MCC_VERB_ALTER_OOS);
2727                 while (!(mcr = qm_mc_result(low_p)))
2728                         cpu_relax();
2729                 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2730                            QM_MCR_VERB_ALTER_OOS);
2731                 if (mcr->result != QM_MCR_RESULT_OK) {
2732                         pr_err(
2733                         "OOS after drain Failed on FQID 0x%x, result 0x%x\n",
2734                                fqid, mcr->result);
2735                         return -1;
2736                 }
2737                 return 0;
2738
2739         case QM_MCR_NP_STATE_RETIRED:
2740                 /* Send OOS Command */
2741                 mcc = qm_mc_start(low_p);
2742                 mcc->alterfq.fqid = cpu_to_be32(fqid);
2743                 qm_mc_commit(low_p, QM_MCC_VERB_ALTER_OOS);
2744                 while (!(mcr = qm_mc_result(low_p)))
2745                         cpu_relax();
2746                 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2747                            QM_MCR_VERB_ALTER_OOS);
2748                 if (mcr->result) {
2749                         pr_err("OOS Failed on FQID 0x%x\n", fqid);
2750                         return -1;
2751                 }
2752                 return 0;
2753
2754         }
2755         return -1;
2756 }