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43 #include "qman_priv.h"
44 #include <sys/ioctl.h>
45 #include <rte_branch_prediction.h>
47 /* Global variable containing revision id (even on non-control plane systems
48 * where CCSR isn't available).
51 u16 qm_channel_pool1 = QMAN_CHANNEL_POOL1;
52 u16 qm_channel_caam = QMAN_CHANNEL_CAAM;
53 u16 qm_channel_pme = QMAN_CHANNEL_PME;
55 /* Ccsr map address to access ccsrbased register */
57 /* The qman clock frequency */
60 static __thread int fd = -1;
61 static __thread struct qm_portal_config pcfg;
62 static __thread struct dpaa_ioctl_portal_map map = {
63 .type = dpaa_portal_qman
66 static int fsl_qman_portal_init(uint32_t index, int is_shared)
70 struct dpaa_ioctl_irq_map irq_map;
72 /* Verify the thread's cpu-affinity */
73 ret = pthread_getaffinity_np(pthread_self(), sizeof(cpu_set_t),
76 error(0, ret, "pthread_getaffinity_np()");
80 for (loop = 0; loop < CPU_SETSIZE; loop++)
81 if (CPU_ISSET(loop, &cpuset)) {
83 pr_err("Thread is not affine to 1 cpu\n");
89 pr_err("Bug in getaffinity handling!\n");
93 /* Allocate and map a qman portal */
95 ret = process_portal_map(&map);
97 error(0, ret, "process_portal_map()");
100 pcfg.channel = map.channel;
101 pcfg.pools = map.pools;
102 pcfg.index = map.index;
104 /* Make the portal's cache-[enabled|inhibited] regions */
105 pcfg.addr_virt[DPAA_PORTAL_CE] = map.addr.cena;
106 pcfg.addr_virt[DPAA_PORTAL_CI] = map.addr.cinh;
108 fd = open(QMAN_PORTAL_IRQ_PATH, O_RDONLY);
110 pr_err("QMan irq init failed\n");
111 process_portal_unmap(&map.addr);
115 pcfg.is_shared = is_shared;
119 irq_map.type = dpaa_portal_qman;
120 irq_map.portal_cinh = map.addr.cinh;
121 process_portal_irq_map(fd, &irq_map);
125 static int fsl_qman_portal_finish(void)
129 process_portal_irq_unmap(fd);
131 ret = process_portal_unmap(&map.addr);
133 error(0, ret, "process_portal_unmap()");
137 int qman_thread_init(void)
139 /* Convert from contiguous/virtual cpu numbering to real cpu when
140 * calling into the code that is dependent on the device naming.
142 return fsl_qman_portal_init(QBMAN_ANY_PORTAL_IDX, 0);
145 int qman_thread_finish(void)
147 return fsl_qman_portal_finish();
150 void qman_thread_irq(void)
152 qbman_invoke_irq(pcfg.irq);
154 /* Now we need to uninhibit interrupts. This is the only code outside
155 * the regular portal driver that manipulates any portal register, so
156 * rather than breaking that encapsulation I am simply hard-coding the
157 * offset to the inhibit register here.
159 out_be32(pcfg.addr_virt[DPAA_PORTAL_CI] + 0xe0c, 0);
162 int qman_global_init(void)
164 const struct device_node *dt_node;
168 static int ccsr_map_fd;
169 const uint32_t *qman_addr;
179 /* Use the device-tree to determine IP revision until something better
182 dt_node = of_find_compatible_node(NULL, NULL, "fsl,qman-portal");
184 pr_err("No qman portals available for any CPU\n");
187 if (of_device_is_compatible(dt_node, "fsl,qman-portal-1.0") ||
188 of_device_is_compatible(dt_node, "fsl,qman-portal-1.0.0"))
189 pr_err("QMan rev1.0 on P4080 rev1 is not supported!\n");
190 else if (of_device_is_compatible(dt_node, "fsl,qman-portal-1.1") ||
191 of_device_is_compatible(dt_node, "fsl,qman-portal-1.1.0"))
192 qman_ip_rev = QMAN_REV11;
193 else if (of_device_is_compatible(dt_node, "fsl,qman-portal-1.2") ||
194 of_device_is_compatible(dt_node, "fsl,qman-portal-1.2.0"))
195 qman_ip_rev = QMAN_REV12;
196 else if (of_device_is_compatible(dt_node, "fsl,qman-portal-2.0") ||
197 of_device_is_compatible(dt_node, "fsl,qman-portal-2.0.0"))
198 qman_ip_rev = QMAN_REV20;
199 else if (of_device_is_compatible(dt_node, "fsl,qman-portal-3.0.0") ||
200 of_device_is_compatible(dt_node, "fsl,qman-portal-3.0.1"))
201 qman_ip_rev = QMAN_REV30;
202 else if (of_device_is_compatible(dt_node, "fsl,qman-portal-3.1.0") ||
203 of_device_is_compatible(dt_node, "fsl,qman-portal-3.1.1") ||
204 of_device_is_compatible(dt_node, "fsl,qman-portal-3.1.2") ||
205 of_device_is_compatible(dt_node, "fsl,qman-portal-3.1.3"))
206 qman_ip_rev = QMAN_REV31;
207 else if (of_device_is_compatible(dt_node, "fsl,qman-portal-3.2.0") ||
208 of_device_is_compatible(dt_node, "fsl,qman-portal-3.2.1"))
209 qman_ip_rev = QMAN_REV32;
211 qman_ip_rev = QMAN_REV11;
214 pr_err("Unknown qman portal version\n");
217 if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) {
218 qm_channel_pool1 = QMAN_CHANNEL_POOL1_REV3;
219 qm_channel_caam = QMAN_CHANNEL_CAAM_REV3;
220 qm_channel_pme = QMAN_CHANNEL_PME_REV3;
223 dt_node = of_find_compatible_node(NULL, NULL, "fsl,pool-channel-range");
225 pr_err("No qman pool channel range available\n");
228 chanid = of_get_property(dt_node, "fsl,pool-channel-range", &lenp);
230 pr_err("Can not get pool-channel-range property\n");
235 dt_node = of_find_compatible_node(NULL, NULL, "fsl,qman");
237 pr_err("No qman device node available\n");
240 qman_addr = of_get_address(dt_node, 0, ®s_size, NULL);
242 pr_err("of_get_address cannot return qman address\n");
245 phys_addr = of_translate_address(dt_node, qman_addr);
247 pr_err("of_translate_address failed\n");
251 ccsr_map_fd = open("/dev/mem", O_RDWR);
252 if (unlikely(ccsr_map_fd < 0)) {
253 pr_err("Can not open /dev/mem for qman ccsr map\n");
257 qman_ccsr_map = mmap(NULL, regs_size, PROT_READ | PROT_WRITE,
258 MAP_SHARED, ccsr_map_fd, phys_addr);
259 if (qman_ccsr_map == MAP_FAILED) {
260 pr_err("Can not map qman ccsr base\n");
264 clk = of_get_property(dt_node, "clock-frequency", NULL);
266 pr_warn("Can't find Qman clock frequency\n");
268 qman_clk = be32_to_cpu(*clk);