1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2016-2019 NXP
17 #include <sys/types.h>
18 #include <sys/queue.h>
19 #include <sys/ioctl.h>
22 #include <sys/syscall.h>
23 #include <sys/epoll.h>
24 #include<sys/eventfd.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_malloc.h>
29 #include <rte_memcpy.h>
30 #include <rte_string_fns.h>
31 #include <rte_cycles.h>
32 #include <rte_kvargs.h>
35 #include <fslmc_logs.h>
36 #include <rte_fslmc.h>
37 #include "dpaa2_hw_pvt.h"
38 #include "dpaa2_hw_dpio.h"
39 #include <mc/fsl_dpmng.h>
41 #define NUM_HOST_CPUS RTE_MAX_LCORE
43 struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE];
44 RTE_DEFINE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io);
46 struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP];
48 TAILQ_HEAD(dpio_dev_list, dpaa2_dpio_dev);
49 static struct dpio_dev_list dpio_dev_list
50 = TAILQ_HEAD_INITIALIZER(dpio_dev_list); /*!< DPIO device list */
51 static uint32_t io_space_count;
53 /* Variable to store DPAA2 platform type */
54 uint32_t dpaa2_svr_family;
56 /* Physical core id for lcores running on dpaa2. */
57 /* DPAA2 only support 1 lcore to 1 phy cpu mapping */
58 static unsigned int dpaa2_cpu[RTE_MAX_LCORE];
60 /* Variable to store DPAA2 DQRR size */
61 uint8_t dpaa2_dqrr_size;
62 /* Variable to store DPAA2 EQCR size */
63 uint8_t dpaa2_eqcr_size;
65 /* Variable to hold the portal_key, once created.*/
66 static pthread_key_t dpaa2_portal_key;
68 /*Stashing Macros default for LS208x*/
69 static int dpaa2_core_cluster_base = 0x04;
70 static int dpaa2_cluster_sz = 2;
72 /* For LS208X platform There are four clusters with following mapping:
73 * Cluster 1 (ID = x04) : CPU0, CPU1;
74 * Cluster 2 (ID = x05) : CPU2, CPU3;
75 * Cluster 3 (ID = x06) : CPU4, CPU5;
76 * Cluster 4 (ID = x07) : CPU6, CPU7;
78 /* For LS108X platform There are two clusters with following mapping:
79 * Cluster 1 (ID = x02) : CPU0, CPU1, CPU2, CPU3;
80 * Cluster 2 (ID = x03) : CPU4, CPU5, CPU6, CPU7;
82 /* For LX2160 platform There are four clusters with following mapping:
83 * Cluster 1 (ID = x00) : CPU0, CPU1;
84 * Cluster 2 (ID = x01) : CPU2, CPU3;
85 * Cluster 3 (ID = x02) : CPU4, CPU5;
86 * Cluster 4 (ID = x03) : CPU6, CPU7;
87 * Cluster 1 (ID = x04) : CPU8, CPU9;
88 * Cluster 2 (ID = x05) : CPU10, CP11;
89 * Cluster 3 (ID = x06) : CPU12, CPU13;
90 * Cluster 4 (ID = x07) : CPU14, CPU15;
94 dpaa2_get_core_id(void)
97 int i, ret, cpu_id = -1;
99 ret = pthread_getaffinity_np(pthread_self(), sizeof(cpu_set_t),
102 DPAA2_BUS_ERR("pthread_getaffinity_np() failed");
106 for (i = 0; i < RTE_MAX_LCORE; i++) {
107 if (CPU_ISSET(i, &cpuset)) {
111 /* Multiple cpus are affined */
120 dpaa2_core_cluster_sdest(int cpu_id)
122 int x = cpu_id / dpaa2_cluster_sz;
124 return dpaa2_core_cluster_base + x;
127 #ifdef RTE_LIBRTE_PMD_DPAA2_EVENTDEV
129 dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id, int cpu_id)
131 #define STRING_LEN 28
132 #define COMMAND_LEN 50
133 uint32_t cpu_mask = 1;
136 char *temp = NULL, *token = NULL;
137 char string[STRING_LEN], command[COMMAND_LEN];
140 snprintf(string, STRING_LEN, "dpio.%d", dpio_id);
141 file = fopen("/proc/interrupts", "r");
143 DPAA2_BUS_WARN("Failed to open /proc/interrupts file");
146 while (getline(&temp, &len, file) != -1) {
147 if ((strstr(temp, string)) != NULL) {
148 token = strtok(temp, ":");
154 DPAA2_BUS_WARN("Failed to get interrupt id for dpio.%d",
162 cpu_mask = cpu_mask << dpaa2_cpu[cpu_id];
163 snprintf(command, COMMAND_LEN, "echo %X > /proc/irq/%s/smp_affinity",
165 ret = system(command);
168 "Failed to affine interrupts on respective core");
170 DPAA2_BUS_DEBUG(" %s command is executed", command);
176 static int dpaa2_dpio_intr_init(struct dpaa2_dpio_dev *dpio_dev, int cpu_id)
178 struct epoll_event epoll_ev;
179 int eventfd, dpio_epoll_fd, ret;
180 int threshold = 0x3, timeout = 0xFF;
182 dpio_epoll_fd = epoll_create(1);
183 ret = rte_dpaa2_intr_enable(&dpio_dev->intr_handle, 0);
185 DPAA2_BUS_ERR("Interrupt registeration failed");
189 if (getenv("DPAA2_PORTAL_INTR_THRESHOLD"))
190 threshold = atoi(getenv("DPAA2_PORTAL_INTR_THRESHOLD"));
192 if (getenv("DPAA2_PORTAL_INTR_TIMEOUT"))
193 sscanf(getenv("DPAA2_PORTAL_INTR_TIMEOUT"), "%x", &timeout);
195 qbman_swp_interrupt_set_trigger(dpio_dev->sw_portal,
196 QBMAN_SWP_INTERRUPT_DQRI);
197 qbman_swp_interrupt_clear_status(dpio_dev->sw_portal, 0xffffffff);
198 qbman_swp_interrupt_set_inhibit(dpio_dev->sw_portal, 0);
199 qbman_swp_dqrr_thrshld_write(dpio_dev->sw_portal, threshold);
200 qbman_swp_intr_timeout_write(dpio_dev->sw_portal, timeout);
202 eventfd = dpio_dev->intr_handle.fd;
203 epoll_ev.events = EPOLLIN | EPOLLPRI | EPOLLET;
204 epoll_ev.data.fd = eventfd;
206 ret = epoll_ctl(dpio_epoll_fd, EPOLL_CTL_ADD, eventfd, &epoll_ev);
208 DPAA2_BUS_ERR("epoll_ctl failed");
211 dpio_dev->epoll_fd = dpio_epoll_fd;
213 dpaa2_affine_dpio_intr_to_respective_core(dpio_dev->hw_id, cpu_id);
218 static void dpaa2_dpio_intr_deinit(struct dpaa2_dpio_dev *dpio_dev)
222 ret = rte_dpaa2_intr_disable(&dpio_dev->intr_handle, 0);
224 DPAA2_BUS_ERR("DPIO interrupt disable failed");
226 close(dpio_dev->epoll_fd);
231 dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev)
236 /* Set the Stashing Destination */
237 cpu_id = dpaa2_get_core_id();
239 DPAA2_BUS_ERR("Thread not affined to a single core");
243 /* Set the STASH Destination depending on Current CPU ID.
244 * Valid values of SDEST are 4,5,6,7. Where,
246 sdest = dpaa2_core_cluster_sdest(cpu_id);
247 DPAA2_BUS_DEBUG("Portal= %d CPU= %u SDEST= %d",
248 dpio_dev->index, cpu_id, sdest);
250 ret = dpio_set_stashing_destination(dpio_dev->dpio, CMD_PRI_LOW,
251 dpio_dev->token, sdest);
253 DPAA2_BUS_ERR("%d ERROR in SDEST", ret);
257 #ifdef RTE_LIBRTE_PMD_DPAA2_EVENTDEV
258 if (dpaa2_dpio_intr_init(dpio_dev, cpu_id)) {
259 DPAA2_BUS_ERR("Interrupt registration failed for dpio");
267 static void dpaa2_put_qbman_swp(struct dpaa2_dpio_dev *dpio_dev)
270 #ifdef RTE_LIBRTE_PMD_DPAA2_EVENTDEV
271 dpaa2_dpio_intr_deinit(dpio_dev);
273 rte_atomic16_clear(&dpio_dev->ref_count);
277 static struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void)
279 struct dpaa2_dpio_dev *dpio_dev = NULL;
282 /* Get DPIO dev handle from list using index */
283 TAILQ_FOREACH(dpio_dev, &dpio_dev_list, next) {
284 if (dpio_dev && rte_atomic16_test_and_set(&dpio_dev->ref_count))
288 DPAA2_BUS_ERR("No software portal resource left");
292 DPAA2_BUS_DEBUG("New Portal %p (%d) affined thread - %lu",
293 dpio_dev, dpio_dev->index, syscall(SYS_gettid));
295 ret = dpaa2_configure_stashing(dpio_dev);
297 DPAA2_BUS_ERR("dpaa2_configure_stashing failed");
298 rte_atomic16_clear(&dpio_dev->ref_count);
302 ret = pthread_setspecific(dpaa2_portal_key, (void *)dpio_dev);
304 DPAA2_BUS_ERR("pthread_setspecific failed with ret: %d", ret);
305 dpaa2_put_qbman_swp(dpio_dev);
313 dpaa2_affine_qbman_swp(void)
315 struct dpaa2_dpio_dev *dpio_dev;
316 uint64_t tid = syscall(SYS_gettid);
318 /* Populate the dpaa2_io_portal structure */
319 if (!RTE_PER_LCORE(_dpaa2_io).dpio_dev) {
320 dpio_dev = dpaa2_get_qbman_swp();
322 DPAA2_BUS_ERR("Error in software portal allocation");
325 RTE_PER_LCORE(_dpaa2_io).dpio_dev = dpio_dev;
328 "DPAA Portal=%p (%d) is affined to thread %" PRIu64,
329 dpio_dev, dpio_dev->index, tid);
335 dpaa2_affine_qbman_ethrx_swp(void)
337 struct dpaa2_dpio_dev *dpio_dev;
338 uint64_t tid = syscall(SYS_gettid);
340 /* Populate the dpaa2_io_portal structure */
341 if (!RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev) {
342 dpio_dev = dpaa2_get_qbman_swp();
344 DPAA2_BUS_ERR("Error in software portal allocation");
347 RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev = dpio_dev;
350 "DPAA Portal=%p (%d) is affined for eth rx to thread %"
351 PRIu64, dpio_dev, dpio_dev->index, tid);
356 static void dpaa2_portal_finish(void *arg)
360 dpaa2_put_qbman_swp(RTE_PER_LCORE(_dpaa2_io).dpio_dev);
361 dpaa2_put_qbman_swp(RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev);
363 pthread_setspecific(dpaa2_portal_key, NULL);
367 * This checks for not supported lcore mappings as well as get the physical
368 * cpuid for the lcore.
369 * one lcore can only map to 1 cpu i.e. 1@10-14 not supported.
370 * one cpu can be mapped to more than one lcores.
373 dpaa2_check_lcore_cpuset(void)
375 unsigned int lcore_id, i;
378 for (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++)
379 dpaa2_cpu[lcore_id] = 0xffffffff;
381 for (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {
382 rte_cpuset_t cpuset = rte_lcore_cpuset(lcore_id);
384 for (i = 0; i < CPU_SETSIZE; i++) {
385 if (!CPU_ISSET(i, &cpuset))
387 if (i >= RTE_MAX_LCORE) {
388 DPAA2_BUS_ERR("ERR:lcore map to core %u (>= %u) not supported",
393 RTE_LOG(DEBUG, EAL, "lcore id = %u cpu=%u\n",
395 if (dpaa2_cpu[lcore_id] != 0xffffffff) {
396 DPAA2_BUS_ERR("ERR:lcore map to multi-cpu not supported");
400 dpaa2_cpu[lcore_id] = i;
407 dpaa2_create_dpio_device(int vdev_fd,
408 struct vfio_device_info *obj_info,
411 struct dpaa2_dpio_dev *dpio_dev = NULL;
412 struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)};
413 struct qbman_swp_desc p_des;
414 struct dpio_attr attr;
416 static int check_lcore_cpuset;
418 if (obj_info->num_regions < NUM_DPIO_REGIONS) {
419 DPAA2_BUS_ERR("Not sufficient number of DPIO regions");
423 dpio_dev = rte_zmalloc(NULL, sizeof(struct dpaa2_dpio_dev),
424 RTE_CACHE_LINE_SIZE);
426 DPAA2_BUS_ERR("Memory allocation failed for DPIO Device");
430 dpio_dev->dpio = NULL;
431 dpio_dev->hw_id = object_id;
432 rte_atomic16_init(&dpio_dev->ref_count);
433 /* Using single portal for all devices */
434 dpio_dev->mc_portal = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
436 if (!check_lcore_cpuset) {
437 check_lcore_cpuset = 1;
439 if (dpaa2_check_lcore_cpuset() < 0)
443 dpio_dev->dpio = rte_zmalloc(NULL, sizeof(struct fsl_mc_io),
444 RTE_CACHE_LINE_SIZE);
445 if (!dpio_dev->dpio) {
446 DPAA2_BUS_ERR("Memory allocation failure");
450 dpio_dev->dpio->regs = dpio_dev->mc_portal;
451 if (dpio_open(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->hw_id,
453 DPAA2_BUS_ERR("Failed to allocate IO space");
457 if (dpio_reset(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
458 DPAA2_BUS_ERR("Failed to reset dpio");
462 if (dpio_enable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
463 DPAA2_BUS_ERR("Failed to Enable dpio");
467 if (dpio_get_attributes(dpio_dev->dpio, CMD_PRI_LOW,
468 dpio_dev->token, &attr)) {
469 DPAA2_BUS_ERR("DPIO Get attribute failed");
473 /* find the SoC type for the first time */
474 if (!dpaa2_svr_family) {
475 struct mc_soc_version mc_plat_info = {0};
477 if (mc_get_soc_version(dpio_dev->dpio,
478 CMD_PRI_LOW, &mc_plat_info)) {
479 DPAA2_BUS_ERR("Unable to get SoC version information");
480 } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LS1080A) {
481 dpaa2_core_cluster_base = 0x02;
482 dpaa2_cluster_sz = 4;
483 DPAA2_BUS_DEBUG("LS108x (A53) Platform Detected");
484 } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LX2160A) {
485 dpaa2_core_cluster_base = 0x00;
486 dpaa2_cluster_sz = 2;
487 DPAA2_BUS_DEBUG("LX2160 Platform Detected");
489 dpaa2_svr_family = (mc_plat_info.svr & 0xffff0000);
491 if (dpaa2_svr_family == SVR_LX2160A) {
492 dpaa2_dqrr_size = DPAA2_LX2_DQRR_RING_SIZE;
493 dpaa2_eqcr_size = DPAA2_LX2_EQCR_RING_SIZE;
495 dpaa2_dqrr_size = DPAA2_DQRR_RING_SIZE;
496 dpaa2_eqcr_size = DPAA2_EQCR_RING_SIZE;
500 if (dpaa2_svr_family == SVR_LX2160A)
501 reg_info.index = DPAA2_SWP_CENA_MEM_REGION;
503 reg_info.index = DPAA2_SWP_CENA_REGION;
505 if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
506 DPAA2_BUS_ERR("vfio: error getting region info");
510 dpio_dev->ce_size = reg_info.size;
511 dpio_dev->qbman_portal_ce_paddr = (size_t)mmap(NULL, reg_info.size,
512 PROT_WRITE | PROT_READ, MAP_SHARED,
513 vdev_fd, reg_info.offset);
515 reg_info.index = DPAA2_SWP_CINH_REGION;
516 if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
517 DPAA2_BUS_ERR("vfio: error getting region info");
521 dpio_dev->ci_size = reg_info.size;
522 dpio_dev->qbman_portal_ci_paddr = (size_t)mmap(NULL, reg_info.size,
523 PROT_WRITE | PROT_READ, MAP_SHARED,
524 vdev_fd, reg_info.offset);
526 /* Configure & setup SW portal */
528 p_des.idx = attr.qbman_portal_id;
529 p_des.cena_bar = (void *)(dpio_dev->qbman_portal_ce_paddr);
530 p_des.cinh_bar = (void *)(dpio_dev->qbman_portal_ci_paddr);
532 p_des.qman_version = attr.qbman_version;
533 p_des.eqcr_mode = qman_eqcr_vb_ring;
534 p_des.cena_access_mode = qman_cena_fastest_access;
536 dpio_dev->sw_portal = qbman_swp_init(&p_des);
537 if (dpio_dev->sw_portal == NULL) {
538 DPAA2_BUS_ERR("QBMan SW Portal Init failed");
543 dpio_dev->index = io_space_count;
545 if (rte_dpaa2_vfio_setup_intr(&dpio_dev->intr_handle, vdev_fd, 1)) {
546 DPAA2_BUS_ERR("Fail to setup interrupt for %d",
551 dpio_dev->eqresp = rte_zmalloc(NULL, MAX_EQ_RESP_ENTRIES *
552 (sizeof(struct qbman_result) +
553 sizeof(struct eqresp_metadata)),
554 RTE_CACHE_LINE_SIZE);
555 if (!dpio_dev->eqresp) {
556 DPAA2_BUS_ERR("Memory allocation failed for eqresp");
559 dpio_dev->eqresp_meta = (struct eqresp_metadata *)(dpio_dev->eqresp +
560 MAX_EQ_RESP_ENTRIES);
563 TAILQ_INSERT_TAIL(&dpio_dev_list, dpio_dev, next);
565 if (!dpaa2_portal_key) {
566 /* create the key, supplying a function that'll be invoked
567 * when a portal affined thread will be deleted.
569 ret = pthread_key_create(&dpaa2_portal_key,
570 dpaa2_portal_finish);
572 DPAA2_BUS_DEBUG("Unable to create pthread key (%d)",
581 if (dpio_dev->dpio) {
582 dpio_disable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
583 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
584 rte_free(dpio_dev->eqresp);
585 rte_free(dpio_dev->dpio);
590 /* For each element in the list, cleanup */
591 TAILQ_FOREACH(dpio_dev, &dpio_dev_list, next) {
592 if (dpio_dev->dpio) {
593 dpio_disable(dpio_dev->dpio, CMD_PRI_LOW,
595 dpio_close(dpio_dev->dpio, CMD_PRI_LOW,
597 rte_free(dpio_dev->dpio);
602 /* Preventing re-use of the list with old entries */
603 TAILQ_INIT(&dpio_dev_list);
609 dpaa2_free_dq_storage(struct queue_storage_info_t *q_storage)
613 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
614 if (q_storage->dq_storage[i])
615 rte_free(q_storage->dq_storage[i]);
620 dpaa2_alloc_dq_storage(struct queue_storage_info_t *q_storage)
624 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
625 q_storage->dq_storage[i] = rte_malloc(NULL,
626 dpaa2_dqrr_size * sizeof(struct qbman_result),
627 RTE_CACHE_LINE_SIZE);
628 if (!q_storage->dq_storage[i])
634 rte_free(q_storage->dq_storage[i]);
640 dpaa2_free_eq_descriptors(void)
642 struct dpaa2_dpio_dev *dpio_dev = DPAA2_PER_LCORE_DPIO;
643 struct qbman_result *eqresp;
644 struct eqresp_metadata *eqresp_meta;
645 struct dpaa2_queue *txq;
647 while (dpio_dev->eqresp_ci != dpio_dev->eqresp_pi) {
648 eqresp = &dpio_dev->eqresp[dpio_dev->eqresp_ci];
649 eqresp_meta = &dpio_dev->eqresp_meta[dpio_dev->eqresp_ci];
651 if (!qbman_result_eqresp_rspid(eqresp))
654 if (qbman_result_eqresp_rc(eqresp)) {
655 txq = eqresp_meta->dpaa2_q;
656 txq->cb_eqresp_free(dpio_dev->eqresp_ci);
658 qbman_result_eqresp_set_rspid(eqresp, 0);
660 dpio_dev->eqresp_ci + 1 < MAX_EQ_RESP_ENTRIES ?
661 dpio_dev->eqresp_ci++ : (dpio_dev->eqresp_ci = 0);
664 /* Return 1 less entry so that PI and CI are never same in a
665 * case there all the EQ responses are in use.
667 if (dpio_dev->eqresp_ci > dpio_dev->eqresp_pi)
668 return dpio_dev->eqresp_ci - dpio_dev->eqresp_pi - 1;
670 return dpio_dev->eqresp_ci - dpio_dev->eqresp_pi +
671 MAX_EQ_RESP_ENTRIES - 1;
674 static struct rte_dpaa2_object rte_dpaa2_dpio_obj = {
675 .dev_type = DPAA2_IO,
676 .create = dpaa2_create_dpio_device,
679 RTE_PMD_REGISTER_DPAA2_OBJECT(dpio, rte_dpaa2_dpio_obj);