4 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
5 * Copyright (c) 2016 NXP. All rights reserved.
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21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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43 #include <sys/types.h>
44 #include <sys/queue.h>
45 #include <sys/ioctl.h>
48 #include <sys/syscall.h>
51 #include <rte_ethdev.h>
52 #include <rte_malloc.h>
53 #include <rte_memcpy.h>
54 #include <rte_string_fns.h>
55 #include <rte_cycles.h>
56 #include <rte_kvargs.h>
58 #include <rte_ethdev.h>
60 #include <fslmc_logs.h>
61 #include <fslmc_vfio.h>
62 #include "dpaa2_hw_pvt.h"
63 #include "dpaa2_hw_dpio.h"
65 #define NUM_HOST_CPUS RTE_MAX_LCORE
67 struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE];
68 RTE_DEFINE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io);
70 struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP];
72 TAILQ_HEAD(dpio_dev_list, dpaa2_dpio_dev);
73 static struct dpio_dev_list dpio_dev_list
74 = TAILQ_HEAD_INITIALIZER(dpio_dev_list); /*!< DPIO device list */
75 static uint32_t io_space_count;
77 /*Stashing Macros default for LS208x*/
78 static int dpaa2_core_cluster_base = 0x04;
79 static int dpaa2_cluster_sz = 2;
81 /* For LS208X platform There are four clusters with following mapping:
82 * Cluster 1 (ID = x04) : CPU0, CPU1;
83 * Cluster 2 (ID = x05) : CPU2, CPU3;
84 * Cluster 3 (ID = x06) : CPU4, CPU5;
85 * Cluster 4 (ID = x07) : CPU6, CPU7;
87 /* For LS108X platform There are two clusters with following mapping:
88 * Cluster 1 (ID = x02) : CPU0, CPU1, CPU2, CPU3;
89 * Cluster 2 (ID = x03) : CPU4, CPU5, CPU6, CPU7;
92 /* Set the STASH Destination depending on Current CPU ID.
93 * e.g. Valid values of SDEST are 4,5,6,7. Where,
94 * CPU 0-1 will have SDEST 4
95 * CPU 2-3 will have SDEST 5.....and so on.
98 dpaa2_core_cluster_sdest(int cpu_id)
100 int x = cpu_id / dpaa2_cluster_sz;
105 return dpaa2_core_cluster_base + x;
109 configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev)
111 struct qbman_swp_desc p_des;
112 struct dpio_attr attr;
114 dpio_dev->dpio = malloc(sizeof(struct fsl_mc_io));
115 if (!dpio_dev->dpio) {
116 PMD_INIT_LOG(ERR, "Memory allocation failure\n");
120 PMD_DRV_LOG(DEBUG, "\t Allocated DPIO Portal[%p]", dpio_dev->dpio);
121 dpio_dev->dpio->regs = dpio_dev->mc_portal;
122 if (dpio_open(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->hw_id,
124 PMD_INIT_LOG(ERR, "Failed to allocate IO space\n");
125 free(dpio_dev->dpio);
129 if (dpio_reset(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
130 PMD_INIT_LOG(ERR, "Failed to reset dpio\n");
131 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
132 free(dpio_dev->dpio);
136 if (dpio_enable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
137 PMD_INIT_LOG(ERR, "Failed to Enable dpio\n");
138 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
139 free(dpio_dev->dpio);
143 if (dpio_get_attributes(dpio_dev->dpio, CMD_PRI_LOW,
144 dpio_dev->token, &attr)) {
145 PMD_INIT_LOG(ERR, "DPIO Get attribute failed\n");
146 dpio_disable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
147 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
148 free(dpio_dev->dpio);
152 PMD_INIT_LOG(DEBUG, "Qbman Portal ID %d", attr.qbman_portal_id);
153 PMD_INIT_LOG(DEBUG, "Portal CE adr 0x%lX", attr.qbman_portal_ce_offset);
154 PMD_INIT_LOG(DEBUG, "Portal CI adr 0x%lX", attr.qbman_portal_ci_offset);
156 /* Configure & setup SW portal */
158 p_des.idx = attr.qbman_portal_id;
159 p_des.cena_bar = (void *)(dpio_dev->qbman_portal_ce_paddr);
160 p_des.cinh_bar = (void *)(dpio_dev->qbman_portal_ci_paddr);
162 p_des.qman_version = attr.qbman_version;
164 dpio_dev->sw_portal = qbman_swp_init(&p_des);
165 if (dpio_dev->sw_portal == NULL) {
166 PMD_DRV_LOG(ERR, " QBMan SW Portal Init failed\n");
167 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
168 free(dpio_dev->dpio);
172 PMD_INIT_LOG(DEBUG, "QBMan SW Portal 0x%p\n", dpio_dev->sw_portal);
178 dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev)
183 /* Set the Stashing Destination */
184 cpu_id = rte_lcore_id();
186 cpu_id = rte_get_master_lcore();
188 RTE_LOG(ERR, PMD, "\tGetting CPU Index failed\n");
192 /* Set the STASH Destination depending on Current CPU ID.
193 * Valid values of SDEST are 4,5,6,7. Where,
194 * CPU 0-1 will have SDEST 4
195 * CPU 2-3 will have SDEST 5.....and so on.
198 sdest = dpaa2_core_cluster_sdest(cpu_id);
199 PMD_DRV_LOG(DEBUG, "Portal= %d CPU= %u SDEST= %d",
200 dpio_dev->index, cpu_id, sdest);
202 ret = dpio_set_stashing_destination(dpio_dev->dpio, CMD_PRI_LOW,
203 dpio_dev->token, sdest);
205 PMD_DRV_LOG(ERR, "%d ERROR in SDEST\n", ret);
212 static inline struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void)
214 struct dpaa2_dpio_dev *dpio_dev = NULL;
217 /* Get DPIO dev handle from list using index */
218 TAILQ_FOREACH(dpio_dev, &dpio_dev_list, next) {
219 if (dpio_dev && rte_atomic16_test_and_set(&dpio_dev->ref_count))
225 PMD_DRV_LOG(DEBUG, "New Portal=0x%x (%d) affined thread - %lu",
226 dpio_dev, dpio_dev->index, syscall(SYS_gettid));
228 ret = dpaa2_configure_stashing(dpio_dev);
230 PMD_DRV_LOG(ERR, "dpaa2_configure_stashing failed");
236 dpaa2_affine_qbman_swp(void)
238 unsigned int lcore_id = rte_lcore_id();
239 uint64_t tid = syscall(SYS_gettid);
241 if (lcore_id == LCORE_ID_ANY)
242 lcore_id = rte_get_master_lcore();
243 /* if the core id is not supported */
244 else if (lcore_id >= RTE_MAX_LCORE)
247 if (dpaa2_io_portal[lcore_id].dpio_dev) {
248 PMD_DRV_LOG(INFO, "DPAA Portal=0x%x (%d) is being shared"
249 " between thread %lu and current %lu",
250 dpaa2_io_portal[lcore_id].dpio_dev,
251 dpaa2_io_portal[lcore_id].dpio_dev->index,
252 dpaa2_io_portal[lcore_id].net_tid,
254 RTE_PER_LCORE(_dpaa2_io).dpio_dev
255 = dpaa2_io_portal[lcore_id].dpio_dev;
256 rte_atomic16_inc(&dpaa2_io_portal
257 [lcore_id].dpio_dev->ref_count);
258 dpaa2_io_portal[lcore_id].net_tid = tid;
260 PMD_DRV_LOG(DEBUG, "Old Portal=0x%x (%d) affined thread - %lu",
261 dpaa2_io_portal[lcore_id].dpio_dev,
262 dpaa2_io_portal[lcore_id].dpio_dev->index,
267 /* Populate the dpaa2_io_portal structure */
268 dpaa2_io_portal[lcore_id].dpio_dev = dpaa2_get_qbman_swp();
270 if (dpaa2_io_portal[lcore_id].dpio_dev) {
271 RTE_PER_LCORE(_dpaa2_io).dpio_dev
272 = dpaa2_io_portal[lcore_id].dpio_dev;
273 dpaa2_io_portal[lcore_id].net_tid = tid;
282 dpaa2_affine_qbman_swp_sec(void)
284 unsigned int lcore_id = rte_lcore_id();
285 uint64_t tid = syscall(SYS_gettid);
287 if (lcore_id == LCORE_ID_ANY)
288 lcore_id = rte_get_master_lcore();
289 /* if the core id is not supported */
290 else if (lcore_id >= RTE_MAX_LCORE)
293 if (dpaa2_io_portal[lcore_id].sec_dpio_dev) {
294 PMD_DRV_LOG(INFO, "DPAA Portal=0x%x (%d) is being shared"
295 " between thread %lu and current %lu",
296 dpaa2_io_portal[lcore_id].sec_dpio_dev,
297 dpaa2_io_portal[lcore_id].sec_dpio_dev->index,
298 dpaa2_io_portal[lcore_id].sec_tid,
300 RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev
301 = dpaa2_io_portal[lcore_id].sec_dpio_dev;
302 rte_atomic16_inc(&dpaa2_io_portal
303 [lcore_id].sec_dpio_dev->ref_count);
304 dpaa2_io_portal[lcore_id].sec_tid = tid;
306 PMD_DRV_LOG(DEBUG, "Old Portal=0x%x (%d) affined thread - %lu",
307 dpaa2_io_portal[lcore_id].sec_dpio_dev,
308 dpaa2_io_portal[lcore_id].sec_dpio_dev->index,
313 /* Populate the dpaa2_io_portal structure */
314 dpaa2_io_portal[lcore_id].sec_dpio_dev = dpaa2_get_qbman_swp();
316 if (dpaa2_io_portal[lcore_id].sec_dpio_dev) {
317 RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev
318 = dpaa2_io_portal[lcore_id].sec_dpio_dev;
319 dpaa2_io_portal[lcore_id].sec_tid = tid;
327 dpaa2_create_dpio_device(struct fslmc_vfio_device *vdev,
328 struct vfio_device_info *obj_info,
331 struct dpaa2_dpio_dev *dpio_dev;
332 struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)};
334 if (obj_info->num_regions < NUM_DPIO_REGIONS) {
335 PMD_INIT_LOG(ERR, "ERROR, Not sufficient number "
336 "of DPIO regions.\n");
340 dpio_dev = rte_malloc(NULL, sizeof(struct dpaa2_dpio_dev),
341 RTE_CACHE_LINE_SIZE);
343 PMD_INIT_LOG(ERR, "Memory allocation failed for DPIO Device\n");
347 PMD_DRV_LOG(INFO, "\t Aloocated DPIO [%p]", dpio_dev);
348 dpio_dev->dpio = NULL;
349 dpio_dev->hw_id = object_id;
350 dpio_dev->vfio_fd = vdev->fd;
351 rte_atomic16_init(&dpio_dev->ref_count);
352 /* Using single portal for all devices */
353 dpio_dev->mc_portal = rte_mcp_ptr_list[MC_PORTAL_INDEX];
356 if (ioctl(dpio_dev->vfio_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
357 PMD_INIT_LOG(ERR, "vfio: error getting region info\n");
362 PMD_DRV_LOG(DEBUG, "\t Region Offset = %llx", reg_info.offset);
363 PMD_DRV_LOG(DEBUG, "\t Region Size = %llx", reg_info.size);
364 dpio_dev->ce_size = reg_info.size;
365 dpio_dev->qbman_portal_ce_paddr = (uint64_t)mmap(NULL, reg_info.size,
366 PROT_WRITE | PROT_READ, MAP_SHARED,
367 dpio_dev->vfio_fd, reg_info.offset);
369 /* Create Mapping for QBMan Cache Enabled area. This is a fix for
370 * SMMU fault for DQRR statshing transaction.
372 if (vfio_dmamap_mem_region(dpio_dev->qbman_portal_ce_paddr,
373 reg_info.offset, reg_info.size)) {
374 PMD_INIT_LOG(ERR, "DMAMAP for Portal CE area failed.\n");
380 if (ioctl(dpio_dev->vfio_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
381 PMD_INIT_LOG(ERR, "vfio: error getting region info\n");
386 PMD_DRV_LOG(DEBUG, "\t Region Offset = %llx", reg_info.offset);
387 PMD_DRV_LOG(DEBUG, "\t Region Size = %llx", reg_info.size);
388 dpio_dev->ci_size = reg_info.size;
389 dpio_dev->qbman_portal_ci_paddr = (uint64_t)mmap(NULL, reg_info.size,
390 PROT_WRITE | PROT_READ, MAP_SHARED,
391 dpio_dev->vfio_fd, reg_info.offset);
393 if (configure_dpio_qbman_swp(dpio_dev)) {
395 "Fail to configure the dpio qbman portal for %d\n",
402 dpio_dev->index = io_space_count;
403 TAILQ_INSERT_TAIL(&dpio_dev_list, dpio_dev, next);
404 PMD_INIT_LOG(DEBUG, "DPAA2:Added [dpio-%d]", object_id);
410 dpaa2_free_dq_storage(struct queue_storage_info_t *q_storage)
414 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
415 if (q_storage->dq_storage[i])
416 rte_free(q_storage->dq_storage[i]);
421 dpaa2_alloc_dq_storage(struct queue_storage_info_t *q_storage)
425 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
426 q_storage->dq_storage[i] = rte_malloc(NULL,
427 DPAA2_DQRR_RING_SIZE * sizeof(struct qbman_result),
428 RTE_CACHE_LINE_SIZE);
429 if (!q_storage->dq_storage[i])
436 rte_free(q_storage->dq_storage[i]);