1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_COMMON_H_
6 #define RTE_PMD_MLX5_COMMON_H_
12 #include <rte_atomic.h>
14 #include <rte_kvargs.h>
15 #include <rte_devargs.h>
21 * Helper macros to work around __VA_ARGS__ limitations in a C99 compliant
24 #define PMD_DRV_LOG_STRIP(a, b) a
25 #define PMD_DRV_LOG_OPAREN (
26 #define PMD_DRV_LOG_CPAREN )
27 #define PMD_DRV_LOG_COMMA ,
29 /* Return the file name part of a path. */
30 static inline const char *
31 pmd_drv_log_basename(const char *s)
41 #define PMD_DRV_LOG___(level, type, name, ...) \
42 rte_log(RTE_LOG_ ## level, \
45 RTE_FMT_HEAD(__VA_ARGS__,), \
46 RTE_FMT_TAIL(__VA_ARGS__,)))
49 * When debugging is enabled (NDEBUG not defined), file, line and function
50 * information replace the driver name (MLX5_DRIVER_NAME) in log messages.
54 #define PMD_DRV_LOG__(level, type, name, ...) \
55 PMD_DRV_LOG___(level, type, name, "%s:%u: %s(): " __VA_ARGS__)
56 #define PMD_DRV_LOG_(level, type, name, s, ...) \
57 PMD_DRV_LOG__(level, type, name,\
58 s "\n" PMD_DRV_LOG_COMMA \
59 pmd_drv_log_basename(__FILE__) PMD_DRV_LOG_COMMA \
60 __LINE__ PMD_DRV_LOG_COMMA \
65 #define PMD_DRV_LOG__(level, type, name, ...) \
66 PMD_DRV_LOG___(level, type, name, __VA_ARGS__)
67 #define PMD_DRV_LOG_(level, type, name, s, ...) \
68 PMD_DRV_LOG__(level, type, name, s "\n", __VA_ARGS__)
72 /* claim_zero() does not perform any check when debugging is disabled. */
75 #define DEBUG(...) DRV_LOG(DEBUG, __VA_ARGS__)
76 #define claim_zero(...) assert((__VA_ARGS__) == 0)
77 #define claim_nonzero(...) assert((__VA_ARGS__) != 0)
81 #define DEBUG(...) (void)0
82 #define claim_zero(...) (__VA_ARGS__)
83 #define claim_nonzero(...) (__VA_ARGS__)
87 /* Allocate a buffer on the stack and fill it with a printf format string. */
88 #define MKSTR(name, ...) \
89 int mkstr_size_##name = snprintf(NULL, 0, "" __VA_ARGS__); \
90 char name[mkstr_size_##name + 1]; \
92 snprintf(name, sizeof(name), "" __VA_ARGS__)
95 PCI_VENDOR_ID_MELLANOX = 0x15b3,
99 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
100 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
101 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
102 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
103 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
104 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
105 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
106 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
107 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
108 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
109 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
110 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
111 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d,
112 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF = 0x101e,
116 enum mlx5_cqe_status {
117 MLX5_CQE_STATUS_SW_OWN = -1,
118 MLX5_CQE_STATUS_HW_OWN = -2,
119 MLX5_CQE_STATUS_ERR = -3,
123 * Check whether CQE is valid.
128 * Size of completion queue.
135 static __rte_always_inline enum mlx5_cqe_status
136 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n,
139 const uint16_t idx = ci & cqes_n;
140 const uint8_t op_own = cqe->op_own;
141 const uint8_t op_owner = MLX5_CQE_OWNER(op_own);
142 const uint8_t op_code = MLX5_CQE_OPCODE(op_own);
144 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
145 return MLX5_CQE_STATUS_HW_OWN;
147 if (unlikely(op_code == MLX5_CQE_RESP_ERR ||
148 op_code == MLX5_CQE_REQ_ERR))
149 return MLX5_CQE_STATUS_ERR;
150 return MLX5_CQE_STATUS_SW_OWN;
153 int mlx5_dev_to_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr);
155 #define MLX5_CLASS_ARG_NAME "class"
162 enum mlx5_class mlx5_class_get(struct rte_devargs *devargs);
164 #endif /* RTE_PMD_MLX5_COMMON_H_ */