drivers/common/mlx5/mlx5_devx_cmds.c

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /* Copyright 2018 Mellanox Technologies, Ltd */
   3
   4 #include <unistd.h>
   5
   6 #include <rte_errno.h>
   7 #include <rte_malloc.h>
   8
   9 #include "mlx5_prm.h"
  10 #include "mlx5_devx_cmds.h"
  11 #include "mlx5_common_utils.h"
  12
  13
  14 /**
  15  * Allocate flow counters via devx interface.
  16  *
  17  * @param[in] ctx
  18  *   ibv contexts returned from mlx5dv_open_device.
  19  * @param dcs
  20  *   Pointer to counters properties structure to be filled by the routine.
  21  * @param bulk_n_128
  22  *   Bulk counter numbers in 128 counters units.
  23  *
  24  * @return
  25  *   Pointer to counter object on success, a negative value otherwise and
  26  *   rte_errno is set.
  27  */
  28 struct mlx5_devx_obj *
  29 mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx, uint32_t bulk_n_128)
  30 {
  31         struct mlx5_devx_obj *dcs = rte_zmalloc("dcs", sizeof(*dcs), 0);
  32         uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)]   = {0};
  33         uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
  34
  35         if (!dcs) {
  36                 rte_errno = ENOMEM;
  37                 return NULL;
  38         }
  39         MLX5_SET(alloc_flow_counter_in, in, opcode,
  40                  MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
  41         MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
  42         dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
  43                                               sizeof(in), out, sizeof(out));
  44         if (!dcs->obj) {
  45                 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
  46                 rte_errno = errno;
  47                 rte_free(dcs);
  48                 return NULL;
  49         }
  50         dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
  51         return dcs;
  52 }
  53
  54 /**
  55  * Query flow counters values.
  56  *
  57  * @param[in] dcs
  58  *   devx object that was obtained from mlx5_devx_cmd_fc_alloc.
  59  * @param[in] clear
  60  *   Whether hardware should clear the counters after the query or not.
  61  * @param[in] n_counters
  62  *   0 in case of 1 counter to read, otherwise the counter number to read.
  63  *  @param pkts
  64  *   The number of packets that matched the flow.
  65  *  @param bytes
  66  *    The number of bytes that matched the flow.
  67  *  @param mkey
  68  *   The mkey key for batch query.
  69  *  @param addr
  70  *    The address in the mkey range for batch query.
  71  *  @param cmd_comp
  72  *   The completion object for asynchronous batch query.
  73  *  @param async_id
  74  *    The ID to be returned in the asynchronous batch query response.
  75  *
  76  * @return
  77  *   0 on success, a negative value otherwise.
  78  */
  79 int
  80 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
  81                                  int clear, uint32_t n_counters,
  82                                  uint64_t *pkts, uint64_t *bytes,
  83                                  uint32_t mkey, void *addr,
  84                                  struct mlx5dv_devx_cmd_comp *cmd_comp,
  85                                  uint64_t async_id)
  86 {
  87         int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
  88                         MLX5_ST_SZ_BYTES(traffic_counter);
  89         uint32_t out[out_len];
  90         uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
  91         void *stats;
  92         int rc;
  93
  94         MLX5_SET(query_flow_counter_in, in, opcode,
  95                  MLX5_CMD_OP_QUERY_FLOW_COUNTER);
  96         MLX5_SET(query_flow_counter_in, in, op_mod, 0);
  97         MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
  98         MLX5_SET(query_flow_counter_in, in, clear, !!clear);
  99
 100         if (n_counters) {
 101                 MLX5_SET(query_flow_counter_in, in, num_of_counters,
 102                          n_counters);
 103                 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
 104                 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
 105                 MLX5_SET64(query_flow_counter_in, in, address,
 106                            (uint64_t)(uintptr_t)addr);
 107         }
 108         if (!cmd_comp)
 109                 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
 110                                                out_len);
 111         else
 112                 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
 113                                                      out_len, async_id,
 114                                                      cmd_comp);
 115         if (rc) {
 116                 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
 117                 rte_errno = rc;
 118                 return -rc;
 119         }
 120         if (!n_counters) {
 121                 stats = MLX5_ADDR_OF(query_flow_counter_out,
 122                                      out, flow_statistics);
 123                 *pkts = MLX5_GET64(traffic_counter, stats, packets);
 124                 *bytes = MLX5_GET64(traffic_counter, stats, octets);
 125         }
 126         return 0;
 127 }
 128
 129 /**
 130  * Create a new mkey.
 131  *
 132  * @param[in] ctx
 133  *   ibv contexts returned from mlx5dv_open_device.
 134  * @param[in] attr
 135  *   Attributes of the requested mkey.
 136  *
 137  * @return
 138  *   Pointer to Devx mkey on success, a negative value otherwise and rte_errno
 139  *   is set.
 140  */
 141 struct mlx5_devx_obj *
 142 mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
 143                           struct mlx5_devx_mkey_attr *attr)
 144 {
 145         struct mlx5_klm *klm_array = attr->klm_array;
 146         int klm_num = attr->klm_num;
 147         int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
 148                      (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
 149         uint32_t in[in_size_dw];
 150         uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
 151         void *mkc;
 152         struct mlx5_devx_obj *mkey = rte_zmalloc("mkey", sizeof(*mkey), 0);
 153         size_t pgsize;
 154         uint32_t translation_size;
 155
 156         if (!mkey) {
 157                 rte_errno = ENOMEM;
 158                 return NULL;
 159         }
 160         memset(in, 0, in_size_dw * 4);
 161         pgsize = sysconf(_SC_PAGESIZE);
 162         MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
 163         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 164         if (klm_num > 0) {
 165                 int i;
 166                 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
 167                                                        klm_pas_mtt);
 168                 translation_size = RTE_ALIGN(klm_num, 4);
 169                 for (i = 0; i < klm_num; i++) {
 170                         MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
 171                         MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
 172                         MLX5_SET64(klm, klm, address, klm_array[i].address);
 173                         klm += MLX5_ST_SZ_BYTES(klm);
 174                 }
 175                 for (; i < (int)translation_size; i++) {
 176                         MLX5_SET(klm, klm, mkey, 0x0);
 177                         MLX5_SET64(klm, klm, address, 0x0);
 178                         klm += MLX5_ST_SZ_BYTES(klm);
 179                 }
 180                 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
 181                          MLX5_MKC_ACCESS_MODE_KLM_FBS :
 182                          MLX5_MKC_ACCESS_MODE_KLM);
 183                 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
 184         } else {
 185                 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
 186                 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 187                 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
 188         }
 189         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 190                  translation_size);
 191         MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
 192         MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
 193         MLX5_SET(mkc, mkc, lw, 0x1);
 194         MLX5_SET(mkc, mkc, lr, 0x1);
 195         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 196         MLX5_SET(mkc, mkc, pd, attr->pd);
 197         MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
 198         MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
 199         MLX5_SET64(mkc, mkc, start_addr, attr->addr);
 200         MLX5_SET64(mkc, mkc, len, attr->size);
 201         mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
 202                                                sizeof(out));
 203         if (!mkey->obj) {
 204                 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d\n",
 205                         klm_num ? "an in" : "a ", errno);
 206                 rte_errno = errno;
 207                 rte_free(mkey);
 208                 return NULL;
 209         }
 210         mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
 211         mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
 212         return mkey;
 213 }
 214
 215 /**
 216  * Get status of devx command response.
 217  * Mainly used for asynchronous commands.
 218  *
 219  * @param[in] out
 220  *   The out response buffer.
 221  *
 222  * @return
 223  *   0 on success, non-zero value otherwise.
 224  */
 225 int
 226 mlx5_devx_get_out_command_status(void *out)
 227 {
 228         int status;
 229
 230         if (!out)
 231                 return -EINVAL;
 232         status = MLX5_GET(query_flow_counter_out, out, status);
 233         if (status) {
 234                 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
 235
 236                 DRV_LOG(ERR, "Bad devX status %x, syndrome = %x", status,
 237                         syndrome);
 238         }
 239         return status;
 240 }
 241
 242 /**
 243  * Destroy any object allocated by a Devx API.
 244  *
 245  * @param[in] obj
 246  *   Pointer to a general object.
 247  *
 248  * @return
 249  *   0 on success, a negative value otherwise.
 250  */
 251 int
 252 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
 253 {
 254         int ret;
 255
 256         if (!obj)
 257                 return 0;
 258         ret =  mlx5_glue->devx_obj_destroy(obj->obj);
 259         rte_free(obj);
 260         return ret;
 261 }
 262
 263 /**
 264  * Query NIC vport context.
 265  * Fills minimal inline attribute.
 266  *
 267  * @param[in] ctx
 268  *   ibv contexts returned from mlx5dv_open_device.
 269  * @param[in] vport
 270  *   vport index
 271  * @param[out] attr
 272  *   Attributes device values.
 273  *
 274  * @return
 275  *   0 on success, a negative value otherwise.
 276  */
 277 static int
 278 mlx5_devx_cmd_query_nic_vport_context(struct ibv_context *ctx,
 279                                       unsigned int vport,
 280                                       struct mlx5_hca_attr *attr)
 281 {
 282         uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
 283         uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
 284         void *vctx;
 285         int status, syndrome, rc;
 286
 287         /* Query NIC vport context to determine inline mode. */
 288         MLX5_SET(query_nic_vport_context_in, in, opcode,
 289                  MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
 290         MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
 291         if (vport)
 292                 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
 293         rc = mlx5_glue->devx_general_cmd(ctx,
 294                                          in, sizeof(in),
 295                                          out, sizeof(out));
 296         if (rc)
 297                 goto error;
 298         status = MLX5_GET(query_nic_vport_context_out, out, status);
 299         syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
 300         if (status) {
 301                 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
 302                         "status %x, syndrome = %x",
 303                         status, syndrome);
 304                 return -1;
 305         }
 306         vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
 307                             nic_vport_context);
 308         attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
 309                                            min_wqe_inline_mode);
 310         return 0;
 311 error:
 312         rc = (rc > 0) ? -rc : rc;
 313         return rc;
 314 }
 315
 316 /**
 317  * Query NIC vDPA attributes.
 318  *
 319  * @param[in] ctx
 320  *   ibv contexts returned from mlx5dv_open_device.
 321  * @param[out] vdpa_attr
 322  *   vDPA Attributes structure to fill.
 323  */
 324 static void
 325 mlx5_devx_cmd_query_hca_vdpa_attr(struct ibv_context *ctx,
 326                                   struct mlx5_hca_vdpa_attr *vdpa_attr)
 327 {
 328         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 329         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 330         void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 331         int status, syndrome, rc;
 332
 333         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 334         MLX5_SET(query_hca_cap_in, in, op_mod,
 335                  MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
 336                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 337         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 338         status = MLX5_GET(query_hca_cap_out, out, status);
 339         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 340         if (rc || status) {
 341                 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities,"
 342                         " status %x, syndrome = %x", status, syndrome);
 343                 vdpa_attr->valid = 0;
 344         } else {
 345                 vdpa_attr->valid = 1;
 346                 vdpa_attr->desc_tunnel_offload_type =
 347                         MLX5_GET(virtio_emulation_cap, hcattr,
 348                                  desc_tunnel_offload_type);
 349                 vdpa_attr->eth_frame_offload_type =
 350                         MLX5_GET(virtio_emulation_cap, hcattr,
 351                                  eth_frame_offload_type);
 352                 vdpa_attr->virtio_version_1_0 =
 353                         MLX5_GET(virtio_emulation_cap, hcattr,
 354                                  virtio_version_1_0);
 355                 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
 356                                                tso_ipv4);
 357                 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
 358                                                tso_ipv6);
 359                 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 360                                               tx_csum);
 361                 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 362                                               rx_csum);
 363                 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
 364                                                  event_mode);
 365                 vdpa_attr->virtio_queue_type =
 366                         MLX5_GET(virtio_emulation_cap, hcattr,
 367                                  virtio_queue_type);
 368                 vdpa_attr->log_doorbell_stride =
 369                         MLX5_GET(virtio_emulation_cap, hcattr,
 370                                  log_doorbell_stride);
 371                 vdpa_attr->log_doorbell_bar_size =
 372                         MLX5_GET(virtio_emulation_cap, hcattr,
 373                                  log_doorbell_bar_size);
 374                 vdpa_attr->doorbell_bar_offset =
 375                         MLX5_GET64(virtio_emulation_cap, hcattr,
 376                                    doorbell_bar_offset);
 377                 vdpa_attr->max_num_virtio_queues =
 378                         MLX5_GET(virtio_emulation_cap, hcattr,
 379                                  max_num_virtio_queues);
 380                 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
 381                                                  umem_1_buffer_param_a);
 382                 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
 383                                                  umem_1_buffer_param_b);
 384                 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
 385                                                  umem_2_buffer_param_a);
 386                 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
 387                                                  umem_2_buffer_param_b);
 388                 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
 389                                                  umem_3_buffer_param_a);
 390                 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
 391                                                  umem_3_buffer_param_b);
 392         }
 393 }
 394
 395 /**
 396  * Query HCA attributes.
 397  * Using those attributes we can check on run time if the device
 398  * is having the required capabilities.
 399  *
 400  * @param[in] ctx
 401  *   ibv contexts returned from mlx5dv_open_device.
 402  * @param[out] attr
 403  *   Attributes device values.
 404  *
 405  * @return
 406  *   0 on success, a negative value otherwise.
 407  */
 408 int
 409 mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
 410                              struct mlx5_hca_attr *attr)
 411 {
 412         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 413         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 414         void *hcattr;
 415         int status, syndrome, rc;
 416
 417         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 418         MLX5_SET(query_hca_cap_in, in, op_mod,
 419                  MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
 420                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 421
 422         rc = mlx5_glue->devx_general_cmd(ctx,
 423                                          in, sizeof(in), out, sizeof(out));
 424         if (rc)
 425                 goto error;
 426         status = MLX5_GET(query_hca_cap_out, out, status);
 427         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 428         if (status) {
 429                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 430                         "status %x, syndrome = %x",
 431                         status, syndrome);
 432                 return -1;
 433         }
 434         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 435         attr->flow_counter_bulk_alloc_bitmap =
 436                         MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
 437         attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
 438                                             flow_counters_dump);
 439         attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
 440         attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
 441         attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
 442                                                 log_max_hairpin_queues);
 443         attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
 444                                                     log_max_hairpin_wq_data_sz);
 445         attr->log_max_hairpin_num_packets = MLX5_GET
 446                 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
 447         attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
 448         attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
 449                                           eth_net_offloads);
 450         attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
 451         attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
 452                                                flex_parser_protocols);
 453         attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
 454         attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 455                                          general_obj_types) &
 456                               MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
 457         if (attr->qos.sup) {
 458                 MLX5_SET(query_hca_cap_in, in, op_mod,
 459                          MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
 460                          MLX5_HCA_CAP_OPMOD_GET_CUR);
 461                 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
 462                                                  out, sizeof(out));
 463                 if (rc)
 464                         goto error;
 465                 if (status) {
 466                         DRV_LOG(DEBUG, "Failed to query devx QOS capabilities,"
 467                                 " status %x, syndrome = %x",
 468                                 status, syndrome);
 469                         return -1;
 470                 }
 471                 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 472                 attr->qos.srtcm_sup =
 473                                 MLX5_GET(qos_cap, hcattr, flow_meter_srtcm);
 474                 attr->qos.log_max_flow_meter =
 475                                 MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
 476                 attr->qos.flow_meter_reg_c_ids =
 477                         MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
 478                 attr->qos.flow_meter_reg_share =
 479                         MLX5_GET(qos_cap, hcattr, flow_meter_reg_share);
 480         }
 481         if (attr->vdpa.valid)
 482                 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
 483         if (!attr->eth_net_offloads)
 484                 return 0;
 485
 486         /* Query HCA offloads for Ethernet protocol. */
 487         memset(in, 0, sizeof(in));
 488         memset(out, 0, sizeof(out));
 489         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 490         MLX5_SET(query_hca_cap_in, in, op_mod,
 491                  MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
 492                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 493
 494         rc = mlx5_glue->devx_general_cmd(ctx,
 495                                          in, sizeof(in),
 496                                          out, sizeof(out));
 497         if (rc) {
 498                 attr->eth_net_offloads = 0;
 499                 goto error;
 500         }
 501         status = MLX5_GET(query_hca_cap_out, out, status);
 502         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 503         if (status) {
 504                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 505                         "status %x, syndrome = %x",
 506                         status, syndrome);
 507                 attr->eth_net_offloads = 0;
 508                 return -1;
 509         }
 510         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 511         attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
 512                                          hcattr, wqe_vlan_insert);
 513         attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
 514                                  lro_cap);
 515         attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
 516                                         hcattr, tunnel_lro_gre);
 517         attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
 518                                           hcattr, tunnel_lro_vxlan);
 519         attr->lro_max_msg_sz_mode = MLX5_GET
 520                                         (per_protocol_networking_offload_caps,
 521                                          hcattr, lro_max_msg_sz_mode);
 522         for (int i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
 523                 attr->lro_timer_supported_periods[i] =
 524                         MLX5_GET(per_protocol_networking_offload_caps, hcattr,
 525                                  lro_timer_supported_periods[i]);
 526         }
 527         attr->tunnel_stateless_geneve_rx =
 528                             MLX5_GET(per_protocol_networking_offload_caps,
 529                                      hcattr, tunnel_stateless_geneve_rx);
 530         attr->geneve_max_opt_len =
 531                     MLX5_GET(per_protocol_networking_offload_caps,
 532                              hcattr, max_geneve_opt_len);
 533         attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
 534                                          hcattr, wqe_inline_mode);
 535         attr->tunnel_stateless_gtp = MLX5_GET
 536                                         (per_protocol_networking_offload_caps,
 537                                          hcattr, tunnel_stateless_gtp);
 538         if (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
 539                 return 0;
 540         if (attr->eth_virt) {
 541                 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
 542                 if (rc) {
 543                         attr->eth_virt = 0;
 544                         goto error;
 545                 }
 546         }
 547         return 0;
 548 error:
 549         rc = (rc > 0) ? -rc : rc;
 550         return rc;
 551 }
 552
 553 /**
 554  * Query TIS transport domain from QP verbs object using DevX API.
 555  *
 556  * @param[in] qp
 557  *   Pointer to verbs QP returned by ibv_create_qp .
 558  * @param[in] tis_num
 559  *   TIS number of TIS to query.
 560  * @param[out] tis_td
 561  *   Pointer to TIS transport domain variable, to be set by the routine.
 562  *
 563  * @return
 564  *   0 on success, a negative value otherwise.
 565  */
 566 int
 567 mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
 568                               uint32_t *tis_td)
 569 {
 570         uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
 571         uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
 572         int rc;
 573         void *tis_ctx;
 574
 575         MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
 576         MLX5_SET(query_tis_in, in, tisn, tis_num);
 577         rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
 578         if (rc) {
 579                 DRV_LOG(ERR, "Failed to query QP using DevX");
 580                 return -rc;
 581         };
 582         tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
 583         *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
 584         return 0;
 585 }
 586
 587 /**
 588  * Fill WQ data for DevX API command.
 589  * Utility function for use when creating DevX objects containing a WQ.
 590  *
 591  * @param[in] wq_ctx
 592  *   Pointer to WQ context to fill with data.
 593  * @param [in] wq_attr
 594  *   Pointer to WQ attributes structure to fill in WQ context.
 595  */
 596 static void
 597 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
 598 {
 599         MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
 600         MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
 601         MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
 602         MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
 603         MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
 604         MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
 605         MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
 606         MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
 607         MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
 608         MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
 609         MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
 610         MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
 611         MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
 612         MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
 613         MLX5_SET(wq, wq_ctx, log_wq_pg_sz, wq_attr->log_wq_pg_sz);
 614         MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
 615         MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
 616         MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
 617         MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
 618                  wq_attr->log_hairpin_num_packets);
 619         MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
 620         MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
 621                  wq_attr->single_wqe_log_num_of_strides);
 622         MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
 623         MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
 624                  wq_attr->single_stride_log_num_of_bytes);
 625         MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
 626         MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
 627         MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
 628 }
 629
 630 /**
 631  * Create RQ using DevX API.
 632  *
 633  * @param[in] ctx
 634  *   ibv_context returned from mlx5dv_open_device.
 635  * @param [in] rq_attr
 636  *   Pointer to create RQ attributes structure.
 637  * @param [in] socket
 638  *   CPU socket ID for allocations.
 639  *
 640  * @return
 641  *   The DevX object created, NULL otherwise and rte_errno is set.
 642  */
 643 struct mlx5_devx_obj *
 644 mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
 645                         struct mlx5_devx_create_rq_attr *rq_attr,
 646                         int socket)
 647 {
 648         uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
 649         uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
 650         void *rq_ctx, *wq_ctx;
 651         struct mlx5_devx_wq_attr *wq_attr;
 652         struct mlx5_devx_obj *rq = NULL;
 653
 654         rq = rte_calloc_socket(__func__, 1, sizeof(*rq), 0, socket);
 655         if (!rq) {
 656                 DRV_LOG(ERR, "Failed to allocate RQ data");
 657                 rte_errno = ENOMEM;
 658                 return NULL;
 659         }
 660         MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
 661         rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
 662         MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
 663         MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
 664         MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
 665         MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
 666         MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
 667         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
 668         MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
 669         MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
 670         MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
 671         MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
 672         MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
 673         MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
 674         wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
 675         wq_attr = &rq_attr->wq_attr;
 676         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
 677         rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
 678                                                   out, sizeof(out));
 679         if (!rq->obj) {
 680                 DRV_LOG(ERR, "Failed to create RQ using DevX");
 681                 rte_errno = errno;
 682                 rte_free(rq);
 683                 return NULL;
 684         }
 685         rq->id = MLX5_GET(create_rq_out, out, rqn);
 686         return rq;
 687 }
 688
 689 /**
 690  * Modify RQ using DevX API.
 691  *
 692  * @param[in] rq
 693  *   Pointer to RQ object structure.
 694  * @param [in] rq_attr
 695  *   Pointer to modify RQ attributes structure.
 696  *
 697  * @return
 698  *   0 on success, a negative errno value otherwise and rte_errno is set.
 699  */
 700 int
 701 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
 702                         struct mlx5_devx_modify_rq_attr *rq_attr)
 703 {
 704         uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
 705         uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
 706         void *rq_ctx, *wq_ctx;
 707         int ret;
 708
 709         MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
 710         MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
 711         MLX5_SET(modify_rq_in, in, rqn, rq->id);
 712         MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
 713         rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 714         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
 715         if (rq_attr->modify_bitmask &
 716                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
 717                 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
 718         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
 719                 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
 720         if (rq_attr->modify_bitmask &
 721                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
 722                 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
 723         MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
 724         MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
 725         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
 726                 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
 727                 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
 728         }
 729         ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
 730                                          out, sizeof(out));
 731         if (ret) {
 732                 DRV_LOG(ERR, "Failed to modify RQ using DevX");
 733                 rte_errno = errno;
 734                 return -errno;
 735         }
 736         return ret;
 737 }
 738
 739 /**
 740  * Create TIR using DevX API.
 741  *
 742  * @param[in] ctx
 743  *   ibv_context returned from mlx5dv_open_device.
 744  * @param [in] tir_attr
 745  *   Pointer to TIR attributes structure.
 746  *
 747  * @return
 748  *   The DevX object created, NULL otherwise and rte_errno is set.
 749  */
 750 struct mlx5_devx_obj *
 751 mlx5_devx_cmd_create_tir(struct ibv_context *ctx,
 752                          struct mlx5_devx_tir_attr *tir_attr)
 753 {
 754         uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
 755         uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
 756         void *tir_ctx, *outer, *inner;
 757         struct mlx5_devx_obj *tir = NULL;
 758         int i;
 759
 760         tir = rte_calloc(__func__, 1, sizeof(*tir), 0);
 761         if (!tir) {
 762                 DRV_LOG(ERR, "Failed to allocate TIR data");
 763                 rte_errno = ENOMEM;
 764                 return NULL;
 765         }
 766         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
 767         tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
 768         MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
 769         MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
 770                  tir_attr->lro_timeout_period_usecs);
 771         MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
 772         MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
 773         MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
 774         MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
 775         MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
 776                  tir_attr->tunneled_offload_en);
 777         MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
 778         MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
 779         MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
 780         MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
 781         for (i = 0; i < 10; i++) {
 782                 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
 783                          tir_attr->rx_hash_toeplitz_key[i]);
 784         }
 785         outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
 786         MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
 787                  tir_attr->rx_hash_field_selector_outer.l3_prot_type);
 788         MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
 789                  tir_attr->rx_hash_field_selector_outer.l4_prot_type);
 790         MLX5_SET(rx_hash_field_select, outer, selected_fields,
 791                  tir_attr->rx_hash_field_selector_outer.selected_fields);
 792         inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
 793         MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
 794                  tir_attr->rx_hash_field_selector_inner.l3_prot_type);
 795         MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
 796                  tir_attr->rx_hash_field_selector_inner.l4_prot_type);
 797         MLX5_SET(rx_hash_field_select, inner, selected_fields,
 798                  tir_attr->rx_hash_field_selector_inner.selected_fields);
 799         tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
 800                                                    out, sizeof(out));
 801         if (!tir->obj) {
 802                 DRV_LOG(ERR, "Failed to create TIR using DevX");
 803                 rte_errno = errno;
 804                 rte_free(tir);
 805                 return NULL;
 806         }
 807         tir->id = MLX5_GET(create_tir_out, out, tirn);
 808         return tir;
 809 }
 810
 811 /**
 812  * Create RQT using DevX API.
 813  *
 814  * @param[in] ctx
 815  *   ibv_context returned from mlx5dv_open_device.
 816  * @param [in] rqt_attr
 817  *   Pointer to RQT attributes structure.
 818  *
 819  * @return
 820  *   The DevX object created, NULL otherwise and rte_errno is set.
 821  */
 822 struct mlx5_devx_obj *
 823 mlx5_devx_cmd_create_rqt(struct ibv_context *ctx,
 824                          struct mlx5_devx_rqt_attr *rqt_attr)
 825 {
 826         uint32_t *in = NULL;
 827         uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
 828                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
 829         uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
 830         void *rqt_ctx;
 831         struct mlx5_devx_obj *rqt = NULL;
 832         int i;
 833
 834         in = rte_calloc(__func__, 1, inlen, 0);
 835         if (!in) {
 836                 DRV_LOG(ERR, "Failed to allocate RQT IN data");
 837                 rte_errno = ENOMEM;
 838                 return NULL;
 839         }
 840         rqt = rte_calloc(__func__, 1, sizeof(*rqt), 0);
 841         if (!rqt) {
 842                 DRV_LOG(ERR, "Failed to allocate RQT data");
 843                 rte_errno = ENOMEM;
 844                 rte_free(in);
 845                 return NULL;
 846         }
 847         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
 848         rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
 849         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
 850         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
 851         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
 852         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
 853                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
 854         rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
 855         rte_free(in);
 856         if (!rqt->obj) {
 857                 DRV_LOG(ERR, "Failed to create RQT using DevX");
 858                 rte_errno = errno;
 859                 rte_free(rqt);
 860                 return NULL;
 861         }
 862         rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
 863         return rqt;
 864 }
 865
 866 /**
 867  * Modify RQT using DevX API.
 868  *
 869  * @param[in] rqt
 870  *   Pointer to RQT DevX object structure.
 871  * @param [in] rqt_attr
 872  *   Pointer to RQT attributes structure.
 873  *
 874  * @return
 875  *   0 on success, a negative errno value otherwise and rte_errno is set.
 876  */
 877 int
 878 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
 879                          struct mlx5_devx_rqt_attr *rqt_attr)
 880 {
 881         uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) +
 882                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
 883         uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
 884         uint32_t *in = rte_calloc(__func__, 1, inlen, 0);
 885         void *rqt_ctx;
 886         int i;
 887         int ret;
 888
 889         if (!in) {
 890                 DRV_LOG(ERR, "Failed to allocate RQT modify IN data.");
 891                 rte_errno = ENOMEM;
 892                 return -ENOMEM;
 893         }
 894         MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
 895         MLX5_SET(modify_rqt_in, in, rqtn, rqt->id);
 896         MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1);
 897         rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context);
 898         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
 899         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
 900         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
 901         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
 902                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
 903         ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out));
 904         rte_free(in);
 905         if (ret) {
 906                 DRV_LOG(ERR, "Failed to modify RQT using DevX.");
 907                 rte_errno = errno;
 908                 return -rte_errno;
 909         }
 910         return ret;
 911 }
 912
 913 /**
 914  * Create SQ using DevX API.
 915  *
 916  * @param[in] ctx
 917  *   ibv_context returned from mlx5dv_open_device.
 918  * @param [in] sq_attr
 919  *   Pointer to SQ attributes structure.
 920  * @param [in] socket
 921  *   CPU socket ID for allocations.
 922  *
 923  * @return
 924  *   The DevX object created, NULL otherwise and rte_errno is set.
 925  **/
 926 struct mlx5_devx_obj *
 927 mlx5_devx_cmd_create_sq(struct ibv_context *ctx,
 928                         struct mlx5_devx_create_sq_attr *sq_attr)
 929 {
 930         uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
 931         uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
 932         void *sq_ctx;
 933         void *wq_ctx;
 934         struct mlx5_devx_wq_attr *wq_attr;
 935         struct mlx5_devx_obj *sq = NULL;
 936
 937         sq = rte_calloc(__func__, 1, sizeof(*sq), 0);
 938         if (!sq) {
 939                 DRV_LOG(ERR, "Failed to allocate SQ data");
 940                 rte_errno = ENOMEM;
 941                 return NULL;
 942         }
 943         MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
 944         sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
 945         MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
 946         MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
 947         MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
 948         MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
 949         MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
 950                  sq_attr->flush_in_error_en);
 951         MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
 952                  sq_attr->min_wqe_inline_mode);
 953         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
 954         MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
 955         MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
 956         MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
 957         MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
 958         MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
 959         MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
 960                  sq_attr->packet_pacing_rate_limit_index);
 961         MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
 962         MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
 963         wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
 964         wq_attr = &sq_attr->wq_attr;
 965         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
 966         sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
 967                                              out, sizeof(out));
 968         if (!sq->obj) {
 969                 DRV_LOG(ERR, "Failed to create SQ using DevX");
 970                 rte_errno = errno;
 971                 rte_free(sq);
 972                 return NULL;
 973         }
 974         sq->id = MLX5_GET(create_sq_out, out, sqn);
 975         return sq;
 976 }
 977
 978 /**
 979  * Modify SQ using DevX API.
 980  *
 981  * @param[in] sq
 982  *   Pointer to SQ object structure.
 983  * @param [in] sq_attr
 984  *   Pointer to SQ attributes structure.
 985  *
 986  * @return
 987  *   0 on success, a negative errno value otherwise and rte_errno is set.
 988  */
 989 int
 990 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
 991                         struct mlx5_devx_modify_sq_attr *sq_attr)
 992 {
 993         uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
 994         uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
 995         void *sq_ctx;
 996         int ret;
 997
 998         MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
 999         MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
1000         MLX5_SET(modify_sq_in, in, sqn, sq->id);
1001         sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1002         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1003         MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
1004         MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
1005         ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
1006                                          out, sizeof(out));
1007         if (ret) {
1008                 DRV_LOG(ERR, "Failed to modify SQ using DevX");
1009                 rte_errno = errno;
1010                 return -errno;
1011         }
1012         return ret;
1013 }
1014
1015 /**
1016  * Create TIS using DevX API.
1017  *
1018  * @param[in] ctx
1019  *   ibv_context returned from mlx5dv_open_device.
1020  * @param [in] tis_attr
1021  *   Pointer to TIS attributes structure.
1022  *
1023  * @return
1024  *   The DevX object created, NULL otherwise and rte_errno is set.
1025  */
1026 struct mlx5_devx_obj *
1027 mlx5_devx_cmd_create_tis(struct ibv_context *ctx,
1028                          struct mlx5_devx_tis_attr *tis_attr)
1029 {
1030         uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1031         uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
1032         struct mlx5_devx_obj *tis = NULL;
1033         void *tis_ctx;
1034
1035         tis = rte_calloc(__func__, 1, sizeof(*tis), 0);
1036         if (!tis) {
1037                 DRV_LOG(ERR, "Failed to allocate TIS object");
1038                 rte_errno = ENOMEM;
1039                 return NULL;
1040         }
1041         MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
1042         tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
1043         MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
1044                  tis_attr->strict_lag_tx_port_affinity);
1045         MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
1046                  tis_attr->strict_lag_tx_port_affinity);
1047         MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
1048         MLX5_SET(tisc, tis_ctx, transport_domain,
1049                  tis_attr->transport_domain);
1050         tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1051                                               out, sizeof(out));
1052         if (!tis->obj) {
1053                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1054                 rte_errno = errno;
1055                 rte_free(tis);
1056                 return NULL;
1057         }
1058         tis->id = MLX5_GET(create_tis_out, out, tisn);
1059         return tis;
1060 }
1061
1062 /**
1063  * Create transport domain using DevX API.
1064  *
1065  * @param[in] ctx
1066  *   ibv_context returned from mlx5dv_open_device.
1067  *
1068  * @return
1069  *   The DevX object created, NULL otherwise and rte_errno is set.
1070  */
1071 struct mlx5_devx_obj *
1072 mlx5_devx_cmd_create_td(struct ibv_context *ctx)
1073 {
1074         uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
1075         uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
1076         struct mlx5_devx_obj *td = NULL;
1077
1078         td = rte_calloc(__func__, 1, sizeof(*td), 0);
1079         if (!td) {
1080                 DRV_LOG(ERR, "Failed to allocate TD object");
1081                 rte_errno = ENOMEM;
1082                 return NULL;
1083         }
1084         MLX5_SET(alloc_transport_domain_in, in, opcode,
1085                  MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
1086         td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1087                                              out, sizeof(out));
1088         if (!td->obj) {
1089                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1090                 rte_errno = errno;
1091                 rte_free(td);
1092                 return NULL;
1093         }
1094         td->id = MLX5_GET(alloc_transport_domain_out, out,
1095                            transport_domain);
1096         return td;
1097 }
1098
1099 /**
1100  * Dump all flows to file.
1101  *
1102  * @param[in] fdb_domain
1103  *   FDB domain.
1104  * @param[in] rx_domain
1105  *   RX domain.
1106  * @param[in] tx_domain
1107  *   TX domain.
1108  * @param[out] file
1109  *   Pointer to file stream.
1110  *
1111  * @return
1112  *   0 on success, a nagative value otherwise.
1113  */
1114 int
1115 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
1116                         void *rx_domain __rte_unused,
1117                         void *tx_domain __rte_unused, FILE *file __rte_unused)
1118 {
1119         int ret = 0;
1120
1121 #ifdef HAVE_MLX5_DR_FLOW_DUMP
1122         if (fdb_domain) {
1123                 ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
1124                 if (ret)
1125                         return ret;
1126         }
1127         assert(rx_domain);
1128         ret = mlx5_glue->dr_dump_domain(file, rx_domain);
1129         if (ret)
1130                 return ret;
1131         assert(tx_domain);
1132         ret = mlx5_glue->dr_dump_domain(file, tx_domain);
1133 #else
1134         ret = ENOTSUP;
1135 #endif
1136         return -ret;
1137 }
1138
1139 /*
1140  * Create CQ using DevX API.
1141  *
1142  * @param[in] ctx
1143  *   ibv_context returned from mlx5dv_open_device.
1144  * @param [in] attr
1145  *   Pointer to CQ attributes structure.
1146  *
1147  * @return
1148  *   The DevX object created, NULL otherwise and rte_errno is set.
1149  */
1150 struct mlx5_devx_obj *
1151 mlx5_devx_cmd_create_cq(struct ibv_context *ctx, struct mlx5_devx_cq_attr *attr)
1152 {
1153         uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
1154         uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
1155         struct mlx5_devx_obj *cq_obj = rte_zmalloc(__func__, sizeof(*cq_obj),
1156                                                    0);
1157         void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1158
1159         if (!cq_obj) {
1160                 DRV_LOG(ERR, "Failed to allocate CQ object memory.");
1161                 rte_errno = ENOMEM;
1162                 return NULL;
1163         }
1164         MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
1165         if (attr->db_umem_valid) {
1166                 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
1167                 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
1168                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
1169         } else {
1170                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
1171         }
1172         MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
1173         MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
1174         MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
1175         MLX5_SET(cqc, cqctx, log_page_size, attr->log_page_size -
1176                  MLX5_ADAPTER_PAGE_SHIFT);
1177         MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
1178         MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
1179         if (attr->q_umem_valid) {
1180                 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
1181                 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
1182                 MLX5_SET64(create_cq_in, in, cq_umem_offset,
1183                            attr->q_umem_offset);
1184         }
1185         cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1186                                                  sizeof(out));
1187         if (!cq_obj->obj) {
1188                 rte_errno = errno;
1189                 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno);
1190                 rte_free(cq_obj);
1191                 return NULL;
1192         }
1193         cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
1194         return cq_obj;
1195 }
1196
1197 /**
1198  * Create VIRTQ using DevX API.
1199  *
1200  * @param[in] ctx
1201  *   ibv_context returned from mlx5dv_open_device.
1202  * @param [in] attr
1203  *   Pointer to VIRTQ attributes structure.
1204  *
1205  * @return
1206  *   The DevX object created, NULL otherwise and rte_errno is set.
1207  */
1208 struct mlx5_devx_obj *
1209 mlx5_devx_cmd_create_virtq(struct ibv_context *ctx,
1210                            struct mlx5_devx_virtq_attr *attr)
1211 {
1212         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1213         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1214         struct mlx5_devx_obj *virtq_obj = rte_zmalloc(__func__,
1215                                                      sizeof(*virtq_obj), 0);
1216         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1217         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1218         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1219
1220         if (!virtq_obj) {
1221                 DRV_LOG(ERR, "Failed to allocate virtq data.");
1222                 rte_errno = ENOMEM;
1223                 return NULL;
1224         }
1225         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1226                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
1227         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1228                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1229         MLX5_SET16(virtio_net_q, virtq, hw_available_index,
1230                    attr->hw_available_index);
1231         MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
1232         MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
1233         MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
1234         MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
1235         MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
1236         MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
1237                    attr->virtio_version_1_0);
1238         MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
1239         MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
1240         MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
1241         MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
1242         MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
1243         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1244         MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
1245         MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
1246         MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
1247         MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
1248         MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
1249         MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
1250         MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
1251         MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
1252         MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
1253         MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
1254         MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
1255         MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
1256         virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1257                                                     sizeof(out));
1258         if (!virtq_obj->obj) {
1259                 rte_errno = errno;
1260                 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX.");
1261                 rte_free(virtq_obj);
1262                 return NULL;
1263         }
1264         virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
1265         return virtq_obj;
1266 }
1267
1268 /**
1269  * Modify VIRTQ using DevX API.
1270  *
1271  * @param[in] virtq_obj
1272  *   Pointer to virtq object structure.
1273  * @param [in] attr
1274  *   Pointer to modify virtq attributes structure.
1275  *
1276  * @return
1277  *   0 on success, a negative errno value otherwise and rte_errno is set.
1278  */
1279 int
1280 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
1281                            struct mlx5_devx_virtq_attr *attr)
1282 {
1283         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1284         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1285         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1286         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1287         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1288         int ret;
1289
1290         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1291                  MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
1292         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1293                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1294         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1295         MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type);
1296         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1297         switch (attr->type) {
1298         case MLX5_VIRTQ_MODIFY_TYPE_STATE:
1299                 MLX5_SET16(virtio_net_q, virtq, state, attr->state);
1300                 break;
1301         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS:
1302                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
1303                          attr->dirty_bitmap_mkey);
1304                 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
1305                          attr->dirty_bitmap_addr);
1306                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
1307                          attr->dirty_bitmap_size);
1308                 break;
1309         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE:
1310                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
1311                          attr->dirty_bitmap_dump_enable);
1312                 break;
1313         default:
1314                 rte_errno = EINVAL;
1315                 return -rte_errno;
1316         }
1317         ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
1318                                          out, sizeof(out));
1319         if (ret) {
1320                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1321                 rte_errno = errno;
1322                 return -errno;
1323         }
1324         return ret;
1325 }
1326
1327 /**
1328  * Query VIRTQ using DevX API.
1329  *
1330  * @param[in] virtq_obj
1331  *   Pointer to virtq object structure.
1332  * @param [in/out] attr
1333  *   Pointer to virtq attributes structure.
1334  *
1335  * @return
1336  *   0 on success, a negative errno value otherwise and rte_errno is set.
1337  */
1338 int
1339 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
1340                            struct mlx5_devx_virtq_attr *attr)
1341 {
1342         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
1343         uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
1344         void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
1345         void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
1346         int ret;
1347
1348         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1349                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
1350         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1351                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1352         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1353         ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
1354                                          out, sizeof(out));
1355         if (ret) {
1356                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1357                 rte_errno = errno;
1358                 return -errno;
1359         }
1360         attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
1361                                               hw_available_index);
1362         attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
1363         return ret;
1364 }
1365
1366 /**
1367  * Create QP using DevX API.
1368  *
1369  * @param[in] ctx
1370  *   ibv_context returned from mlx5dv_open_device.
1371  * @param [in] attr
1372  *   Pointer to QP attributes structure.
1373  *
1374  * @return
1375  *   The DevX object created, NULL otherwise and rte_errno is set.
1376  */
1377 struct mlx5_devx_obj *
1378 mlx5_devx_cmd_create_qp(struct ibv_context *ctx,
1379                         struct mlx5_devx_qp_attr *attr)
1380 {
1381         uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
1382         uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
1383         struct mlx5_devx_obj *qp_obj = rte_zmalloc(__func__, sizeof(*qp_obj),
1384                                                    0);
1385         void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1386
1387         if (!qp_obj) {
1388                 DRV_LOG(ERR, "Failed to allocate QP data.");
1389                 rte_errno = ENOMEM;
1390                 return NULL;
1391         }
1392         MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
1393         MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
1394         MLX5_SET(qpc, qpc, pd, attr->pd);
1395         if (attr->uar_index) {
1396                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1397                 MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
1398                 MLX5_SET(qpc, qpc, log_page_size, attr->log_page_size -
1399                          MLX5_ADAPTER_PAGE_SHIFT);
1400                 if (attr->sq_size) {
1401                         RTE_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size));
1402                         MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
1403                         MLX5_SET(qpc, qpc, log_sq_size,
1404                                  rte_log2_u32(attr->sq_size));
1405                 } else {
1406                         MLX5_SET(qpc, qpc, no_sq, 1);
1407                 }
1408                 if (attr->rq_size) {
1409                         RTE_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size));
1410                         MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
1411                         MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
1412                                  MLX5_LOG_RQ_STRIDE_SHIFT);
1413                         MLX5_SET(qpc, qpc, log_rq_size,
1414                                  rte_log2_u32(attr->rq_size));
1415                         MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
1416                 } else {
1417                         MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1418                 }
1419                 if (attr->dbr_umem_valid) {
1420                         MLX5_SET(qpc, qpc, dbr_umem_valid,
1421                                  attr->dbr_umem_valid);
1422                         MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
1423                 }
1424                 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
1425                 MLX5_SET64(create_qp_in, in, wq_umem_offset,
1426                            attr->wq_umem_offset);
1427                 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
1428                 MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
1429         } else {
1430                 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
1431                 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1432                 MLX5_SET(qpc, qpc, no_sq, 1);
1433         }
1434         qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1435                                                  sizeof(out));
1436         if (!qp_obj->obj) {
1437                 rte_errno = errno;
1438                 DRV_LOG(ERR, "Failed to create QP Obj using DevX.");
1439                 rte_free(qp_obj);
1440                 return NULL;
1441         }
1442         qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
1443         return qp_obj;
1444 }
1445
1446 /**
1447  * Modify QP using DevX API.
1448  * Currently supports only force loop-back QP.
1449  *
1450  * @param[in] qp
1451  *   Pointer to QP object structure.
1452  * @param [in] qp_st_mod_op
1453  *   The QP state modification operation.
1454  * @param [in] remote_qp_id
1455  *   The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
1456  *
1457  * @return
1458  *   0 on success, a negative errno value otherwise and rte_errno is set.
1459  */
1460 int
1461 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
1462                               uint32_t remote_qp_id)
1463 {
1464         union {
1465                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
1466                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
1467                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
1468         } in;
1469         union {
1470                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
1471                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
1472                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
1473         } out;
1474         void *qpc;
1475         int ret;
1476         unsigned int inlen;
1477         unsigned int outlen;
1478
1479         memset(&in, 0, sizeof(in));
1480         memset(&out, 0, sizeof(out));
1481         MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
1482         switch (qp_st_mod_op) {
1483         case MLX5_CMD_OP_RST2INIT_QP:
1484                 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
1485                 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
1486                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
1487                 MLX5_SET(qpc, qpc, rre, 1);
1488                 MLX5_SET(qpc, qpc, rwe, 1);
1489                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1490                 inlen = sizeof(in.rst2init);
1491                 outlen = sizeof(out.rst2init);
1492                 break;
1493         case MLX5_CMD_OP_INIT2RTR_QP:
1494                 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
1495                 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
1496                 MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
1497                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
1498                 MLX5_SET(qpc, qpc, mtu, 1);
1499                 MLX5_SET(qpc, qpc, log_msg_max, 30);
1500                 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
1501                 MLX5_SET(qpc, qpc, min_rnr_nak, 0);
1502                 inlen = sizeof(in.init2rtr);
1503                 outlen = sizeof(out.init2rtr);
1504                 break;
1505         case MLX5_CMD_OP_RTR2RTS_QP:
1506                 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
1507                 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
1508                 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14);
1509                 MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
1510                 MLX5_SET(qpc, qpc, retry_count, 7);
1511                 MLX5_SET(qpc, qpc, rnr_retry, 7);
1512                 inlen = sizeof(in.rtr2rts);
1513                 outlen = sizeof(out.rtr2rts);
1514                 break;
1515         default:
1516                 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
1517                         qp_st_mod_op);
1518                 rte_errno = EINVAL;
1519                 return -rte_errno;
1520         }
1521         ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
1522         if (ret) {
1523                 DRV_LOG(ERR, "Failed to modify QP using DevX.");
1524                 rte_errno = errno;
1525                 return -errno;
1526         }
1527         return ret;
1528 }