drivers/common/mlx5/mlx5_devx_cmds.c

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /* Copyright 2018 Mellanox Technologies, Ltd */
   3
   4 #include <unistd.h>
   5
   6 #include <rte_errno.h>
   7 #include <rte_malloc.h>
   8
   9 #include "mlx5_prm.h"
  10 #include "mlx5_devx_cmds.h"
  11 #include "mlx5_common_utils.h"
  12
  13
  14 /**
  15  * Allocate flow counters via devx interface.
  16  *
  17  * @param[in] ctx
  18  *   ibv contexts returned from mlx5dv_open_device.
  19  * @param dcs
  20  *   Pointer to counters properties structure to be filled by the routine.
  21  * @param bulk_n_128
  22  *   Bulk counter numbers in 128 counters units.
  23  *
  24  * @return
  25  *   Pointer to counter object on success, a negative value otherwise and
  26  *   rte_errno is set.
  27  */
  28 struct mlx5_devx_obj *
  29 mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx, uint32_t bulk_n_128)
  30 {
  31         struct mlx5_devx_obj *dcs = rte_zmalloc("dcs", sizeof(*dcs), 0);
  32         uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)]   = {0};
  33         uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
  34
  35         if (!dcs) {
  36                 rte_errno = ENOMEM;
  37                 return NULL;
  38         }
  39         MLX5_SET(alloc_flow_counter_in, in, opcode,
  40                  MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
  41         MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
  42         dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
  43                                               sizeof(in), out, sizeof(out));
  44         if (!dcs->obj) {
  45                 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
  46                 rte_errno = errno;
  47                 rte_free(dcs);
  48                 return NULL;
  49         }
  50         dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
  51         return dcs;
  52 }
  53
  54 /**
  55  * Query flow counters values.
  56  *
  57  * @param[in] dcs
  58  *   devx object that was obtained from mlx5_devx_cmd_fc_alloc.
  59  * @param[in] clear
  60  *   Whether hardware should clear the counters after the query or not.
  61  * @param[in] n_counters
  62  *   0 in case of 1 counter to read, otherwise the counter number to read.
  63  *  @param pkts
  64  *   The number of packets that matched the flow.
  65  *  @param bytes
  66  *    The number of bytes that matched the flow.
  67  *  @param mkey
  68  *   The mkey key for batch query.
  69  *  @param addr
  70  *    The address in the mkey range for batch query.
  71  *  @param cmd_comp
  72  *   The completion object for asynchronous batch query.
  73  *  @param async_id
  74  *    The ID to be returned in the asynchronous batch query response.
  75  *
  76  * @return
  77  *   0 on success, a negative value otherwise.
  78  */
  79 int
  80 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
  81                                  int clear, uint32_t n_counters,
  82                                  uint64_t *pkts, uint64_t *bytes,
  83                                  uint32_t mkey, void *addr,
  84                                  struct mlx5dv_devx_cmd_comp *cmd_comp,
  85                                  uint64_t async_id)
  86 {
  87         int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
  88                         MLX5_ST_SZ_BYTES(traffic_counter);
  89         uint32_t out[out_len];
  90         uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
  91         void *stats;
  92         int rc;
  93
  94         MLX5_SET(query_flow_counter_in, in, opcode,
  95                  MLX5_CMD_OP_QUERY_FLOW_COUNTER);
  96         MLX5_SET(query_flow_counter_in, in, op_mod, 0);
  97         MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
  98         MLX5_SET(query_flow_counter_in, in, clear, !!clear);
  99
 100         if (n_counters) {
 101                 MLX5_SET(query_flow_counter_in, in, num_of_counters,
 102                          n_counters);
 103                 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
 104                 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
 105                 MLX5_SET64(query_flow_counter_in, in, address,
 106                            (uint64_t)(uintptr_t)addr);
 107         }
 108         if (!cmd_comp)
 109                 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
 110                                                out_len);
 111         else
 112                 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
 113                                                      out_len, async_id,
 114                                                      cmd_comp);
 115         if (rc) {
 116                 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
 117                 rte_errno = rc;
 118                 return -rc;
 119         }
 120         if (!n_counters) {
 121                 stats = MLX5_ADDR_OF(query_flow_counter_out,
 122                                      out, flow_statistics);
 123                 *pkts = MLX5_GET64(traffic_counter, stats, packets);
 124                 *bytes = MLX5_GET64(traffic_counter, stats, octets);
 125         }
 126         return 0;
 127 }
 128
 129 /**
 130  * Create a new mkey.
 131  *
 132  * @param[in] ctx
 133  *   ibv contexts returned from mlx5dv_open_device.
 134  * @param[in] attr
 135  *   Attributes of the requested mkey.
 136  *
 137  * @return
 138  *   Pointer to Devx mkey on success, a negative value otherwise and rte_errno
 139  *   is set.
 140  */
 141 struct mlx5_devx_obj *
 142 mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
 143                           struct mlx5_devx_mkey_attr *attr)
 144 {
 145         struct mlx5_klm *klm_array = attr->klm_array;
 146         int klm_num = attr->klm_num;
 147         int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
 148                      (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
 149         uint32_t in[in_size_dw];
 150         uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
 151         void *mkc;
 152         struct mlx5_devx_obj *mkey = rte_zmalloc("mkey", sizeof(*mkey), 0);
 153         size_t pgsize;
 154         uint32_t translation_size;
 155
 156         if (!mkey) {
 157                 rte_errno = ENOMEM;
 158                 return NULL;
 159         }
 160         memset(in, 0, in_size_dw * 4);
 161         pgsize = sysconf(_SC_PAGESIZE);
 162         MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
 163         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 164         if (klm_num > 0) {
 165                 int i;
 166                 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
 167                                                        klm_pas_mtt);
 168                 translation_size = RTE_ALIGN(klm_num, 4);
 169                 for (i = 0; i < klm_num; i++) {
 170                         MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
 171                         MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
 172                         MLX5_SET64(klm, klm, address, klm_array[i].address);
 173                         klm += MLX5_ST_SZ_BYTES(klm);
 174                 }
 175                 for (; i < (int)translation_size; i++) {
 176                         MLX5_SET(klm, klm, mkey, 0x0);
 177                         MLX5_SET64(klm, klm, address, 0x0);
 178                         klm += MLX5_ST_SZ_BYTES(klm);
 179                 }
 180                 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
 181                          MLX5_MKC_ACCESS_MODE_KLM_FBS :
 182                          MLX5_MKC_ACCESS_MODE_KLM);
 183                 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
 184         } else {
 185                 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
 186                 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 187                 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
 188         }
 189         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 190                  translation_size);
 191         MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
 192         MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
 193         MLX5_SET(mkc, mkc, lw, 0x1);
 194         MLX5_SET(mkc, mkc, lr, 0x1);
 195         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 196         MLX5_SET(mkc, mkc, pd, attr->pd);
 197         MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
 198         MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
 199         MLX5_SET64(mkc, mkc, start_addr, attr->addr);
 200         MLX5_SET64(mkc, mkc, len, attr->size);
 201         mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
 202                                                sizeof(out));
 203         if (!mkey->obj) {
 204                 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d\n",
 205                         klm_num ? "an in" : "a ", errno);
 206                 rte_errno = errno;
 207                 rte_free(mkey);
 208                 return NULL;
 209         }
 210         mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
 211         mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
 212         return mkey;
 213 }
 214
 215 /**
 216  * Get status of devx command response.
 217  * Mainly used for asynchronous commands.
 218  *
 219  * @param[in] out
 220  *   The out response buffer.
 221  *
 222  * @return
 223  *   0 on success, non-zero value otherwise.
 224  */
 225 int
 226 mlx5_devx_get_out_command_status(void *out)
 227 {
 228         int status;
 229
 230         if (!out)
 231                 return -EINVAL;
 232         status = MLX5_GET(query_flow_counter_out, out, status);
 233         if (status) {
 234                 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
 235
 236                 DRV_LOG(ERR, "Bad devX status %x, syndrome = %x", status,
 237                         syndrome);
 238         }
 239         return status;
 240 }
 241
 242 /**
 243  * Destroy any object allocated by a Devx API.
 244  *
 245  * @param[in] obj
 246  *   Pointer to a general object.
 247  *
 248  * @return
 249  *   0 on success, a negative value otherwise.
 250  */
 251 int
 252 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
 253 {
 254         int ret;
 255
 256         if (!obj)
 257                 return 0;
 258         ret =  mlx5_glue->devx_obj_destroy(obj->obj);
 259         rte_free(obj);
 260         return ret;
 261 }
 262
 263 /**
 264  * Query NIC vport context.
 265  * Fills minimal inline attribute.
 266  *
 267  * @param[in] ctx
 268  *   ibv contexts returned from mlx5dv_open_device.
 269  * @param[in] vport
 270  *   vport index
 271  * @param[out] attr
 272  *   Attributes device values.
 273  *
 274  * @return
 275  *   0 on success, a negative value otherwise.
 276  */
 277 static int
 278 mlx5_devx_cmd_query_nic_vport_context(struct ibv_context *ctx,
 279                                       unsigned int vport,
 280                                       struct mlx5_hca_attr *attr)
 281 {
 282         uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
 283         uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
 284         void *vctx;
 285         int status, syndrome, rc;
 286
 287         /* Query NIC vport context to determine inline mode. */
 288         MLX5_SET(query_nic_vport_context_in, in, opcode,
 289                  MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
 290         MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
 291         if (vport)
 292                 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
 293         rc = mlx5_glue->devx_general_cmd(ctx,
 294                                          in, sizeof(in),
 295                                          out, sizeof(out));
 296         if (rc)
 297                 goto error;
 298         status = MLX5_GET(query_nic_vport_context_out, out, status);
 299         syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
 300         if (status) {
 301                 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
 302                         "status %x, syndrome = %x",
 303                         status, syndrome);
 304                 return -1;
 305         }
 306         vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
 307                             nic_vport_context);
 308         attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
 309                                            min_wqe_inline_mode);
 310         return 0;
 311 error:
 312         rc = (rc > 0) ? -rc : rc;
 313         return rc;
 314 }
 315
 316 /**
 317  * Query NIC vDPA attributes.
 318  *
 319  * @param[in] ctx
 320  *   ibv contexts returned from mlx5dv_open_device.
 321  * @param[out] vdpa_attr
 322  *   vDPA Attributes structure to fill.
 323  */
 324 static void
 325 mlx5_devx_cmd_query_hca_vdpa_attr(struct ibv_context *ctx,
 326                                   struct mlx5_hca_vdpa_attr *vdpa_attr)
 327 {
 328         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 329         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 330         void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 331         int status, syndrome, rc;
 332
 333         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 334         MLX5_SET(query_hca_cap_in, in, op_mod,
 335                  MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
 336                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 337         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 338         status = MLX5_GET(query_hca_cap_out, out, status);
 339         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 340         if (rc || status) {
 341                 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities,"
 342                         " status %x, syndrome = %x", status, syndrome);
 343                 vdpa_attr->valid = 0;
 344         } else {
 345                 vdpa_attr->valid = 1;
 346                 vdpa_attr->desc_tunnel_offload_type =
 347                         MLX5_GET(virtio_emulation_cap, hcattr,
 348                                  desc_tunnel_offload_type);
 349                 vdpa_attr->eth_frame_offload_type =
 350                         MLX5_GET(virtio_emulation_cap, hcattr,
 351                                  eth_frame_offload_type);
 352                 vdpa_attr->virtio_version_1_0 =
 353                         MLX5_GET(virtio_emulation_cap, hcattr,
 354                                  virtio_version_1_0);
 355                 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
 356                                                tso_ipv4);
 357                 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
 358                                                tso_ipv6);
 359                 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 360                                               tx_csum);
 361                 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 362                                               rx_csum);
 363                 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
 364                                                  event_mode);
 365                 vdpa_attr->virtio_queue_type =
 366                         MLX5_GET(virtio_emulation_cap, hcattr,
 367                                  virtio_queue_type);
 368                 vdpa_attr->log_doorbell_stride =
 369                         MLX5_GET(virtio_emulation_cap, hcattr,
 370                                  log_doorbell_stride);
 371                 vdpa_attr->log_doorbell_bar_size =
 372                         MLX5_GET(virtio_emulation_cap, hcattr,
 373                                  log_doorbell_bar_size);
 374                 vdpa_attr->doorbell_bar_offset =
 375                         MLX5_GET64(virtio_emulation_cap, hcattr,
 376                                    doorbell_bar_offset);
 377                 vdpa_attr->max_num_virtio_queues =
 378                         MLX5_GET(virtio_emulation_cap, hcattr,
 379                                  max_num_virtio_queues);
 380                 vdpa_attr->umem_1_buffer_param_a =
 381                         MLX5_GET(virtio_emulation_cap, hcattr,
 382                                  umem_1_buffer_param_a);
 383                 vdpa_attr->umem_1_buffer_param_b =
 384                         MLX5_GET(virtio_emulation_cap, hcattr,
 385                                  umem_1_buffer_param_b);
 386                 vdpa_attr->umem_2_buffer_param_a =
 387                         MLX5_GET(virtio_emulation_cap, hcattr,
 388                                  umem_2_buffer_param_a);
 389                 vdpa_attr->umem_2_buffer_param_b =
 390                         MLX5_GET(virtio_emulation_cap, hcattr,
 391                                  umem_2_buffer_param_a);
 392                 vdpa_attr->umem_3_buffer_param_a =
 393                         MLX5_GET(virtio_emulation_cap, hcattr,
 394                                  umem_3_buffer_param_a);
 395                 vdpa_attr->umem_3_buffer_param_b =
 396                         MLX5_GET(virtio_emulation_cap, hcattr,
 397                                  umem_3_buffer_param_b);
 398         }
 399 }
 400
 401 /**
 402  * Query HCA attributes.
 403  * Using those attributes we can check on run time if the device
 404  * is having the required capabilities.
 405  *
 406  * @param[in] ctx
 407  *   ibv contexts returned from mlx5dv_open_device.
 408  * @param[out] attr
 409  *   Attributes device values.
 410  *
 411  * @return
 412  *   0 on success, a negative value otherwise.
 413  */
 414 int
 415 mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
 416                              struct mlx5_hca_attr *attr)
 417 {
 418         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 419         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 420         void *hcattr;
 421         int status, syndrome, rc;
 422
 423         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 424         MLX5_SET(query_hca_cap_in, in, op_mod,
 425                  MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
 426                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 427
 428         rc = mlx5_glue->devx_general_cmd(ctx,
 429                                          in, sizeof(in), out, sizeof(out));
 430         if (rc)
 431                 goto error;
 432         status = MLX5_GET(query_hca_cap_out, out, status);
 433         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 434         if (status) {
 435                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 436                         "status %x, syndrome = %x",
 437                         status, syndrome);
 438                 return -1;
 439         }
 440         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 441         attr->flow_counter_bulk_alloc_bitmap =
 442                         MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
 443         attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
 444                                             flow_counters_dump);
 445         attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
 446         attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
 447         attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
 448                                                 log_max_hairpin_queues);
 449         attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
 450                                                     log_max_hairpin_wq_data_sz);
 451         attr->log_max_hairpin_num_packets = MLX5_GET
 452                 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
 453         attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
 454         attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
 455                                           eth_net_offloads);
 456         attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
 457         attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
 458                                                flex_parser_protocols);
 459         attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
 460         attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 461                                          general_obj_types) &
 462                               MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
 463         if (attr->qos.sup) {
 464                 MLX5_SET(query_hca_cap_in, in, op_mod,
 465                          MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
 466                          MLX5_HCA_CAP_OPMOD_GET_CUR);
 467                 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
 468                                                  out, sizeof(out));
 469                 if (rc)
 470                         goto error;
 471                 if (status) {
 472                         DRV_LOG(DEBUG, "Failed to query devx QOS capabilities,"
 473                                 " status %x, syndrome = %x",
 474                                 status, syndrome);
 475                         return -1;
 476                 }
 477                 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 478                 attr->qos.srtcm_sup =
 479                                 MLX5_GET(qos_cap, hcattr, flow_meter_srtcm);
 480                 attr->qos.log_max_flow_meter =
 481                                 MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
 482                 attr->qos.flow_meter_reg_c_ids =
 483                         MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
 484                 attr->qos.flow_meter_reg_share =
 485                         MLX5_GET(qos_cap, hcattr, flow_meter_reg_share);
 486         }
 487         if (attr->vdpa.valid)
 488                 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
 489         if (!attr->eth_net_offloads)
 490                 return 0;
 491
 492         /* Query HCA offloads for Ethernet protocol. */
 493         memset(in, 0, sizeof(in));
 494         memset(out, 0, sizeof(out));
 495         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 496         MLX5_SET(query_hca_cap_in, in, op_mod,
 497                  MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
 498                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 499
 500         rc = mlx5_glue->devx_general_cmd(ctx,
 501                                          in, sizeof(in),
 502                                          out, sizeof(out));
 503         if (rc) {
 504                 attr->eth_net_offloads = 0;
 505                 goto error;
 506         }
 507         status = MLX5_GET(query_hca_cap_out, out, status);
 508         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 509         if (status) {
 510                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 511                         "status %x, syndrome = %x",
 512                         status, syndrome);
 513                 attr->eth_net_offloads = 0;
 514                 return -1;
 515         }
 516         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 517         attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
 518                                          hcattr, wqe_vlan_insert);
 519         attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
 520                                  lro_cap);
 521         attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
 522                                         hcattr, tunnel_lro_gre);
 523         attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
 524                                           hcattr, tunnel_lro_vxlan);
 525         attr->lro_max_msg_sz_mode = MLX5_GET
 526                                         (per_protocol_networking_offload_caps,
 527                                          hcattr, lro_max_msg_sz_mode);
 528         for (int i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
 529                 attr->lro_timer_supported_periods[i] =
 530                         MLX5_GET(per_protocol_networking_offload_caps, hcattr,
 531                                  lro_timer_supported_periods[i]);
 532         }
 533         attr->tunnel_stateless_geneve_rx =
 534                             MLX5_GET(per_protocol_networking_offload_caps,
 535                                      hcattr, tunnel_stateless_geneve_rx);
 536         attr->geneve_max_opt_len =
 537                     MLX5_GET(per_protocol_networking_offload_caps,
 538                              hcattr, max_geneve_opt_len);
 539         attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
 540                                          hcattr, wqe_inline_mode);
 541         attr->tunnel_stateless_gtp = MLX5_GET
 542                                         (per_protocol_networking_offload_caps,
 543                                          hcattr, tunnel_stateless_gtp);
 544         if (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
 545                 return 0;
 546         if (attr->eth_virt) {
 547                 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
 548                 if (rc) {
 549                         attr->eth_virt = 0;
 550                         goto error;
 551                 }
 552         }
 553         return 0;
 554 error:
 555         rc = (rc > 0) ? -rc : rc;
 556         return rc;
 557 }
 558
 559 /**
 560  * Query TIS transport domain from QP verbs object using DevX API.
 561  *
 562  * @param[in] qp
 563  *   Pointer to verbs QP returned by ibv_create_qp .
 564  * @param[in] tis_num
 565  *   TIS number of TIS to query.
 566  * @param[out] tis_td
 567  *   Pointer to TIS transport domain variable, to be set by the routine.
 568  *
 569  * @return
 570  *   0 on success, a negative value otherwise.
 571  */
 572 int
 573 mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
 574                               uint32_t *tis_td)
 575 {
 576         uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
 577         uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
 578         int rc;
 579         void *tis_ctx;
 580
 581         MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
 582         MLX5_SET(query_tis_in, in, tisn, tis_num);
 583         rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
 584         if (rc) {
 585                 DRV_LOG(ERR, "Failed to query QP using DevX");
 586                 return -rc;
 587         };
 588         tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
 589         *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
 590         return 0;
 591 }
 592
 593 /**
 594  * Fill WQ data for DevX API command.
 595  * Utility function for use when creating DevX objects containing a WQ.
 596  *
 597  * @param[in] wq_ctx
 598  *   Pointer to WQ context to fill with data.
 599  * @param [in] wq_attr
 600  *   Pointer to WQ attributes structure to fill in WQ context.
 601  */
 602 static void
 603 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
 604 {
 605         MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
 606         MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
 607         MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
 608         MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
 609         MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
 610         MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
 611         MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
 612         MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
 613         MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
 614         MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
 615         MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
 616         MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
 617         MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
 618         MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
 619         MLX5_SET(wq, wq_ctx, log_wq_pg_sz, wq_attr->log_wq_pg_sz);
 620         MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
 621         MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
 622         MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
 623         MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
 624                  wq_attr->log_hairpin_num_packets);
 625         MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
 626         MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
 627                  wq_attr->single_wqe_log_num_of_strides);
 628         MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
 629         MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
 630                  wq_attr->single_stride_log_num_of_bytes);
 631         MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
 632         MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
 633         MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
 634 }
 635
 636 /**
 637  * Create RQ using DevX API.
 638  *
 639  * @param[in] ctx
 640  *   ibv_context returned from mlx5dv_open_device.
 641  * @param [in] rq_attr
 642  *   Pointer to create RQ attributes structure.
 643  * @param [in] socket
 644  *   CPU socket ID for allocations.
 645  *
 646  * @return
 647  *   The DevX object created, NULL otherwise and rte_errno is set.
 648  */
 649 struct mlx5_devx_obj *
 650 mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
 651                         struct mlx5_devx_create_rq_attr *rq_attr,
 652                         int socket)
 653 {
 654         uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
 655         uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
 656         void *rq_ctx, *wq_ctx;
 657         struct mlx5_devx_wq_attr *wq_attr;
 658         struct mlx5_devx_obj *rq = NULL;
 659
 660         rq = rte_calloc_socket(__func__, 1, sizeof(*rq), 0, socket);
 661         if (!rq) {
 662                 DRV_LOG(ERR, "Failed to allocate RQ data");
 663                 rte_errno = ENOMEM;
 664                 return NULL;
 665         }
 666         MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
 667         rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
 668         MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
 669         MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
 670         MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
 671         MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
 672         MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
 673         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
 674         MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
 675         MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
 676         MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
 677         MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
 678         MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
 679         MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
 680         wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
 681         wq_attr = &rq_attr->wq_attr;
 682         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
 683         rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
 684                                                   out, sizeof(out));
 685         if (!rq->obj) {
 686                 DRV_LOG(ERR, "Failed to create RQ using DevX");
 687                 rte_errno = errno;
 688                 rte_free(rq);
 689                 return NULL;
 690         }
 691         rq->id = MLX5_GET(create_rq_out, out, rqn);
 692         return rq;
 693 }
 694
 695 /**
 696  * Modify RQ using DevX API.
 697  *
 698  * @param[in] rq
 699  *   Pointer to RQ object structure.
 700  * @param [in] rq_attr
 701  *   Pointer to modify RQ attributes structure.
 702  *
 703  * @return
 704  *   0 on success, a negative errno value otherwise and rte_errno is set.
 705  */
 706 int
 707 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
 708                         struct mlx5_devx_modify_rq_attr *rq_attr)
 709 {
 710         uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
 711         uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
 712         void *rq_ctx, *wq_ctx;
 713         int ret;
 714
 715         MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
 716         MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
 717         MLX5_SET(modify_rq_in, in, rqn, rq->id);
 718         MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
 719         rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 720         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
 721         if (rq_attr->modify_bitmask &
 722                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
 723                 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
 724         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
 725                 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
 726         if (rq_attr->modify_bitmask &
 727                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
 728                 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
 729         MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
 730         MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
 731         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
 732                 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
 733                 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
 734         }
 735         ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
 736                                          out, sizeof(out));
 737         if (ret) {
 738                 DRV_LOG(ERR, "Failed to modify RQ using DevX");
 739                 rte_errno = errno;
 740                 return -errno;
 741         }
 742         return ret;
 743 }
 744
 745 /**
 746  * Create TIR using DevX API.
 747  *
 748  * @param[in] ctx
 749  *   ibv_context returned from mlx5dv_open_device.
 750  * @param [in] tir_attr
 751  *   Pointer to TIR attributes structure.
 752  *
 753  * @return
 754  *   The DevX object created, NULL otherwise and rte_errno is set.
 755  */
 756 struct mlx5_devx_obj *
 757 mlx5_devx_cmd_create_tir(struct ibv_context *ctx,
 758                          struct mlx5_devx_tir_attr *tir_attr)
 759 {
 760         uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
 761         uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
 762         void *tir_ctx, *outer, *inner;
 763         struct mlx5_devx_obj *tir = NULL;
 764         int i;
 765
 766         tir = rte_calloc(__func__, 1, sizeof(*tir), 0);
 767         if (!tir) {
 768                 DRV_LOG(ERR, "Failed to allocate TIR data");
 769                 rte_errno = ENOMEM;
 770                 return NULL;
 771         }
 772         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
 773         tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
 774         MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
 775         MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
 776                  tir_attr->lro_timeout_period_usecs);
 777         MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
 778         MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
 779         MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
 780         MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
 781         MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
 782                  tir_attr->tunneled_offload_en);
 783         MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
 784         MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
 785         MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
 786         MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
 787         for (i = 0; i < 10; i++) {
 788                 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
 789                          tir_attr->rx_hash_toeplitz_key[i]);
 790         }
 791         outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
 792         MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
 793                  tir_attr->rx_hash_field_selector_outer.l3_prot_type);
 794         MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
 795                  tir_attr->rx_hash_field_selector_outer.l4_prot_type);
 796         MLX5_SET(rx_hash_field_select, outer, selected_fields,
 797                  tir_attr->rx_hash_field_selector_outer.selected_fields);
 798         inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
 799         MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
 800                  tir_attr->rx_hash_field_selector_inner.l3_prot_type);
 801         MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
 802                  tir_attr->rx_hash_field_selector_inner.l4_prot_type);
 803         MLX5_SET(rx_hash_field_select, inner, selected_fields,
 804                  tir_attr->rx_hash_field_selector_inner.selected_fields);
 805         tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
 806                                                    out, sizeof(out));
 807         if (!tir->obj) {
 808                 DRV_LOG(ERR, "Failed to create TIR using DevX");
 809                 rte_errno = errno;
 810                 rte_free(tir);
 811                 return NULL;
 812         }
 813         tir->id = MLX5_GET(create_tir_out, out, tirn);
 814         return tir;
 815 }
 816
 817 /**
 818  * Create RQT using DevX API.
 819  *
 820  * @param[in] ctx
 821  *   ibv_context returned from mlx5dv_open_device.
 822  * @param [in] rqt_attr
 823  *   Pointer to RQT attributes structure.
 824  *
 825  * @return
 826  *   The DevX object created, NULL otherwise and rte_errno is set.
 827  */
 828 struct mlx5_devx_obj *
 829 mlx5_devx_cmd_create_rqt(struct ibv_context *ctx,
 830                          struct mlx5_devx_rqt_attr *rqt_attr)
 831 {
 832         uint32_t *in = NULL;
 833         uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
 834                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
 835         uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
 836         void *rqt_ctx;
 837         struct mlx5_devx_obj *rqt = NULL;
 838         int i;
 839
 840         in = rte_calloc(__func__, 1, inlen, 0);
 841         if (!in) {
 842                 DRV_LOG(ERR, "Failed to allocate RQT IN data");
 843                 rte_errno = ENOMEM;
 844                 return NULL;
 845         }
 846         rqt = rte_calloc(__func__, 1, sizeof(*rqt), 0);
 847         if (!rqt) {
 848                 DRV_LOG(ERR, "Failed to allocate RQT data");
 849                 rte_errno = ENOMEM;
 850                 rte_free(in);
 851                 return NULL;
 852         }
 853         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
 854         rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
 855         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
 856         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
 857         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
 858                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
 859         rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
 860         rte_free(in);
 861         if (!rqt->obj) {
 862                 DRV_LOG(ERR, "Failed to create RQT using DevX");
 863                 rte_errno = errno;
 864                 rte_free(rqt);
 865                 return NULL;
 866         }
 867         rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
 868         return rqt;
 869 }
 870
 871 /**
 872  * Create SQ using DevX API.
 873  *
 874  * @param[in] ctx
 875  *   ibv_context returned from mlx5dv_open_device.
 876  * @param [in] sq_attr
 877  *   Pointer to SQ attributes structure.
 878  * @param [in] socket
 879  *   CPU socket ID for allocations.
 880  *
 881  * @return
 882  *   The DevX object created, NULL otherwise and rte_errno is set.
 883  **/
 884 struct mlx5_devx_obj *
 885 mlx5_devx_cmd_create_sq(struct ibv_context *ctx,
 886                         struct mlx5_devx_create_sq_attr *sq_attr)
 887 {
 888         uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
 889         uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
 890         void *sq_ctx;
 891         void *wq_ctx;
 892         struct mlx5_devx_wq_attr *wq_attr;
 893         struct mlx5_devx_obj *sq = NULL;
 894
 895         sq = rte_calloc(__func__, 1, sizeof(*sq), 0);
 896         if (!sq) {
 897                 DRV_LOG(ERR, "Failed to allocate SQ data");
 898                 rte_errno = ENOMEM;
 899                 return NULL;
 900         }
 901         MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
 902         sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
 903         MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
 904         MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
 905         MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
 906         MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
 907         MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
 908                  sq_attr->flush_in_error_en);
 909         MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
 910                  sq_attr->min_wqe_inline_mode);
 911         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
 912         MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
 913         MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
 914         MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
 915         MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
 916         MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
 917         MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
 918                  sq_attr->packet_pacing_rate_limit_index);
 919         MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
 920         MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
 921         wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
 922         wq_attr = &sq_attr->wq_attr;
 923         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
 924         sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
 925                                              out, sizeof(out));
 926         if (!sq->obj) {
 927                 DRV_LOG(ERR, "Failed to create SQ using DevX");
 928                 rte_errno = errno;
 929                 rte_free(sq);
 930                 return NULL;
 931         }
 932         sq->id = MLX5_GET(create_sq_out, out, sqn);
 933         return sq;
 934 }
 935
 936 /**
 937  * Modify SQ using DevX API.
 938  *
 939  * @param[in] sq
 940  *   Pointer to SQ object structure.
 941  * @param [in] sq_attr
 942  *   Pointer to SQ attributes structure.
 943  *
 944  * @return
 945  *   0 on success, a negative errno value otherwise and rte_errno is set.
 946  */
 947 int
 948 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
 949                         struct mlx5_devx_modify_sq_attr *sq_attr)
 950 {
 951         uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
 952         uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
 953         void *sq_ctx;
 954         int ret;
 955
 956         MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
 957         MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
 958         MLX5_SET(modify_sq_in, in, sqn, sq->id);
 959         sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 960         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
 961         MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
 962         MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
 963         ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
 964                                          out, sizeof(out));
 965         if (ret) {
 966                 DRV_LOG(ERR, "Failed to modify SQ using DevX");
 967                 rte_errno = errno;
 968                 return -errno;
 969         }
 970         return ret;
 971 }
 972
 973 /**
 974  * Create TIS using DevX API.
 975  *
 976  * @param[in] ctx
 977  *   ibv_context returned from mlx5dv_open_device.
 978  * @param [in] tis_attr
 979  *   Pointer to TIS attributes structure.
 980  *
 981  * @return
 982  *   The DevX object created, NULL otherwise and rte_errno is set.
 983  */
 984 struct mlx5_devx_obj *
 985 mlx5_devx_cmd_create_tis(struct ibv_context *ctx,
 986                          struct mlx5_devx_tis_attr *tis_attr)
 987 {
 988         uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
 989         uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
 990         struct mlx5_devx_obj *tis = NULL;
 991         void *tis_ctx;
 992
 993         tis = rte_calloc(__func__, 1, sizeof(*tis), 0);
 994         if (!tis) {
 995                 DRV_LOG(ERR, "Failed to allocate TIS object");
 996                 rte_errno = ENOMEM;
 997                 return NULL;
 998         }
 999         MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
1000         tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
1001         MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
1002                  tis_attr->strict_lag_tx_port_affinity);
1003         MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
1004                  tis_attr->strict_lag_tx_port_affinity);
1005         MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
1006         MLX5_SET(tisc, tis_ctx, transport_domain,
1007                  tis_attr->transport_domain);
1008         tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1009                                               out, sizeof(out));
1010         if (!tis->obj) {
1011                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1012                 rte_errno = errno;
1013                 rte_free(tis);
1014                 return NULL;
1015         }
1016         tis->id = MLX5_GET(create_tis_out, out, tisn);
1017         return tis;
1018 }
1019
1020 /**
1021  * Create transport domain using DevX API.
1022  *
1023  * @param[in] ctx
1024  *   ibv_context returned from mlx5dv_open_device.
1025  *
1026  * @return
1027  *   The DevX object created, NULL otherwise and rte_errno is set.
1028  */
1029 struct mlx5_devx_obj *
1030 mlx5_devx_cmd_create_td(struct ibv_context *ctx)
1031 {
1032         uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
1033         uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
1034         struct mlx5_devx_obj *td = NULL;
1035
1036         td = rte_calloc(__func__, 1, sizeof(*td), 0);
1037         if (!td) {
1038                 DRV_LOG(ERR, "Failed to allocate TD object");
1039                 rte_errno = ENOMEM;
1040                 return NULL;
1041         }
1042         MLX5_SET(alloc_transport_domain_in, in, opcode,
1043                  MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
1044         td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1045                                              out, sizeof(out));
1046         if (!td->obj) {
1047                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1048                 rte_errno = errno;
1049                 rte_free(td);
1050                 return NULL;
1051         }
1052         td->id = MLX5_GET(alloc_transport_domain_out, out,
1053                            transport_domain);
1054         return td;
1055 }
1056
1057 /**
1058  * Dump all flows to file.
1059  *
1060  * @param[in] fdb_domain
1061  *   FDB domain.
1062  * @param[in] rx_domain
1063  *   RX domain.
1064  * @param[in] tx_domain
1065  *   TX domain.
1066  * @param[out] file
1067  *   Pointer to file stream.
1068  *
1069  * @return
1070  *   0 on success, a nagative value otherwise.
1071  */
1072 int
1073 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
1074                         void *rx_domain __rte_unused,
1075                         void *tx_domain __rte_unused, FILE *file __rte_unused)
1076 {
1077         int ret = 0;
1078
1079 #ifdef HAVE_MLX5_DR_FLOW_DUMP
1080         if (fdb_domain) {
1081                 ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
1082                 if (ret)
1083                         return ret;
1084         }
1085         assert(rx_domain);
1086         ret = mlx5_glue->dr_dump_domain(file, rx_domain);
1087         if (ret)
1088                 return ret;
1089         assert(tx_domain);
1090         ret = mlx5_glue->dr_dump_domain(file, tx_domain);
1091 #else
1092         ret = ENOTSUP;
1093 #endif
1094         return -ret;
1095 }