drivers/common/mlx5/mlx5_devx_cmds.c

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /* Copyright 2018 Mellanox Technologies, Ltd */
   3
   4 #include <unistd.h>
   5
   6 #include <rte_errno.h>
   7 #include <rte_malloc.h>
   8
   9 #include "mlx5_prm.h"
  10 #include "mlx5_devx_cmds.h"
  11 #include "mlx5_common_utils.h"
  12
  13
  14 /**
  15  * Allocate flow counters via devx interface.
  16  *
  17  * @param[in] ctx
  18  *   ibv contexts returned from mlx5dv_open_device.
  19  * @param dcs
  20  *   Pointer to counters properties structure to be filled by the routine.
  21  * @param bulk_n_128
  22  *   Bulk counter numbers in 128 counters units.
  23  *
  24  * @return
  25  *   Pointer to counter object on success, a negative value otherwise and
  26  *   rte_errno is set.
  27  */
  28 struct mlx5_devx_obj *
  29 mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx, uint32_t bulk_n_128)
  30 {
  31         struct mlx5_devx_obj *dcs = rte_zmalloc("dcs", sizeof(*dcs), 0);
  32         uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)]   = {0};
  33         uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
  34
  35         if (!dcs) {
  36                 rte_errno = ENOMEM;
  37                 return NULL;
  38         }
  39         MLX5_SET(alloc_flow_counter_in, in, opcode,
  40                  MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
  41         MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
  42         dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
  43                                               sizeof(in), out, sizeof(out));
  44         if (!dcs->obj) {
  45                 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
  46                 rte_errno = errno;
  47                 rte_free(dcs);
  48                 return NULL;
  49         }
  50         dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
  51         return dcs;
  52 }
  53
  54 /**
  55  * Query flow counters values.
  56  *
  57  * @param[in] dcs
  58  *   devx object that was obtained from mlx5_devx_cmd_fc_alloc.
  59  * @param[in] clear
  60  *   Whether hardware should clear the counters after the query or not.
  61  * @param[in] n_counters
  62  *   0 in case of 1 counter to read, otherwise the counter number to read.
  63  *  @param pkts
  64  *   The number of packets that matched the flow.
  65  *  @param bytes
  66  *    The number of bytes that matched the flow.
  67  *  @param mkey
  68  *   The mkey key for batch query.
  69  *  @param addr
  70  *    The address in the mkey range for batch query.
  71  *  @param cmd_comp
  72  *   The completion object for asynchronous batch query.
  73  *  @param async_id
  74  *    The ID to be returned in the asynchronous batch query response.
  75  *
  76  * @return
  77  *   0 on success, a negative value otherwise.
  78  */
  79 int
  80 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
  81                                  int clear, uint32_t n_counters,
  82                                  uint64_t *pkts, uint64_t *bytes,
  83                                  uint32_t mkey, void *addr,
  84                                  struct mlx5dv_devx_cmd_comp *cmd_comp,
  85                                  uint64_t async_id)
  86 {
  87         int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
  88                         MLX5_ST_SZ_BYTES(traffic_counter);
  89         uint32_t out[out_len];
  90         uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
  91         void *stats;
  92         int rc;
  93
  94         MLX5_SET(query_flow_counter_in, in, opcode,
  95                  MLX5_CMD_OP_QUERY_FLOW_COUNTER);
  96         MLX5_SET(query_flow_counter_in, in, op_mod, 0);
  97         MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
  98         MLX5_SET(query_flow_counter_in, in, clear, !!clear);
  99
 100         if (n_counters) {
 101                 MLX5_SET(query_flow_counter_in, in, num_of_counters,
 102                          n_counters);
 103                 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
 104                 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
 105                 MLX5_SET64(query_flow_counter_in, in, address,
 106                            (uint64_t)(uintptr_t)addr);
 107         }
 108         if (!cmd_comp)
 109                 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
 110                                                out_len);
 111         else
 112                 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
 113                                                      out_len, async_id,
 114                                                      cmd_comp);
 115         if (rc) {
 116                 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
 117                 rte_errno = rc;
 118                 return -rc;
 119         }
 120         if (!n_counters) {
 121                 stats = MLX5_ADDR_OF(query_flow_counter_out,
 122                                      out, flow_statistics);
 123                 *pkts = MLX5_GET64(traffic_counter, stats, packets);
 124                 *bytes = MLX5_GET64(traffic_counter, stats, octets);
 125         }
 126         return 0;
 127 }
 128
 129 /**
 130  * Create a new mkey.
 131  *
 132  * @param[in] ctx
 133  *   ibv contexts returned from mlx5dv_open_device.
 134  * @param[in] attr
 135  *   Attributes of the requested mkey.
 136  *
 137  * @return
 138  *   Pointer to Devx mkey on success, a negative value otherwise and rte_errno
 139  *   is set.
 140  */
 141 struct mlx5_devx_obj *
 142 mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
 143                           struct mlx5_devx_mkey_attr *attr)
 144 {
 145         uint32_t in[MLX5_ST_SZ_DW(create_mkey_in)] = {0};
 146         uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
 147         void *mkc;
 148         struct mlx5_devx_obj *mkey = rte_zmalloc("mkey", sizeof(*mkey), 0);
 149         size_t pgsize;
 150         uint32_t translation_size;
 151
 152         if (!mkey) {
 153                 rte_errno = ENOMEM;
 154                 return NULL;
 155         }
 156         pgsize = sysconf(_SC_PAGESIZE);
 157         translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
 158         MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
 159         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 160                  translation_size);
 161         MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
 162         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 163         MLX5_SET(mkc, mkc, lw, 0x1);
 164         MLX5_SET(mkc, mkc, lr, 0x1);
 165         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 166         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 167         MLX5_SET(mkc, mkc, pd, attr->pd);
 168         MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
 169         MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
 170         MLX5_SET64(mkc, mkc, start_addr, attr->addr);
 171         MLX5_SET64(mkc, mkc, len, attr->size);
 172         MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
 173         mkey->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
 174                                                sizeof(out));
 175         if (!mkey->obj) {
 176                 DRV_LOG(ERR, "Can't create mkey - error %d", errno);
 177                 rte_errno = errno;
 178                 rte_free(mkey);
 179                 return NULL;
 180         }
 181         mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
 182         mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
 183         return mkey;
 184 }
 185
 186 /**
 187  * Get status of devx command response.
 188  * Mainly used for asynchronous commands.
 189  *
 190  * @param[in] out
 191  *   The out response buffer.
 192  *
 193  * @return
 194  *   0 on success, non-zero value otherwise.
 195  */
 196 int
 197 mlx5_devx_get_out_command_status(void *out)
 198 {
 199         int status;
 200
 201         if (!out)
 202                 return -EINVAL;
 203         status = MLX5_GET(query_flow_counter_out, out, status);
 204         if (status) {
 205                 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
 206
 207                 DRV_LOG(ERR, "Bad devX status %x, syndrome = %x", status,
 208                         syndrome);
 209         }
 210         return status;
 211 }
 212
 213 /**
 214  * Destroy any object allocated by a Devx API.
 215  *
 216  * @param[in] obj
 217  *   Pointer to a general object.
 218  *
 219  * @return
 220  *   0 on success, a negative value otherwise.
 221  */
 222 int
 223 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
 224 {
 225         int ret;
 226
 227         if (!obj)
 228                 return 0;
 229         ret =  mlx5_glue->devx_obj_destroy(obj->obj);
 230         rte_free(obj);
 231         return ret;
 232 }
 233
 234 /**
 235  * Query NIC vport context.
 236  * Fills minimal inline attribute.
 237  *
 238  * @param[in] ctx
 239  *   ibv contexts returned from mlx5dv_open_device.
 240  * @param[in] vport
 241  *   vport index
 242  * @param[out] attr
 243  *   Attributes device values.
 244  *
 245  * @return
 246  *   0 on success, a negative value otherwise.
 247  */
 248 static int
 249 mlx5_devx_cmd_query_nic_vport_context(struct ibv_context *ctx,
 250                                       unsigned int vport,
 251                                       struct mlx5_hca_attr *attr)
 252 {
 253         uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
 254         uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
 255         void *vctx;
 256         int status, syndrome, rc;
 257
 258         /* Query NIC vport context to determine inline mode. */
 259         MLX5_SET(query_nic_vport_context_in, in, opcode,
 260                  MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
 261         MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
 262         if (vport)
 263                 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
 264         rc = mlx5_glue->devx_general_cmd(ctx,
 265                                          in, sizeof(in),
 266                                          out, sizeof(out));
 267         if (rc)
 268                 goto error;
 269         status = MLX5_GET(query_nic_vport_context_out, out, status);
 270         syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
 271         if (status) {
 272                 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
 273                         "status %x, syndrome = %x",
 274                         status, syndrome);
 275                 return -1;
 276         }
 277         vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
 278                             nic_vport_context);
 279         attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
 280                                            min_wqe_inline_mode);
 281         return 0;
 282 error:
 283         rc = (rc > 0) ? -rc : rc;
 284         return rc;
 285 }
 286
 287 /**
 288  * Query NIC vDPA attributes.
 289  *
 290  * @param[in] ctx
 291  *   ibv contexts returned from mlx5dv_open_device.
 292  * @param[out] vdpa_attr
 293  *   vDPA Attributes structure to fill.
 294  */
 295 static void
 296 mlx5_devx_cmd_query_hca_vdpa_attr(struct ibv_context *ctx,
 297                                   struct mlx5_hca_vdpa_attr *vdpa_attr)
 298 {
 299         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 300         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 301         void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 302         int status, syndrome, rc;
 303
 304         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 305         MLX5_SET(query_hca_cap_in, in, op_mod,
 306                  MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
 307                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 308         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 309         status = MLX5_GET(query_hca_cap_out, out, status);
 310         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 311         if (rc || status) {
 312                 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities,"
 313                         " status %x, syndrome = %x", status, syndrome);
 314                 vdpa_attr->valid = 0;
 315         } else {
 316                 vdpa_attr->valid = 1;
 317                 vdpa_attr->desc_tunnel_offload_type =
 318                         MLX5_GET(virtio_emulation_cap, hcattr,
 319                                  desc_tunnel_offload_type);
 320                 vdpa_attr->eth_frame_offload_type =
 321                         MLX5_GET(virtio_emulation_cap, hcattr,
 322                                  eth_frame_offload_type);
 323                 vdpa_attr->virtio_version_1_0 =
 324                         MLX5_GET(virtio_emulation_cap, hcattr,
 325                                  virtio_version_1_0);
 326                 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
 327                                                tso_ipv4);
 328                 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
 329                                                tso_ipv6);
 330                 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 331                                               tx_csum);
 332                 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 333                                               rx_csum);
 334                 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
 335                                                  event_mode);
 336                 vdpa_attr->virtio_queue_type =
 337                         MLX5_GET(virtio_emulation_cap, hcattr,
 338                                  virtio_queue_type);
 339                 vdpa_attr->log_doorbell_stride =
 340                         MLX5_GET(virtio_emulation_cap, hcattr,
 341                                  log_doorbell_stride);
 342                 vdpa_attr->log_doorbell_bar_size =
 343                         MLX5_GET(virtio_emulation_cap, hcattr,
 344                                  log_doorbell_bar_size);
 345                 vdpa_attr->doorbell_bar_offset =
 346                         MLX5_GET64(virtio_emulation_cap, hcattr,
 347                                    doorbell_bar_offset);
 348                 vdpa_attr->max_num_virtio_queues =
 349                         MLX5_GET(virtio_emulation_cap, hcattr,
 350                                  max_num_virtio_queues);
 351                 vdpa_attr->umem_1_buffer_param_a =
 352                         MLX5_GET(virtio_emulation_cap, hcattr,
 353                                  umem_1_buffer_param_a);
 354                 vdpa_attr->umem_1_buffer_param_b =
 355                         MLX5_GET(virtio_emulation_cap, hcattr,
 356                                  umem_1_buffer_param_b);
 357                 vdpa_attr->umem_2_buffer_param_a =
 358                         MLX5_GET(virtio_emulation_cap, hcattr,
 359                                  umem_2_buffer_param_a);
 360                 vdpa_attr->umem_2_buffer_param_b =
 361                         MLX5_GET(virtio_emulation_cap, hcattr,
 362                                  umem_2_buffer_param_a);
 363                 vdpa_attr->umem_3_buffer_param_a =
 364                         MLX5_GET(virtio_emulation_cap, hcattr,
 365                                  umem_3_buffer_param_a);
 366                 vdpa_attr->umem_3_buffer_param_b =
 367                         MLX5_GET(virtio_emulation_cap, hcattr,
 368                                  umem_3_buffer_param_b);
 369         }
 370 }
 371
 372 /**
 373  * Query HCA attributes.
 374  * Using those attributes we can check on run time if the device
 375  * is having the required capabilities.
 376  *
 377  * @param[in] ctx
 378  *   ibv contexts returned from mlx5dv_open_device.
 379  * @param[out] attr
 380  *   Attributes device values.
 381  *
 382  * @return
 383  *   0 on success, a negative value otherwise.
 384  */
 385 int
 386 mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
 387                              struct mlx5_hca_attr *attr)
 388 {
 389         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 390         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 391         void *hcattr;
 392         int status, syndrome, rc;
 393
 394         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 395         MLX5_SET(query_hca_cap_in, in, op_mod,
 396                  MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
 397                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 398
 399         rc = mlx5_glue->devx_general_cmd(ctx,
 400                                          in, sizeof(in), out, sizeof(out));
 401         if (rc)
 402                 goto error;
 403         status = MLX5_GET(query_hca_cap_out, out, status);
 404         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 405         if (status) {
 406                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 407                         "status %x, syndrome = %x",
 408                         status, syndrome);
 409                 return -1;
 410         }
 411         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 412         attr->flow_counter_bulk_alloc_bitmap =
 413                         MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
 414         attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
 415                                             flow_counters_dump);
 416         attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
 417         attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
 418         attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
 419                                                 log_max_hairpin_queues);
 420         attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
 421                                                     log_max_hairpin_wq_data_sz);
 422         attr->log_max_hairpin_num_packets = MLX5_GET
 423                 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
 424         attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
 425         attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
 426                                           eth_net_offloads);
 427         attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
 428         attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
 429                                                flex_parser_protocols);
 430         attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
 431         attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 432                                          general_obj_types) &
 433                               MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
 434         if (attr->qos.sup) {
 435                 MLX5_SET(query_hca_cap_in, in, op_mod,
 436                          MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
 437                          MLX5_HCA_CAP_OPMOD_GET_CUR);
 438                 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
 439                                                  out, sizeof(out));
 440                 if (rc)
 441                         goto error;
 442                 if (status) {
 443                         DRV_LOG(DEBUG, "Failed to query devx QOS capabilities,"
 444                                 " status %x, syndrome = %x",
 445                                 status, syndrome);
 446                         return -1;
 447                 }
 448                 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 449                 attr->qos.srtcm_sup =
 450                                 MLX5_GET(qos_cap, hcattr, flow_meter_srtcm);
 451                 attr->qos.log_max_flow_meter =
 452                                 MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
 453                 attr->qos.flow_meter_reg_c_ids =
 454                         MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
 455                 attr->qos.flow_meter_reg_share =
 456                         MLX5_GET(qos_cap, hcattr, flow_meter_reg_share);
 457         }
 458         if (attr->vdpa.valid)
 459                 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
 460         if (!attr->eth_net_offloads)
 461                 return 0;
 462
 463         /* Query HCA offloads for Ethernet protocol. */
 464         memset(in, 0, sizeof(in));
 465         memset(out, 0, sizeof(out));
 466         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 467         MLX5_SET(query_hca_cap_in, in, op_mod,
 468                  MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
 469                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 470
 471         rc = mlx5_glue->devx_general_cmd(ctx,
 472                                          in, sizeof(in),
 473                                          out, sizeof(out));
 474         if (rc) {
 475                 attr->eth_net_offloads = 0;
 476                 goto error;
 477         }
 478         status = MLX5_GET(query_hca_cap_out, out, status);
 479         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 480         if (status) {
 481                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 482                         "status %x, syndrome = %x",
 483                         status, syndrome);
 484                 attr->eth_net_offloads = 0;
 485                 return -1;
 486         }
 487         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 488         attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
 489                                          hcattr, wqe_vlan_insert);
 490         attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
 491                                  lro_cap);
 492         attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
 493                                         hcattr, tunnel_lro_gre);
 494         attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
 495                                           hcattr, tunnel_lro_vxlan);
 496         attr->lro_max_msg_sz_mode = MLX5_GET
 497                                         (per_protocol_networking_offload_caps,
 498                                          hcattr, lro_max_msg_sz_mode);
 499         for (int i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
 500                 attr->lro_timer_supported_periods[i] =
 501                         MLX5_GET(per_protocol_networking_offload_caps, hcattr,
 502                                  lro_timer_supported_periods[i]);
 503         }
 504         attr->tunnel_stateless_geneve_rx =
 505                             MLX5_GET(per_protocol_networking_offload_caps,
 506                                      hcattr, tunnel_stateless_geneve_rx);
 507         attr->geneve_max_opt_len =
 508                     MLX5_GET(per_protocol_networking_offload_caps,
 509                              hcattr, max_geneve_opt_len);
 510         attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
 511                                          hcattr, wqe_inline_mode);
 512         attr->tunnel_stateless_gtp = MLX5_GET
 513                                         (per_protocol_networking_offload_caps,
 514                                          hcattr, tunnel_stateless_gtp);
 515         if (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
 516                 return 0;
 517         if (attr->eth_virt) {
 518                 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
 519                 if (rc) {
 520                         attr->eth_virt = 0;
 521                         goto error;
 522                 }
 523         }
 524         return 0;
 525 error:
 526         rc = (rc > 0) ? -rc : rc;
 527         return rc;
 528 }
 529
 530 /**
 531  * Query TIS transport domain from QP verbs object using DevX API.
 532  *
 533  * @param[in] qp
 534  *   Pointer to verbs QP returned by ibv_create_qp .
 535  * @param[in] tis_num
 536  *   TIS number of TIS to query.
 537  * @param[out] tis_td
 538  *   Pointer to TIS transport domain variable, to be set by the routine.
 539  *
 540  * @return
 541  *   0 on success, a negative value otherwise.
 542  */
 543 int
 544 mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
 545                               uint32_t *tis_td)
 546 {
 547         uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
 548         uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
 549         int rc;
 550         void *tis_ctx;
 551
 552         MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
 553         MLX5_SET(query_tis_in, in, tisn, tis_num);
 554         rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
 555         if (rc) {
 556                 DRV_LOG(ERR, "Failed to query QP using DevX");
 557                 return -rc;
 558         };
 559         tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
 560         *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
 561         return 0;
 562 }
 563
 564 /**
 565  * Fill WQ data for DevX API command.
 566  * Utility function for use when creating DevX objects containing a WQ.
 567  *
 568  * @param[in] wq_ctx
 569  *   Pointer to WQ context to fill with data.
 570  * @param [in] wq_attr
 571  *   Pointer to WQ attributes structure to fill in WQ context.
 572  */
 573 static void
 574 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
 575 {
 576         MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
 577         MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
 578         MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
 579         MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
 580         MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
 581         MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
 582         MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
 583         MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
 584         MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
 585         MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
 586         MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
 587         MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
 588         MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
 589         MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
 590         MLX5_SET(wq, wq_ctx, log_wq_pg_sz, wq_attr->log_wq_pg_sz);
 591         MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
 592         MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
 593         MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
 594         MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
 595                  wq_attr->log_hairpin_num_packets);
 596         MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
 597         MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
 598                  wq_attr->single_wqe_log_num_of_strides);
 599         MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
 600         MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
 601                  wq_attr->single_stride_log_num_of_bytes);
 602         MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
 603         MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
 604         MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
 605 }
 606
 607 /**
 608  * Create RQ using DevX API.
 609  *
 610  * @param[in] ctx
 611  *   ibv_context returned from mlx5dv_open_device.
 612  * @param [in] rq_attr
 613  *   Pointer to create RQ attributes structure.
 614  * @param [in] socket
 615  *   CPU socket ID for allocations.
 616  *
 617  * @return
 618  *   The DevX object created, NULL otherwise and rte_errno is set.
 619  */
 620 struct mlx5_devx_obj *
 621 mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
 622                         struct mlx5_devx_create_rq_attr *rq_attr,
 623                         int socket)
 624 {
 625         uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
 626         uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
 627         void *rq_ctx, *wq_ctx;
 628         struct mlx5_devx_wq_attr *wq_attr;
 629         struct mlx5_devx_obj *rq = NULL;
 630
 631         rq = rte_calloc_socket(__func__, 1, sizeof(*rq), 0, socket);
 632         if (!rq) {
 633                 DRV_LOG(ERR, "Failed to allocate RQ data");
 634                 rte_errno = ENOMEM;
 635                 return NULL;
 636         }
 637         MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
 638         rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
 639         MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
 640         MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
 641         MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
 642         MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
 643         MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
 644         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
 645         MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
 646         MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
 647         MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
 648         MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
 649         MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
 650         MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
 651         wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
 652         wq_attr = &rq_attr->wq_attr;
 653         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
 654         rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
 655                                                   out, sizeof(out));
 656         if (!rq->obj) {
 657                 DRV_LOG(ERR, "Failed to create RQ using DevX");
 658                 rte_errno = errno;
 659                 rte_free(rq);
 660                 return NULL;
 661         }
 662         rq->id = MLX5_GET(create_rq_out, out, rqn);
 663         return rq;
 664 }
 665
 666 /**
 667  * Modify RQ using DevX API.
 668  *
 669  * @param[in] rq
 670  *   Pointer to RQ object structure.
 671  * @param [in] rq_attr
 672  *   Pointer to modify RQ attributes structure.
 673  *
 674  * @return
 675  *   0 on success, a negative errno value otherwise and rte_errno is set.
 676  */
 677 int
 678 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
 679                         struct mlx5_devx_modify_rq_attr *rq_attr)
 680 {
 681         uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
 682         uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
 683         void *rq_ctx, *wq_ctx;
 684         int ret;
 685
 686         MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
 687         MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
 688         MLX5_SET(modify_rq_in, in, rqn, rq->id);
 689         MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
 690         rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 691         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
 692         if (rq_attr->modify_bitmask &
 693                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
 694                 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
 695         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
 696                 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
 697         if (rq_attr->modify_bitmask &
 698                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
 699                 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
 700         MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
 701         MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
 702         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
 703                 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
 704                 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
 705         }
 706         ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
 707                                          out, sizeof(out));
 708         if (ret) {
 709                 DRV_LOG(ERR, "Failed to modify RQ using DevX");
 710                 rte_errno = errno;
 711                 return -errno;
 712         }
 713         return ret;
 714 }
 715
 716 /**
 717  * Create TIR using DevX API.
 718  *
 719  * @param[in] ctx
 720  *   ibv_context returned from mlx5dv_open_device.
 721  * @param [in] tir_attr
 722  *   Pointer to TIR attributes structure.
 723  *
 724  * @return
 725  *   The DevX object created, NULL otherwise and rte_errno is set.
 726  */
 727 struct mlx5_devx_obj *
 728 mlx5_devx_cmd_create_tir(struct ibv_context *ctx,
 729                          struct mlx5_devx_tir_attr *tir_attr)
 730 {
 731         uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
 732         uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
 733         void *tir_ctx, *outer, *inner;
 734         struct mlx5_devx_obj *tir = NULL;
 735         int i;
 736
 737         tir = rte_calloc(__func__, 1, sizeof(*tir), 0);
 738         if (!tir) {
 739                 DRV_LOG(ERR, "Failed to allocate TIR data");
 740                 rte_errno = ENOMEM;
 741                 return NULL;
 742         }
 743         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
 744         tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
 745         MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
 746         MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
 747                  tir_attr->lro_timeout_period_usecs);
 748         MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
 749         MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
 750         MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
 751         MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
 752         MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
 753                  tir_attr->tunneled_offload_en);
 754         MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
 755         MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
 756         MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
 757         MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
 758         for (i = 0; i < 10; i++) {
 759                 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
 760                          tir_attr->rx_hash_toeplitz_key[i]);
 761         }
 762         outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
 763         MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
 764                  tir_attr->rx_hash_field_selector_outer.l3_prot_type);
 765         MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
 766                  tir_attr->rx_hash_field_selector_outer.l4_prot_type);
 767         MLX5_SET(rx_hash_field_select, outer, selected_fields,
 768                  tir_attr->rx_hash_field_selector_outer.selected_fields);
 769         inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
 770         MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
 771                  tir_attr->rx_hash_field_selector_inner.l3_prot_type);
 772         MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
 773                  tir_attr->rx_hash_field_selector_inner.l4_prot_type);
 774         MLX5_SET(rx_hash_field_select, inner, selected_fields,
 775                  tir_attr->rx_hash_field_selector_inner.selected_fields);
 776         tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
 777                                                    out, sizeof(out));
 778         if (!tir->obj) {
 779                 DRV_LOG(ERR, "Failed to create TIR using DevX");
 780                 rte_errno = errno;
 781                 rte_free(tir);
 782                 return NULL;
 783         }
 784         tir->id = MLX5_GET(create_tir_out, out, tirn);
 785         return tir;
 786 }
 787
 788 /**
 789  * Create RQT using DevX API.
 790  *
 791  * @param[in] ctx
 792  *   ibv_context returned from mlx5dv_open_device.
 793  * @param [in] rqt_attr
 794  *   Pointer to RQT attributes structure.
 795  *
 796  * @return
 797  *   The DevX object created, NULL otherwise and rte_errno is set.
 798  */
 799 struct mlx5_devx_obj *
 800 mlx5_devx_cmd_create_rqt(struct ibv_context *ctx,
 801                          struct mlx5_devx_rqt_attr *rqt_attr)
 802 {
 803         uint32_t *in = NULL;
 804         uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
 805                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
 806         uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
 807         void *rqt_ctx;
 808         struct mlx5_devx_obj *rqt = NULL;
 809         int i;
 810
 811         in = rte_calloc(__func__, 1, inlen, 0);
 812         if (!in) {
 813                 DRV_LOG(ERR, "Failed to allocate RQT IN data");
 814                 rte_errno = ENOMEM;
 815                 return NULL;
 816         }
 817         rqt = rte_calloc(__func__, 1, sizeof(*rqt), 0);
 818         if (!rqt) {
 819                 DRV_LOG(ERR, "Failed to allocate RQT data");
 820                 rte_errno = ENOMEM;
 821                 rte_free(in);
 822                 return NULL;
 823         }
 824         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
 825         rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
 826         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
 827         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
 828         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
 829                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
 830         rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
 831         rte_free(in);
 832         if (!rqt->obj) {
 833                 DRV_LOG(ERR, "Failed to create RQT using DevX");
 834                 rte_errno = errno;
 835                 rte_free(rqt);
 836                 return NULL;
 837         }
 838         rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
 839         return rqt;
 840 }
 841
 842 /**
 843  * Create SQ using DevX API.
 844  *
 845  * @param[in] ctx
 846  *   ibv_context returned from mlx5dv_open_device.
 847  * @param [in] sq_attr
 848  *   Pointer to SQ attributes structure.
 849  * @param [in] socket
 850  *   CPU socket ID for allocations.
 851  *
 852  * @return
 853  *   The DevX object created, NULL otherwise and rte_errno is set.
 854  **/
 855 struct mlx5_devx_obj *
 856 mlx5_devx_cmd_create_sq(struct ibv_context *ctx,
 857                         struct mlx5_devx_create_sq_attr *sq_attr)
 858 {
 859         uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
 860         uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
 861         void *sq_ctx;
 862         void *wq_ctx;
 863         struct mlx5_devx_wq_attr *wq_attr;
 864         struct mlx5_devx_obj *sq = NULL;
 865
 866         sq = rte_calloc(__func__, 1, sizeof(*sq), 0);
 867         if (!sq) {
 868                 DRV_LOG(ERR, "Failed to allocate SQ data");
 869                 rte_errno = ENOMEM;
 870                 return NULL;
 871         }
 872         MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
 873         sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
 874         MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
 875         MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
 876         MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
 877         MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
 878         MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
 879                  sq_attr->flush_in_error_en);
 880         MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
 881                  sq_attr->min_wqe_inline_mode);
 882         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
 883         MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
 884         MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
 885         MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
 886         MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
 887         MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
 888         MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
 889                  sq_attr->packet_pacing_rate_limit_index);
 890         MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
 891         MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
 892         wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
 893         wq_attr = &sq_attr->wq_attr;
 894         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
 895         sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
 896                                              out, sizeof(out));
 897         if (!sq->obj) {
 898                 DRV_LOG(ERR, "Failed to create SQ using DevX");
 899                 rte_errno = errno;
 900                 rte_free(sq);
 901                 return NULL;
 902         }
 903         sq->id = MLX5_GET(create_sq_out, out, sqn);
 904         return sq;
 905 }
 906
 907 /**
 908  * Modify SQ using DevX API.
 909  *
 910  * @param[in] sq
 911  *   Pointer to SQ object structure.
 912  * @param [in] sq_attr
 913  *   Pointer to SQ attributes structure.
 914  *
 915  * @return
 916  *   0 on success, a negative errno value otherwise and rte_errno is set.
 917  */
 918 int
 919 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
 920                         struct mlx5_devx_modify_sq_attr *sq_attr)
 921 {
 922         uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
 923         uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
 924         void *sq_ctx;
 925         int ret;
 926
 927         MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
 928         MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
 929         MLX5_SET(modify_sq_in, in, sqn, sq->id);
 930         sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 931         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
 932         MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
 933         MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
 934         ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
 935                                          out, sizeof(out));
 936         if (ret) {
 937                 DRV_LOG(ERR, "Failed to modify SQ using DevX");
 938                 rte_errno = errno;
 939                 return -errno;
 940         }
 941         return ret;
 942 }
 943
 944 /**
 945  * Create TIS using DevX API.
 946  *
 947  * @param[in] ctx
 948  *   ibv_context returned from mlx5dv_open_device.
 949  * @param [in] tis_attr
 950  *   Pointer to TIS attributes structure.
 951  *
 952  * @return
 953  *   The DevX object created, NULL otherwise and rte_errno is set.
 954  */
 955 struct mlx5_devx_obj *
 956 mlx5_devx_cmd_create_tis(struct ibv_context *ctx,
 957                          struct mlx5_devx_tis_attr *tis_attr)
 958 {
 959         uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
 960         uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
 961         struct mlx5_devx_obj *tis = NULL;
 962         void *tis_ctx;
 963
 964         tis = rte_calloc(__func__, 1, sizeof(*tis), 0);
 965         if (!tis) {
 966                 DRV_LOG(ERR, "Failed to allocate TIS object");
 967                 rte_errno = ENOMEM;
 968                 return NULL;
 969         }
 970         MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
 971         tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
 972         MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
 973                  tis_attr->strict_lag_tx_port_affinity);
 974         MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
 975                  tis_attr->strict_lag_tx_port_affinity);
 976         MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
 977         MLX5_SET(tisc, tis_ctx, transport_domain,
 978                  tis_attr->transport_domain);
 979         tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
 980                                               out, sizeof(out));
 981         if (!tis->obj) {
 982                 DRV_LOG(ERR, "Failed to create TIS using DevX");
 983                 rte_errno = errno;
 984                 rte_free(tis);
 985                 return NULL;
 986         }
 987         tis->id = MLX5_GET(create_tis_out, out, tisn);
 988         return tis;
 989 }
 990
 991 /**
 992  * Create transport domain using DevX API.
 993  *
 994  * @param[in] ctx
 995  *   ibv_context returned from mlx5dv_open_device.
 996  *
 997  * @return
 998  *   The DevX object created, NULL otherwise and rte_errno is set.
 999  */
1000 struct mlx5_devx_obj *
1001 mlx5_devx_cmd_create_td(struct ibv_context *ctx)
1002 {
1003         uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
1004         uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
1005         struct mlx5_devx_obj *td = NULL;
1006
1007         td = rte_calloc(__func__, 1, sizeof(*td), 0);
1008         if (!td) {
1009                 DRV_LOG(ERR, "Failed to allocate TD object");
1010                 rte_errno = ENOMEM;
1011                 return NULL;
1012         }
1013         MLX5_SET(alloc_transport_domain_in, in, opcode,
1014                  MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
1015         td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1016                                              out, sizeof(out));
1017         if (!td->obj) {
1018                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1019                 rte_errno = errno;
1020                 rte_free(td);
1021                 return NULL;
1022         }
1023         td->id = MLX5_GET(alloc_transport_domain_out, out,
1024                            transport_domain);
1025         return td;
1026 }
1027
1028 /**
1029  * Dump all flows to file.
1030  *
1031  * @param[in] fdb_domain
1032  *   FDB domain.
1033  * @param[in] rx_domain
1034  *   RX domain.
1035  * @param[in] tx_domain
1036  *   TX domain.
1037  * @param[out] file
1038  *   Pointer to file stream.
1039  *
1040  * @return
1041  *   0 on success, a nagative value otherwise.
1042  */
1043 int
1044 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
1045                         void *rx_domain __rte_unused,
1046                         void *tx_domain __rte_unused, FILE *file __rte_unused)
1047 {
1048         int ret = 0;
1049
1050 #ifdef HAVE_MLX5_DR_FLOW_DUMP
1051         if (fdb_domain) {
1052                 ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
1053                 if (ret)
1054                         return ret;
1055         }
1056         assert(rx_domain);
1057         ret = mlx5_glue->dr_dump_domain(file, rx_domain);
1058         if (ret)
1059                 return ret;
1060         assert(tx_domain);
1061         ret = mlx5_glue->dr_dump_domain(file, tx_domain);
1062 #else
1063         ret = ENOTSUP;
1064 #endif
1065         return -ret;
1066 }