1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_
6 #define RTE_PMD_MLX5_DEVX_CMDS_H_
12 /* This is limitation of libibverbs: in length variable type is u16. */
13 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \
14 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4))
16 struct mlx5_devx_mkey_attr {
21 uint32_t log_entity_size;
23 uint32_t relaxed_ordering:1;
24 struct mlx5_klm *klm_array;
28 /* HCA qos attributes. */
29 struct mlx5_hca_qos_attr {
30 uint32_t sup:1; /* Whether QOS is supported. */
31 uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */
32 uint32_t flow_meter_reg_share:1;
33 /* Whether reg_c share is supported. */
34 uint8_t log_max_flow_meter;
35 /* Power of the maximum supported meters. */
36 uint8_t flow_meter_reg_c_ids;
37 /* Bitmap of the reg_Cs available for flow meter to use. */
41 struct mlx5_hca_vdpa_attr {
42 uint8_t virtio_queue_type;
44 uint32_t desc_tunnel_offload_type:1;
45 uint32_t eth_frame_offload_type:1;
46 uint32_t virtio_version_1_0:1;
51 uint32_t event_mode:3;
52 uint32_t log_doorbell_stride:5;
53 uint32_t log_doorbell_bar_size:5;
54 uint32_t queue_counters_valid:1;
55 uint32_t max_num_virtio_queues;
60 uint64_t doorbell_bar_offset;
63 /* HCA supports this number of time periods for LRO. */
64 #define MLX5_LRO_NUM_SUPP_PERIODS 4
67 struct mlx5_hca_attr {
68 uint32_t eswitch_manager:1;
69 uint32_t flow_counters_dump:1;
70 uint32_t log_max_rqt_size:5;
71 uint8_t flow_counter_bulk_alloc_bitmap;
72 uint32_t eth_net_offloads:1;
74 uint32_t wqe_vlan_insert:1;
75 uint32_t wqe_inline_mode:2;
76 uint32_t vport_inline_mode:3;
77 uint32_t tunnel_stateless_geneve_rx:1;
78 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
79 uint32_t tunnel_stateless_gtp:1;
81 uint32_t tunnel_lro_gre:1;
82 uint32_t tunnel_lro_vxlan:1;
83 uint32_t lro_max_msg_sz_mode:2;
84 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
85 uint32_t flex_parser_protocols;
87 uint32_t log_max_hairpin_queues:5;
88 uint32_t log_max_hairpin_wq_data_sz:5;
89 uint32_t log_max_hairpin_num_packets:5;
91 uint32_t relaxed_ordering_write:1;
92 uint32_t relaxed_ordering_read:1;
94 uint32_t regexp_num_of_engines;
95 struct mlx5_hca_qos_attr qos;
96 struct mlx5_hca_vdpa_attr vdpa;
99 struct mlx5_devx_wq_attr {
101 uint32_t wq_signature:1;
102 uint32_t end_padding_mode:2;
104 uint32_t hds_skip_first_sge:1;
105 uint32_t log2_hds_buf_size:3;
106 uint32_t page_offset:5;
109 uint32_t uar_page:24;
113 uint32_t log_wq_stride:4;
114 uint32_t log_wq_pg_sz:5;
115 uint32_t log_wq_sz:5;
116 uint32_t dbr_umem_valid:1;
117 uint32_t wq_umem_valid:1;
118 uint32_t log_hairpin_num_packets:5;
119 uint32_t log_hairpin_data_sz:5;
120 uint32_t single_wqe_log_num_of_strides:4;
121 uint32_t two_byte_shift_en:1;
122 uint32_t single_stride_log_num_of_bytes:3;
123 uint32_t dbr_umem_id;
125 uint64_t wq_umem_offset;
128 /* Create RQ attributes structure, used by create RQ operation. */
129 struct mlx5_devx_create_rq_attr {
131 uint32_t delay_drop_en:1;
132 uint32_t scatter_fcs:1;
134 uint32_t mem_rq_type:4;
136 uint32_t flush_in_error_en:1;
138 uint32_t user_index:24;
140 uint32_t counter_set_id:8;
142 struct mlx5_devx_wq_attr wq_attr;
145 /* Modify RQ attributes structure, used by modify RQ operation. */
146 struct mlx5_devx_modify_rq_attr {
148 uint32_t rq_state:4; /* Current RQ state. */
149 uint32_t state:4; /* Required RQ state. */
150 uint32_t scatter_fcs:1;
152 uint32_t counter_set_id:8;
153 uint32_t hairpin_peer_sq:24;
154 uint32_t hairpin_peer_vhca:16;
155 uint64_t modify_bitmask;
156 uint32_t lwm:16; /* Contained WQ lwm. */
159 struct mlx5_rx_hash_field_select {
160 uint32_t l3_prot_type:1;
161 uint32_t l4_prot_type:1;
162 uint32_t selected_fields:30;
165 /* TIR attributes structure, used by TIR operations. */
166 struct mlx5_devx_tir_attr {
167 uint32_t disp_type:4;
168 uint32_t lro_timeout_period_usecs:16;
169 uint32_t lro_enable_mask:4;
170 uint32_t lro_max_msg_sz:8;
171 uint32_t inline_rqn:24;
172 uint32_t rx_hash_symmetric:1;
173 uint32_t tunneled_offload_en:1;
174 uint32_t indirect_table:24;
175 uint32_t rx_hash_fn:4;
176 uint32_t self_lb_block:2;
177 uint32_t transport_domain:24;
178 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN];
179 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
180 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
183 /* RQT attributes structure, used by RQT operations. */
184 struct mlx5_devx_rqt_attr {
186 uint32_t rqt_max_size:16;
187 uint32_t rqt_actual_size:16;
191 /* TIS attributes structure. */
192 struct mlx5_devx_tis_attr {
193 uint32_t strict_lag_tx_port_affinity:1;
195 uint32_t lag_tx_port_affinity:4;
197 uint32_t transport_domain:24;
200 /* SQ attributes structure, used by SQ create operation. */
201 struct mlx5_devx_create_sq_attr {
203 uint32_t cd_master:1;
205 uint32_t flush_in_error_en:1;
206 uint32_t allow_multi_pkt_send_wqe:1;
207 uint32_t min_wqe_inline_mode:3;
210 uint32_t allow_swp:1;
212 uint32_t user_index:24;
214 uint32_t packet_pacing_rate_limit_index:16;
215 uint32_t tis_lst_sz:16;
217 struct mlx5_devx_wq_attr wq_attr;
220 /* SQ attributes structure, used by SQ modify operation. */
221 struct mlx5_devx_modify_sq_attr {
224 uint32_t hairpin_peer_rq:24;
225 uint32_t hairpin_peer_vhca:16;
229 /* CQ attributes structure, used by CQ operations. */
230 struct mlx5_devx_cq_attr {
231 uint32_t q_umem_valid:1;
232 uint32_t db_umem_valid:1;
233 uint32_t use_first_only:1;
234 uint32_t overrun_ignore:1;
235 uint32_t log_cq_size:5;
236 uint32_t log_page_size:5;
237 uint32_t uar_page_id;
239 uint64_t q_umem_offset;
241 uint64_t db_umem_offset;
246 /* Virtq attributes structure, used by VIRTQ operations. */
247 struct mlx5_devx_virtq_attr {
248 uint16_t hw_available_index;
249 uint16_t hw_used_index;
252 uint32_t virtio_version_1_0:1;
257 uint32_t event_mode:3;
259 uint32_t dirty_bitmap_dump_enable:1;
260 uint32_t dirty_bitmap_mkey;
261 uint32_t dirty_bitmap_size;
264 uint32_t queue_index;
266 uint32_t counters_obj_id;
267 uint64_t dirty_bitmap_addr;
271 uint64_t available_addr;
280 struct mlx5_devx_qp_attr {
282 uint32_t uar_index:24;
284 uint32_t log_page_size:5;
285 uint32_t rq_size:17; /* Must be power of 2. */
286 uint32_t log_rq_stride:3;
287 uint32_t sq_size:17; /* Must be power of 2. */
288 uint32_t dbr_umem_valid:1;
289 uint32_t dbr_umem_id;
290 uint64_t dbr_address;
292 uint64_t wq_umem_offset;
295 struct mlx5_devx_virtio_q_couners_attr {
296 uint64_t received_desc;
297 uint64_t completed_desc;
299 uint32_t bad_desc_errors;
300 uint32_t exceed_max_chain;
301 uint32_t invalid_buffer;
304 /* mlx5_devx_cmds.c */
307 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx,
310 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
312 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
313 int clear, uint32_t n_counters,
314 uint64_t *pkts, uint64_t *bytes,
315 uint32_t mkey, void *addr,
319 int mlx5_devx_cmd_query_hca_attr(void *ctx,
320 struct mlx5_hca_attr *attr);
322 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx,
323 struct mlx5_devx_mkey_attr *attr);
325 int mlx5_devx_get_out_command_status(void *out);
327 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
330 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx,
331 struct mlx5_devx_create_rq_attr *rq_attr,
334 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
335 struct mlx5_devx_modify_rq_attr *rq_attr);
337 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx,
338 struct mlx5_devx_tir_attr *tir_attr);
340 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx,
341 struct mlx5_devx_rqt_attr *rqt_attr);
343 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx,
344 struct mlx5_devx_create_sq_attr *sq_attr);
346 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
347 struct mlx5_devx_modify_sq_attr *sq_attr);
349 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx,
350 struct mlx5_devx_tis_attr *tis_attr);
352 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx);
354 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain,
357 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx,
358 struct mlx5_devx_cq_attr *attr);
360 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx,
361 struct mlx5_devx_virtq_attr *attr);
363 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
364 struct mlx5_devx_virtq_attr *attr);
366 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
367 struct mlx5_devx_virtq_attr *attr);
369 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx,
370 struct mlx5_devx_qp_attr *attr);
372 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp,
373 uint32_t qp_st_mod_op, uint32_t remote_qp_id);
375 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
376 struct mlx5_devx_rqt_attr *rqt_attr);
379 * Create virtio queue counters object DevX API.
385 * The DevX object created, NULL otherwise and rte_errno is set.
388 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx);
391 * Query virtio queue counters object using DevX API.
393 * @param[in] couners_obj
394 * Pointer to virtq object structure.
395 * @param [in/out] attr
396 * Pointer to virtio queue counters attributes structure.
399 * 0 on success, a negative errno value otherwise and rte_errno is set.
402 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
403 struct mlx5_devx_virtio_q_couners_attr *attr);
405 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */