drivers/common/mlx5/mlx5_prm.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2016 6WIND S.A.
   3  * Copyright 2016 Mellanox Technologies, Ltd
   4  */
   5
   6 #ifndef RTE_PMD_MLX5_PRM_H_
   7 #define RTE_PMD_MLX5_PRM_H_
   8
   9 #include <assert.h>
  10 /* Verbs header. */
  11 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  12 #ifdef PEDANTIC
  13 #pragma GCC diagnostic ignored "-Wpedantic"
  14 #endif
  15 #include <infiniband/mlx5dv.h>
  16 #ifdef PEDANTIC
  17 #pragma GCC diagnostic error "-Wpedantic"
  18 #endif
  19
  20 #include <rte_vect.h>
  21 #include <rte_byteorder.h>
  22
  23 #include "mlx5_autoconf.h"
  24
  25 /* RSS hash key size. */
  26 #define MLX5_RSS_HASH_KEY_LEN 40
  27
  28 /* Get CQE owner bit. */
  29 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
  30
  31 /* Get CQE format. */
  32 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
  33
  34 /* Get CQE opcode. */
  35 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
  36
  37 /* Get CQE solicited event. */
  38 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
  39
  40 /* Invalidate a CQE. */
  41 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
  42
  43 /* WQE Segment sizes in bytes. */
  44 #define MLX5_WSEG_SIZE 16u
  45 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)
  46 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg)
  47 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg)
  48
  49 /* WQE/WQEBB size in bytes. */
  50 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe)
  51
  52 /*
  53  * Max size of a WQE session.
  54  * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments,
  55  * the WQE size field in Control Segment is 6 bits wide.
  56  */
  57 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE)
  58
  59 /*
  60  * Default minimum number of Tx queues for inlining packets.
  61  * If there are less queues as specified we assume we have
  62  * no enough CPU resources (cycles) to perform inlining,
  63  * the PCIe throughput is not supposed as bottleneck and
  64  * inlining is disabled.
  65  */
  66 #define MLX5_INLINE_MAX_TXQS 8u
  67 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u
  68
  69 /*
  70  * Default packet length threshold to be inlined with
  71  * enhanced MPW. If packet length exceeds the threshold
  72  * the data are not inlined. Should be aligned in WQEBB
  73  * boundary with accounting the title Control and Ethernet
  74  * segments.
  75  */
  76 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \
  77                                   MLX5_DSEG_MIN_INLINE_SIZE)
  78 /*
  79  * Maximal inline data length sent with enhanced MPW.
  80  * Is based on maximal WQE size.
  81  */
  82 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
  83                                   MLX5_WQE_CSEG_SIZE - \
  84                                   MLX5_WQE_ESEG_SIZE - \
  85                                   MLX5_WQE_DSEG_SIZE + \
  86                                   MLX5_DSEG_MIN_INLINE_SIZE)
  87 /*
  88  * Minimal amount of packets to be sent with EMPW.
  89  * This limits the minimal required size of sent EMPW.
  90  * If there are no enough resources to built minimal
  91  * EMPW the sending loop exits.
  92  */
  93 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u)
  94 /*
  95  * Maximal amount of packets to be sent with EMPW.
  96  * This value is not recommended to exceed MLX5_TX_COMP_THRESH,
  97  * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs
  98  * without CQE generation request, being multiplied by
  99  * MLX5_TX_COMP_MAX_CQE it may cause significant latency
 100  * in tx burst routine at the moment of freeing multiple mbufs.
 101  */
 102 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
 103 #define MLX5_MPW_MAX_PACKETS 6
 104 #define MLX5_MPW_INLINE_MAX_PACKETS 2
 105
 106 /*
 107  * Default packet length threshold to be inlined with
 108  * ordinary SEND. Inlining saves the MR key search
 109  * and extra PCIe data fetch transaction, but eats the
 110  * CPU cycles.
 111  */
 112 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \
 113                                   MLX5_ESEG_MIN_INLINE_SIZE - \
 114                                   MLX5_WQE_CSEG_SIZE - \
 115                                   MLX5_WQE_ESEG_SIZE - \
 116                                   MLX5_WQE_DSEG_SIZE)
 117 /*
 118  * Maximal inline data length sent with ordinary SEND.
 119  * Is based on maximal WQE size.
 120  */
 121 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
 122                                   MLX5_WQE_CSEG_SIZE - \
 123                                   MLX5_WQE_ESEG_SIZE - \
 124                                   MLX5_WQE_DSEG_SIZE + \
 125                                   MLX5_ESEG_MIN_INLINE_SIZE)
 126
 127 /* Missed in mlv5dv.h, should define here. */
 128 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u
 129
 130 /* CQE value to inform that VLAN is stripped. */
 131 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
 132
 133 /* IPv4 options. */
 134 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
 135
 136 /* IPv6 packet. */
 137 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
 138
 139 /* IPv4 packet. */
 140 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
 141
 142 /* TCP packet. */
 143 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
 144
 145 /* UDP packet. */
 146 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
 147
 148 /* IP is fragmented. */
 149 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
 150
 151 /* L2 header is valid. */
 152 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
 153
 154 /* L3 header is valid. */
 155 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
 156
 157 /* L4 header is valid. */
 158 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
 159
 160 /* Outer packet, 0 IPv4, 1 IPv6. */
 161 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
 162
 163 /* Tunnel packet bit in the CQE. */
 164 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
 165
 166 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
 167 #define MLX5_CQE_LRO_PUSH_MASK 0x40
 168
 169 /* Mask for L4 type in the CQE hdr_type_etc field. */
 170 #define MLX5_CQE_L4_TYPE_MASK 0x70
 171
 172 /* The bit index of L4 type in CQE hdr_type_etc field. */
 173 #define MLX5_CQE_L4_TYPE_SHIFT 0x4
 174
 175 /* L4 type to indicate TCP packet without acknowledgment. */
 176 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
 177
 178 /* L4 type to indicate TCP packet with acknowledgment. */
 179 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
 180
 181 /* Inner L3 checksum offload (Tunneled packets only). */
 182 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
 183
 184 /* Inner L4 checksum offload (Tunneled packets only). */
 185 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
 186
 187 /* Outer L4 type is TCP. */
 188 #define MLX5_ETH_WQE_L4_OUTER_TCP  (0u << 5)
 189
 190 /* Outer L4 type is UDP. */
 191 #define MLX5_ETH_WQE_L4_OUTER_UDP  (1u << 5)
 192
 193 /* Outer L3 type is IPV4. */
 194 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
 195
 196 /* Outer L3 type is IPV6. */
 197 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
 198
 199 /* Inner L4 type is TCP. */
 200 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
 201
 202 /* Inner L4 type is UDP. */
 203 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
 204
 205 /* Inner L3 type is IPV4. */
 206 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
 207
 208 /* Inner L3 type is IPV6. */
 209 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
 210
 211 /* VLAN insertion flag. */
 212 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31)
 213
 214 /* Data inline segment flag. */
 215 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31)
 216
 217 /* Is flow mark valid. */
 218 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
 219 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
 220 #else
 221 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
 222 #endif
 223
 224 /* INVALID is used by packets matching no flow rules. */
 225 #define MLX5_FLOW_MARK_INVALID 0
 226
 227 /* Maximum allowed value to mark a packet. */
 228 #define MLX5_FLOW_MARK_MAX 0xfffff0
 229
 230 /* Default mark value used when none is provided. */
 231 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
 232
 233 /* Default mark mask for metadata legacy mode. */
 234 #define MLX5_FLOW_MARK_MASK 0xffffff
 235
 236 /* Maximum number of DS in WQE. Limited by 6-bit field. */
 237 #define MLX5_DSEG_MAX 63
 238
 239 /* The completion mode offset in the WQE control segment line 2. */
 240 #define MLX5_COMP_MODE_OFFSET 2
 241
 242 /* Amount of data bytes in minimal inline data segment. */
 243 #define MLX5_DSEG_MIN_INLINE_SIZE 12u
 244
 245 /* Amount of data bytes in minimal inline eth segment. */
 246 #define MLX5_ESEG_MIN_INLINE_SIZE 18u
 247
 248 /* Amount of data bytes after eth data segment. */
 249 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
 250
 251 /* The maximum log value of segments per RQ WQE. */
 252 #define MLX5_MAX_LOG_RQ_SEGS 5u
 253
 254 /* The alignment needed for WQ buffer. */
 255 #define MLX5_WQE_BUF_ALIGNMENT 512
 256
 257 /* Completion mode. */
 258 enum mlx5_completion_mode {
 259         MLX5_COMP_ONLY_ERR = 0x0,
 260         MLX5_COMP_ONLY_FIRST_ERR = 0x1,
 261         MLX5_COMP_ALWAYS = 0x2,
 262         MLX5_COMP_CQE_AND_EQE = 0x3,
 263 };
 264
 265 /* MPW mode. */
 266 enum mlx5_mpw_mode {
 267         MLX5_MPW_DISABLED,
 268         MLX5_MPW,
 269         MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
 270 };
 271
 272 /* WQE Control segment. */
 273 struct mlx5_wqe_cseg {
 274         uint32_t opcode;
 275         uint32_t sq_ds;
 276         uint32_t flags;
 277         uint32_t misc;
 278 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
 279
 280 /* Header of data segment. Minimal size Data Segment */
 281 struct mlx5_wqe_dseg {
 282         uint32_t bcount;
 283         union {
 284                 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];
 285                 struct {
 286                         uint32_t lkey;
 287                         uint64_t pbuf;
 288                 } __rte_packed;
 289         };
 290 } __rte_packed;
 291
 292 /* Subset of struct WQE Ethernet Segment. */
 293 struct mlx5_wqe_eseg {
 294         union {
 295                 struct {
 296                         uint32_t swp_offs;
 297                         uint8_t cs_flags;
 298                         uint8_t swp_flags;
 299                         uint16_t mss;
 300                         uint32_t metadata;
 301                         uint16_t inline_hdr_sz;
 302                         union {
 303                                 uint16_t inline_data;
 304                                 uint16_t vlan_tag;
 305                         };
 306                 } __rte_packed;
 307                 struct {
 308                         uint32_t offsets;
 309                         uint32_t flags;
 310                         uint32_t flow_metadata;
 311                         uint32_t inline_hdr;
 312                 } __rte_packed;
 313         };
 314 } __rte_packed;
 315
 316 /* The title WQEBB, header of WQE. */
 317 struct mlx5_wqe {
 318         union {
 319                 struct mlx5_wqe_cseg cseg;
 320                 uint32_t ctrl[4];
 321         };
 322         struct mlx5_wqe_eseg eseg;
 323         union {
 324                 struct mlx5_wqe_dseg dseg[2];
 325                 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE];
 326         };
 327 } __rte_packed;
 328
 329 /* WQE for Multi-Packet RQ. */
 330 struct mlx5_wqe_mprq {
 331         struct mlx5_wqe_srq_next_seg next_seg;
 332         struct mlx5_wqe_data_seg dseg;
 333 };
 334
 335 #define MLX5_MPRQ_LEN_MASK 0x000ffff
 336 #define MLX5_MPRQ_LEN_SHIFT 0
 337 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
 338 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
 339 #define MLX5_MPRQ_FILLER_MASK 0x80000000
 340 #define MLX5_MPRQ_FILLER_SHIFT 31
 341
 342 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
 343
 344 /* CQ element structure - should be equal to the cache line size */
 345 struct mlx5_cqe {
 346 #if (RTE_CACHE_LINE_SIZE == 128)
 347         uint8_t padding[64];
 348 #endif
 349         uint8_t pkt_info;
 350         uint8_t rsvd0;
 351         uint16_t wqe_id;
 352         uint8_t lro_tcppsh_abort_dupack;
 353         uint8_t lro_min_ttl;
 354         uint16_t lro_tcp_win;
 355         uint32_t lro_ack_seq_num;
 356         uint32_t rx_hash_res;
 357         uint8_t rx_hash_type;
 358         uint8_t rsvd1[3];
 359         uint16_t csum;
 360         uint8_t rsvd2[6];
 361         uint16_t hdr_type_etc;
 362         uint16_t vlan_info;
 363         uint8_t lro_num_seg;
 364         uint8_t rsvd3[3];
 365         uint32_t flow_table_metadata;
 366         uint8_t rsvd4[4];
 367         uint32_t byte_cnt;
 368         uint64_t timestamp;
 369         uint32_t sop_drop_qpn;
 370         uint16_t wqe_counter;
 371         uint8_t rsvd5;
 372         uint8_t op_own;
 373 };
 374
 375 /* Adding direct verbs to data-path. */
 376
 377 /* CQ sequence number mask. */
 378 #define MLX5_CQ_SQN_MASK 0x3
 379
 380 /* CQ sequence number index. */
 381 #define MLX5_CQ_SQN_OFFSET 28
 382
 383 /* CQ doorbell index mask. */
 384 #define MLX5_CI_MASK 0xffffff
 385
 386 /* CQ doorbell offset. */
 387 #define MLX5_CQ_ARM_DB 1
 388
 389 /* CQ doorbell offset*/
 390 #define MLX5_CQ_DOORBELL 0x20
 391
 392 /* CQE format value. */
 393 #define MLX5_COMPRESSED 0x3
 394
 395 /* Action type of header modification. */
 396 enum {
 397         MLX5_MODIFICATION_TYPE_SET = 0x1,
 398         MLX5_MODIFICATION_TYPE_ADD = 0x2,
 399         MLX5_MODIFICATION_TYPE_COPY = 0x3,
 400 };
 401
 402 /* The field of packet to be modified. */
 403 enum mlx5_modification_field {
 404         MLX5_MODI_OUT_NONE = -1,
 405         MLX5_MODI_OUT_SMAC_47_16 = 1,
 406         MLX5_MODI_OUT_SMAC_15_0,
 407         MLX5_MODI_OUT_ETHERTYPE,
 408         MLX5_MODI_OUT_DMAC_47_16,
 409         MLX5_MODI_OUT_DMAC_15_0,
 410         MLX5_MODI_OUT_IP_DSCP,
 411         MLX5_MODI_OUT_TCP_FLAGS,
 412         MLX5_MODI_OUT_TCP_SPORT,
 413         MLX5_MODI_OUT_TCP_DPORT,
 414         MLX5_MODI_OUT_IPV4_TTL,
 415         MLX5_MODI_OUT_UDP_SPORT,
 416         MLX5_MODI_OUT_UDP_DPORT,
 417         MLX5_MODI_OUT_SIPV6_127_96,
 418         MLX5_MODI_OUT_SIPV6_95_64,
 419         MLX5_MODI_OUT_SIPV6_63_32,
 420         MLX5_MODI_OUT_SIPV6_31_0,
 421         MLX5_MODI_OUT_DIPV6_127_96,
 422         MLX5_MODI_OUT_DIPV6_95_64,
 423         MLX5_MODI_OUT_DIPV6_63_32,
 424         MLX5_MODI_OUT_DIPV6_31_0,
 425         MLX5_MODI_OUT_SIPV4,
 426         MLX5_MODI_OUT_DIPV4,
 427         MLX5_MODI_OUT_FIRST_VID,
 428         MLX5_MODI_IN_SMAC_47_16 = 0x31,
 429         MLX5_MODI_IN_SMAC_15_0,
 430         MLX5_MODI_IN_ETHERTYPE,
 431         MLX5_MODI_IN_DMAC_47_16,
 432         MLX5_MODI_IN_DMAC_15_0,
 433         MLX5_MODI_IN_IP_DSCP,
 434         MLX5_MODI_IN_TCP_FLAGS,
 435         MLX5_MODI_IN_TCP_SPORT,
 436         MLX5_MODI_IN_TCP_DPORT,
 437         MLX5_MODI_IN_IPV4_TTL,
 438         MLX5_MODI_IN_UDP_SPORT,
 439         MLX5_MODI_IN_UDP_DPORT,
 440         MLX5_MODI_IN_SIPV6_127_96,
 441         MLX5_MODI_IN_SIPV6_95_64,
 442         MLX5_MODI_IN_SIPV6_63_32,
 443         MLX5_MODI_IN_SIPV6_31_0,
 444         MLX5_MODI_IN_DIPV6_127_96,
 445         MLX5_MODI_IN_DIPV6_95_64,
 446         MLX5_MODI_IN_DIPV6_63_32,
 447         MLX5_MODI_IN_DIPV6_31_0,
 448         MLX5_MODI_IN_SIPV4,
 449         MLX5_MODI_IN_DIPV4,
 450         MLX5_MODI_OUT_IPV6_HOPLIMIT,
 451         MLX5_MODI_IN_IPV6_HOPLIMIT,
 452         MLX5_MODI_META_DATA_REG_A,
 453         MLX5_MODI_META_DATA_REG_B = 0x50,
 454         MLX5_MODI_META_REG_C_0,
 455         MLX5_MODI_META_REG_C_1,
 456         MLX5_MODI_META_REG_C_2,
 457         MLX5_MODI_META_REG_C_3,
 458         MLX5_MODI_META_REG_C_4,
 459         MLX5_MODI_META_REG_C_5,
 460         MLX5_MODI_META_REG_C_6,
 461         MLX5_MODI_META_REG_C_7,
 462         MLX5_MODI_OUT_TCP_SEQ_NUM,
 463         MLX5_MODI_IN_TCP_SEQ_NUM,
 464         MLX5_MODI_OUT_TCP_ACK_NUM,
 465         MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
 466 };
 467
 468 /* Total number of metadata reg_c's. */
 469 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1)
 470
 471 enum modify_reg {
 472         REG_NONE = 0,
 473         REG_A,
 474         REG_B,
 475         REG_C_0,
 476         REG_C_1,
 477         REG_C_2,
 478         REG_C_3,
 479         REG_C_4,
 480         REG_C_5,
 481         REG_C_6,
 482         REG_C_7,
 483 };
 484
 485 /* Modification sub command. */
 486 struct mlx5_modification_cmd {
 487         union {
 488                 uint32_t data0;
 489                 struct {
 490                         unsigned int length:5;
 491                         unsigned int rsvd0:3;
 492                         unsigned int offset:5;
 493                         unsigned int rsvd1:3;
 494                         unsigned int field:12;
 495                         unsigned int action_type:4;
 496                 };
 497         };
 498         union {
 499                 uint32_t data1;
 500                 uint8_t data[4];
 501                 struct {
 502                         unsigned int rsvd2:8;
 503                         unsigned int dst_offset:5;
 504                         unsigned int rsvd3:3;
 505                         unsigned int dst_field:12;
 506                         unsigned int rsvd4:4;
 507                 };
 508         };
 509 };
 510
 511 typedef uint32_t u32;
 512 typedef uint16_t u16;
 513 typedef uint8_t u8;
 514
 515 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
 516 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
 517 #define __mlx5_bit_off(typ, fld) ((unsigned int)(unsigned long) \
 518                                   (&(__mlx5_nullp(typ)->fld)))
 519 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
 520                                     (__mlx5_bit_off(typ, fld) & 0x1f))
 521 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
 522 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
 523 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
 524                                   __mlx5_dw_bit_off(typ, fld))
 525 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
 526 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
 527 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
 528                                     (__mlx5_bit_off(typ, fld) & 0xf))
 529 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
 530 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \
 531                                   __mlx5_16_bit_off(typ, fld))
 532 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
 533 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
 534 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
 535 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
 536
 537 /* insert a value to a struct */
 538 #define MLX5_SET(typ, p, fld, v) \
 539         do { \
 540                 u32 _v = v; \
 541                 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
 542                 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
 543                                   __mlx5_dw_off(typ, fld))) & \
 544                                   (~__mlx5_dw_mask(typ, fld))) | \
 545                                  (((_v) & __mlx5_mask(typ, fld)) << \
 546                                    __mlx5_dw_bit_off(typ, fld))); \
 547         } while (0)
 548
 549 #define MLX5_SET64(typ, p, fld, v) \
 550         do { \
 551                 assert(__mlx5_bit_sz(typ, fld) == 64); \
 552                 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = \
 553                         rte_cpu_to_be_64(v); \
 554         } while (0)
 555
 556 #define MLX5_SET16(typ, p, fld, v) \
 557         do { \
 558                 u16 _v = v; \
 559                 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
 560                 rte_cpu_to_be_16((rte_be_to_cpu_16(*((__be16 *)(p) + \
 561                                   __mlx5_16_off(typ, fld))) & \
 562                                   (~__mlx5_16_mask(typ, fld))) | \
 563                                  (((_v) & __mlx5_mask16(typ, fld)) << \
 564                                   __mlx5_16_bit_off(typ, fld))); \
 565         } while (0)
 566
 567 #define MLX5_GET(typ, p, fld) \
 568         ((rte_be_to_cpu_32(*((__be32 *)(p) +\
 569         __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
 570         __mlx5_mask(typ, fld))
 571 #define MLX5_GET16(typ, p, fld) \
 572         ((rte_be_to_cpu_16(*((__be16 *)(p) + \
 573           __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
 574          __mlx5_mask16(typ, fld))
 575 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((__be64 *)(p) + \
 576                                                    __mlx5_64_off(typ, fld)))
 577 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
 578
 579 struct mlx5_ifc_fte_match_set_misc_bits {
 580         u8 gre_c_present[0x1];
 581         u8 reserved_at_1[0x1];
 582         u8 gre_k_present[0x1];
 583         u8 gre_s_present[0x1];
 584         u8 source_vhci_port[0x4];
 585         u8 source_sqn[0x18];
 586         u8 reserved_at_20[0x10];
 587         u8 source_port[0x10];
 588         u8 outer_second_prio[0x3];
 589         u8 outer_second_cfi[0x1];
 590         u8 outer_second_vid[0xc];
 591         u8 inner_second_prio[0x3];
 592         u8 inner_second_cfi[0x1];
 593         u8 inner_second_vid[0xc];
 594         u8 outer_second_cvlan_tag[0x1];
 595         u8 inner_second_cvlan_tag[0x1];
 596         u8 outer_second_svlan_tag[0x1];
 597         u8 inner_second_svlan_tag[0x1];
 598         u8 reserved_at_64[0xc];
 599         u8 gre_protocol[0x10];
 600         u8 gre_key_h[0x18];
 601         u8 gre_key_l[0x8];
 602         u8 vxlan_vni[0x18];
 603         u8 reserved_at_b8[0x8];
 604         u8 geneve_vni[0x18];
 605         u8 reserved_at_e4[0x7];
 606         u8 geneve_oam[0x1];
 607         u8 reserved_at_e0[0xc];
 608         u8 outer_ipv6_flow_label[0x14];
 609         u8 reserved_at_100[0xc];
 610         u8 inner_ipv6_flow_label[0x14];
 611         u8 reserved_at_120[0xa];
 612         u8 geneve_opt_len[0x6];
 613         u8 geneve_protocol_type[0x10];
 614         u8 reserved_at_140[0xc0];
 615 };
 616
 617 struct mlx5_ifc_ipv4_layout_bits {
 618         u8 reserved_at_0[0x60];
 619         u8 ipv4[0x20];
 620 };
 621
 622 struct mlx5_ifc_ipv6_layout_bits {
 623         u8 ipv6[16][0x8];
 624 };
 625
 626 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 627         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 628         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 629         u8 reserved_at_0[0x80];
 630 };
 631
 632 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 633         u8 smac_47_16[0x20];
 634         u8 smac_15_0[0x10];
 635         u8 ethertype[0x10];
 636         u8 dmac_47_16[0x20];
 637         u8 dmac_15_0[0x10];
 638         u8 first_prio[0x3];
 639         u8 first_cfi[0x1];
 640         u8 first_vid[0xc];
 641         u8 ip_protocol[0x8];
 642         u8 ip_dscp[0x6];
 643         u8 ip_ecn[0x2];
 644         u8 cvlan_tag[0x1];
 645         u8 svlan_tag[0x1];
 646         u8 frag[0x1];
 647         u8 ip_version[0x4];
 648         u8 tcp_flags[0x9];
 649         u8 tcp_sport[0x10];
 650         u8 tcp_dport[0x10];
 651         u8 reserved_at_c0[0x20];
 652         u8 udp_sport[0x10];
 653         u8 udp_dport[0x10];
 654         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 655         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 656 };
 657
 658 struct mlx5_ifc_fte_match_mpls_bits {
 659         u8 mpls_label[0x14];
 660         u8 mpls_exp[0x3];
 661         u8 mpls_s_bos[0x1];
 662         u8 mpls_ttl[0x8];
 663 };
 664
 665 struct mlx5_ifc_fte_match_set_misc2_bits {
 666         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 667         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 668         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 669         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 670         u8 metadata_reg_c_7[0x20];
 671         u8 metadata_reg_c_6[0x20];
 672         u8 metadata_reg_c_5[0x20];
 673         u8 metadata_reg_c_4[0x20];
 674         u8 metadata_reg_c_3[0x20];
 675         u8 metadata_reg_c_2[0x20];
 676         u8 metadata_reg_c_1[0x20];
 677         u8 metadata_reg_c_0[0x20];
 678         u8 metadata_reg_a[0x20];
 679         u8 metadata_reg_b[0x20];
 680         u8 reserved_at_1c0[0x40];
 681 };
 682
 683 struct mlx5_ifc_fte_match_set_misc3_bits {
 684         u8 inner_tcp_seq_num[0x20];
 685         u8 outer_tcp_seq_num[0x20];
 686         u8 inner_tcp_ack_num[0x20];
 687         u8 outer_tcp_ack_num[0x20];
 688         u8 reserved_at_auto1[0x8];
 689         u8 outer_vxlan_gpe_vni[0x18];
 690         u8 outer_vxlan_gpe_next_protocol[0x8];
 691         u8 outer_vxlan_gpe_flags[0x8];
 692         u8 reserved_at_a8[0x10];
 693         u8 icmp_header_data[0x20];
 694         u8 icmpv6_header_data[0x20];
 695         u8 icmp_type[0x8];
 696         u8 icmp_code[0x8];
 697         u8 icmpv6_type[0x8];
 698         u8 icmpv6_code[0x8];
 699         u8 reserved_at_120[0x20];
 700         u8 gtpu_teid[0x20];
 701         u8 gtpu_msg_type[0x08];
 702         u8 gtpu_msg_flags[0x08];
 703         u8 reserved_at_170[0x90];
 704 };
 705
 706 /* Flow matcher. */
 707 struct mlx5_ifc_fte_match_param_bits {
 708         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
 709         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
 710         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
 711         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
 712         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
 713 };
 714
 715 enum {
 716         MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
 717         MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
 718         MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
 719         MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
 720         MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT
 721 };
 722
 723 enum {
 724         MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
 725         MLX5_CMD_OP_CREATE_MKEY = 0x200,
 726         MLX5_CMD_OP_CREATE_CQ = 0x400,
 727         MLX5_CMD_OP_CREATE_QP = 0x500,
 728         MLX5_CMD_OP_RST2INIT_QP = 0x502,
 729         MLX5_CMD_OP_INIT2RTR_QP = 0x503,
 730         MLX5_CMD_OP_RTR2RTS_QP = 0x504,
 731         MLX5_CMD_OP_RTS2RTS_QP = 0x505,
 732         MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
 733         MLX5_CMD_OP_QP_2ERR = 0x507,
 734         MLX5_CMD_OP_QP_2RST = 0x50A,
 735         MLX5_CMD_OP_QUERY_QP = 0x50B,
 736         MLX5_CMD_OP_SQD2RTS_QP = 0x50C,
 737         MLX5_CMD_OP_INIT2INIT_QP = 0x50E,
 738         MLX5_CMD_OP_SUSPEND_QP = 0x50F,
 739         MLX5_CMD_OP_RESUME_QP = 0x510,
 740         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
 741         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
 742         MLX5_CMD_OP_CREATE_TIR = 0x900,
 743         MLX5_CMD_OP_CREATE_SQ = 0X904,
 744         MLX5_CMD_OP_MODIFY_SQ = 0X905,
 745         MLX5_CMD_OP_CREATE_RQ = 0x908,
 746         MLX5_CMD_OP_MODIFY_RQ = 0x909,
 747         MLX5_CMD_OP_CREATE_TIS = 0x912,
 748         MLX5_CMD_OP_QUERY_TIS = 0x915,
 749         MLX5_CMD_OP_CREATE_RQT = 0x916,
 750         MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
 751         MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
 752         MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
 753         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
 754         MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
 755 };
 756
 757 enum {
 758         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
 759         MLX5_MKC_ACCESS_MODE_KLM   = 0x2,
 760         MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3,
 761 };
 762
 763 #define MLX5_ADAPTER_PAGE_SHIFT 12
 764 #define MLX5_LOG_RQ_STRIDE_SHIFT 4
 765
 766 /* Flow counters. */
 767 struct mlx5_ifc_alloc_flow_counter_out_bits {
 768         u8         status[0x8];
 769         u8         reserved_at_8[0x18];
 770         u8         syndrome[0x20];
 771         u8         flow_counter_id[0x20];
 772         u8         reserved_at_60[0x20];
 773 };
 774
 775 struct mlx5_ifc_alloc_flow_counter_in_bits {
 776         u8         opcode[0x10];
 777         u8         reserved_at_10[0x10];
 778         u8         reserved_at_20[0x10];
 779         u8         op_mod[0x10];
 780         u8         flow_counter_id[0x20];
 781         u8         reserved_at_40[0x18];
 782         u8         flow_counter_bulk[0x8];
 783 };
 784
 785 struct mlx5_ifc_dealloc_flow_counter_out_bits {
 786         u8         status[0x8];
 787         u8         reserved_at_8[0x18];
 788         u8         syndrome[0x20];
 789         u8         reserved_at_40[0x40];
 790 };
 791
 792 struct mlx5_ifc_dealloc_flow_counter_in_bits {
 793         u8         opcode[0x10];
 794         u8         reserved_at_10[0x10];
 795         u8         reserved_at_20[0x10];
 796         u8         op_mod[0x10];
 797         u8         flow_counter_id[0x20];
 798         u8         reserved_at_60[0x20];
 799 };
 800
 801 struct mlx5_ifc_traffic_counter_bits {
 802         u8         packets[0x40];
 803         u8         octets[0x40];
 804 };
 805
 806 struct mlx5_ifc_query_flow_counter_out_bits {
 807         u8         status[0x8];
 808         u8         reserved_at_8[0x18];
 809         u8         syndrome[0x20];
 810         u8         reserved_at_40[0x40];
 811         struct mlx5_ifc_traffic_counter_bits flow_statistics[];
 812 };
 813
 814 struct mlx5_ifc_query_flow_counter_in_bits {
 815         u8         opcode[0x10];
 816         u8         reserved_at_10[0x10];
 817         u8         reserved_at_20[0x10];
 818         u8         op_mod[0x10];
 819         u8         reserved_at_40[0x20];
 820         u8         mkey[0x20];
 821         u8         address[0x40];
 822         u8         clear[0x1];
 823         u8         dump_to_memory[0x1];
 824         u8         num_of_counters[0x1e];
 825         u8         flow_counter_id[0x20];
 826 };
 827
 828 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u
 829 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u
 830
 831
 832 struct mlx5_ifc_klm_bits {
 833         u8         byte_count[0x20];
 834         u8         mkey[0x20];
 835         u8         address[0x40];
 836 };
 837
 838 struct mlx5_ifc_mkc_bits {
 839         u8         reserved_at_0[0x1];
 840         u8         free[0x1];
 841         u8         reserved_at_2[0x1];
 842         u8         access_mode_4_2[0x3];
 843         u8         reserved_at_6[0x7];
 844         u8         relaxed_ordering_write[0x1];
 845         u8         reserved_at_e[0x1];
 846         u8         small_fence_on_rdma_read_response[0x1];
 847         u8         umr_en[0x1];
 848         u8         a[0x1];
 849         u8         rw[0x1];
 850         u8         rr[0x1];
 851         u8         lw[0x1];
 852         u8         lr[0x1];
 853         u8         access_mode_1_0[0x2];
 854         u8         reserved_at_18[0x8];
 855
 856         u8         qpn[0x18];
 857         u8         mkey_7_0[0x8];
 858
 859         u8         reserved_at_40[0x20];
 860
 861         u8         length64[0x1];
 862         u8         bsf_en[0x1];
 863         u8         sync_umr[0x1];
 864         u8         reserved_at_63[0x2];
 865         u8         expected_sigerr_count[0x1];
 866         u8         reserved_at_66[0x1];
 867         u8         en_rinval[0x1];
 868         u8         pd[0x18];
 869
 870         u8         start_addr[0x40];
 871
 872         u8         len[0x40];
 873
 874         u8         bsf_octword_size[0x20];
 875
 876         u8         reserved_at_120[0x80];
 877
 878         u8         translations_octword_size[0x20];
 879
 880         u8         reserved_at_1c0[0x1b];
 881         u8         log_page_size[0x5];
 882
 883         u8         reserved_at_1e0[0x20];
 884 };
 885
 886 struct mlx5_ifc_create_mkey_out_bits {
 887         u8         status[0x8];
 888         u8         reserved_at_8[0x18];
 889
 890         u8         syndrome[0x20];
 891
 892         u8         reserved_at_40[0x8];
 893         u8         mkey_index[0x18];
 894
 895         u8         reserved_at_60[0x20];
 896 };
 897
 898 struct mlx5_ifc_create_mkey_in_bits {
 899         u8         opcode[0x10];
 900         u8         reserved_at_10[0x10];
 901
 902         u8         reserved_at_20[0x10];
 903         u8         op_mod[0x10];
 904
 905         u8         reserved_at_40[0x20];
 906
 907         u8         pg_access[0x1];
 908         u8         reserved_at_61[0x1f];
 909
 910         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
 911
 912         u8         reserved_at_280[0x80];
 913
 914         u8         translations_octword_actual_size[0x20];
 915
 916         u8         mkey_umem_id[0x20];
 917
 918         u8         mkey_umem_offset[0x40];
 919
 920         u8         reserved_at_380[0x500];
 921
 922         u8         klm_pas_mtt[][0x20];
 923 };
 924
 925 enum {
 926         MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
 927         MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
 928         MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
 929         MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
 930 };
 931
 932 enum {
 933         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q = (1ULL << 0xd),
 934 };
 935
 936 enum {
 937         MLX5_HCA_CAP_OPMOD_GET_MAX   = 0,
 938         MLX5_HCA_CAP_OPMOD_GET_CUR   = 1,
 939 };
 940
 941 enum {
 942         MLX5_CAP_INLINE_MODE_L2,
 943         MLX5_CAP_INLINE_MODE_VPORT_CONTEXT,
 944         MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
 945 };
 946
 947 enum {
 948         MLX5_INLINE_MODE_NONE,
 949         MLX5_INLINE_MODE_L2,
 950         MLX5_INLINE_MODE_IP,
 951         MLX5_INLINE_MODE_TCP_UDP,
 952         MLX5_INLINE_MODE_RESERVED4,
 953         MLX5_INLINE_MODE_INNER_L2,
 954         MLX5_INLINE_MODE_INNER_IP,
 955         MLX5_INLINE_MODE_INNER_TCP_UDP,
 956 };
 957
 958 /* HCA bit masks indicating which Flex parser protocols are already enabled. */
 959 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0)
 960 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1)
 961 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2)
 962 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3)
 963 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4)
 964 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5)
 965 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6)
 966 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7)
 967 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8)
 968 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)
 969
 970 struct mlx5_ifc_cmd_hca_cap_bits {
 971         u8 reserved_at_0[0x30];
 972         u8 vhca_id[0x10];
 973         u8 reserved_at_40[0x40];
 974         u8 log_max_srq_sz[0x8];
 975         u8 log_max_qp_sz[0x8];
 976         u8 reserved_at_90[0xb];
 977         u8 log_max_qp[0x5];
 978         u8 reserved_at_a0[0xb];
 979         u8 log_max_srq[0x5];
 980         u8 reserved_at_b0[0x10];
 981         u8 reserved_at_c0[0x8];
 982         u8 log_max_cq_sz[0x8];
 983         u8 reserved_at_d0[0xb];
 984         u8 log_max_cq[0x5];
 985         u8 log_max_eq_sz[0x8];
 986         u8 reserved_at_e8[0x2];
 987         u8 log_max_mkey[0x6];
 988         u8 reserved_at_f0[0x8];
 989         u8 dump_fill_mkey[0x1];
 990         u8 reserved_at_f9[0x3];
 991         u8 log_max_eq[0x4];
 992         u8 max_indirection[0x8];
 993         u8 fixed_buffer_size[0x1];
 994         u8 log_max_mrw_sz[0x7];
 995         u8 force_teardown[0x1];
 996         u8 reserved_at_111[0x1];
 997         u8 log_max_bsf_list_size[0x6];
 998         u8 umr_extended_translation_offset[0x1];
 999         u8 null_mkey[0x1];
1000         u8 log_max_klm_list_size[0x6];
1001         u8 reserved_at_120[0xa];
1002         u8 log_max_ra_req_dc[0x6];
1003         u8 reserved_at_130[0xa];
1004         u8 log_max_ra_res_dc[0x6];
1005         u8 reserved_at_140[0xa];
1006         u8 log_max_ra_req_qp[0x6];
1007         u8 reserved_at_150[0xa];
1008         u8 log_max_ra_res_qp[0x6];
1009         u8 end_pad[0x1];
1010         u8 cc_query_allowed[0x1];
1011         u8 cc_modify_allowed[0x1];
1012         u8 start_pad[0x1];
1013         u8 cache_line_128byte[0x1];
1014         u8 reserved_at_165[0xa];
1015         u8 qcam_reg[0x1];
1016         u8 gid_table_size[0x10];
1017         u8 out_of_seq_cnt[0x1];
1018         u8 vport_counters[0x1];
1019         u8 retransmission_q_counters[0x1];
1020         u8 debug[0x1];
1021         u8 modify_rq_counter_set_id[0x1];
1022         u8 rq_delay_drop[0x1];
1023         u8 max_qp_cnt[0xa];
1024         u8 pkey_table_size[0x10];
1025         u8 vport_group_manager[0x1];
1026         u8 vhca_group_manager[0x1];
1027         u8 ib_virt[0x1];
1028         u8 eth_virt[0x1];
1029         u8 vnic_env_queue_counters[0x1];
1030         u8 ets[0x1];
1031         u8 nic_flow_table[0x1];
1032         u8 eswitch_manager[0x1];
1033         u8 device_memory[0x1];
1034         u8 mcam_reg[0x1];
1035         u8 pcam_reg[0x1];
1036         u8 local_ca_ack_delay[0x5];
1037         u8 port_module_event[0x1];
1038         u8 enhanced_error_q_counters[0x1];
1039         u8 ports_check[0x1];
1040         u8 reserved_at_1b3[0x1];
1041         u8 disable_link_up[0x1];
1042         u8 beacon_led[0x1];
1043         u8 port_type[0x2];
1044         u8 num_ports[0x8];
1045         u8 reserved_at_1c0[0x1];
1046         u8 pps[0x1];
1047         u8 pps_modify[0x1];
1048         u8 log_max_msg[0x5];
1049         u8 reserved_at_1c8[0x4];
1050         u8 max_tc[0x4];
1051         u8 temp_warn_event[0x1];
1052         u8 dcbx[0x1];
1053         u8 general_notification_event[0x1];
1054         u8 reserved_at_1d3[0x2];
1055         u8 fpga[0x1];
1056         u8 rol_s[0x1];
1057         u8 rol_g[0x1];
1058         u8 reserved_at_1d8[0x1];
1059         u8 wol_s[0x1];
1060         u8 wol_g[0x1];
1061         u8 wol_a[0x1];
1062         u8 wol_b[0x1];
1063         u8 wol_m[0x1];
1064         u8 wol_u[0x1];
1065         u8 wol_p[0x1];
1066         u8 stat_rate_support[0x10];
1067         u8 reserved_at_1f0[0xc];
1068         u8 cqe_version[0x4];
1069         u8 compact_address_vector[0x1];
1070         u8 striding_rq[0x1];
1071         u8 reserved_at_202[0x1];
1072         u8 ipoib_enhanced_offloads[0x1];
1073         u8 ipoib_basic_offloads[0x1];
1074         u8 reserved_at_205[0x1];
1075         u8 repeated_block_disabled[0x1];
1076         u8 umr_modify_entity_size_disabled[0x1];
1077         u8 umr_modify_atomic_disabled[0x1];
1078         u8 umr_indirect_mkey_disabled[0x1];
1079         u8 umr_fence[0x2];
1080         u8 reserved_at_20c[0x3];
1081         u8 drain_sigerr[0x1];
1082         u8 cmdif_checksum[0x2];
1083         u8 sigerr_cqe[0x1];
1084         u8 reserved_at_213[0x1];
1085         u8 wq_signature[0x1];
1086         u8 sctr_data_cqe[0x1];
1087         u8 reserved_at_216[0x1];
1088         u8 sho[0x1];
1089         u8 tph[0x1];
1090         u8 rf[0x1];
1091         u8 dct[0x1];
1092         u8 qos[0x1];
1093         u8 eth_net_offloads[0x1];
1094         u8 roce[0x1];
1095         u8 atomic[0x1];
1096         u8 reserved_at_21f[0x1];
1097         u8 cq_oi[0x1];
1098         u8 cq_resize[0x1];
1099         u8 cq_moderation[0x1];
1100         u8 reserved_at_223[0x3];
1101         u8 cq_eq_remap[0x1];
1102         u8 pg[0x1];
1103         u8 block_lb_mc[0x1];
1104         u8 reserved_at_229[0x1];
1105         u8 scqe_break_moderation[0x1];
1106         u8 cq_period_start_from_cqe[0x1];
1107         u8 cd[0x1];
1108         u8 reserved_at_22d[0x1];
1109         u8 apm[0x1];
1110         u8 vector_calc[0x1];
1111         u8 umr_ptr_rlky[0x1];
1112         u8 imaicl[0x1];
1113         u8 reserved_at_232[0x4];
1114         u8 qkv[0x1];
1115         u8 pkv[0x1];
1116         u8 set_deth_sqpn[0x1];
1117         u8 reserved_at_239[0x3];
1118         u8 xrc[0x1];
1119         u8 ud[0x1];
1120         u8 uc[0x1];
1121         u8 rc[0x1];
1122         u8 uar_4k[0x1];
1123         u8 reserved_at_241[0x9];
1124         u8 uar_sz[0x6];
1125         u8 reserved_at_250[0x8];
1126         u8 log_pg_sz[0x8];
1127         u8 bf[0x1];
1128         u8 driver_version[0x1];
1129         u8 pad_tx_eth_packet[0x1];
1130         u8 reserved_at_263[0x8];
1131         u8 log_bf_reg_size[0x5];
1132         u8 reserved_at_270[0xb];
1133         u8 lag_master[0x1];
1134         u8 num_lag_ports[0x4];
1135         u8 reserved_at_280[0x10];
1136         u8 max_wqe_sz_sq[0x10];
1137         u8 reserved_at_2a0[0x10];
1138         u8 max_wqe_sz_rq[0x10];
1139         u8 max_flow_counter_31_16[0x10];
1140         u8 max_wqe_sz_sq_dc[0x10];
1141         u8 reserved_at_2e0[0x7];
1142         u8 max_qp_mcg[0x19];
1143         u8 reserved_at_300[0x10];
1144         u8 flow_counter_bulk_alloc[0x08];
1145         u8 log_max_mcg[0x8];
1146         u8 reserved_at_320[0x3];
1147         u8 log_max_transport_domain[0x5];
1148         u8 reserved_at_328[0x3];
1149         u8 log_max_pd[0x5];
1150         u8 reserved_at_330[0xb];
1151         u8 log_max_xrcd[0x5];
1152         u8 nic_receive_steering_discard[0x1];
1153         u8 receive_discard_vport_down[0x1];
1154         u8 transmit_discard_vport_down[0x1];
1155         u8 reserved_at_343[0x5];
1156         u8 log_max_flow_counter_bulk[0x8];
1157         u8 max_flow_counter_15_0[0x10];
1158         u8 modify_tis[0x1];
1159         u8 flow_counters_dump[0x1];
1160         u8 reserved_at_360[0x1];
1161         u8 log_max_rq[0x5];
1162         u8 reserved_at_368[0x3];
1163         u8 log_max_sq[0x5];
1164         u8 reserved_at_370[0x3];
1165         u8 log_max_tir[0x5];
1166         u8 reserved_at_378[0x3];
1167         u8 log_max_tis[0x5];
1168         u8 basic_cyclic_rcv_wqe[0x1];
1169         u8 reserved_at_381[0x2];
1170         u8 log_max_rmp[0x5];
1171         u8 reserved_at_388[0x3];
1172         u8 log_max_rqt[0x5];
1173         u8 reserved_at_390[0x3];
1174         u8 log_max_rqt_size[0x5];
1175         u8 reserved_at_398[0x3];
1176         u8 log_max_tis_per_sq[0x5];
1177         u8 ext_stride_num_range[0x1];
1178         u8 reserved_at_3a1[0x2];
1179         u8 log_max_stride_sz_rq[0x5];
1180         u8 reserved_at_3a8[0x3];
1181         u8 log_min_stride_sz_rq[0x5];
1182         u8 reserved_at_3b0[0x3];
1183         u8 log_max_stride_sz_sq[0x5];
1184         u8 reserved_at_3b8[0x3];
1185         u8 log_min_stride_sz_sq[0x5];
1186         u8 hairpin[0x1];
1187         u8 reserved_at_3c1[0x2];
1188         u8 log_max_hairpin_queues[0x5];
1189         u8 reserved_at_3c8[0x3];
1190         u8 log_max_hairpin_wq_data_sz[0x5];
1191         u8 reserved_at_3d0[0x3];
1192         u8 log_max_hairpin_num_packets[0x5];
1193         u8 reserved_at_3d8[0x3];
1194         u8 log_max_wq_sz[0x5];
1195         u8 nic_vport_change_event[0x1];
1196         u8 disable_local_lb_uc[0x1];
1197         u8 disable_local_lb_mc[0x1];
1198         u8 log_min_hairpin_wq_data_sz[0x5];
1199         u8 reserved_at_3e8[0x3];
1200         u8 log_max_vlan_list[0x5];
1201         u8 reserved_at_3f0[0x3];
1202         u8 log_max_current_mc_list[0x5];
1203         u8 reserved_at_3f8[0x3];
1204         u8 log_max_current_uc_list[0x5];
1205         u8 general_obj_types[0x40];
1206         u8 reserved_at_440[0x20];
1207         u8 reserved_at_460[0x10];
1208         u8 max_num_eqs[0x10];
1209         u8 reserved_at_480[0x3];
1210         u8 log_max_l2_table[0x5];
1211         u8 reserved_at_488[0x8];
1212         u8 log_uar_page_sz[0x10];
1213         u8 reserved_at_4a0[0x20];
1214         u8 device_frequency_mhz[0x20];
1215         u8 device_frequency_khz[0x20];
1216         u8 reserved_at_500[0x20];
1217         u8 num_of_uars_per_page[0x20];
1218         u8 flex_parser_protocols[0x20];
1219         u8 reserved_at_560[0x20];
1220         u8 reserved_at_580[0x3c];
1221         u8 mini_cqe_resp_stride_index[0x1];
1222         u8 cqe_128_always[0x1];
1223         u8 cqe_compression_128[0x1];
1224         u8 cqe_compression[0x1];
1225         u8 cqe_compression_timeout[0x10];
1226         u8 cqe_compression_max_num[0x10];
1227         u8 reserved_at_5e0[0x10];
1228         u8 tag_matching[0x1];
1229         u8 rndv_offload_rc[0x1];
1230         u8 rndv_offload_dc[0x1];
1231         u8 log_tag_matching_list_sz[0x5];
1232         u8 reserved_at_5f8[0x3];
1233         u8 log_max_xrq[0x5];
1234         u8 affiliate_nic_vport_criteria[0x8];
1235         u8 native_port_num[0x8];
1236         u8 num_vhca_ports[0x8];
1237         u8 reserved_at_618[0x6];
1238         u8 sw_owner_id[0x1];
1239         u8 reserved_at_61f[0x1e1];
1240 };
1241
1242 struct mlx5_ifc_qos_cap_bits {
1243         u8 packet_pacing[0x1];
1244         u8 esw_scheduling[0x1];
1245         u8 esw_bw_share[0x1];
1246         u8 esw_rate_limit[0x1];
1247         u8 reserved_at_4[0x1];
1248         u8 packet_pacing_burst_bound[0x1];
1249         u8 packet_pacing_typical_size[0x1];
1250         u8 flow_meter_srtcm[0x1];
1251         u8 reserved_at_8[0x8];
1252         u8 log_max_flow_meter[0x8];
1253         u8 flow_meter_reg_id[0x8];
1254         u8 reserved_at_25[0x8];
1255         u8 flow_meter_reg_share[0x1];
1256         u8 reserved_at_2e[0x17];
1257         u8 packet_pacing_max_rate[0x20];
1258         u8 packet_pacing_min_rate[0x20];
1259         u8 reserved_at_80[0x10];
1260         u8 packet_pacing_rate_table_size[0x10];
1261         u8 esw_element_type[0x10];
1262         u8 esw_tsar_type[0x10];
1263         u8 reserved_at_c0[0x10];
1264         u8 max_qos_para_vport[0x10];
1265         u8 max_tsar_bw_share[0x20];
1266         u8 reserved_at_100[0x6e8];
1267 };
1268
1269 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1270         u8 csum_cap[0x1];
1271         u8 vlan_cap[0x1];
1272         u8 lro_cap[0x1];
1273         u8 lro_psh_flag[0x1];
1274         u8 lro_time_stamp[0x1];
1275         u8 lro_max_msg_sz_mode[0x2];
1276         u8 wqe_vlan_insert[0x1];
1277         u8 self_lb_en_modifiable[0x1];
1278         u8 self_lb_mc[0x1];
1279         u8 self_lb_uc[0x1];
1280         u8 max_lso_cap[0x5];
1281         u8 multi_pkt_send_wqe[0x2];
1282         u8 wqe_inline_mode[0x2];
1283         u8 rss_ind_tbl_cap[0x4];
1284         u8 reg_umr_sq[0x1];
1285         u8 scatter_fcs[0x1];
1286         u8 enhanced_multi_pkt_send_wqe[0x1];
1287         u8 tunnel_lso_const_out_ip_id[0x1];
1288         u8 tunnel_lro_gre[0x1];
1289         u8 tunnel_lro_vxlan[0x1];
1290         u8 tunnel_stateless_gre[0x1];
1291         u8 tunnel_stateless_vxlan[0x1];
1292         u8 swp[0x1];
1293         u8 swp_csum[0x1];
1294         u8 swp_lso[0x1];
1295         u8 reserved_at_23[0x8];
1296         u8 tunnel_stateless_gtp[0x1];
1297         u8 reserved_at_25[0x4];
1298         u8 max_vxlan_udp_ports[0x8];
1299         u8 reserved_at_38[0x6];
1300         u8 max_geneve_opt_len[0x1];
1301         u8 tunnel_stateless_geneve_rx[0x1];
1302         u8 reserved_at_40[0x10];
1303         u8 lro_min_mss_size[0x10];
1304         u8 reserved_at_60[0x120];
1305         u8 lro_timer_supported_periods[4][0x20];
1306         u8 reserved_at_200[0x600];
1307 };
1308
1309 enum {
1310         MLX5_VIRTQ_TYPE_SPLIT = 0,
1311         MLX5_VIRTQ_TYPE_PACKED = 1,
1312 };
1313
1314 enum {
1315         MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0,
1316         MLX5_VIRTQ_EVENT_MODE_QP = 1,
1317         MLX5_VIRTQ_EVENT_MODE_MSIX = 2,
1318 };
1319
1320 struct mlx5_ifc_virtio_emulation_cap_bits {
1321         u8 desc_tunnel_offload_type[0x1];
1322         u8 eth_frame_offload_type[0x1];
1323         u8 virtio_version_1_0[0x1];
1324         u8 tso_ipv4[0x1];
1325         u8 tso_ipv6[0x1];
1326         u8 tx_csum[0x1];
1327         u8 rx_csum[0x1];
1328         u8 reserved_at_7[0x1][0x9];
1329         u8 event_mode[0x8];
1330         u8 virtio_queue_type[0x8];
1331         u8 reserved_at_20[0x13];
1332         u8 log_doorbell_stride[0x5];
1333         u8 reserved_at_3b[0x3];
1334         u8 log_doorbell_bar_size[0x5];
1335         u8 doorbell_bar_offset[0x40];
1336         u8 reserved_at_80[0x8];
1337         u8 max_num_virtio_queues[0x18];
1338         u8 reserved_at_a0[0x60];
1339         u8 umem_1_buffer_param_a[0x20];
1340         u8 umem_1_buffer_param_b[0x20];
1341         u8 umem_2_buffer_param_a[0x20];
1342         u8 umem_2_buffer_param_b[0x20];
1343         u8 umem_3_buffer_param_a[0x20];
1344         u8 umem_3_buffer_param_b[0x20];
1345         u8 reserved_at_1c0[0x620];
1346 };
1347
1348 union mlx5_ifc_hca_cap_union_bits {
1349         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1350         struct mlx5_ifc_per_protocol_networking_offload_caps_bits
1351                per_protocol_networking_offload_caps;
1352         struct mlx5_ifc_qos_cap_bits qos_cap;
1353         struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;
1354         u8 reserved_at_0[0x8000];
1355 };
1356
1357 struct mlx5_ifc_query_hca_cap_out_bits {
1358         u8 status[0x8];
1359         u8 reserved_at_8[0x18];
1360         u8 syndrome[0x20];
1361         u8 reserved_at_40[0x40];
1362         union mlx5_ifc_hca_cap_union_bits capability;
1363 };
1364
1365 struct mlx5_ifc_query_hca_cap_in_bits {
1366         u8 opcode[0x10];
1367         u8 reserved_at_10[0x10];
1368         u8 reserved_at_20[0x10];
1369         u8 op_mod[0x10];
1370         u8 reserved_at_40[0x40];
1371 };
1372
1373 struct mlx5_ifc_mac_address_layout_bits {
1374         u8 reserved_at_0[0x10];
1375         u8 mac_addr_47_32[0x10];
1376         u8 mac_addr_31_0[0x20];
1377 };
1378
1379 struct mlx5_ifc_nic_vport_context_bits {
1380         u8 reserved_at_0[0x5];
1381         u8 min_wqe_inline_mode[0x3];
1382         u8 reserved_at_8[0x15];
1383         u8 disable_mc_local_lb[0x1];
1384         u8 disable_uc_local_lb[0x1];
1385         u8 roce_en[0x1];
1386         u8 arm_change_event[0x1];
1387         u8 reserved_at_21[0x1a];
1388         u8 event_on_mtu[0x1];
1389         u8 event_on_promisc_change[0x1];
1390         u8 event_on_vlan_change[0x1];
1391         u8 event_on_mc_address_change[0x1];
1392         u8 event_on_uc_address_change[0x1];
1393         u8 reserved_at_40[0xc];
1394         u8 affiliation_criteria[0x4];
1395         u8 affiliated_vhca_id[0x10];
1396         u8 reserved_at_60[0xd0];
1397         u8 mtu[0x10];
1398         u8 system_image_guid[0x40];
1399         u8 port_guid[0x40];
1400         u8 node_guid[0x40];
1401         u8 reserved_at_200[0x140];
1402         u8 qkey_violation_counter[0x10];
1403         u8 reserved_at_350[0x430];
1404         u8 promisc_uc[0x1];
1405         u8 promisc_mc[0x1];
1406         u8 promisc_all[0x1];
1407         u8 reserved_at_783[0x2];
1408         u8 allowed_list_type[0x3];
1409         u8 reserved_at_788[0xc];
1410         u8 allowed_list_size[0xc];
1411         struct mlx5_ifc_mac_address_layout_bits permanent_address;
1412         u8 reserved_at_7e0[0x20];
1413 };
1414
1415 struct mlx5_ifc_query_nic_vport_context_out_bits {
1416         u8 status[0x8];
1417         u8 reserved_at_8[0x18];
1418         u8 syndrome[0x20];
1419         u8 reserved_at_40[0x40];
1420         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
1421 };
1422
1423 struct mlx5_ifc_query_nic_vport_context_in_bits {
1424         u8 opcode[0x10];
1425         u8 reserved_at_10[0x10];
1426         u8 reserved_at_20[0x10];
1427         u8 op_mod[0x10];
1428         u8 other_vport[0x1];
1429         u8 reserved_at_41[0xf];
1430         u8 vport_number[0x10];
1431         u8 reserved_at_60[0x5];
1432         u8 allowed_list_type[0x3];
1433         u8 reserved_at_68[0x18];
1434 };
1435
1436 struct mlx5_ifc_tisc_bits {
1437         u8 strict_lag_tx_port_affinity[0x1];
1438         u8 reserved_at_1[0x3];
1439         u8 lag_tx_port_affinity[0x04];
1440         u8 reserved_at_8[0x4];
1441         u8 prio[0x4];
1442         u8 reserved_at_10[0x10];
1443         u8 reserved_at_20[0x100];
1444         u8 reserved_at_120[0x8];
1445         u8 transport_domain[0x18];
1446         u8 reserved_at_140[0x8];
1447         u8 underlay_qpn[0x18];
1448         u8 reserved_at_160[0x3a0];
1449 };
1450
1451 struct mlx5_ifc_query_tis_out_bits {
1452         u8 status[0x8];
1453         u8 reserved_at_8[0x18];
1454         u8 syndrome[0x20];
1455         u8 reserved_at_40[0x40];
1456         struct mlx5_ifc_tisc_bits tis_context;
1457 };
1458
1459 struct mlx5_ifc_query_tis_in_bits {
1460         u8 opcode[0x10];
1461         u8 reserved_at_10[0x10];
1462         u8 reserved_at_20[0x10];
1463         u8 op_mod[0x10];
1464         u8 reserved_at_40[0x8];
1465         u8 tisn[0x18];
1466         u8 reserved_at_60[0x20];
1467 };
1468
1469 struct mlx5_ifc_alloc_transport_domain_out_bits {
1470         u8 status[0x8];
1471         u8 reserved_at_8[0x18];
1472         u8 syndrome[0x20];
1473         u8 reserved_at_40[0x8];
1474         u8 transport_domain[0x18];
1475         u8 reserved_at_60[0x20];
1476 };
1477
1478 struct mlx5_ifc_alloc_transport_domain_in_bits {
1479         u8 opcode[0x10];
1480         u8 reserved_at_10[0x10];
1481         u8 reserved_at_20[0x10];
1482         u8 op_mod[0x10];
1483         u8 reserved_at_40[0x40];
1484 };
1485
1486 enum {
1487         MLX5_WQ_TYPE_LINKED_LIST                = 0x0,
1488         MLX5_WQ_TYPE_CYCLIC                     = 0x1,
1489         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ    = 0x2,
1490         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ         = 0x3,
1491 };
1492
1493 enum {
1494         MLX5_WQ_END_PAD_MODE_NONE  = 0x0,
1495         MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1496 };
1497
1498 struct mlx5_ifc_wq_bits {
1499         u8 wq_type[0x4];
1500         u8 wq_signature[0x1];
1501         u8 end_padding_mode[0x2];
1502         u8 cd_slave[0x1];
1503         u8 reserved_at_8[0x18];
1504         u8 hds_skip_first_sge[0x1];
1505         u8 log2_hds_buf_size[0x3];
1506         u8 reserved_at_24[0x7];
1507         u8 page_offset[0x5];
1508         u8 lwm[0x10];
1509         u8 reserved_at_40[0x8];
1510         u8 pd[0x18];
1511         u8 reserved_at_60[0x8];
1512         u8 uar_page[0x18];
1513         u8 dbr_addr[0x40];
1514         u8 hw_counter[0x20];
1515         u8 sw_counter[0x20];
1516         u8 reserved_at_100[0xc];
1517         u8 log_wq_stride[0x4];
1518         u8 reserved_at_110[0x3];
1519         u8 log_wq_pg_sz[0x5];
1520         u8 reserved_at_118[0x3];
1521         u8 log_wq_sz[0x5];
1522         u8 dbr_umem_valid[0x1];
1523         u8 wq_umem_valid[0x1];
1524         u8 reserved_at_122[0x1];
1525         u8 log_hairpin_num_packets[0x5];
1526         u8 reserved_at_128[0x3];
1527         u8 log_hairpin_data_sz[0x5];
1528         u8 reserved_at_130[0x4];
1529         u8 single_wqe_log_num_of_strides[0x4];
1530         u8 two_byte_shift_en[0x1];
1531         u8 reserved_at_139[0x4];
1532         u8 single_stride_log_num_of_bytes[0x3];
1533         u8 dbr_umem_id[0x20];
1534         u8 wq_umem_id[0x20];
1535         u8 wq_umem_offset[0x40];
1536         u8 reserved_at_1c0[0x440];
1537 };
1538
1539 enum {
1540         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
1541         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
1542 };
1543
1544 enum {
1545         MLX5_RQC_STATE_RST  = 0x0,
1546         MLX5_RQC_STATE_RDY  = 0x1,
1547         MLX5_RQC_STATE_ERR  = 0x3,
1548 };
1549
1550 struct mlx5_ifc_rqc_bits {
1551         u8 rlky[0x1];
1552         u8 delay_drop_en[0x1];
1553         u8 scatter_fcs[0x1];
1554         u8 vsd[0x1];
1555         u8 mem_rq_type[0x4];
1556         u8 state[0x4];
1557         u8 reserved_at_c[0x1];
1558         u8 flush_in_error_en[0x1];
1559         u8 hairpin[0x1];
1560         u8 reserved_at_f[0x11];
1561         u8 reserved_at_20[0x8];
1562         u8 user_index[0x18];
1563         u8 reserved_at_40[0x8];
1564         u8 cqn[0x18];
1565         u8 counter_set_id[0x8];
1566         u8 reserved_at_68[0x18];
1567         u8 reserved_at_80[0x8];
1568         u8 rmpn[0x18];
1569         u8 reserved_at_a0[0x8];
1570         u8 hairpin_peer_sq[0x18];
1571         u8 reserved_at_c0[0x10];
1572         u8 hairpin_peer_vhca[0x10];
1573         u8 reserved_at_e0[0xa0];
1574         struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */
1575 };
1576
1577 struct mlx5_ifc_create_rq_out_bits {
1578         u8 status[0x8];
1579         u8 reserved_at_8[0x18];
1580         u8 syndrome[0x20];
1581         u8 reserved_at_40[0x8];
1582         u8 rqn[0x18];
1583         u8 reserved_at_60[0x20];
1584 };
1585
1586 struct mlx5_ifc_create_rq_in_bits {
1587         u8 opcode[0x10];
1588         u8 uid[0x10];
1589         u8 reserved_at_20[0x10];
1590         u8 op_mod[0x10];
1591         u8 reserved_at_40[0xc0];
1592         struct mlx5_ifc_rqc_bits ctx;
1593 };
1594
1595 struct mlx5_ifc_modify_rq_out_bits {
1596         u8 status[0x8];
1597         u8 reserved_at_8[0x18];
1598         u8 syndrome[0x20];
1599         u8 reserved_at_40[0x40];
1600 };
1601
1602 struct mlx5_ifc_create_tis_out_bits {
1603         u8 status[0x8];
1604         u8 reserved_at_8[0x18];
1605         u8 syndrome[0x20];
1606         u8 reserved_at_40[0x8];
1607         u8 tisn[0x18];
1608         u8 reserved_at_60[0x20];
1609 };
1610
1611 struct mlx5_ifc_create_tis_in_bits {
1612         u8 opcode[0x10];
1613         u8 uid[0x10];
1614         u8 reserved_at_20[0x10];
1615         u8 op_mod[0x10];
1616         u8 reserved_at_40[0xc0];
1617         struct mlx5_ifc_tisc_bits ctx;
1618 };
1619
1620 enum {
1621         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,
1622         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
1623         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
1624         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
1625 };
1626
1627 struct mlx5_ifc_modify_rq_in_bits {
1628         u8 opcode[0x10];
1629         u8 uid[0x10];
1630         u8 reserved_at_20[0x10];
1631         u8 op_mod[0x10];
1632         u8 rq_state[0x4];
1633         u8 reserved_at_44[0x4];
1634         u8 rqn[0x18];
1635         u8 reserved_at_60[0x20];
1636         u8 modify_bitmask[0x40];
1637         u8 reserved_at_c0[0x40];
1638         struct mlx5_ifc_rqc_bits ctx;
1639 };
1640
1641 enum {
1642         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1643         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1644         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1645         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1646         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1647 };
1648
1649 struct mlx5_ifc_rx_hash_field_select_bits {
1650         u8 l3_prot_type[0x1];
1651         u8 l4_prot_type[0x1];
1652         u8 selected_fields[0x1e];
1653 };
1654
1655 enum {
1656         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
1657         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
1658 };
1659
1660 enum {
1661         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
1662         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
1663 };
1664
1665 enum {
1666         MLX5_RX_HASH_FN_NONE           = 0x0,
1667         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
1668         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
1669 };
1670
1671 enum {
1672         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
1673         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
1674 };
1675
1676 enum {
1677         MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4    = 0x0,
1678         MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2  = 0x1,
1679 };
1680
1681 struct mlx5_ifc_tirc_bits {
1682         u8 reserved_at_0[0x20];
1683         u8 disp_type[0x4];
1684         u8 reserved_at_24[0x1c];
1685         u8 reserved_at_40[0x40];
1686         u8 reserved_at_80[0x4];
1687         u8 lro_timeout_period_usecs[0x10];
1688         u8 lro_enable_mask[0x4];
1689         u8 lro_max_msg_sz[0x8];
1690         u8 reserved_at_a0[0x40];
1691         u8 reserved_at_e0[0x8];
1692         u8 inline_rqn[0x18];
1693         u8 rx_hash_symmetric[0x1];
1694         u8 reserved_at_101[0x1];
1695         u8 tunneled_offload_en[0x1];
1696         u8 reserved_at_103[0x5];
1697         u8 indirect_table[0x18];
1698         u8 rx_hash_fn[0x4];
1699         u8 reserved_at_124[0x2];
1700         u8 self_lb_block[0x2];
1701         u8 transport_domain[0x18];
1702         u8 rx_hash_toeplitz_key[10][0x20];
1703         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
1704         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
1705         u8 reserved_at_2c0[0x4c0];
1706 };
1707
1708 struct mlx5_ifc_create_tir_out_bits {
1709         u8 status[0x8];
1710         u8 reserved_at_8[0x18];
1711         u8 syndrome[0x20];
1712         u8 reserved_at_40[0x8];
1713         u8 tirn[0x18];
1714         u8 reserved_at_60[0x20];
1715 };
1716
1717 struct mlx5_ifc_create_tir_in_bits {
1718         u8 opcode[0x10];
1719         u8 uid[0x10];
1720         u8 reserved_at_20[0x10];
1721         u8 op_mod[0x10];
1722         u8 reserved_at_40[0xc0];
1723         struct mlx5_ifc_tirc_bits ctx;
1724 };
1725
1726 enum {
1727         MLX5_INLINE_Q_TYPE_RQ = 0x0,
1728         MLX5_INLINE_Q_TYPE_VIRTQ = 0x1,
1729 };
1730
1731 struct mlx5_ifc_rq_num_bits {
1732         u8 reserved_at_0[0x8];
1733         u8 rq_num[0x18];
1734 };
1735
1736 struct mlx5_ifc_rqtc_bits {
1737         u8 reserved_at_0[0xa5];
1738         u8 list_q_type[0x3];
1739         u8 reserved_at_a8[0x8];
1740         u8 rqt_max_size[0x10];
1741         u8 reserved_at_c0[0x10];
1742         u8 rqt_actual_size[0x10];
1743         u8 reserved_at_e0[0x6a0];
1744         struct mlx5_ifc_rq_num_bits rq_num[];
1745 };
1746
1747 struct mlx5_ifc_create_rqt_out_bits {
1748         u8 status[0x8];
1749         u8 reserved_at_8[0x18];
1750         u8 syndrome[0x20];
1751         u8 reserved_at_40[0x8];
1752         u8 rqtn[0x18];
1753         u8 reserved_at_60[0x20];
1754 };
1755
1756 #ifdef PEDANTIC
1757 #pragma GCC diagnostic ignored "-Wpedantic"
1758 #endif
1759 struct mlx5_ifc_create_rqt_in_bits {
1760         u8 opcode[0x10];
1761         u8 uid[0x10];
1762         u8 reserved_at_20[0x10];
1763         u8 op_mod[0x10];
1764         u8 reserved_at_40[0xc0];
1765         struct mlx5_ifc_rqtc_bits rqt_context;
1766 };
1767 #ifdef PEDANTIC
1768 #pragma GCC diagnostic error "-Wpedantic"
1769 #endif
1770
1771 enum {
1772         MLX5_SQC_STATE_RST  = 0x0,
1773         MLX5_SQC_STATE_RDY  = 0x1,
1774         MLX5_SQC_STATE_ERR  = 0x3,
1775 };
1776
1777 struct mlx5_ifc_sqc_bits {
1778         u8 rlky[0x1];
1779         u8 cd_master[0x1];
1780         u8 fre[0x1];
1781         u8 flush_in_error_en[0x1];
1782         u8 allow_multi_pkt_send_wqe[0x1];
1783         u8 min_wqe_inline_mode[0x3];
1784         u8 state[0x4];
1785         u8 reg_umr[0x1];
1786         u8 allow_swp[0x1];
1787         u8 hairpin[0x1];
1788         u8 reserved_at_f[0x11];
1789         u8 reserved_at_20[0x8];
1790         u8 user_index[0x18];
1791         u8 reserved_at_40[0x8];
1792         u8 cqn[0x18];
1793         u8 reserved_at_60[0x8];
1794         u8 hairpin_peer_rq[0x18];
1795         u8 reserved_at_80[0x10];
1796         u8 hairpin_peer_vhca[0x10];
1797         u8 reserved_at_a0[0x50];
1798         u8 packet_pacing_rate_limit_index[0x10];
1799         u8 tis_lst_sz[0x10];
1800         u8 reserved_at_110[0x10];
1801         u8 reserved_at_120[0x40];
1802         u8 reserved_at_160[0x8];
1803         u8 tis_num_0[0x18];
1804         struct mlx5_ifc_wq_bits wq;
1805 };
1806
1807 struct mlx5_ifc_query_sq_in_bits {
1808         u8 opcode[0x10];
1809         u8 reserved_at_10[0x10];
1810         u8 reserved_at_20[0x10];
1811         u8 op_mod[0x10];
1812         u8 reserved_at_40[0x8];
1813         u8 sqn[0x18];
1814         u8 reserved_at_60[0x20];
1815 };
1816
1817 struct mlx5_ifc_modify_sq_out_bits {
1818         u8 status[0x8];
1819         u8 reserved_at_8[0x18];
1820         u8 syndrome[0x20];
1821         u8 reserved_at_40[0x40];
1822 };
1823
1824 struct mlx5_ifc_modify_sq_in_bits {
1825         u8 opcode[0x10];
1826         u8 uid[0x10];
1827         u8 reserved_at_20[0x10];
1828         u8 op_mod[0x10];
1829         u8 sq_state[0x4];
1830         u8 reserved_at_44[0x4];
1831         u8 sqn[0x18];
1832         u8 reserved_at_60[0x20];
1833         u8 modify_bitmask[0x40];
1834         u8 reserved_at_c0[0x40];
1835         struct mlx5_ifc_sqc_bits ctx;
1836 };
1837
1838 struct mlx5_ifc_create_sq_out_bits {
1839         u8 status[0x8];
1840         u8 reserved_at_8[0x18];
1841         u8 syndrome[0x20];
1842         u8 reserved_at_40[0x8];
1843         u8 sqn[0x18];
1844         u8 reserved_at_60[0x20];
1845 };
1846
1847 struct mlx5_ifc_create_sq_in_bits {
1848         u8 opcode[0x10];
1849         u8 uid[0x10];
1850         u8 reserved_at_20[0x10];
1851         u8 op_mod[0x10];
1852         u8 reserved_at_40[0xc0];
1853         struct mlx5_ifc_sqc_bits ctx;
1854 };
1855
1856 enum {
1857         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0),
1858         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1),
1859         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2),
1860         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3),
1861         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4),
1862 };
1863
1864 struct mlx5_ifc_flow_meter_parameters_bits {
1865         u8         valid[0x1];                  // 00h
1866         u8         bucket_overflow[0x1];
1867         u8         start_color[0x2];
1868         u8         both_buckets_on_green[0x1];
1869         u8         meter_mode[0x2];
1870         u8         reserved_at_1[0x19];
1871         u8         reserved_at_2[0x20]; //04h
1872         u8         reserved_at_3[0x3];
1873         u8         cbs_exponent[0x5];           // 08h
1874         u8         cbs_mantissa[0x8];
1875         u8         reserved_at_4[0x3];
1876         u8         cir_exponent[0x5];
1877         u8         cir_mantissa[0x8];
1878         u8         reserved_at_5[0x20];         // 0Ch
1879         u8         reserved_at_6[0x3];
1880         u8         ebs_exponent[0x5];           // 10h
1881         u8         ebs_mantissa[0x8];
1882         u8         reserved_at_7[0x3];
1883         u8         eir_exponent[0x5];
1884         u8         eir_mantissa[0x8];
1885         u8         reserved_at_8[0x60];         // 14h-1Ch
1886 };
1887
1888 struct mlx5_ifc_cqc_bits {
1889         u8 status[0x4];
1890         u8 as_notify[0x1];
1891         u8 initiator_src_dct[0x1];
1892         u8 dbr_umem_valid[0x1];
1893         u8 reserved_at_7[0x1];
1894         u8 cqe_sz[0x3];
1895         u8 cc[0x1];
1896         u8 reserved_at_c[0x1];
1897         u8 scqe_break_moderation_en[0x1];
1898         u8 oi[0x1];
1899         u8 cq_period_mode[0x2];
1900         u8 cqe_comp_en[0x1];
1901         u8 mini_cqe_res_format[0x2];
1902         u8 st[0x4];
1903         u8 reserved_at_18[0x8];
1904         u8 dbr_umem_id[0x20];
1905         u8 reserved_at_40[0x14];
1906         u8 page_offset[0x6];
1907         u8 reserved_at_5a[0x6];
1908         u8 reserved_at_60[0x3];
1909         u8 log_cq_size[0x5];
1910         u8 uar_page[0x18];
1911         u8 reserved_at_80[0x4];
1912         u8 cq_period[0xc];
1913         u8 cq_max_count[0x10];
1914         u8 reserved_at_a0[0x18];
1915         u8 c_eqn[0x8];
1916         u8 reserved_at_c0[0x3];
1917         u8 log_page_size[0x5];
1918         u8 reserved_at_c8[0x18];
1919         u8 reserved_at_e0[0x20];
1920         u8 reserved_at_100[0x8];
1921         u8 last_notified_index[0x18];
1922         u8 reserved_at_120[0x8];
1923         u8 last_solicit_index[0x18];
1924         u8 reserved_at_140[0x8];
1925         u8 consumer_counter[0x18];
1926         u8 reserved_at_160[0x8];
1927         u8 producer_counter[0x18];
1928         u8 local_partition_id[0xc];
1929         u8 process_id[0x14];
1930         u8 reserved_at_1A0[0x20];
1931         u8 dbr_addr[0x40];
1932 };
1933
1934 struct mlx5_ifc_create_cq_out_bits {
1935         u8 status[0x8];
1936         u8 reserved_at_8[0x18];
1937         u8 syndrome[0x20];
1938         u8 reserved_at_40[0x8];
1939         u8 cqn[0x18];
1940         u8 reserved_at_60[0x20];
1941 };
1942
1943 struct mlx5_ifc_create_cq_in_bits {
1944         u8 opcode[0x10];
1945         u8 uid[0x10];
1946         u8 reserved_at_20[0x10];
1947         u8 op_mod[0x10];
1948         u8 reserved_at_40[0x40];
1949         struct mlx5_ifc_cqc_bits cq_context;
1950         u8 cq_umem_offset[0x40];
1951         u8 cq_umem_id[0x20];
1952         u8 cq_umem_valid[0x1];
1953         u8 reserved_at_2e1[0x1f];
1954         u8 reserved_at_300[0x580];
1955         u8 pas[];
1956 };
1957
1958 enum {
1959         MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,
1960 };
1961
1962 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
1963         u8 opcode[0x10];
1964         u8 reserved_at_10[0x20];
1965         u8 obj_type[0x10];
1966         u8 obj_id[0x20];
1967         u8 reserved_at_60[0x20];
1968 };
1969
1970 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
1971         u8 status[0x8];
1972         u8 reserved_at_8[0x18];
1973         u8 syndrome[0x20];
1974         u8 obj_id[0x20];
1975         u8 reserved_at_60[0x20];
1976 };
1977
1978 enum {
1979         MLX5_VIRTQ_STATE_INIT = 0,
1980         MLX5_VIRTQ_STATE_RDY = 1,
1981         MLX5_VIRTQ_STATE_SUSPEND = 2,
1982         MLX5_VIRTQ_STATE_ERROR = 3,
1983 };
1984
1985 enum {
1986         MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0),
1987         MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3),
1988         MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4),
1989 };
1990
1991 struct mlx5_ifc_virtio_q_bits {
1992         u8 virtio_q_type[0x8];
1993         u8 reserved_at_8[0x5];
1994         u8 event_mode[0x3];
1995         u8 queue_index[0x10];
1996         u8 full_emulation[0x1];
1997         u8 virtio_version_1_0[0x1];
1998         u8 reserved_at_22[0x2];
1999         u8 offload_type[0x4];
2000         u8 event_qpn_or_msix[0x18];
2001         u8 doorbell_stride_idx[0x10];
2002         u8 queue_size[0x10];
2003         u8 device_emulation_id[0x20];
2004         u8 desc_addr[0x40];
2005         u8 used_addr[0x40];
2006         u8 available_addr[0x40];
2007         u8 virtio_q_mkey[0x20];
2008         u8 reserved_at_160[0x20];
2009         u8 umem_1_id[0x20];
2010         u8 umem_1_size[0x20];
2011         u8 umem_1_offset[0x40];
2012         u8 umem_2_id[0x20];
2013         u8 umem_2_size[0x20];
2014         u8 umem_2_offset[0x40];
2015         u8 umem_3_id[0x20];
2016         u8 umem_3_size[0x20];
2017         u8 umem_3_offset[0x40];
2018         u8 reserved_at_300[0x100];
2019 };
2020
2021 struct mlx5_ifc_virtio_net_q_bits {
2022         u8 modify_field_select[0x40];
2023         u8 reserved_at_40[0x40];
2024         u8 tso_ipv4[0x1];
2025         u8 tso_ipv6[0x1];
2026         u8 tx_csum[0x1];
2027         u8 rx_csum[0x1];
2028         u8 reserved_at_84[0x6];
2029         u8 dirty_bitmap_dump_enable[0x1];
2030         u8 vhost_log_page[0x5];
2031         u8 reserved_at_90[0xc];
2032         u8 state[0x4];
2033         u8 error_type[0x8];
2034         u8 tisn_or_qpn[0x18];
2035         u8 dirty_bitmap_mkey[0x20];
2036         u8 dirty_bitmap_size[0x20];
2037         u8 dirty_bitmap_addr[0x40];
2038         u8 hw_available_index[0x10];
2039         u8 hw_used_index[0x10];
2040         u8 reserved_at_160[0xa0];
2041         struct mlx5_ifc_virtio_q_bits virtio_q_context;
2042 };
2043
2044 struct mlx5_ifc_create_virtq_in_bits {
2045         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2046         struct mlx5_ifc_virtio_net_q_bits virtq;
2047 };
2048
2049 struct mlx5_ifc_query_virtq_out_bits {
2050         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2051         struct mlx5_ifc_virtio_net_q_bits virtq;
2052 };
2053
2054 enum {
2055         MLX5_QP_ST_RC = 0x0,
2056 };
2057
2058 enum {
2059         MLX5_QP_PM_MIGRATED = 0x3,
2060 };
2061
2062 enum {
2063         MLX5_NON_ZERO_RQ = 0x0,
2064         MLX5_SRQ_RQ = 0x1,
2065         MLX5_CRQ_RQ = 0x2,
2066         MLX5_ZERO_LEN_RQ = 0x3,
2067 };
2068
2069 struct mlx5_ifc_ads_bits {
2070         u8 fl[0x1];
2071         u8 free_ar[0x1];
2072         u8 reserved_at_2[0xe];
2073         u8 pkey_index[0x10];
2074         u8 reserved_at_20[0x8];
2075         u8 grh[0x1];
2076         u8 mlid[0x7];
2077         u8 rlid[0x10];
2078         u8 ack_timeout[0x5];
2079         u8 reserved_at_45[0x3];
2080         u8 src_addr_index[0x8];
2081         u8 reserved_at_50[0x4];
2082         u8 stat_rate[0x4];
2083         u8 hop_limit[0x8];
2084         u8 reserved_at_60[0x4];
2085         u8 tclass[0x8];
2086         u8 flow_label[0x14];
2087         u8 rgid_rip[16][0x8];
2088         u8 reserved_at_100[0x4];
2089         u8 f_dscp[0x1];
2090         u8 f_ecn[0x1];
2091         u8 reserved_at_106[0x1];
2092         u8 f_eth_prio[0x1];
2093         u8 ecn[0x2];
2094         u8 dscp[0x6];
2095         u8 udp_sport[0x10];
2096         u8 dei_cfi[0x1];
2097         u8 eth_prio[0x3];
2098         u8 sl[0x4];
2099         u8 vhca_port_num[0x8];
2100         u8 rmac_47_32[0x10];
2101         u8 rmac_31_0[0x20];
2102 };
2103
2104 struct mlx5_ifc_qpc_bits {
2105         u8 state[0x4];
2106         u8 lag_tx_port_affinity[0x4];
2107         u8 st[0x8];
2108         u8 reserved_at_10[0x3];
2109         u8 pm_state[0x2];
2110         u8 reserved_at_15[0x1];
2111         u8 req_e2e_credit_mode[0x2];
2112         u8 offload_type[0x4];
2113         u8 end_padding_mode[0x2];
2114         u8 reserved_at_1e[0x2];
2115         u8 wq_signature[0x1];
2116         u8 block_lb_mc[0x1];
2117         u8 atomic_like_write_en[0x1];
2118         u8 latency_sensitive[0x1];
2119         u8 reserved_at_24[0x1];
2120         u8 drain_sigerr[0x1];
2121         u8 reserved_at_26[0x2];
2122         u8 pd[0x18];
2123         u8 mtu[0x3];
2124         u8 log_msg_max[0x5];
2125         u8 reserved_at_48[0x1];
2126         u8 log_rq_size[0x4];
2127         u8 log_rq_stride[0x3];
2128         u8 no_sq[0x1];
2129         u8 log_sq_size[0x4];
2130         u8 reserved_at_55[0x6];
2131         u8 rlky[0x1];
2132         u8 ulp_stateless_offload_mode[0x4];
2133         u8 counter_set_id[0x8];
2134         u8 uar_page[0x18];
2135         u8 reserved_at_80[0x8];
2136         u8 user_index[0x18];
2137         u8 reserved_at_a0[0x3];
2138         u8 log_page_size[0x5];
2139         u8 remote_qpn[0x18];
2140         struct mlx5_ifc_ads_bits primary_address_path;
2141         struct mlx5_ifc_ads_bits secondary_address_path;
2142         u8 log_ack_req_freq[0x4];
2143         u8 reserved_at_384[0x4];
2144         u8 log_sra_max[0x3];
2145         u8 reserved_at_38b[0x2];
2146         u8 retry_count[0x3];
2147         u8 rnr_retry[0x3];
2148         u8 reserved_at_393[0x1];
2149         u8 fre[0x1];
2150         u8 cur_rnr_retry[0x3];
2151         u8 cur_retry_count[0x3];
2152         u8 reserved_at_39b[0x5];
2153         u8 reserved_at_3a0[0x20];
2154         u8 reserved_at_3c0[0x8];
2155         u8 next_send_psn[0x18];
2156         u8 reserved_at_3e0[0x8];
2157         u8 cqn_snd[0x18];
2158         u8 reserved_at_400[0x8];
2159         u8 deth_sqpn[0x18];
2160         u8 reserved_at_420[0x20];
2161         u8 reserved_at_440[0x8];
2162         u8 last_acked_psn[0x18];
2163         u8 reserved_at_460[0x8];
2164         u8 ssn[0x18];
2165         u8 reserved_at_480[0x8];
2166         u8 log_rra_max[0x3];
2167         u8 reserved_at_48b[0x1];
2168         u8 atomic_mode[0x4];
2169         u8 rre[0x1];
2170         u8 rwe[0x1];
2171         u8 rae[0x1];
2172         u8 reserved_at_493[0x1];
2173         u8 page_offset[0x6];
2174         u8 reserved_at_49a[0x3];
2175         u8 cd_slave_receive[0x1];
2176         u8 cd_slave_send[0x1];
2177         u8 cd_master[0x1];
2178         u8 reserved_at_4a0[0x3];
2179         u8 min_rnr_nak[0x5];
2180         u8 next_rcv_psn[0x18];
2181         u8 reserved_at_4c0[0x8];
2182         u8 xrcd[0x18];
2183         u8 reserved_at_4e0[0x8];
2184         u8 cqn_rcv[0x18];
2185         u8 dbr_addr[0x40];
2186         u8 q_key[0x20];
2187         u8 reserved_at_560[0x5];
2188         u8 rq_type[0x3];
2189         u8 srqn_rmpn_xrqn[0x18];
2190         u8 reserved_at_580[0x8];
2191         u8 rmsn[0x18];
2192         u8 hw_sq_wqebb_counter[0x10];
2193         u8 sw_sq_wqebb_counter[0x10];
2194         u8 hw_rq_counter[0x20];
2195         u8 sw_rq_counter[0x20];
2196         u8 reserved_at_600[0x20];
2197         u8 reserved_at_620[0xf];
2198         u8 cgs[0x1];
2199         u8 cs_req[0x8];
2200         u8 cs_res[0x8];
2201         u8 dc_access_key[0x40];
2202         u8 reserved_at_680[0x3];
2203         u8 dbr_umem_valid[0x1];
2204         u8 reserved_at_684[0x9c];
2205         u8 dbr_umem_id[0x20];
2206 };
2207
2208 struct mlx5_ifc_create_qp_out_bits {
2209         u8 status[0x8];
2210         u8 reserved_at_8[0x18];
2211         u8 syndrome[0x20];
2212         u8 reserved_at_40[0x8];
2213         u8 qpn[0x18];
2214         u8 reserved_at_60[0x20];
2215 };
2216
2217 #ifdef PEDANTIC
2218 #pragma GCC diagnostic ignored "-Wpedantic"
2219 #endif
2220 struct mlx5_ifc_create_qp_in_bits {
2221         u8 opcode[0x10];
2222         u8 uid[0x10];
2223         u8 reserved_at_20[0x10];
2224         u8 op_mod[0x10];
2225         u8 reserved_at_40[0x40];
2226         u8 opt_param_mask[0x20];
2227         u8 reserved_at_a0[0x20];
2228         struct mlx5_ifc_qpc_bits qpc;
2229         u8 wq_umem_offset[0x40];
2230         u8 wq_umem_id[0x20];
2231         u8 wq_umem_valid[0x1];
2232         u8 reserved_at_861[0x1f];
2233         u8 pas[0][0x40];
2234 };
2235 #ifdef PEDANTIC
2236 #pragma GCC diagnostic error "-Wpedantic"
2237 #endif
2238
2239 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2240         u8 status[0x8];
2241         u8 reserved_at_8[0x18];
2242         u8 syndrome[0x20];
2243         u8 reserved_at_40[0x40];
2244 };
2245
2246 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2247         u8 opcode[0x10];
2248         u8 uid[0x10];
2249         u8 reserved_at_20[0x10];
2250         u8 op_mod[0x10];
2251         u8 reserved_at_40[0x8];
2252         u8 qpn[0x18];
2253         u8 reserved_at_60[0x20];
2254         u8 opt_param_mask[0x20];
2255         u8 reserved_at_a0[0x20];
2256         struct mlx5_ifc_qpc_bits qpc;
2257         u8 reserved_at_800[0x80];
2258 };
2259
2260 struct mlx5_ifc_sqd2rts_qp_out_bits {
2261         u8 status[0x8];
2262         u8 reserved_at_8[0x18];
2263         u8 syndrome[0x20];
2264         u8 reserved_at_40[0x40];
2265 };
2266
2267 struct mlx5_ifc_sqd2rts_qp_in_bits {
2268         u8 opcode[0x10];
2269         u8 uid[0x10];
2270         u8 reserved_at_20[0x10];
2271         u8 op_mod[0x10];
2272         u8 reserved_at_40[0x8];
2273         u8 qpn[0x18];
2274         u8 reserved_at_60[0x20];
2275         u8 opt_param_mask[0x20];
2276         u8 reserved_at_a0[0x20];
2277         struct mlx5_ifc_qpc_bits qpc;
2278         u8 reserved_at_800[0x80];
2279 };
2280
2281 struct mlx5_ifc_rts2rts_qp_out_bits {
2282         u8 status[0x8];
2283         u8 reserved_at_8[0x18];
2284         u8 syndrome[0x20];
2285         u8 reserved_at_40[0x40];
2286 };
2287
2288 struct mlx5_ifc_rts2rts_qp_in_bits {
2289         u8 opcode[0x10];
2290         u8 uid[0x10];
2291         u8 reserved_at_20[0x10];
2292         u8 op_mod[0x10];
2293         u8 reserved_at_40[0x8];
2294         u8 qpn[0x18];
2295         u8 reserved_at_60[0x20];
2296         u8 opt_param_mask[0x20];
2297         u8 reserved_at_a0[0x20];
2298         struct mlx5_ifc_qpc_bits qpc;
2299         u8 reserved_at_800[0x80];
2300 };
2301
2302 struct mlx5_ifc_rtr2rts_qp_out_bits {
2303         u8 status[0x8];
2304         u8 reserved_at_8[0x18];
2305         u8 syndrome[0x20];
2306         u8 reserved_at_40[0x40];
2307 };
2308
2309 struct mlx5_ifc_rtr2rts_qp_in_bits {
2310         u8 opcode[0x10];
2311         u8 uid[0x10];
2312         u8 reserved_at_20[0x10];
2313         u8 op_mod[0x10];
2314         u8 reserved_at_40[0x8];
2315         u8 qpn[0x18];
2316         u8 reserved_at_60[0x20];
2317         u8 opt_param_mask[0x20];
2318         u8 reserved_at_a0[0x20];
2319         struct mlx5_ifc_qpc_bits qpc;
2320         u8 reserved_at_800[0x80];
2321 };
2322
2323 struct mlx5_ifc_rst2init_qp_out_bits {
2324         u8 status[0x8];
2325         u8 reserved_at_8[0x18];
2326         u8 syndrome[0x20];
2327         u8 reserved_at_40[0x40];
2328 };
2329
2330 struct mlx5_ifc_rst2init_qp_in_bits {
2331         u8 opcode[0x10];
2332         u8 uid[0x10];
2333         u8 reserved_at_20[0x10];
2334         u8 op_mod[0x10];
2335         u8 reserved_at_40[0x8];
2336         u8 qpn[0x18];
2337         u8 reserved_at_60[0x20];
2338         u8 opt_param_mask[0x20];
2339         u8 reserved_at_a0[0x20];
2340         struct mlx5_ifc_qpc_bits qpc;
2341         u8 reserved_at_800[0x80];
2342 };
2343
2344 struct mlx5_ifc_init2rtr_qp_out_bits {
2345         u8 status[0x8];
2346         u8 reserved_at_8[0x18];
2347         u8 syndrome[0x20];
2348         u8 reserved_at_40[0x40];
2349 };
2350
2351 struct mlx5_ifc_init2rtr_qp_in_bits {
2352         u8 opcode[0x10];
2353         u8 uid[0x10];
2354         u8 reserved_at_20[0x10];
2355         u8 op_mod[0x10];
2356         u8 reserved_at_40[0x8];
2357         u8 qpn[0x18];
2358         u8 reserved_at_60[0x20];
2359         u8 opt_param_mask[0x20];
2360         u8 reserved_at_a0[0x20];
2361         struct mlx5_ifc_qpc_bits qpc;
2362         u8 reserved_at_800[0x80];
2363 };
2364
2365 struct mlx5_ifc_init2init_qp_out_bits {
2366         u8 status[0x8];
2367         u8 reserved_at_8[0x18];
2368         u8 syndrome[0x20];
2369         u8 reserved_at_40[0x40];
2370 };
2371
2372 struct mlx5_ifc_init2init_qp_in_bits {
2373         u8 opcode[0x10];
2374         u8 uid[0x10];
2375         u8 reserved_at_20[0x10];
2376         u8 op_mod[0x10];
2377         u8 reserved_at_40[0x8];
2378         u8 qpn[0x18];
2379         u8 reserved_at_60[0x20];
2380         u8 opt_param_mask[0x20];
2381         u8 reserved_at_a0[0x20];
2382         struct mlx5_ifc_qpc_bits qpc;
2383         u8 reserved_at_800[0x80];
2384 };
2385
2386 #ifdef PEDANTIC
2387 #pragma GCC diagnostic ignored "-Wpedantic"
2388 #endif
2389 struct mlx5_ifc_query_qp_out_bits {
2390         u8 status[0x8];
2391         u8 reserved_at_8[0x18];
2392         u8 syndrome[0x20];
2393         u8 reserved_at_40[0x40];
2394         u8 opt_param_mask[0x20];
2395         u8 reserved_at_a0[0x20];
2396         struct mlx5_ifc_qpc_bits qpc;
2397         u8 reserved_at_800[0x80];
2398         u8 pas[0][0x40];
2399 };
2400 #ifdef PEDANTIC
2401 #pragma GCC diagnostic error "-Wpedantic"
2402 #endif
2403
2404 struct mlx5_ifc_query_qp_in_bits {
2405         u8 opcode[0x10];
2406         u8 reserved_at_10[0x10];
2407         u8 reserved_at_20[0x10];
2408         u8 op_mod[0x10];
2409         u8 reserved_at_40[0x8];
2410         u8 qpn[0x18];
2411         u8 reserved_at_60[0x20];
2412 };
2413
2414 /* CQE format mask. */
2415 #define MLX5E_CQE_FORMAT_MASK 0xc
2416
2417 /* MPW opcode. */
2418 #define MLX5_OPC_MOD_MPW 0x01
2419
2420 /* Compressed Rx CQE structure. */
2421 struct mlx5_mini_cqe8 {
2422         union {
2423                 uint32_t rx_hash_result;
2424                 struct {
2425                         uint16_t checksum;
2426                         uint16_t stride_idx;
2427                 };
2428                 struct {
2429                         uint16_t wqe_counter;
2430                         uint8_t  s_wqe_opcode;
2431                         uint8_t  reserved;
2432                 } s_wqe_info;
2433         };
2434         uint32_t byte_cnt;
2435 };
2436
2437 /* srTCM PRM flow meter parameters. */
2438 enum {
2439         MLX5_FLOW_COLOR_RED = 0,
2440         MLX5_FLOW_COLOR_YELLOW,
2441         MLX5_FLOW_COLOR_GREEN,
2442         MLX5_FLOW_COLOR_UNDEFINED,
2443 };
2444
2445 /* Maximum value of srTCM metering parameters. */
2446 #define MLX5_SRTCM_CBS_MAX (0xFF * (1ULL << 0x1F))
2447 #define MLX5_SRTCM_CIR_MAX (8 * (1ULL << 30) * 0xFF)
2448 #define MLX5_SRTCM_EBS_MAX 0
2449
2450 /* The bits meter color use. */
2451 #define MLX5_MTR_COLOR_BITS 8
2452
2453 /**
2454  * Convert a user mark to flow mark.
2455  *
2456  * @param val
2457  *   Mark value to convert.
2458  *
2459  * @return
2460  *   Converted mark value.
2461  */
2462 static inline uint32_t
2463 mlx5_flow_mark_set(uint32_t val)
2464 {
2465         uint32_t ret;
2466
2467         /*
2468          * Add one to the user value to differentiate un-marked flows from
2469          * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
2470          * remains untouched.
2471          */
2472         if (val != MLX5_FLOW_MARK_DEFAULT)
2473                 ++val;
2474 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
2475         /*
2476          * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
2477          * word, byte-swapped by the kernel on little-endian systems. In this
2478          * case, left-shifting the resulting big-endian value ensures the
2479          * least significant 24 bits are retained when converting it back.
2480          */
2481         ret = rte_cpu_to_be_32(val) >> 8;
2482 #else
2483         ret = val;
2484 #endif
2485         return ret;
2486 }
2487
2488 /**
2489  * Convert a mark to user mark.
2490  *
2491  * @param val
2492  *   Mark value to convert.
2493  *
2494  * @return
2495  *   Converted mark value.
2496  */
2497 static inline uint32_t
2498 mlx5_flow_mark_get(uint32_t val)
2499 {
2500         /*
2501          * Subtract one from the retrieved value. It was added by
2502          * mlx5_flow_mark_set() to distinguish unmarked flows.
2503          */
2504 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
2505         return (val >> 8) - 1;
2506 #else
2507         return val - 1;
2508 #endif
2509 }
2510
2511 #endif /* RTE_PMD_MLX5_PRM_H_ */