drivers/common/mlx5/mlx5_prm.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2016 6WIND S.A.
   3  * Copyright 2016 Mellanox Technologies, Ltd
   4  */
   5
   6 #ifndef RTE_PMD_MLX5_PRM_H_
   7 #define RTE_PMD_MLX5_PRM_H_
   8
   9 #include <unistd.h>
  10
  11 #include <rte_vect.h>
  12 #include <rte_byteorder.h>
  13
  14 #include <mlx5_glue.h>
  15 #include "mlx5_autoconf.h"
  16
  17 /* RSS hash key size. */
  18 #define MLX5_RSS_HASH_KEY_LEN 40
  19
  20 /* Get CQE owner bit. */
  21 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
  22
  23 /* Get CQE format. */
  24 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
  25
  26 /* Get CQE opcode. */
  27 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
  28
  29 /* Get CQE solicited event. */
  30 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
  31
  32 /* Invalidate a CQE. */
  33 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
  34
  35 /* Hardware index widths. */
  36 #define MLX5_CQ_INDEX_WIDTH 24
  37 #define MLX5_WQ_INDEX_WIDTH 16
  38
  39 /* WQE Segment sizes in bytes. */
  40 #define MLX5_WSEG_SIZE 16u
  41 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)
  42 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg)
  43 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg)
  44
  45 /* WQE/WQEBB size in bytes. */
  46 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe)
  47
  48 /*
  49  * Max size of a WQE session.
  50  * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments,
  51  * the WQE size field in Control Segment is 6 bits wide.
  52  */
  53 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE)
  54
  55 /*
  56  * Default minimum number of Tx queues for inlining packets.
  57  * If there are less queues as specified we assume we have
  58  * no enough CPU resources (cycles) to perform inlining,
  59  * the PCIe throughput is not supposed as bottleneck and
  60  * inlining is disabled.
  61  */
  62 #define MLX5_INLINE_MAX_TXQS 8u
  63 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u
  64
  65 /*
  66  * Default packet length threshold to be inlined with
  67  * enhanced MPW. If packet length exceeds the threshold
  68  * the data are not inlined. Should be aligned in WQEBB
  69  * boundary with accounting the title Control and Ethernet
  70  * segments.
  71  */
  72 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \
  73                                   MLX5_DSEG_MIN_INLINE_SIZE)
  74 /*
  75  * Maximal inline data length sent with enhanced MPW.
  76  * Is based on maximal WQE size.
  77  */
  78 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
  79                                   MLX5_WQE_CSEG_SIZE - \
  80                                   MLX5_WQE_ESEG_SIZE - \
  81                                   MLX5_WQE_DSEG_SIZE + \
  82                                   MLX5_DSEG_MIN_INLINE_SIZE)
  83 /*
  84  * Minimal amount of packets to be sent with EMPW.
  85  * This limits the minimal required size of sent EMPW.
  86  * If there are no enough resources to built minimal
  87  * EMPW the sending loop exits.
  88  */
  89 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u)
  90 /*
  91  * Maximal amount of packets to be sent with EMPW.
  92  * This value is not recommended to exceed MLX5_TX_COMP_THRESH,
  93  * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs
  94  * without CQE generation request, being multiplied by
  95  * MLX5_TX_COMP_MAX_CQE it may cause significant latency
  96  * in tx burst routine at the moment of freeing multiple mbufs.
  97  */
  98 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
  99 #define MLX5_MPW_MAX_PACKETS 6
 100 #define MLX5_MPW_INLINE_MAX_PACKETS 6
 101
 102 /*
 103  * Default packet length threshold to be inlined with
 104  * ordinary SEND. Inlining saves the MR key search
 105  * and extra PCIe data fetch transaction, but eats the
 106  * CPU cycles.
 107  */
 108 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \
 109                                   MLX5_ESEG_MIN_INLINE_SIZE - \
 110                                   MLX5_WQE_CSEG_SIZE - \
 111                                   MLX5_WQE_ESEG_SIZE - \
 112                                   MLX5_WQE_DSEG_SIZE)
 113 /*
 114  * Maximal inline data length sent with ordinary SEND.
 115  * Is based on maximal WQE size.
 116  */
 117 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
 118                                   MLX5_WQE_CSEG_SIZE - \
 119                                   MLX5_WQE_ESEG_SIZE - \
 120                                   MLX5_WQE_DSEG_SIZE + \
 121                                   MLX5_ESEG_MIN_INLINE_SIZE)
 122
 123 /* Missed in mlx5dv.h, should define here. */
 124 #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW
 125 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u
 126 #endif
 127
 128 #ifndef HAVE_MLX5_OPCODE_SEND_EN
 129 #define MLX5_OPCODE_SEND_EN 0x17u
 130 #endif
 131
 132 #ifndef HAVE_MLX5_OPCODE_WAIT
 133 #define MLX5_OPCODE_WAIT 0x0fu
 134 #endif
 135
 136 #ifndef HAVE_MLX5_OPCODE_ACCESS_ASO
 137 #define MLX5_OPCODE_ACCESS_ASO 0x2du
 138 #endif
 139
 140 /* CQE value to inform that VLAN is stripped. */
 141 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
 142
 143 /* IPv4 options. */
 144 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
 145
 146 /* IPv6 packet. */
 147 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
 148
 149 /* IPv4 packet. */
 150 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
 151
 152 /* TCP packet. */
 153 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
 154
 155 /* UDP packet. */
 156 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
 157
 158 /* IP is fragmented. */
 159 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
 160
 161 /* L2 header is valid. */
 162 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
 163
 164 /* L3 header is valid. */
 165 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
 166
 167 /* L4 header is valid. */
 168 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
 169
 170 /* Outer packet, 0 IPv4, 1 IPv6. */
 171 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
 172
 173 /* Tunnel packet bit in the CQE. */
 174 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
 175
 176 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
 177 #define MLX5_CQE_LRO_PUSH_MASK 0x40
 178
 179 /* Mask for L4 type in the CQE hdr_type_etc field. */
 180 #define MLX5_CQE_L4_TYPE_MASK 0x70
 181
 182 /* The bit index of L4 type in CQE hdr_type_etc field. */
 183 #define MLX5_CQE_L4_TYPE_SHIFT 0x4
 184
 185 /* L4 type to indicate TCP packet without acknowledgment. */
 186 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
 187
 188 /* L4 type to indicate TCP packet with acknowledgment. */
 189 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
 190
 191 /* Inner L3 checksum offload (Tunneled packets only). */
 192 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
 193
 194 /* Inner L4 checksum offload (Tunneled packets only). */
 195 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
 196
 197 /* Outer L4 type is TCP. */
 198 #define MLX5_ETH_WQE_L4_OUTER_TCP  (0u << 5)
 199
 200 /* Outer L4 type is UDP. */
 201 #define MLX5_ETH_WQE_L4_OUTER_UDP  (1u << 5)
 202
 203 /* Outer L3 type is IPV4. */
 204 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
 205
 206 /* Outer L3 type is IPV6. */
 207 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
 208
 209 /* Inner L4 type is TCP. */
 210 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
 211
 212 /* Inner L4 type is UDP. */
 213 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
 214
 215 /* Inner L3 type is IPV4. */
 216 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
 217
 218 /* Inner L3 type is IPV6. */
 219 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
 220
 221 /* VLAN insertion flag. */
 222 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31)
 223
 224 /* Data inline segment flag. */
 225 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31)
 226
 227 /* Is flow mark valid. */
 228 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
 229 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
 230 #else
 231 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
 232 #endif
 233
 234 /* INVALID is used by packets matching no flow rules. */
 235 #define MLX5_FLOW_MARK_INVALID 0
 236
 237 /* Maximum allowed value to mark a packet. */
 238 #define MLX5_FLOW_MARK_MAX 0xfffff0
 239
 240 /* Default mark value used when none is provided. */
 241 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
 242
 243 /* Default mark mask for metadata legacy mode. */
 244 #define MLX5_FLOW_MARK_MASK 0xffffff
 245
 246 /* Byte length mask when mark is enable in miniCQE */
 247 #define MLX5_LEN_WITH_MARK_MASK 0xffffff00
 248
 249 /* Maximum number of DS in WQE. Limited by 6-bit field. */
 250 #define MLX5_DSEG_MAX 63
 251
 252 /* The completion mode offset in the WQE control segment line 2. */
 253 #define MLX5_COMP_MODE_OFFSET 2
 254
 255 /* Amount of data bytes in minimal inline data segment. */
 256 #define MLX5_DSEG_MIN_INLINE_SIZE 12u
 257
 258 /* Amount of data bytes in minimal inline eth segment. */
 259 #define MLX5_ESEG_MIN_INLINE_SIZE 18u
 260
 261 /* Amount of data bytes after eth data segment. */
 262 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
 263
 264 /* The maximum log value of segments per RQ WQE. */
 265 #define MLX5_MAX_LOG_RQ_SEGS 5u
 266
 267 /* The alignment needed for WQ buffer. */
 268 #define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size()
 269
 270 /* The alignment needed for CQ buffer. */
 271 #define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size()
 272
 273 /* Completion mode. */
 274 enum mlx5_completion_mode {
 275         MLX5_COMP_ONLY_ERR = 0x0,
 276         MLX5_COMP_ONLY_FIRST_ERR = 0x1,
 277         MLX5_COMP_ALWAYS = 0x2,
 278         MLX5_COMP_CQE_AND_EQE = 0x3,
 279 };
 280
 281 /* MPW mode. */
 282 enum mlx5_mpw_mode {
 283         MLX5_MPW_DISABLED,
 284         MLX5_MPW,
 285         MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
 286 };
 287
 288 /* WQE Control segment. */
 289 struct mlx5_wqe_cseg {
 290         uint32_t opcode;
 291         uint32_t sq_ds;
 292         uint32_t flags;
 293         uint32_t misc;
 294 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
 295
 296 /*
 297  * WQE CSEG opcode field size is 32 bits, divided:
 298  * Bits 31:24 OPC_MOD
 299  * Bits 23:8 wqe_index
 300  * Bits 7:0 OPCODE
 301  */
 302 #define WQE_CSEG_OPC_MOD_OFFSET         24
 303 #define WQE_CSEG_WQE_INDEX_OFFSET        8
 304
 305 /* Header of data segment. Minimal size Data Segment */
 306 struct mlx5_wqe_dseg {
 307         uint32_t bcount;
 308         union {
 309                 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];
 310                 struct {
 311                         uint32_t lkey;
 312                         uint64_t pbuf;
 313                 } __rte_packed;
 314         };
 315 } __rte_packed;
 316
 317 /* Subset of struct WQE Ethernet Segment. */
 318 struct mlx5_wqe_eseg {
 319         union {
 320                 struct {
 321                         uint32_t swp_offs;
 322                         uint8_t cs_flags;
 323                         uint8_t swp_flags;
 324                         uint16_t mss;
 325                         uint32_t metadata;
 326                         uint16_t inline_hdr_sz;
 327                         union {
 328                                 uint16_t inline_data;
 329                                 uint16_t vlan_tag;
 330                         };
 331                 } __rte_packed;
 332                 struct {
 333                         uint32_t offsets;
 334                         uint32_t flags;
 335                         uint32_t flow_metadata;
 336                         uint32_t inline_hdr;
 337                 } __rte_packed;
 338         };
 339 } __rte_packed;
 340
 341 struct mlx5_wqe_qseg {
 342         uint32_t reserved0;
 343         uint32_t reserved1;
 344         uint32_t max_index;
 345         uint32_t qpn_cqn;
 346 } __rte_packed;
 347
 348 /* The title WQEBB, header of WQE. */
 349 struct mlx5_wqe {
 350         union {
 351                 struct mlx5_wqe_cseg cseg;
 352                 uint32_t ctrl[4];
 353         };
 354         struct mlx5_wqe_eseg eseg;
 355         union {
 356                 struct mlx5_wqe_dseg dseg[2];
 357                 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE];
 358         };
 359 } __rte_packed;
 360
 361 /* WQE for Multi-Packet RQ. */
 362 struct mlx5_wqe_mprq {
 363         struct mlx5_wqe_srq_next_seg next_seg;
 364         struct mlx5_wqe_data_seg dseg;
 365 };
 366
 367 #define MLX5_MPRQ_LEN_MASK 0x000ffff
 368 #define MLX5_MPRQ_LEN_SHIFT 0
 369 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
 370 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
 371 #define MLX5_MPRQ_FILLER_MASK 0x80000000
 372 #define MLX5_MPRQ_FILLER_SHIFT 31
 373
 374 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
 375
 376 /* CQ element structure - should be equal to the cache line size */
 377 struct mlx5_cqe {
 378 #if (RTE_CACHE_LINE_SIZE == 128)
 379         uint8_t padding[64];
 380 #endif
 381         uint8_t pkt_info;
 382         uint8_t rsvd0;
 383         uint16_t wqe_id;
 384         uint8_t lro_tcppsh_abort_dupack;
 385         uint8_t lro_min_ttl;
 386         uint16_t lro_tcp_win;
 387         uint32_t lro_ack_seq_num;
 388         uint32_t rx_hash_res;
 389         uint8_t rx_hash_type;
 390         uint8_t rsvd1[3];
 391         uint16_t csum;
 392         uint8_t rsvd2[6];
 393         uint16_t hdr_type_etc;
 394         uint16_t vlan_info;
 395         uint8_t lro_num_seg;
 396         uint8_t rsvd3[3];
 397         uint32_t flow_table_metadata;
 398         uint8_t rsvd4[4];
 399         uint32_t byte_cnt;
 400         uint64_t timestamp;
 401         uint32_t sop_drop_qpn;
 402         uint16_t wqe_counter;
 403         uint8_t rsvd5;
 404         uint8_t op_own;
 405 };
 406
 407 struct mlx5_cqe_ts {
 408         uint64_t timestamp;
 409         uint32_t sop_drop_qpn;
 410         uint16_t wqe_counter;
 411         uint8_t rsvd5;
 412         uint8_t op_own;
 413 };
 414
 415 /* GGA */
 416 /* MMO metadata segment */
 417
 418 #define MLX5_OPCODE_MMO 0x2fu
 419 #define MLX5_OPC_MOD_MMO_REGEX 0x4u
 420 #define MLX5_OPC_MOD_MMO_COMP 0x2u
 421 #define MLX5_OPC_MOD_MMO_DECOMP 0x3u
 422 #define MLX5_OPC_MOD_MMO_DMA 0x1u
 423
 424 #define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u
 425 #define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u
 426 #define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u
 427 #define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u
 428 #define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS)
 429 #define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u
 430 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX 15u
 431 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN 0u
 432
 433 struct mlx5_wqe_metadata_seg {
 434         uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */
 435         uint32_t lkey;
 436         uint64_t addr;
 437 };
 438
 439 struct mlx5_gga_wqe {
 440         uint32_t opcode;
 441         uint32_t sq_ds;
 442         uint32_t flags;
 443         uint32_t gga_ctrl1;  /* ws 12-15, bs 16-19, dyns 20-23. */
 444         uint32_t gga_ctrl2;
 445         uint32_t opaque_lkey;
 446         uint64_t opaque_vaddr;
 447         struct mlx5_wqe_dseg gather;
 448         struct mlx5_wqe_dseg scatter;
 449 } __rte_packed;
 450
 451 struct mlx5_gga_compress_opaque {
 452         uint32_t syndrom;
 453         uint32_t reserved0;
 454         uint32_t scattered_length;
 455         uint32_t gathered_length;
 456         uint64_t scatter_crc;
 457         uint64_t gather_crc;
 458         uint32_t crc32;
 459         uint32_t adler32;
 460         uint8_t reserved1[216];
 461 } __rte_packed;
 462
 463 struct mlx5_ifc_regexp_mmo_control_bits {
 464         uint8_t reserved_at_31[0x2];
 465         uint8_t le[0x1];
 466         uint8_t reserved_at_28[0x1];
 467         uint8_t subset_id_0[0xc];
 468         uint8_t reserved_at_16[0x4];
 469         uint8_t subset_id_1[0xc];
 470         uint8_t ctrl[0x4];
 471         uint8_t subset_id_2[0xc];
 472         uint8_t reserved_at_16_1[0x4];
 473         uint8_t subset_id_3[0xc];
 474 };
 475
 476 struct mlx5_ifc_regexp_metadata_bits {
 477         uint8_t rof_version[0x10];
 478         uint8_t latency_count[0x10];
 479         uint8_t instruction_count[0x10];
 480         uint8_t primary_thread_count[0x10];
 481         uint8_t match_count[0x8];
 482         uint8_t detected_match_count[0x8];
 483         uint8_t status[0x10];
 484         uint8_t job_id[0x20];
 485         uint8_t reserved[0x80];
 486 };
 487
 488 struct mlx5_ifc_regexp_match_tuple_bits {
 489         uint8_t length[0x10];
 490         uint8_t start_ptr[0x10];
 491         uint8_t rule_id[0x20];
 492 };
 493
 494 /* Adding direct verbs to data-path. */
 495
 496 /* CQ sequence number mask. */
 497 #define MLX5_CQ_SQN_MASK 0x3
 498
 499 /* CQ sequence number index. */
 500 #define MLX5_CQ_SQN_OFFSET 28
 501
 502 /* CQ doorbell index mask. */
 503 #define MLX5_CI_MASK 0xffffff
 504
 505 /* CQ doorbell offset. */
 506 #define MLX5_CQ_ARM_DB 1
 507
 508 /* CQ doorbell offset*/
 509 #define MLX5_CQ_DOORBELL 0x20
 510
 511 /* CQE format value. */
 512 #define MLX5_COMPRESSED 0x3
 513
 514 /* CQ doorbell cmd types. */
 515 #define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24)
 516 #define MLX5_CQ_DBR_CMD_ALL (0 << 24)
 517
 518 /* Action type of header modification. */
 519 enum {
 520         MLX5_MODIFICATION_TYPE_SET = 0x1,
 521         MLX5_MODIFICATION_TYPE_ADD = 0x2,
 522         MLX5_MODIFICATION_TYPE_COPY = 0x3,
 523 };
 524
 525 /* The field of packet to be modified. */
 526 enum mlx5_modification_field {
 527         MLX5_MODI_OUT_NONE = -1,
 528         MLX5_MODI_OUT_SMAC_47_16 = 1,
 529         MLX5_MODI_OUT_SMAC_15_0,
 530         MLX5_MODI_OUT_ETHERTYPE,
 531         MLX5_MODI_OUT_DMAC_47_16,
 532         MLX5_MODI_OUT_DMAC_15_0,
 533         MLX5_MODI_OUT_IP_DSCP,
 534         MLX5_MODI_OUT_TCP_FLAGS,
 535         MLX5_MODI_OUT_TCP_SPORT,
 536         MLX5_MODI_OUT_TCP_DPORT,
 537         MLX5_MODI_OUT_IPV4_TTL,
 538         MLX5_MODI_OUT_UDP_SPORT,
 539         MLX5_MODI_OUT_UDP_DPORT,
 540         MLX5_MODI_OUT_SIPV6_127_96,
 541         MLX5_MODI_OUT_SIPV6_95_64,
 542         MLX5_MODI_OUT_SIPV6_63_32,
 543         MLX5_MODI_OUT_SIPV6_31_0,
 544         MLX5_MODI_OUT_DIPV6_127_96,
 545         MLX5_MODI_OUT_DIPV6_95_64,
 546         MLX5_MODI_OUT_DIPV6_63_32,
 547         MLX5_MODI_OUT_DIPV6_31_0,
 548         MLX5_MODI_OUT_SIPV4,
 549         MLX5_MODI_OUT_DIPV4,
 550         MLX5_MODI_OUT_FIRST_VID,
 551         MLX5_MODI_IN_SMAC_47_16 = 0x31,
 552         MLX5_MODI_IN_SMAC_15_0,
 553         MLX5_MODI_IN_ETHERTYPE,
 554         MLX5_MODI_IN_DMAC_47_16,
 555         MLX5_MODI_IN_DMAC_15_0,
 556         MLX5_MODI_IN_IP_DSCP,
 557         MLX5_MODI_IN_TCP_FLAGS,
 558         MLX5_MODI_IN_TCP_SPORT,
 559         MLX5_MODI_IN_TCP_DPORT,
 560         MLX5_MODI_IN_IPV4_TTL,
 561         MLX5_MODI_IN_UDP_SPORT,
 562         MLX5_MODI_IN_UDP_DPORT,
 563         MLX5_MODI_IN_SIPV6_127_96,
 564         MLX5_MODI_IN_SIPV6_95_64,
 565         MLX5_MODI_IN_SIPV6_63_32,
 566         MLX5_MODI_IN_SIPV6_31_0,
 567         MLX5_MODI_IN_DIPV6_127_96,
 568         MLX5_MODI_IN_DIPV6_95_64,
 569         MLX5_MODI_IN_DIPV6_63_32,
 570         MLX5_MODI_IN_DIPV6_31_0,
 571         MLX5_MODI_IN_SIPV4,
 572         MLX5_MODI_IN_DIPV4,
 573         MLX5_MODI_OUT_IPV6_HOPLIMIT,
 574         MLX5_MODI_IN_IPV6_HOPLIMIT,
 575         MLX5_MODI_META_DATA_REG_A,
 576         MLX5_MODI_META_DATA_REG_B = 0x50,
 577         MLX5_MODI_META_REG_C_0,
 578         MLX5_MODI_META_REG_C_1,
 579         MLX5_MODI_META_REG_C_2,
 580         MLX5_MODI_META_REG_C_3,
 581         MLX5_MODI_META_REG_C_4,
 582         MLX5_MODI_META_REG_C_5,
 583         MLX5_MODI_META_REG_C_6,
 584         MLX5_MODI_META_REG_C_7,
 585         MLX5_MODI_OUT_TCP_SEQ_NUM,
 586         MLX5_MODI_IN_TCP_SEQ_NUM,
 587         MLX5_MODI_OUT_TCP_ACK_NUM,
 588         MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
 589         MLX5_MODI_GTP_TEID = 0x6E,
 590 };
 591
 592 /* Total number of metadata reg_c's. */
 593 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1)
 594
 595 enum modify_reg {
 596         REG_NON = 0,
 597         REG_A,
 598         REG_B,
 599         REG_C_0,
 600         REG_C_1,
 601         REG_C_2,
 602         REG_C_3,
 603         REG_C_4,
 604         REG_C_5,
 605         REG_C_6,
 606         REG_C_7,
 607 };
 608
 609 /* Modification sub command. */
 610 struct mlx5_modification_cmd {
 611         union {
 612                 uint32_t data0;
 613                 struct {
 614                         unsigned int length:5;
 615                         unsigned int rsvd0:3;
 616                         unsigned int offset:5;
 617                         unsigned int rsvd1:3;
 618                         unsigned int field:12;
 619                         unsigned int action_type:4;
 620                 };
 621         };
 622         union {
 623                 uint32_t data1;
 624                 uint8_t data[4];
 625                 struct {
 626                         unsigned int rsvd2:8;
 627                         unsigned int dst_offset:5;
 628                         unsigned int rsvd3:3;
 629                         unsigned int dst_field:12;
 630                         unsigned int rsvd4:4;
 631                 };
 632         };
 633 };
 634
 635 typedef uint64_t u64;
 636 typedef uint32_t u32;
 637 typedef uint16_t u16;
 638 typedef uint8_t u8;
 639
 640 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
 641 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
 642 #define __mlx5_bit_off(typ, fld) ((unsigned int)(uintptr_t) \
 643                                   (&(__mlx5_nullp(typ)->fld)))
 644 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
 645                                     (__mlx5_bit_off(typ, fld) & 0x1f))
 646 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
 647 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
 648 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
 649                                   __mlx5_dw_bit_off(typ, fld))
 650 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
 651 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
 652 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
 653                                     (__mlx5_bit_off(typ, fld) & 0xf))
 654 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
 655 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \
 656                                   __mlx5_16_bit_off(typ, fld))
 657 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
 658 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
 659 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
 660 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
 661
 662 /* insert a value to a struct */
 663 #define MLX5_SET(typ, p, fld, v) \
 664         do { \
 665                 u32 _v = v; \
 666                 *((rte_be32_t *)(p) + __mlx5_dw_off(typ, fld)) = \
 667                 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
 668                                   __mlx5_dw_off(typ, fld))) & \
 669                                   (~__mlx5_dw_mask(typ, fld))) | \
 670                                  (((_v) & __mlx5_mask(typ, fld)) << \
 671                                    __mlx5_dw_bit_off(typ, fld))); \
 672         } while (0)
 673
 674 #define MLX5_SET64(typ, p, fld, v) \
 675         do { \
 676                 MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \
 677                 *((rte_be64_t *)(p) + __mlx5_64_off(typ, fld)) = \
 678                         rte_cpu_to_be_64(v); \
 679         } while (0)
 680
 681 #define MLX5_SET16(typ, p, fld, v) \
 682         do { \
 683                 u16 _v = v; \
 684                 *((rte_be16_t *)(p) + __mlx5_16_off(typ, fld)) = \
 685                 rte_cpu_to_be_16((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
 686                                   __mlx5_16_off(typ, fld))) & \
 687                                   (~__mlx5_16_mask(typ, fld))) | \
 688                                  (((_v) & __mlx5_mask16(typ, fld)) << \
 689                                   __mlx5_16_bit_off(typ, fld))); \
 690         } while (0)
 691
 692 #define MLX5_GET_VOLATILE(typ, p, fld) \
 693         ((rte_be_to_cpu_32(*((volatile __be32 *)(p) +\
 694         __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
 695         __mlx5_mask(typ, fld))
 696 #define MLX5_GET(typ, p, fld) \
 697         ((rte_be_to_cpu_32(*((rte_be32_t *)(p) +\
 698         __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
 699         __mlx5_mask(typ, fld))
 700 #define MLX5_GET16(typ, p, fld) \
 701         ((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
 702           __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
 703          __mlx5_mask16(typ, fld))
 704 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((rte_be64_t *)(p) + \
 705                                                    __mlx5_64_off(typ, fld)))
 706 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
 707 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
 708
 709 struct mlx5_ifc_fte_match_set_misc_bits {
 710         u8 gre_c_present[0x1];
 711         u8 reserved_at_1[0x1];
 712         u8 gre_k_present[0x1];
 713         u8 gre_s_present[0x1];
 714         u8 source_vhci_port[0x4];
 715         u8 source_sqn[0x18];
 716         u8 reserved_at_20[0x10];
 717         u8 source_port[0x10];
 718         u8 outer_second_prio[0x3];
 719         u8 outer_second_cfi[0x1];
 720         u8 outer_second_vid[0xc];
 721         u8 inner_second_prio[0x3];
 722         u8 inner_second_cfi[0x1];
 723         u8 inner_second_vid[0xc];
 724         u8 outer_second_cvlan_tag[0x1];
 725         u8 inner_second_cvlan_tag[0x1];
 726         u8 outer_second_svlan_tag[0x1];
 727         u8 inner_second_svlan_tag[0x1];
 728         u8 reserved_at_64[0xc];
 729         u8 gre_protocol[0x10];
 730         u8 gre_key_h[0x18];
 731         u8 gre_key_l[0x8];
 732         u8 vxlan_vni[0x18];
 733         u8 reserved_at_b8[0x8];
 734         u8 geneve_vni[0x18];
 735         u8 reserved_at_e4[0x7];
 736         u8 geneve_oam[0x1];
 737         u8 reserved_at_e0[0xc];
 738         u8 outer_ipv6_flow_label[0x14];
 739         u8 reserved_at_100[0xc];
 740         u8 inner_ipv6_flow_label[0x14];
 741         u8 reserved_at_120[0xa];
 742         u8 geneve_opt_len[0x6];
 743         u8 geneve_protocol_type[0x10];
 744         u8 reserved_at_140[0xc0];
 745 };
 746
 747 struct mlx5_ifc_ipv4_layout_bits {
 748         u8 reserved_at_0[0x60];
 749         u8 ipv4[0x20];
 750 };
 751
 752 struct mlx5_ifc_ipv6_layout_bits {
 753         u8 ipv6[16][0x8];
 754 };
 755
 756 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 757         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 758         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 759         u8 reserved_at_0[0x80];
 760 };
 761
 762 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 763         u8 smac_47_16[0x20];
 764         u8 smac_15_0[0x10];
 765         u8 ethertype[0x10];
 766         u8 dmac_47_16[0x20];
 767         u8 dmac_15_0[0x10];
 768         u8 first_prio[0x3];
 769         u8 first_cfi[0x1];
 770         u8 first_vid[0xc];
 771         u8 ip_protocol[0x8];
 772         u8 ip_dscp[0x6];
 773         u8 ip_ecn[0x2];
 774         u8 cvlan_tag[0x1];
 775         u8 svlan_tag[0x1];
 776         u8 frag[0x1];
 777         u8 ip_version[0x4];
 778         u8 tcp_flags[0x9];
 779         u8 tcp_sport[0x10];
 780         u8 tcp_dport[0x10];
 781         u8 reserved_at_c0[0x18];
 782         u8 ip_ttl_hoplimit[0x8];
 783         u8 udp_sport[0x10];
 784         u8 udp_dport[0x10];
 785         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 786         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 787 };
 788
 789 struct mlx5_ifc_fte_match_mpls_bits {
 790         u8 mpls_label[0x14];
 791         u8 mpls_exp[0x3];
 792         u8 mpls_s_bos[0x1];
 793         u8 mpls_ttl[0x8];
 794 };
 795
 796 struct mlx5_ifc_fte_match_set_misc2_bits {
 797         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 798         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 799         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 800         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 801         u8 metadata_reg_c_7[0x20];
 802         u8 metadata_reg_c_6[0x20];
 803         u8 metadata_reg_c_5[0x20];
 804         u8 metadata_reg_c_4[0x20];
 805         u8 metadata_reg_c_3[0x20];
 806         u8 metadata_reg_c_2[0x20];
 807         u8 metadata_reg_c_1[0x20];
 808         u8 metadata_reg_c_0[0x20];
 809         u8 metadata_reg_a[0x20];
 810         u8 metadata_reg_b[0x20];
 811         u8 reserved_at_1c0[0x40];
 812 };
 813
 814 struct mlx5_ifc_fte_match_set_misc3_bits {
 815         u8 inner_tcp_seq_num[0x20];
 816         u8 outer_tcp_seq_num[0x20];
 817         u8 inner_tcp_ack_num[0x20];
 818         u8 outer_tcp_ack_num[0x20];
 819         u8 reserved_at_auto1[0x8];
 820         u8 outer_vxlan_gpe_vni[0x18];
 821         u8 outer_vxlan_gpe_next_protocol[0x8];
 822         u8 outer_vxlan_gpe_flags[0x8];
 823         u8 reserved_at_a8[0x10];
 824         u8 icmp_header_data[0x20];
 825         u8 icmpv6_header_data[0x20];
 826         u8 icmp_type[0x8];
 827         u8 icmp_code[0x8];
 828         u8 icmpv6_type[0x8];
 829         u8 icmpv6_code[0x8];
 830         u8 geneve_tlv_option_0_data[0x20];
 831         u8 gtpu_teid[0x20];
 832         u8 gtpu_msg_type[0x08];
 833         u8 gtpu_msg_flags[0x08];
 834         u8 reserved_at_170[0x10];
 835         u8 gtpu_dw_2[0x20];
 836         u8 gtpu_first_ext_dw_0[0x20];
 837         u8 gtpu_dw_0[0x20];
 838         u8 reserved_at_240[0x20];
 839
 840 };
 841
 842 struct mlx5_ifc_fte_match_set_misc4_bits {
 843         u8 prog_sample_field_value_0[0x20];
 844         u8 prog_sample_field_id_0[0x20];
 845         u8 prog_sample_field_value_1[0x20];
 846         u8 prog_sample_field_id_1[0x20];
 847         u8 prog_sample_field_value_2[0x20];
 848         u8 prog_sample_field_id_2[0x20];
 849         u8 prog_sample_field_value_3[0x20];
 850         u8 prog_sample_field_id_3[0x20];
 851         u8 reserved_at_100[0x100];
 852 };
 853
 854 /* Flow matcher. */
 855 struct mlx5_ifc_fte_match_param_bits {
 856         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
 857         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
 858         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
 859         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
 860         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
 861         struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
 862 /*
 863  * Add reserved bit to match the struct size with the size defined in PRM.
 864  * This extension is not required in Linux.
 865  */
 866 #ifndef HAVE_INFINIBAND_VERBS_H
 867         u8 reserved_0[0x400];
 868 #endif
 869 };
 870
 871 struct mlx5_ifc_dest_format_struct_bits {
 872         u8 destination_type[0x8];
 873         u8 destination_id[0x18];
 874         u8 reserved_0[0x20];
 875 };
 876
 877 enum {
 878         MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
 879         MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
 880         MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
 881         MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
 882         MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT,
 883         MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT,
 884 };
 885
 886 enum {
 887         MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
 888         MLX5_CMD_OP_CREATE_MKEY = 0x200,
 889         MLX5_CMD_OP_CREATE_CQ = 0x400,
 890         MLX5_CMD_OP_CREATE_QP = 0x500,
 891         MLX5_CMD_OP_RST2INIT_QP = 0x502,
 892         MLX5_CMD_OP_INIT2RTR_QP = 0x503,
 893         MLX5_CMD_OP_RTR2RTS_QP = 0x504,
 894         MLX5_CMD_OP_RTS2RTS_QP = 0x505,
 895         MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
 896         MLX5_CMD_OP_QP_2ERR = 0x507,
 897         MLX5_CMD_OP_QP_2RST = 0x50A,
 898         MLX5_CMD_OP_QUERY_QP = 0x50B,
 899         MLX5_CMD_OP_SQD2RTS_QP = 0x50C,
 900         MLX5_CMD_OP_INIT2INIT_QP = 0x50E,
 901         MLX5_CMD_OP_SUSPEND_QP = 0x50F,
 902         MLX5_CMD_OP_RESUME_QP = 0x510,
 903         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
 904         MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
 905         MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
 906         MLX5_CMD_OP_ALLOC_PD = 0x800,
 907         MLX5_CMD_OP_DEALLOC_PD = 0x801,
 908         MLX5_CMD_OP_ACCESS_REGISTER = 0x805,
 909         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
 910         MLX5_CMD_OP_CREATE_TIR = 0x900,
 911         MLX5_CMD_OP_MODIFY_TIR = 0x901,
 912         MLX5_CMD_OP_CREATE_SQ = 0X904,
 913         MLX5_CMD_OP_MODIFY_SQ = 0X905,
 914         MLX5_CMD_OP_CREATE_RQ = 0x908,
 915         MLX5_CMD_OP_MODIFY_RQ = 0x909,
 916         MLX5_CMD_OP_QUERY_RQ = 0x90b,
 917         MLX5_CMD_OP_CREATE_TIS = 0x912,
 918         MLX5_CMD_OP_QUERY_TIS = 0x915,
 919         MLX5_CMD_OP_CREATE_RQT = 0x916,
 920         MLX5_CMD_OP_MODIFY_RQT = 0x917,
 921         MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
 922         MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
 923         MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
 924         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
 925         MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
 926         MLX5_CMD_SET_REGEX_PARAMS = 0xb04,
 927         MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05,
 928         MLX5_CMD_SET_REGEX_REGISTERS = 0xb06,
 929         MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07,
 930         MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c,
 931 };
 932
 933 enum {
 934         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
 935         MLX5_MKC_ACCESS_MODE_KLM   = 0x2,
 936         MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3,
 937 };
 938
 939 #define MLX5_ADAPTER_PAGE_SHIFT 12
 940 #define MLX5_LOG_RQ_STRIDE_SHIFT 4
 941 /**
 942  * The batch counter dcs id starts from 0x800000 and none batch counter
 943  * starts from 0. As currently, the counter is changed to be indexed by
 944  * pool index and the offset of the counter in the pool counters_raw array.
 945  * It means now the counter index is same for batch and none batch counter.
 946  * Add the 0x800000 batch counter offset to the batch counter index helps
 947  * indicate the counter index is from batch or none batch container pool.
 948  */
 949 #define MLX5_CNT_BATCH_OFFSET 0x800000
 950
 951 /* The counter batch query requires ID align with 4. */
 952 #define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4
 953
 954 /* Flow counters. */
 955 struct mlx5_ifc_alloc_flow_counter_out_bits {
 956         u8         status[0x8];
 957         u8         reserved_at_8[0x18];
 958         u8         syndrome[0x20];
 959         u8         flow_counter_id[0x20];
 960         u8         reserved_at_60[0x20];
 961 };
 962
 963 struct mlx5_ifc_alloc_flow_counter_in_bits {
 964         u8         opcode[0x10];
 965         u8         reserved_at_10[0x10];
 966         u8         reserved_at_20[0x10];
 967         u8         op_mod[0x10];
 968         u8         flow_counter_id[0x20];
 969         u8         reserved_at_40[0x18];
 970         u8         flow_counter_bulk[0x8];
 971 };
 972
 973 struct mlx5_ifc_dealloc_flow_counter_out_bits {
 974         u8         status[0x8];
 975         u8         reserved_at_8[0x18];
 976         u8         syndrome[0x20];
 977         u8         reserved_at_40[0x40];
 978 };
 979
 980 struct mlx5_ifc_dealloc_flow_counter_in_bits {
 981         u8         opcode[0x10];
 982         u8         reserved_at_10[0x10];
 983         u8         reserved_at_20[0x10];
 984         u8         op_mod[0x10];
 985         u8         flow_counter_id[0x20];
 986         u8         reserved_at_60[0x20];
 987 };
 988
 989 struct mlx5_ifc_traffic_counter_bits {
 990         u8         packets[0x40];
 991         u8         octets[0x40];
 992 };
 993
 994 struct mlx5_ifc_query_flow_counter_out_bits {
 995         u8         status[0x8];
 996         u8         reserved_at_8[0x18];
 997         u8         syndrome[0x20];
 998         u8         reserved_at_40[0x40];
 999         struct mlx5_ifc_traffic_counter_bits flow_statistics[];
1000 };
1001
1002 struct mlx5_ifc_query_flow_counter_in_bits {
1003         u8         opcode[0x10];
1004         u8         reserved_at_10[0x10];
1005         u8         reserved_at_20[0x10];
1006         u8         op_mod[0x10];
1007         u8         reserved_at_40[0x20];
1008         u8         mkey[0x20];
1009         u8         address[0x40];
1010         u8         clear[0x1];
1011         u8         dump_to_memory[0x1];
1012         u8         num_of_counters[0x1e];
1013         u8         flow_counter_id[0x20];
1014 };
1015
1016 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u
1017 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u
1018
1019
1020 struct mlx5_ifc_klm_bits {
1021         u8         byte_count[0x20];
1022         u8         mkey[0x20];
1023         u8         address[0x40];
1024 };
1025
1026 struct mlx5_ifc_mkc_bits {
1027         u8         reserved_at_0[0x1];
1028         u8         free[0x1];
1029         u8         reserved_at_2[0x1];
1030         u8         access_mode_4_2[0x3];
1031         u8         reserved_at_6[0x7];
1032         u8         relaxed_ordering_write[0x1];
1033         u8         reserved_at_e[0x1];
1034         u8         small_fence_on_rdma_read_response[0x1];
1035         u8         umr_en[0x1];
1036         u8         a[0x1];
1037         u8         rw[0x1];
1038         u8         rr[0x1];
1039         u8         lw[0x1];
1040         u8         lr[0x1];
1041         u8         access_mode_1_0[0x2];
1042         u8         reserved_at_18[0x8];
1043
1044         u8         qpn[0x18];
1045         u8         mkey_7_0[0x8];
1046
1047         u8         reserved_at_40[0x20];
1048
1049         u8         length64[0x1];
1050         u8         bsf_en[0x1];
1051         u8         sync_umr[0x1];
1052         u8         reserved_at_63[0x2];
1053         u8         expected_sigerr_count[0x1];
1054         u8         reserved_at_66[0x1];
1055         u8         en_rinval[0x1];
1056         u8         pd[0x18];
1057
1058         u8         start_addr[0x40];
1059
1060         u8         len[0x40];
1061
1062         u8         bsf_octword_size[0x20];
1063
1064         u8         reserved_at_120[0x80];
1065
1066         u8         translations_octword_size[0x20];
1067
1068         u8         reserved_at_1c0[0x19];
1069         u8                 relaxed_ordering_read[0x1];
1070         u8                 reserved_at_1da[0x1];
1071         u8         log_page_size[0x5];
1072
1073         u8         reserved_at_1e0[0x20];
1074 };
1075
1076 struct mlx5_ifc_create_mkey_out_bits {
1077         u8         status[0x8];
1078         u8         reserved_at_8[0x18];
1079
1080         u8         syndrome[0x20];
1081
1082         u8         reserved_at_40[0x8];
1083         u8         mkey_index[0x18];
1084
1085         u8         reserved_at_60[0x20];
1086 };
1087
1088 struct mlx5_ifc_create_mkey_in_bits {
1089         u8         opcode[0x10];
1090         u8         reserved_at_10[0x10];
1091
1092         u8         reserved_at_20[0x10];
1093         u8         op_mod[0x10];
1094
1095         u8         reserved_at_40[0x20];
1096
1097         u8         pg_access[0x1];
1098         u8         reserved_at_61[0x1f];
1099
1100         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
1101
1102         u8         reserved_at_280[0x80];
1103
1104         u8         translations_octword_actual_size[0x20];
1105
1106         u8         mkey_umem_id[0x20];
1107
1108         u8         mkey_umem_offset[0x40];
1109
1110         u8         reserved_at_380[0x500];
1111
1112         u8         klm_pas_mtt[][0x20];
1113 };
1114
1115 enum {
1116         MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
1117         MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
1118         MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
1119         MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1,
1120         MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1,
1121         MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
1122 };
1123
1124 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \
1125                         (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTQ)
1126 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS \
1127                         (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS)
1128 #define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE \
1129                         (1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH)
1130 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \
1131                         (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO)
1132 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO \
1133                         (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO)
1134 #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \
1135                         (1ULL << MLX5_OBJ_TYPE_GENEVE_TLV_OPT)
1136
1137 enum {
1138         MLX5_HCA_CAP_OPMOD_GET_MAX   = 0,
1139         MLX5_HCA_CAP_OPMOD_GET_CUR   = 1,
1140 };
1141
1142 enum {
1143         MLX5_CAP_INLINE_MODE_L2,
1144         MLX5_CAP_INLINE_MODE_VPORT_CONTEXT,
1145         MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
1146 };
1147
1148 enum {
1149         MLX5_INLINE_MODE_NONE,
1150         MLX5_INLINE_MODE_L2,
1151         MLX5_INLINE_MODE_IP,
1152         MLX5_INLINE_MODE_TCP_UDP,
1153         MLX5_INLINE_MODE_RESERVED4,
1154         MLX5_INLINE_MODE_INNER_L2,
1155         MLX5_INLINE_MODE_INNER_IP,
1156         MLX5_INLINE_MODE_INNER_TCP_UDP,
1157 };
1158
1159 /* The supported timestamp formats reported in HCA attributes. */
1160 enum {
1161         MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR = 0x0,
1162         MLX5_HCA_CAP_TIMESTAMP_FORMAT_RT = 0x1,
1163         MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR_RT = 0x2,
1164 };
1165
1166 /* The timestamp format attributes to configure queues (RQ/SQ/QP). */
1167 enum {
1168         MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
1169         MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
1170         MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
1171 };
1172
1173 /* HCA bit masks indicating which Flex parser protocols are already enabled. */
1174 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0)
1175 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1)
1176 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2)
1177 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3)
1178 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4)
1179 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5)
1180 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6)
1181 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7)
1182 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8)
1183 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)
1184
1185 struct mlx5_ifc_cmd_hca_cap_bits {
1186         u8 reserved_at_0[0x30];
1187         u8 vhca_id[0x10];
1188         u8 reserved_at_40[0x20];
1189         u8 reserved_at_60[0x3];
1190         u8 log_regexp_scatter_gather_size[0x5];
1191         u8 reserved_at_68[0x3];
1192         u8 log_dma_mmo_size[0x5];
1193         u8 reserved_at_70[0x3];
1194         u8 log_compress_mmo_size[0x5];
1195         u8 reserved_at_78[0x3];
1196         u8 log_decompress_mmo_size[0x5];
1197         u8 log_max_srq_sz[0x8];
1198         u8 log_max_qp_sz[0x8];
1199         u8 reserved_at_90[0x9];
1200         u8 wqe_index_ignore_cap[0x1];
1201         u8 dynamic_qp_allocation[0x1];
1202         u8 log_max_qp[0x5];
1203         u8 regexp[0x1];
1204         u8 reserved_at_a1[0x3];
1205         u8 regexp_num_of_engines[0x4];
1206         u8 reserved_at_a8[0x1];
1207         u8 reg_c_preserve[0x1];
1208         u8 reserved_at_aa[0x1];
1209         u8 log_max_srq[0x5];
1210         u8 reserved_at_b0[0x3];
1211         u8 regexp_log_crspace_size[0x5];
1212         u8 reserved_at_b8[0x3];
1213         u8 scatter_fcs_w_decap_disable[0x1];
1214         u8 reserved_at_bc[0x4];
1215         u8 reserved_at_c0[0x8];
1216         u8 log_max_cq_sz[0x8];
1217         u8 reserved_at_d0[0xb];
1218         u8 log_max_cq[0x5];
1219         u8 log_max_eq_sz[0x8];
1220         u8 relaxed_ordering_write[0x1];
1221         u8 relaxed_ordering_read[0x1];
1222         u8 access_register_user[0x1];
1223         u8 log_max_mkey[0x5];
1224         u8 reserved_at_f0[0x8];
1225         u8 dump_fill_mkey[0x1];
1226         u8 reserved_at_f9[0x3];
1227         u8 log_max_eq[0x4];
1228         u8 max_indirection[0x8];
1229         u8 fixed_buffer_size[0x1];
1230         u8 log_max_mrw_sz[0x7];
1231         u8 force_teardown[0x1];
1232         u8 reserved_at_111[0x1];
1233         u8 log_max_bsf_list_size[0x6];
1234         u8 umr_extended_translation_offset[0x1];
1235         u8 null_mkey[0x1];
1236         u8 log_max_klm_list_size[0x6];
1237         u8 non_wire_sq[0x1];
1238         u8 reserved_at_121[0x9];
1239         u8 log_max_ra_req_dc[0x6];
1240         u8 reserved_at_130[0x3];
1241         u8 log_max_static_sq_wq[0x5];
1242         u8 reserved_at_138[0x2];
1243         u8 log_max_ra_res_dc[0x6];
1244         u8 reserved_at_140[0xa];
1245         u8 log_max_ra_req_qp[0x6];
1246         u8 rtr2rts_qp_counters_set_id[0x1];
1247         u8 rts2rts_udp_sport[0x1];
1248         u8 rts2rts_lag_tx_port_affinity[0x1];
1249         u8 dma_mmo[0x1];
1250         u8 compress_min_block_size[0x4];
1251         u8 compress[0x1];
1252         u8 decompress[0x1];
1253         u8 log_max_ra_res_qp[0x6];
1254         u8 end_pad[0x1];
1255         u8 cc_query_allowed[0x1];
1256         u8 cc_modify_allowed[0x1];
1257         u8 start_pad[0x1];
1258         u8 cache_line_128byte[0x1];
1259         u8 reserved_at_165[0xa];
1260         u8 qcam_reg[0x1];
1261         u8 gid_table_size[0x10];
1262         u8 out_of_seq_cnt[0x1];
1263         u8 vport_counters[0x1];
1264         u8 retransmission_q_counters[0x1];
1265         u8 debug[0x1];
1266         u8 modify_rq_counter_set_id[0x1];
1267         u8 rq_delay_drop[0x1];
1268         u8 max_qp_cnt[0xa];
1269         u8 pkey_table_size[0x10];
1270         u8 vport_group_manager[0x1];
1271         u8 vhca_group_manager[0x1];
1272         u8 ib_virt[0x1];
1273         u8 eth_virt[0x1];
1274         u8 vnic_env_queue_counters[0x1];
1275         u8 ets[0x1];
1276         u8 nic_flow_table[0x1];
1277         u8 eswitch_manager[0x1];
1278         u8 device_memory[0x1];
1279         u8 mcam_reg[0x1];
1280         u8 pcam_reg[0x1];
1281         u8 local_ca_ack_delay[0x5];
1282         u8 port_module_event[0x1];
1283         u8 enhanced_error_q_counters[0x1];
1284         u8 ports_check[0x1];
1285         u8 reserved_at_1b3[0x1];
1286         u8 disable_link_up[0x1];
1287         u8 beacon_led[0x1];
1288         u8 port_type[0x2];
1289         u8 num_ports[0x8];
1290         u8 reserved_at_1c0[0x1];
1291         u8 pps[0x1];
1292         u8 pps_modify[0x1];
1293         u8 log_max_msg[0x5];
1294         u8 reserved_at_1c8[0x4];
1295         u8 max_tc[0x4];
1296         u8 temp_warn_event[0x1];
1297         u8 dcbx[0x1];
1298         u8 general_notification_event[0x1];
1299         u8 reserved_at_1d3[0x2];
1300         u8 fpga[0x1];
1301         u8 rol_s[0x1];
1302         u8 rol_g[0x1];
1303         u8 reserved_at_1d8[0x1];
1304         u8 wol_s[0x1];
1305         u8 wol_g[0x1];
1306         u8 wol_a[0x1];
1307         u8 wol_b[0x1];
1308         u8 wol_m[0x1];
1309         u8 wol_u[0x1];
1310         u8 wol_p[0x1];
1311         u8 stat_rate_support[0x10];
1312         u8 reserved_at_1f0[0xc];
1313         u8 cqe_version[0x4];
1314         u8 compact_address_vector[0x1];
1315         u8 striding_rq[0x1];
1316         u8 reserved_at_202[0x1];
1317         u8 ipoib_enhanced_offloads[0x1];
1318         u8 ipoib_basic_offloads[0x1];
1319         u8 reserved_at_205[0x1];
1320         u8 repeated_block_disabled[0x1];
1321         u8 umr_modify_entity_size_disabled[0x1];
1322         u8 umr_modify_atomic_disabled[0x1];
1323         u8 umr_indirect_mkey_disabled[0x1];
1324         u8 umr_fence[0x2];
1325         u8 reserved_at_20c[0x3];
1326         u8 drain_sigerr[0x1];
1327         u8 cmdif_checksum[0x2];
1328         u8 sigerr_cqe[0x1];
1329         u8 reserved_at_213[0x1];
1330         u8 wq_signature[0x1];
1331         u8 sctr_data_cqe[0x1];
1332         u8 reserved_at_216[0x1];
1333         u8 sho[0x1];
1334         u8 tph[0x1];
1335         u8 rf[0x1];
1336         u8 dct[0x1];
1337         u8 qos[0x1];
1338         u8 eth_net_offloads[0x1];
1339         u8 roce[0x1];
1340         u8 atomic[0x1];
1341         u8 reserved_at_21f[0x1];
1342         u8 cq_oi[0x1];
1343         u8 cq_resize[0x1];
1344         u8 cq_moderation[0x1];
1345         u8 reserved_at_223[0x3];
1346         u8 cq_eq_remap[0x1];
1347         u8 pg[0x1];
1348         u8 block_lb_mc[0x1];
1349         u8 reserved_at_229[0x1];
1350         u8 scqe_break_moderation[0x1];
1351         u8 cq_period_start_from_cqe[0x1];
1352         u8 cd[0x1];
1353         u8 reserved_at_22d[0x1];
1354         u8 apm[0x1];
1355         u8 vector_calc[0x1];
1356         u8 umr_ptr_rlky[0x1];
1357         u8 imaicl[0x1];
1358         u8 reserved_at_232[0x4];
1359         u8 qkv[0x1];
1360         u8 pkv[0x1];
1361         u8 set_deth_sqpn[0x1];
1362         u8 reserved_at_239[0x3];
1363         u8 xrc[0x1];
1364         u8 ud[0x1];
1365         u8 uc[0x1];
1366         u8 rc[0x1];
1367         u8 uar_4k[0x1];
1368         u8 reserved_at_241[0x9];
1369         u8 uar_sz[0x6];
1370         u8 reserved_at_250[0x8];
1371         u8 log_pg_sz[0x8];
1372         u8 bf[0x1];
1373         u8 driver_version[0x1];
1374         u8 pad_tx_eth_packet[0x1];
1375         u8 reserved_at_263[0x8];
1376         u8 log_bf_reg_size[0x5];
1377         u8 reserved_at_270[0xb];
1378         u8 lag_master[0x1];
1379         u8 num_lag_ports[0x4];
1380         u8 reserved_at_280[0x10];
1381         u8 max_wqe_sz_sq[0x10];
1382         u8 reserved_at_2a0[0x10];
1383         u8 max_wqe_sz_rq[0x10];
1384         u8 max_flow_counter_31_16[0x10];
1385         u8 max_wqe_sz_sq_dc[0x10];
1386         u8 reserved_at_2e0[0x7];
1387         u8 max_qp_mcg[0x19];
1388         u8 reserved_at_300[0x10];
1389         u8 flow_counter_bulk_alloc[0x08];
1390         u8 log_max_mcg[0x8];
1391         u8 reserved_at_320[0x3];
1392         u8 log_max_transport_domain[0x5];
1393         u8 reserved_at_328[0x3];
1394         u8 log_max_pd[0x5];
1395         u8 reserved_at_330[0xb];
1396         u8 log_max_xrcd[0x5];
1397         u8 nic_receive_steering_discard[0x1];
1398         u8 receive_discard_vport_down[0x1];
1399         u8 transmit_discard_vport_down[0x1];
1400         u8 reserved_at_343[0x5];
1401         u8 log_max_flow_counter_bulk[0x8];
1402         u8 max_flow_counter_15_0[0x10];
1403         u8 modify_tis[0x1];
1404         u8 flow_counters_dump[0x1];
1405         u8 reserved_at_360[0x1];
1406         u8 log_max_rq[0x5];
1407         u8 reserved_at_368[0x3];
1408         u8 log_max_sq[0x5];
1409         u8 reserved_at_370[0x3];
1410         u8 log_max_tir[0x5];
1411         u8 reserved_at_378[0x3];
1412         u8 log_max_tis[0x5];
1413         u8 basic_cyclic_rcv_wqe[0x1];
1414         u8 reserved_at_381[0x2];
1415         u8 log_max_rmp[0x5];
1416         u8 reserved_at_388[0x3];
1417         u8 log_max_rqt[0x5];
1418         u8 reserved_at_390[0x3];
1419         u8 log_max_rqt_size[0x5];
1420         u8 reserved_at_398[0x3];
1421         u8 log_max_tis_per_sq[0x5];
1422         u8 ext_stride_num_range[0x1];
1423         u8 reserved_at_3a1[0x2];
1424         u8 log_max_stride_sz_rq[0x5];
1425         u8 reserved_at_3a8[0x3];
1426         u8 log_min_stride_sz_rq[0x5];
1427         u8 reserved_at_3b0[0x3];
1428         u8 log_max_stride_sz_sq[0x5];
1429         u8 reserved_at_3b8[0x3];
1430         u8 log_min_stride_sz_sq[0x5];
1431         u8 hairpin[0x1];
1432         u8 reserved_at_3c1[0x2];
1433         u8 log_max_hairpin_queues[0x5];
1434         u8 reserved_at_3c8[0x3];
1435         u8 log_max_hairpin_wq_data_sz[0x5];
1436         u8 reserved_at_3d0[0x3];
1437         u8 log_max_hairpin_num_packets[0x5];
1438         u8 reserved_at_3d8[0x3];
1439         u8 log_max_wq_sz[0x5];
1440         u8 nic_vport_change_event[0x1];
1441         u8 disable_local_lb_uc[0x1];
1442         u8 disable_local_lb_mc[0x1];
1443         u8 log_min_hairpin_wq_data_sz[0x5];
1444         u8 reserved_at_3e8[0x3];
1445         u8 log_max_vlan_list[0x5];
1446         u8 reserved_at_3f0[0x3];
1447         u8 log_max_current_mc_list[0x5];
1448         u8 reserved_at_3f8[0x3];
1449         u8 log_max_current_uc_list[0x5];
1450         u8 general_obj_types[0x40];
1451         u8 sq_ts_format[0x2];
1452         u8 rq_ts_format[0x2];
1453         u8 reserved_at_444[0x1C];
1454         u8 reserved_at_460[0x10];
1455         u8 max_num_eqs[0x10];
1456         u8 reserved_at_480[0x3];
1457         u8 log_max_l2_table[0x5];
1458         u8 reserved_at_488[0x8];
1459         u8 log_uar_page_sz[0x10];
1460         u8 reserved_at_4a0[0x20];
1461         u8 device_frequency_mhz[0x20];
1462         u8 device_frequency_khz[0x20];
1463         u8 reserved_at_500[0x20];
1464         u8 num_of_uars_per_page[0x20];
1465         u8 flex_parser_protocols[0x20];
1466         u8 max_geneve_tlv_options[0x8];
1467         u8 reserved_at_568[0x3];
1468         u8 max_geneve_tlv_option_data_len[0x5];
1469         u8 reserved_at_570[0x49];
1470         u8 mini_cqe_resp_l3_l4_tag[0x1];
1471         u8 mini_cqe_resp_flow_tag[0x1];
1472         u8 enhanced_cqe_compression[0x1];
1473         u8 mini_cqe_resp_stride_index[0x1];
1474         u8 cqe_128_always[0x1];
1475         u8 cqe_compression_128[0x1];
1476         u8 cqe_compression[0x1];
1477         u8 cqe_compression_timeout[0x10];
1478         u8 cqe_compression_max_num[0x10];
1479         u8 reserved_at_5e0[0x10];
1480         u8 tag_matching[0x1];
1481         u8 rndv_offload_rc[0x1];
1482         u8 rndv_offload_dc[0x1];
1483         u8 log_tag_matching_list_sz[0x5];
1484         u8 reserved_at_5f8[0x3];
1485         u8 log_max_xrq[0x5];
1486         u8 affiliate_nic_vport_criteria[0x8];
1487         u8 native_port_num[0x8];
1488         u8 num_vhca_ports[0x8];
1489         u8 reserved_at_618[0x6];
1490         u8 sw_owner_id[0x1];
1491         u8 reserved_at_61f[0x1e1];
1492 };
1493
1494 struct mlx5_ifc_qos_cap_bits {
1495         u8 packet_pacing[0x1];
1496         u8 esw_scheduling[0x1];
1497         u8 esw_bw_share[0x1];
1498         u8 esw_rate_limit[0x1];
1499         u8 reserved_at_4[0x1];
1500         u8 packet_pacing_burst_bound[0x1];
1501         u8 packet_pacing_typical_size[0x1];
1502         u8 flow_meter_old[0x1];
1503         u8 reserved_at_8[0x8];
1504         u8 log_max_flow_meter[0x8];
1505         u8 flow_meter_reg_id[0x8];
1506         u8 wqe_rate_pp[0x1];
1507         u8 reserved_at_25[0x7];
1508         u8 flow_meter[0x1];
1509         u8 reserved_at_2e[0x17];
1510         u8 packet_pacing_max_rate[0x20];
1511         u8 packet_pacing_min_rate[0x20];
1512         u8 reserved_at_80[0x10];
1513         u8 packet_pacing_rate_table_size[0x10];
1514         u8 esw_element_type[0x10];
1515         u8 esw_tsar_type[0x10];
1516         u8 reserved_at_c0[0x10];
1517         u8 max_qos_para_vport[0x10];
1518         u8 max_tsar_bw_share[0x20];
1519         u8 nic_element_type[0x10];
1520         u8 nic_tsar_type[0x10];
1521         u8 reserved_at_120[0x3];
1522         u8 log_meter_aso_granularity[0x5];
1523         u8 reserved_at_128[0x3];
1524         u8 log_meter_aso_max_alloc[0x5];
1525         u8 reserved_at_130[0x3];
1526         u8 log_max_num_meter_aso[0x5];
1527         u8 reserved_at_138[0x6b0];
1528 };
1529
1530 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1531         u8 csum_cap[0x1];
1532         u8 vlan_cap[0x1];
1533         u8 lro_cap[0x1];
1534         u8 lro_psh_flag[0x1];
1535         u8 lro_time_stamp[0x1];
1536         u8 lro_max_msg_sz_mode[0x2];
1537         u8 wqe_vlan_insert[0x1];
1538         u8 self_lb_en_modifiable[0x1];
1539         u8 self_lb_mc[0x1];
1540         u8 self_lb_uc[0x1];
1541         u8 max_lso_cap[0x5];
1542         u8 multi_pkt_send_wqe[0x2];
1543         u8 wqe_inline_mode[0x2];
1544         u8 rss_ind_tbl_cap[0x4];
1545         u8 reg_umr_sq[0x1];
1546         u8 scatter_fcs[0x1];
1547         u8 enhanced_multi_pkt_send_wqe[0x1];
1548         u8 tunnel_lso_const_out_ip_id[0x1];
1549         u8 tunnel_lro_gre[0x1];
1550         u8 tunnel_lro_vxlan[0x1];
1551         u8 tunnel_stateless_gre[0x1];
1552         u8 tunnel_stateless_vxlan[0x1];
1553         u8 swp[0x1];
1554         u8 swp_csum[0x1];
1555         u8 swp_lso[0x1];
1556         u8 reserved_at_23[0x8];
1557         u8 tunnel_stateless_gtp[0x1];
1558         u8 reserved_at_25[0x4];
1559         u8 max_vxlan_udp_ports[0x8];
1560         u8 reserved_at_38[0x6];
1561         u8 max_geneve_opt_len[0x1];
1562         u8 tunnel_stateless_geneve_rx[0x1];
1563         u8 reserved_at_40[0x10];
1564         u8 lro_min_mss_size[0x10];
1565         u8 reserved_at_60[0x120];
1566         u8 lro_timer_supported_periods[4][0x20];
1567         u8 reserved_at_200[0x600];
1568 };
1569
1570 enum {
1571         MLX5_VIRTQ_TYPE_SPLIT = 0,
1572         MLX5_VIRTQ_TYPE_PACKED = 1,
1573 };
1574
1575 enum {
1576         MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0,
1577         MLX5_VIRTQ_EVENT_MODE_QP = 1,
1578         MLX5_VIRTQ_EVENT_MODE_MSIX = 2,
1579 };
1580
1581 struct mlx5_ifc_virtio_emulation_cap_bits {
1582         u8 desc_tunnel_offload_type[0x1];
1583         u8 eth_frame_offload_type[0x1];
1584         u8 virtio_version_1_0[0x1];
1585         u8 tso_ipv4[0x1];
1586         u8 tso_ipv6[0x1];
1587         u8 tx_csum[0x1];
1588         u8 rx_csum[0x1];
1589         u8 reserved_at_7[0x1][0x9];
1590         u8 event_mode[0x8];
1591         u8 virtio_queue_type[0x8];
1592         u8 reserved_at_20[0x13];
1593         u8 log_doorbell_stride[0x5];
1594         u8 reserved_at_3b[0x3];
1595         u8 log_doorbell_bar_size[0x5];
1596         u8 doorbell_bar_offset[0x40];
1597         u8 reserved_at_80[0x8];
1598         u8 max_num_virtio_queues[0x18];
1599         u8 reserved_at_a0[0x60];
1600         u8 umem_1_buffer_param_a[0x20];
1601         u8 umem_1_buffer_param_b[0x20];
1602         u8 umem_2_buffer_param_a[0x20];
1603         u8 umem_2_buffer_param_b[0x20];
1604         u8 umem_3_buffer_param_a[0x20];
1605         u8 umem_3_buffer_param_b[0x20];
1606         u8 reserved_at_1c0[0x620];
1607 };
1608
1609 struct mlx5_ifc_flow_table_prop_layout_bits {
1610         u8 ft_support[0x1];
1611         u8 flow_tag[0x1];
1612         u8 flow_counter[0x1];
1613         u8 flow_modify_en[0x1];
1614         u8 modify_root[0x1];
1615         u8 identified_miss_table[0x1];
1616         u8 flow_table_modify[0x1];
1617         u8 reformat[0x1];
1618         u8 decap[0x1];
1619         u8 reset_root_to_default[0x1];
1620         u8 pop_vlan[0x1];
1621         u8 push_vlan[0x1];
1622         u8 fpga_vendor_acceleration[0x1];
1623         u8 pop_vlan_2[0x1];
1624         u8 push_vlan_2[0x1];
1625         u8 reformat_and_vlan_action[0x1];
1626         u8 modify_and_vlan_action[0x1];
1627         u8 sw_owner[0x1];
1628         u8 reformat_l3_tunnel_to_l2[0x1];
1629         u8 reformat_l2_to_l3_tunnel[0x1];
1630         u8 reformat_and_modify_action[0x1];
1631         u8 reserved_at_15[0x9];
1632         u8 sw_owner_v2[0x1];
1633         u8 reserved_at_1f[0x1];
1634         u8 reserved_at_20[0x2];
1635         u8 log_max_ft_size[0x6];
1636         u8 log_max_modify_header_context[0x8];
1637         u8 max_modify_header_actions[0x8];
1638         u8 max_ft_level[0x8];
1639         u8 reserved_at_40[0x8];
1640         u8 log_max_ft_sampler_num[8];
1641         u8 metadata_reg_b_width[0x8];
1642         u8 metadata_reg_a_width[0x8];
1643         u8 reserved_at_60[0x18];
1644         u8 log_max_ft_num[0x8];
1645         u8 reserved_at_80[0x10];
1646         u8 log_max_flow_counter[0x8];
1647         u8 log_max_destination[0x8];
1648         u8 reserved_at_a0[0x18];
1649         u8 log_max_flow[0x8];
1650         u8 reserved_at_c0[0x140];
1651 };
1652
1653 struct mlx5_ifc_roce_caps_bits {
1654         u8 reserved_0[0x1e];
1655         u8 qp_ts_format[0x2];
1656         u8 reserved_at_20[0x7e0];
1657 };
1658
1659 struct mlx5_ifc_flow_table_nic_cap_bits {
1660         u8         reserved_at_0[0x200];
1661         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties;
1662 };
1663
1664 union mlx5_ifc_hca_cap_union_bits {
1665         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1666         struct mlx5_ifc_per_protocol_networking_offload_caps_bits
1667                per_protocol_networking_offload_caps;
1668         struct mlx5_ifc_qos_cap_bits qos_cap;
1669         struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;
1670         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1671         struct mlx5_ifc_roce_caps_bits roce_caps;
1672         u8 reserved_at_0[0x8000];
1673 };
1674
1675 struct mlx5_ifc_set_action_in_bits {
1676         u8 action_type[0x4];
1677         u8 field[0xc];
1678         u8 reserved_at_10[0x3];
1679         u8 offset[0x5];
1680         u8 reserved_at_18[0x3];
1681         u8 length[0x5];
1682         u8 data[0x20];
1683 };
1684
1685 struct mlx5_ifc_query_hca_cap_out_bits {
1686         u8 status[0x8];
1687         u8 reserved_at_8[0x18];
1688         u8 syndrome[0x20];
1689         u8 reserved_at_40[0x40];
1690         union mlx5_ifc_hca_cap_union_bits capability;
1691 };
1692
1693 struct mlx5_ifc_query_hca_cap_in_bits {
1694         u8 opcode[0x10];
1695         u8 reserved_at_10[0x10];
1696         u8 reserved_at_20[0x10];
1697         u8 op_mod[0x10];
1698         u8 reserved_at_40[0x40];
1699 };
1700
1701 struct mlx5_ifc_mac_address_layout_bits {
1702         u8 reserved_at_0[0x10];
1703         u8 mac_addr_47_32[0x10];
1704         u8 mac_addr_31_0[0x20];
1705 };
1706
1707 struct mlx5_ifc_nic_vport_context_bits {
1708         u8 reserved_at_0[0x5];
1709         u8 min_wqe_inline_mode[0x3];
1710         u8 reserved_at_8[0x15];
1711         u8 disable_mc_local_lb[0x1];
1712         u8 disable_uc_local_lb[0x1];
1713         u8 roce_en[0x1];
1714         u8 arm_change_event[0x1];
1715         u8 reserved_at_21[0x1a];
1716         u8 event_on_mtu[0x1];
1717         u8 event_on_promisc_change[0x1];
1718         u8 event_on_vlan_change[0x1];
1719         u8 event_on_mc_address_change[0x1];
1720         u8 event_on_uc_address_change[0x1];
1721         u8 reserved_at_40[0xc];
1722         u8 affiliation_criteria[0x4];
1723         u8 affiliated_vhca_id[0x10];
1724         u8 reserved_at_60[0xd0];
1725         u8 mtu[0x10];
1726         u8 system_image_guid[0x40];
1727         u8 port_guid[0x40];
1728         u8 node_guid[0x40];
1729         u8 reserved_at_200[0x140];
1730         u8 qkey_violation_counter[0x10];
1731         u8 reserved_at_350[0x430];
1732         u8 promisc_uc[0x1];
1733         u8 promisc_mc[0x1];
1734         u8 promisc_all[0x1];
1735         u8 reserved_at_783[0x2];
1736         u8 allowed_list_type[0x3];
1737         u8 reserved_at_788[0xc];
1738         u8 allowed_list_size[0xc];
1739         struct mlx5_ifc_mac_address_layout_bits permanent_address;
1740         u8 reserved_at_7e0[0x20];
1741 };
1742
1743 struct mlx5_ifc_query_nic_vport_context_out_bits {
1744         u8 status[0x8];
1745         u8 reserved_at_8[0x18];
1746         u8 syndrome[0x20];
1747         u8 reserved_at_40[0x40];
1748         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
1749 };
1750
1751 struct mlx5_ifc_query_nic_vport_context_in_bits {
1752         u8 opcode[0x10];
1753         u8 reserved_at_10[0x10];
1754         u8 reserved_at_20[0x10];
1755         u8 op_mod[0x10];
1756         u8 other_vport[0x1];
1757         u8 reserved_at_41[0xf];
1758         u8 vport_number[0x10];
1759         u8 reserved_at_60[0x5];
1760         u8 allowed_list_type[0x3];
1761         u8 reserved_at_68[0x18];
1762 };
1763
1764 struct mlx5_ifc_tisc_bits {
1765         u8 strict_lag_tx_port_affinity[0x1];
1766         u8 reserved_at_1[0x3];
1767         u8 lag_tx_port_affinity[0x04];
1768         u8 reserved_at_8[0x4];
1769         u8 prio[0x4];
1770         u8 reserved_at_10[0x10];
1771         u8 reserved_at_20[0x100];
1772         u8 reserved_at_120[0x8];
1773         u8 transport_domain[0x18];
1774         u8 reserved_at_140[0x8];
1775         u8 underlay_qpn[0x18];
1776         u8 reserved_at_160[0x3a0];
1777 };
1778
1779 struct mlx5_ifc_query_tis_out_bits {
1780         u8 status[0x8];
1781         u8 reserved_at_8[0x18];
1782         u8 syndrome[0x20];
1783         u8 reserved_at_40[0x40];
1784         struct mlx5_ifc_tisc_bits tis_context;
1785 };
1786
1787 struct mlx5_ifc_query_tis_in_bits {
1788         u8 opcode[0x10];
1789         u8 reserved_at_10[0x10];
1790         u8 reserved_at_20[0x10];
1791         u8 op_mod[0x10];
1792         u8 reserved_at_40[0x8];
1793         u8 tisn[0x18];
1794         u8 reserved_at_60[0x20];
1795 };
1796
1797 struct mlx5_ifc_alloc_transport_domain_out_bits {
1798         u8 status[0x8];
1799         u8 reserved_at_8[0x18];
1800         u8 syndrome[0x20];
1801         u8 reserved_at_40[0x8];
1802         u8 transport_domain[0x18];
1803         u8 reserved_at_60[0x20];
1804 };
1805
1806 struct mlx5_ifc_alloc_transport_domain_in_bits {
1807         u8 opcode[0x10];
1808         u8 reserved_at_10[0x10];
1809         u8 reserved_at_20[0x10];
1810         u8 op_mod[0x10];
1811         u8 reserved_at_40[0x40];
1812 };
1813
1814 enum {
1815         MLX5_WQ_TYPE_LINKED_LIST                = 0x0,
1816         MLX5_WQ_TYPE_CYCLIC                     = 0x1,
1817         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ    = 0x2,
1818         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ         = 0x3,
1819 };
1820
1821 enum {
1822         MLX5_WQ_END_PAD_MODE_NONE  = 0x0,
1823         MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1824 };
1825
1826 struct mlx5_ifc_wq_bits {
1827         u8 wq_type[0x4];
1828         u8 wq_signature[0x1];
1829         u8 end_padding_mode[0x2];
1830         u8 cd_slave[0x1];
1831         u8 reserved_at_8[0x18];
1832         u8 hds_skip_first_sge[0x1];
1833         u8 log2_hds_buf_size[0x3];
1834         u8 reserved_at_24[0x7];
1835         u8 page_offset[0x5];
1836         u8 lwm[0x10];
1837         u8 reserved_at_40[0x8];
1838         u8 pd[0x18];
1839         u8 reserved_at_60[0x8];
1840         u8 uar_page[0x18];
1841         u8 dbr_addr[0x40];
1842         u8 hw_counter[0x20];
1843         u8 sw_counter[0x20];
1844         u8 reserved_at_100[0xc];
1845         u8 log_wq_stride[0x4];
1846         u8 reserved_at_110[0x3];
1847         u8 log_wq_pg_sz[0x5];
1848         u8 reserved_at_118[0x3];
1849         u8 log_wq_sz[0x5];
1850         u8 dbr_umem_valid[0x1];
1851         u8 wq_umem_valid[0x1];
1852         u8 reserved_at_122[0x1];
1853         u8 log_hairpin_num_packets[0x5];
1854         u8 reserved_at_128[0x3];
1855         u8 log_hairpin_data_sz[0x5];
1856         u8 reserved_at_130[0x4];
1857         u8 single_wqe_log_num_of_strides[0x4];
1858         u8 two_byte_shift_en[0x1];
1859         u8 reserved_at_139[0x4];
1860         u8 single_stride_log_num_of_bytes[0x3];
1861         u8 dbr_umem_id[0x20];
1862         u8 wq_umem_id[0x20];
1863         u8 wq_umem_offset[0x40];
1864         u8 reserved_at_1c0[0x440];
1865 };
1866
1867 enum {
1868         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
1869         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
1870 };
1871
1872 enum {
1873         MLX5_RQC_STATE_RST  = 0x0,
1874         MLX5_RQC_STATE_RDY  = 0x1,
1875         MLX5_RQC_STATE_ERR  = 0x3,
1876 };
1877
1878 struct mlx5_ifc_rqc_bits {
1879         u8 rlky[0x1];
1880         u8 delay_drop_en[0x1];
1881         u8 scatter_fcs[0x1];
1882         u8 vsd[0x1];
1883         u8 mem_rq_type[0x4];
1884         u8 state[0x4];
1885         u8 reserved_at_c[0x1];
1886         u8 flush_in_error_en[0x1];
1887         u8 hairpin[0x1];
1888         u8 reserved_at_f[0xB];
1889         u8 ts_format[0x02];
1890         u8 reserved_at_1c[0x4];
1891         u8 reserved_at_20[0x8];
1892         u8 user_index[0x18];
1893         u8 reserved_at_40[0x8];
1894         u8 cqn[0x18];
1895         u8 counter_set_id[0x8];
1896         u8 reserved_at_68[0x18];
1897         u8 reserved_at_80[0x8];
1898         u8 rmpn[0x18];
1899         u8 reserved_at_a0[0x8];
1900         u8 hairpin_peer_sq[0x18];
1901         u8 reserved_at_c0[0x10];
1902         u8 hairpin_peer_vhca[0x10];
1903         u8 reserved_at_e0[0xa0];
1904         struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */
1905 };
1906
1907 struct mlx5_ifc_create_rq_out_bits {
1908         u8 status[0x8];
1909         u8 reserved_at_8[0x18];
1910         u8 syndrome[0x20];
1911         u8 reserved_at_40[0x8];
1912         u8 rqn[0x18];
1913         u8 reserved_at_60[0x20];
1914 };
1915
1916 struct mlx5_ifc_create_rq_in_bits {
1917         u8 opcode[0x10];
1918         u8 uid[0x10];
1919         u8 reserved_at_20[0x10];
1920         u8 op_mod[0x10];
1921         u8 reserved_at_40[0xc0];
1922         struct mlx5_ifc_rqc_bits ctx;
1923 };
1924
1925 struct mlx5_ifc_modify_rq_out_bits {
1926         u8 status[0x8];
1927         u8 reserved_at_8[0x18];
1928         u8 syndrome[0x20];
1929         u8 reserved_at_40[0x40];
1930 };
1931
1932 struct mlx5_ifc_query_rq_out_bits {
1933         u8 status[0x8];
1934         u8 reserved_at_8[0x18];
1935         u8 syndrome[0x20];
1936         u8 reserved_at_40[0xc0];
1937         struct mlx5_ifc_rqc_bits rq_context;
1938 };
1939
1940 struct mlx5_ifc_query_rq_in_bits {
1941         u8 opcode[0x10];
1942         u8 reserved_at_10[0x10];
1943         u8 reserved_at_20[0x10];
1944         u8 op_mod[0x10];
1945         u8 reserved_at_40[0x8];
1946         u8 rqn[0x18];
1947         u8 reserved_at_60[0x20];
1948 };
1949
1950 struct mlx5_ifc_create_tis_out_bits {
1951         u8 status[0x8];
1952         u8 reserved_at_8[0x18];
1953         u8 syndrome[0x20];
1954         u8 reserved_at_40[0x8];
1955         u8 tisn[0x18];
1956         u8 reserved_at_60[0x20];
1957 };
1958
1959 struct mlx5_ifc_create_tis_in_bits {
1960         u8 opcode[0x10];
1961         u8 uid[0x10];
1962         u8 reserved_at_20[0x10];
1963         u8 op_mod[0x10];
1964         u8 reserved_at_40[0xc0];
1965         struct mlx5_ifc_tisc_bits ctx;
1966 };
1967
1968 enum {
1969         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,
1970         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
1971         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
1972         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
1973 };
1974
1975 struct mlx5_ifc_modify_rq_in_bits {
1976         u8 opcode[0x10];
1977         u8 uid[0x10];
1978         u8 reserved_at_20[0x10];
1979         u8 op_mod[0x10];
1980         u8 rq_state[0x4];
1981         u8 reserved_at_44[0x4];
1982         u8 rqn[0x18];
1983         u8 reserved_at_60[0x20];
1984         u8 modify_bitmask[0x40];
1985         u8 reserved_at_c0[0x40];
1986         struct mlx5_ifc_rqc_bits ctx;
1987 };
1988
1989 enum {
1990         MLX5_L3_PROT_TYPE_IPV4 = 0,
1991         MLX5_L3_PROT_TYPE_IPV6 = 1,
1992 };
1993
1994 enum {
1995         MLX5_L4_PROT_TYPE_TCP = 0,
1996         MLX5_L4_PROT_TYPE_UDP = 1,
1997 };
1998
1999 enum {
2000         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
2001         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
2002         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
2003         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
2004         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
2005 };
2006
2007 struct mlx5_ifc_rx_hash_field_select_bits {
2008         u8 l3_prot_type[0x1];
2009         u8 l4_prot_type[0x1];
2010         u8 selected_fields[0x1e];
2011 };
2012
2013 enum {
2014         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2015         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2016 };
2017
2018 enum {
2019         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2020         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2021 };
2022
2023 enum {
2024         MLX5_RX_HASH_FN_NONE           = 0x0,
2025         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2026         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2027 };
2028
2029 enum {
2030         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
2031         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
2032 };
2033
2034 enum {
2035         MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4    = 0x0,
2036         MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2  = 0x1,
2037 };
2038
2039 struct mlx5_ifc_tirc_bits {
2040         u8 reserved_at_0[0x20];
2041         u8 disp_type[0x4];
2042         u8 reserved_at_24[0x1c];
2043         u8 reserved_at_40[0x40];
2044         u8 reserved_at_80[0x4];
2045         u8 lro_timeout_period_usecs[0x10];
2046         u8 lro_enable_mask[0x4];
2047         u8 lro_max_msg_sz[0x8];
2048         u8 reserved_at_a0[0x40];
2049         u8 reserved_at_e0[0x8];
2050         u8 inline_rqn[0x18];
2051         u8 rx_hash_symmetric[0x1];
2052         u8 reserved_at_101[0x1];
2053         u8 tunneled_offload_en[0x1];
2054         u8 reserved_at_103[0x5];
2055         u8 indirect_table[0x18];
2056         u8 rx_hash_fn[0x4];
2057         u8 reserved_at_124[0x2];
2058         u8 self_lb_block[0x2];
2059         u8 transport_domain[0x18];
2060         u8 rx_hash_toeplitz_key[10][0x20];
2061         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2062         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2063         u8 reserved_at_2c0[0x4c0];
2064 };
2065
2066 struct mlx5_ifc_create_tir_out_bits {
2067         u8 status[0x8];
2068         u8 reserved_at_8[0x18];
2069         u8 syndrome[0x20];
2070         u8 reserved_at_40[0x8];
2071         u8 tirn[0x18];
2072         u8 reserved_at_60[0x20];
2073 };
2074
2075 struct mlx5_ifc_create_tir_in_bits {
2076         u8 opcode[0x10];
2077         u8 uid[0x10];
2078         u8 reserved_at_20[0x10];
2079         u8 op_mod[0x10];
2080         u8 reserved_at_40[0xc0];
2081         struct mlx5_ifc_tirc_bits ctx;
2082 };
2083
2084 enum {
2085         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO = 1ULL << 0,
2086         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE = 1ULL << 1,
2087         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH = 1ULL << 2,
2088         /* bit 3 - tunneled_offload_en modify not supported. */
2089         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN = 1ULL << 4,
2090 };
2091
2092 struct mlx5_ifc_modify_tir_out_bits {
2093         u8 status[0x8];
2094         u8 reserved_at_8[0x18];
2095         u8 syndrome[0x20];
2096         u8 reserved_at_40[0x40];
2097 };
2098
2099 struct mlx5_ifc_modify_tir_in_bits {
2100         u8 opcode[0x10];
2101         u8 uid[0x10];
2102         u8 reserved_at_20[0x10];
2103         u8 op_mod[0x10];
2104         u8 reserved_at_40[0x8];
2105         u8 tirn[0x18];
2106         u8 reserved_at_60[0x20];
2107         u8 modify_bitmask[0x40];
2108         u8 reserved_at_c0[0x40];
2109         struct mlx5_ifc_tirc_bits ctx;
2110 };
2111
2112 enum {
2113         MLX5_INLINE_Q_TYPE_RQ = 0x0,
2114         MLX5_INLINE_Q_TYPE_VIRTQ = 0x1,
2115 };
2116
2117 struct mlx5_ifc_rq_num_bits {
2118         u8 reserved_at_0[0x8];
2119         u8 rq_num[0x18];
2120 };
2121
2122 struct mlx5_ifc_rqtc_bits {
2123         u8 reserved_at_0[0xa5];
2124         u8 list_q_type[0x3];
2125         u8 reserved_at_a8[0x8];
2126         u8 rqt_max_size[0x10];
2127         u8 reserved_at_c0[0x10];
2128         u8 rqt_actual_size[0x10];
2129         u8 reserved_at_e0[0x6a0];
2130         struct mlx5_ifc_rq_num_bits rq_num[];
2131 };
2132
2133 struct mlx5_ifc_create_rqt_out_bits {
2134         u8 status[0x8];
2135         u8 reserved_at_8[0x18];
2136         u8 syndrome[0x20];
2137         u8 reserved_at_40[0x8];
2138         u8 rqtn[0x18];
2139         u8 reserved_at_60[0x20];
2140 };
2141
2142 #ifdef PEDANTIC
2143 #pragma GCC diagnostic ignored "-Wpedantic"
2144 #endif
2145 struct mlx5_ifc_create_rqt_in_bits {
2146         u8 opcode[0x10];
2147         u8 uid[0x10];
2148         u8 reserved_at_20[0x10];
2149         u8 op_mod[0x10];
2150         u8 reserved_at_40[0xc0];
2151         struct mlx5_ifc_rqtc_bits rqt_context;
2152 };
2153
2154 struct mlx5_ifc_modify_rqt_in_bits {
2155         u8 opcode[0x10];
2156         u8 uid[0x10];
2157         u8 reserved_at_20[0x10];
2158         u8 op_mod[0x10];
2159         u8 reserved_at_40[0x8];
2160         u8 rqtn[0x18];
2161         u8 reserved_at_60[0x20];
2162         u8 modify_bitmask[0x40];
2163         u8 reserved_at_c0[0x40];
2164         struct mlx5_ifc_rqtc_bits rqt_context;
2165 };
2166 #ifdef PEDANTIC
2167 #pragma GCC diagnostic error "-Wpedantic"
2168 #endif
2169
2170 struct mlx5_ifc_modify_rqt_out_bits {
2171         u8 status[0x8];
2172         u8 reserved_at_8[0x18];
2173         u8 syndrome[0x20];
2174         u8 reserved_at_40[0x40];
2175 };
2176
2177 enum {
2178         MLX5_SQC_STATE_RST  = 0x0,
2179         MLX5_SQC_STATE_RDY  = 0x1,
2180         MLX5_SQC_STATE_ERR  = 0x3,
2181 };
2182
2183 struct mlx5_ifc_sqc_bits {
2184         u8 rlky[0x1];
2185         u8 cd_master[0x1];
2186         u8 fre[0x1];
2187         u8 flush_in_error_en[0x1];
2188         u8 allow_multi_pkt_send_wqe[0x1];
2189         u8 min_wqe_inline_mode[0x3];
2190         u8 state[0x4];
2191         u8 reg_umr[0x1];
2192         u8 allow_swp[0x1];
2193         u8 hairpin[0x1];
2194         u8 non_wire[0x1];
2195         u8 static_sq_wq[0x1];
2196         u8 reserved_at_11[0x9];
2197         u8 ts_format[0x02];
2198         u8 reserved_at_1c[0x4];
2199         u8 reserved_at_20[0x8];
2200         u8 user_index[0x18];
2201         u8 reserved_at_40[0x8];
2202         u8 cqn[0x18];
2203         u8 reserved_at_60[0x8];
2204         u8 hairpin_peer_rq[0x18];
2205         u8 reserved_at_80[0x10];
2206         u8 hairpin_peer_vhca[0x10];
2207         u8 reserved_at_a0[0x50];
2208         u8 packet_pacing_rate_limit_index[0x10];
2209         u8 tis_lst_sz[0x10];
2210         u8 reserved_at_110[0x10];
2211         u8 reserved_at_120[0x40];
2212         u8 reserved_at_160[0x8];
2213         u8 tis_num_0[0x18];
2214         struct mlx5_ifc_wq_bits wq;
2215 };
2216
2217 struct mlx5_ifc_query_sq_in_bits {
2218         u8 opcode[0x10];
2219         u8 reserved_at_10[0x10];
2220         u8 reserved_at_20[0x10];
2221         u8 op_mod[0x10];
2222         u8 reserved_at_40[0x8];
2223         u8 sqn[0x18];
2224         u8 reserved_at_60[0x20];
2225 };
2226
2227 struct mlx5_ifc_modify_sq_out_bits {
2228         u8 status[0x8];
2229         u8 reserved_at_8[0x18];
2230         u8 syndrome[0x20];
2231         u8 reserved_at_40[0x40];
2232 };
2233
2234 struct mlx5_ifc_modify_sq_in_bits {
2235         u8 opcode[0x10];
2236         u8 uid[0x10];
2237         u8 reserved_at_20[0x10];
2238         u8 op_mod[0x10];
2239         u8 sq_state[0x4];
2240         u8 reserved_at_44[0x4];
2241         u8 sqn[0x18];
2242         u8 reserved_at_60[0x20];
2243         u8 modify_bitmask[0x40];
2244         u8 reserved_at_c0[0x40];
2245         struct mlx5_ifc_sqc_bits ctx;
2246 };
2247
2248 struct mlx5_ifc_create_sq_out_bits {
2249         u8 status[0x8];
2250         u8 reserved_at_8[0x18];
2251         u8 syndrome[0x20];
2252         u8 reserved_at_40[0x8];
2253         u8 sqn[0x18];
2254         u8 reserved_at_60[0x20];
2255 };
2256
2257 struct mlx5_ifc_create_sq_in_bits {
2258         u8 opcode[0x10];
2259         u8 uid[0x10];
2260         u8 reserved_at_20[0x10];
2261         u8 op_mod[0x10];
2262         u8 reserved_at_40[0xc0];
2263         struct mlx5_ifc_sqc_bits ctx;
2264 };
2265
2266 enum {
2267         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0),
2268         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1),
2269         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2),
2270         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3),
2271         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4),
2272 };
2273
2274 struct mlx5_ifc_flow_meter_parameters_bits {
2275         u8         valid[0x1];                  // 00h
2276         u8         bucket_overflow[0x1];
2277         u8         start_color[0x2];
2278         u8         both_buckets_on_green[0x1];
2279         u8         meter_mode[0x2];
2280         u8         reserved_at_1[0x19];
2281         u8         reserved_at_2[0x20]; //04h
2282         u8         reserved_at_3[0x3];
2283         u8         cbs_exponent[0x5];           // 08h
2284         u8         cbs_mantissa[0x8];
2285         u8         reserved_at_4[0x3];
2286         u8         cir_exponent[0x5];
2287         u8         cir_mantissa[0x8];
2288         u8         reserved_at_5[0x20];         // 0Ch
2289         u8         reserved_at_6[0x3];
2290         u8         ebs_exponent[0x5];           // 10h
2291         u8         ebs_mantissa[0x8];
2292         u8         reserved_at_7[0x3];
2293         u8         eir_exponent[0x5];
2294         u8         eir_mantissa[0x8];
2295         u8         reserved_at_8[0x60];         // 14h-1Ch
2296 };
2297 #define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF)
2298 #define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8
2299
2300 enum {
2301         MLX5_CQE_SIZE_64B = 0x0,
2302         MLX5_CQE_SIZE_128B = 0x1,
2303 };
2304
2305 struct mlx5_ifc_cqc_bits {
2306         u8 status[0x4];
2307         u8 as_notify[0x1];
2308         u8 initiator_src_dct[0x1];
2309         u8 dbr_umem_valid[0x1];
2310         u8 reserved_at_7[0x1];
2311         u8 cqe_sz[0x3];
2312         u8 cc[0x1];
2313         u8 reserved_at_c[0x1];
2314         u8 scqe_break_moderation_en[0x1];
2315         u8 oi[0x1];
2316         u8 cq_period_mode[0x2];
2317         u8 cqe_comp_en[0x1];
2318         u8 mini_cqe_res_format[0x2];
2319         u8 st[0x4];
2320         u8 reserved_at_18[0x1];
2321         u8 cqe_comp_layout[0x7];
2322         u8 dbr_umem_id[0x20];
2323         u8 reserved_at_40[0x14];
2324         u8 page_offset[0x6];
2325         u8 reserved_at_5a[0x2];
2326         u8 mini_cqe_res_format_ext[0x2];
2327         u8 cq_timestamp_format[0x2];
2328         u8 reserved_at_60[0x3];
2329         u8 log_cq_size[0x5];
2330         u8 uar_page[0x18];
2331         u8 reserved_at_80[0x4];
2332         u8 cq_period[0xc];
2333         u8 cq_max_count[0x10];
2334         u8 reserved_at_a0[0x18];
2335         u8 c_eqn[0x8];
2336         u8 reserved_at_c0[0x3];
2337         u8 log_page_size[0x5];
2338         u8 reserved_at_c8[0x18];
2339         u8 reserved_at_e0[0x20];
2340         u8 reserved_at_100[0x8];
2341         u8 last_notified_index[0x18];
2342         u8 reserved_at_120[0x8];
2343         u8 last_solicit_index[0x18];
2344         u8 reserved_at_140[0x8];
2345         u8 consumer_counter[0x18];
2346         u8 reserved_at_160[0x8];
2347         u8 producer_counter[0x18];
2348         u8 local_partition_id[0xc];
2349         u8 process_id[0x14];
2350         u8 reserved_at_1A0[0x20];
2351         u8 dbr_addr[0x40];
2352 };
2353
2354 struct mlx5_ifc_health_buffer_bits {
2355         u8         reserved_0[0x100];
2356         u8         assert_existptr[0x20];
2357         u8         assert_callra[0x20];
2358         u8         reserved_1[0x40];
2359         u8         fw_version[0x20];
2360         u8         hw_id[0x20];
2361         u8         reserved_2[0x20];
2362         u8         irisc_index[0x8];
2363         u8         synd[0x8];
2364         u8         ext_synd[0x10];
2365 };
2366
2367 struct mlx5_ifc_initial_seg_bits {
2368         u8         fw_rev_minor[0x10];
2369         u8         fw_rev_major[0x10];
2370         u8         cmd_interface_rev[0x10];
2371         u8         fw_rev_subminor[0x10];
2372         u8         reserved_0[0x40];
2373         u8         cmdq_phy_addr_63_32[0x20];
2374         u8         cmdq_phy_addr_31_12[0x14];
2375         u8         reserved_1[0x2];
2376         u8         nic_interface[0x2];
2377         u8         log_cmdq_size[0x4];
2378         u8         log_cmdq_stride[0x4];
2379         u8         command_doorbell_vector[0x20];
2380         u8         reserved_2[0xf00];
2381         u8         initializing[0x1];
2382         u8         nic_interface_supported[0x7];
2383         u8         reserved_4[0x18];
2384         struct mlx5_ifc_health_buffer_bits health_buffer;
2385         u8         no_dram_nic_offset[0x20];
2386         u8         reserved_5[0x6de0];
2387         u8         internal_timer_h[0x20];
2388         u8         internal_timer_l[0x20];
2389         u8         reserved_6[0x20];
2390         u8         reserved_7[0x1f];
2391         u8         clear_int[0x1];
2392         u8         health_syndrome[0x8];
2393         u8         health_counter[0x18];
2394         u8         reserved_8[0x17fc0];
2395 };
2396
2397 struct mlx5_ifc_create_cq_out_bits {
2398         u8 status[0x8];
2399         u8 reserved_at_8[0x18];
2400         u8 syndrome[0x20];
2401         u8 reserved_at_40[0x8];
2402         u8 cqn[0x18];
2403         u8 reserved_at_60[0x20];
2404 };
2405
2406 struct mlx5_ifc_create_cq_in_bits {
2407         u8 opcode[0x10];
2408         u8 uid[0x10];
2409         u8 reserved_at_20[0x10];
2410         u8 op_mod[0x10];
2411         u8 reserved_at_40[0x40];
2412         struct mlx5_ifc_cqc_bits cq_context;
2413         u8 cq_umem_offset[0x40];
2414         u8 cq_umem_id[0x20];
2415         u8 cq_umem_valid[0x1];
2416         u8 reserved_at_2e1[0x1f];
2417         u8 reserved_at_300[0x580];
2418         u8 pas[];
2419 };
2420
2421 enum {
2422         MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
2423         MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,
2424         MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
2425         MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022,
2426         MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024,
2427         MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025,
2428 };
2429
2430 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
2431         u8 opcode[0x10];
2432         u8 reserved_at_10[0x20];
2433         u8 obj_type[0x10];
2434         u8 obj_id[0x20];
2435         u8 reserved_at_60[0x3];
2436         u8 log_obj_range[0x5];
2437         u8 reserved_at_58[0x18];
2438 };
2439
2440 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
2441         u8 status[0x8];
2442         u8 reserved_at_8[0x18];
2443         u8 syndrome[0x20];
2444         u8 obj_id[0x20];
2445         u8 reserved_at_60[0x20];
2446 };
2447
2448 struct mlx5_ifc_virtio_q_counters_bits {
2449         u8 modify_field_select[0x40];
2450         u8 reserved_at_40[0x40];
2451         u8 received_desc[0x40];
2452         u8 completed_desc[0x40];
2453         u8 error_cqes[0x20];
2454         u8 bad_desc_errors[0x20];
2455         u8 exceed_max_chain[0x20];
2456         u8 invalid_buffer[0x20];
2457         u8 reserved_at_180[0x50];
2458 };
2459
2460 struct mlx5_ifc_geneve_tlv_option_bits {
2461         u8 modify_field_select[0x40];
2462         u8 reserved_at_40[0x18];
2463         u8 geneve_option_fte_index[0x8];
2464         u8 option_class[0x10];
2465         u8 option_type[0x8];
2466         u8 reserved_at_78[0x3];
2467         u8 option_data_length[0x5];
2468         u8 reserved_at_80[0x180];
2469 };
2470
2471 struct mlx5_ifc_create_virtio_q_counters_in_bits {
2472         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2473         struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2474 };
2475
2476 struct mlx5_ifc_query_virtio_q_counters_out_bits {
2477         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2478         struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2479 };
2480
2481 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
2482         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2483         struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
2484 };
2485
2486 enum {
2487         MLX5_VIRTQ_STATE_INIT = 0,
2488         MLX5_VIRTQ_STATE_RDY = 1,
2489         MLX5_VIRTQ_STATE_SUSPEND = 2,
2490         MLX5_VIRTQ_STATE_ERROR = 3,
2491 };
2492
2493 enum {
2494         MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0),
2495         MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3),
2496         MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4),
2497 };
2498
2499 struct mlx5_ifc_virtio_q_bits {
2500         u8 virtio_q_type[0x8];
2501         u8 reserved_at_8[0x5];
2502         u8 event_mode[0x3];
2503         u8 queue_index[0x10];
2504         u8 full_emulation[0x1];
2505         u8 virtio_version_1_0[0x1];
2506         u8 reserved_at_22[0x2];
2507         u8 offload_type[0x4];
2508         u8 event_qpn_or_msix[0x18];
2509         u8 doorbell_stride_idx[0x10];
2510         u8 queue_size[0x10];
2511         u8 device_emulation_id[0x20];
2512         u8 desc_addr[0x40];
2513         u8 used_addr[0x40];
2514         u8 available_addr[0x40];
2515         u8 virtio_q_mkey[0x20];
2516         u8 reserved_at_160[0x18];
2517         u8 error_type[0x8];
2518         u8 umem_1_id[0x20];
2519         u8 umem_1_size[0x20];
2520         u8 umem_1_offset[0x40];
2521         u8 umem_2_id[0x20];
2522         u8 umem_2_size[0x20];
2523         u8 umem_2_offset[0x40];
2524         u8 umem_3_id[0x20];
2525         u8 umem_3_size[0x20];
2526         u8 umem_3_offset[0x40];
2527         u8 counter_set_id[0x20];
2528         u8 reserved_at_320[0x8];
2529         u8 pd[0x18];
2530         u8 reserved_at_340[0x2];
2531         u8 queue_period_mode[0x2];
2532         u8 queue_period_us[0xc];
2533         u8 queue_max_count[0x10];
2534         u8 reserved_at_360[0xa0];
2535 };
2536
2537 struct mlx5_ifc_virtio_net_q_bits {
2538         u8 modify_field_select[0x40];
2539         u8 reserved_at_40[0x40];
2540         u8 tso_ipv4[0x1];
2541         u8 tso_ipv6[0x1];
2542         u8 tx_csum[0x1];
2543         u8 rx_csum[0x1];
2544         u8 reserved_at_84[0x6];
2545         u8 dirty_bitmap_dump_enable[0x1];
2546         u8 vhost_log_page[0x5];
2547         u8 reserved_at_90[0xc];
2548         u8 state[0x4];
2549         u8 reserved_at_a0[0x8];
2550         u8 tisn_or_qpn[0x18];
2551         u8 dirty_bitmap_mkey[0x20];
2552         u8 dirty_bitmap_size[0x20];
2553         u8 dirty_bitmap_addr[0x40];
2554         u8 hw_available_index[0x10];
2555         u8 hw_used_index[0x10];
2556         u8 reserved_at_160[0xa0];
2557         struct mlx5_ifc_virtio_q_bits virtio_q_context;
2558 };
2559
2560 struct mlx5_ifc_create_virtq_in_bits {
2561         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2562         struct mlx5_ifc_virtio_net_q_bits virtq;
2563 };
2564
2565 struct mlx5_ifc_query_virtq_out_bits {
2566         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2567         struct mlx5_ifc_virtio_net_q_bits virtq;
2568 };
2569
2570 struct mlx5_ifc_flow_hit_aso_bits {
2571         u8 modify_field_select[0x40];
2572         u8 reserved_at_40[0x48];
2573         u8 access_pd[0x18];
2574         u8 reserved_at_a0[0x160];
2575         u8 flag[0x200];
2576 };
2577
2578 struct mlx5_ifc_create_flow_hit_aso_in_bits {
2579         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2580         struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso;
2581 };
2582
2583 struct mlx5_ifc_flow_meter_aso_bits {
2584         u8 modify_field_select[0x40];
2585         u8 reserved_at_40[0x48];
2586         u8 access_pd[0x18];
2587         u8 reserved_at_a0[0x160];
2588         u8 parameters[0x200];
2589 };
2590
2591 struct mlx5_ifc_create_flow_meter_aso_in_bits {
2592         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2593         struct mlx5_ifc_flow_meter_aso_bits flow_meter_aso;
2594 };
2595 enum mlx5_access_aso_opc_mod {
2596         ASO_OPC_MOD_IPSEC = 0x0,
2597         ASO_OPC_MOD_CONNECTION_TRACKING = 0x1,
2598         ASO_OPC_MOD_POLICER = 0x2,
2599         ASO_OPC_MOD_RACE_AVOIDANCE = 0x3,
2600         ASO_OPC_MOD_FLOW_HIT = 0x4,
2601 };
2602
2603 #define ASO_CSEG_DATA_MASK_MODE_OFFSET  30
2604
2605 enum mlx5_aso_data_mask_mode {
2606         BITWISE_64BIT = 0x0,
2607         BYTEWISE_64BYTE = 0x1,
2608         CALCULATED_64BYTE = 0x2,
2609 };
2610
2611 #define ASO_CSEG_COND_0_OPER_OFFSET     20
2612 #define ASO_CSEG_COND_1_OPER_OFFSET     16
2613
2614 enum mlx5_aso_pre_cond_op {
2615         ASO_OP_ALWAYS_FALSE = 0x0,
2616         ASO_OP_ALWAYS_TRUE = 0x1,
2617         ASO_OP_EQUAL = 0x2,
2618         ASO_OP_NOT_EQUAL = 0x3,
2619         ASO_OP_GREATER_OR_EQUAL = 0x4,
2620         ASO_OP_LESSER_OR_EQUAL = 0x5,
2621         ASO_OP_LESSER = 0x6,
2622         ASO_OP_GREATER = 0x7,
2623         ASO_OP_CYCLIC_GREATER = 0x8,
2624         ASO_OP_CYCLIC_LESSER = 0x9,
2625 };
2626
2627 #define ASO_CSEG_COND_OPER_OFFSET       6
2628
2629 enum mlx5_aso_op {
2630         ASO_OPER_LOGICAL_AND = 0x0,
2631         ASO_OPER_LOGICAL_OR = 0x1,
2632 };
2633
2634 /* ASO WQE CTRL segment. */
2635 struct mlx5_aso_cseg {
2636         uint32_t va_h;
2637         uint32_t va_l_r;
2638         uint32_t lkey;
2639         uint32_t operand_masks;
2640         uint32_t condition_0_data;
2641         uint32_t condition_0_mask;
2642         uint32_t condition_1_data;
2643         uint32_t condition_1_mask;
2644         uint64_t bitwise_data;
2645         uint64_t data_mask;
2646 } __rte_packed;
2647
2648 /* A meter data segment - 2 per ASO WQE. */
2649 struct mlx5_aso_mtr_dseg {
2650         uint32_t v_bo_sc_bbog_mm;
2651         /*
2652          * bit 31: valid, 30: bucket overflow, 28-29: start color,
2653          * 27: both buckets on green, 24-25: meter mode.
2654          */
2655         uint32_t reserved;
2656         uint32_t cbs_cir;
2657         /*
2658          * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa,
2659          * bit 8-12: cir_exponent, bit 0-7 cir_mantissa.
2660          */
2661         uint32_t c_tokens;
2662         uint32_t ebs_eir;
2663         /*
2664          * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa,
2665          * bit 8-12: eir_exponent, bit 0-7 eir_mantissa.
2666          */
2667         uint32_t e_tokens;
2668         uint64_t timestamp;
2669 } __rte_packed;
2670
2671 #define ASO_DSEG_VALID_OFFSET 31
2672 #define ASO_DSEG_BO_OFFSET 30
2673 #define ASO_DSEG_SC_OFFSET 28
2674 #define ASO_DSEG_CBS_EXP_OFFSET 24
2675 #define ASO_DSEG_CBS_MAN_OFFSET 16
2676 #define ASO_DSEG_CIR_EXP_MASK 0x1F
2677 #define ASO_DSEG_CIR_EXP_OFFSET 8
2678 #define ASO_DSEG_EBS_EXP_OFFSET 24
2679 #define ASO_DSEG_EBS_MAN_OFFSET 16
2680 #define ASO_DSEG_EXP_MASK 0x1F
2681 #define ASO_DSEG_MAN_MASK 0xFF
2682
2683 #define MLX5_ASO_WQE_DSEG_SIZE  0x40
2684 #define MLX5_ASO_METERS_PER_WQE 2
2685 #define MLX5_ASO_MTRS_PER_POOL 128
2686
2687 /* ASO WQE data segment. */
2688 struct mlx5_aso_dseg {
2689         union {
2690                 uint8_t data[MLX5_ASO_WQE_DSEG_SIZE];
2691                 struct mlx5_aso_mtr_dseg mtrs[MLX5_ASO_METERS_PER_WQE];
2692         };
2693 } __rte_packed;
2694
2695 /* ASO WQE. */
2696 struct mlx5_aso_wqe {
2697         struct mlx5_wqe_cseg general_cseg;
2698         struct mlx5_aso_cseg aso_cseg;
2699         struct mlx5_aso_dseg aso_dseg;
2700 } __rte_packed;
2701
2702 enum {
2703         MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27,
2704 };
2705
2706 enum {
2707         MLX5_QP_ST_RC = 0x0,
2708 };
2709
2710 enum {
2711         MLX5_QP_PM_MIGRATED = 0x3,
2712 };
2713
2714 enum {
2715         MLX5_NON_ZERO_RQ = 0x0,
2716         MLX5_SRQ_RQ = 0x1,
2717         MLX5_CRQ_RQ = 0x2,
2718         MLX5_ZERO_LEN_RQ = 0x3,
2719 };
2720
2721 struct mlx5_ifc_ads_bits {
2722         u8 fl[0x1];
2723         u8 free_ar[0x1];
2724         u8 reserved_at_2[0xe];
2725         u8 pkey_index[0x10];
2726         u8 reserved_at_20[0x8];
2727         u8 grh[0x1];
2728         u8 mlid[0x7];
2729         u8 rlid[0x10];
2730         u8 ack_timeout[0x5];
2731         u8 reserved_at_45[0x3];
2732         u8 src_addr_index[0x8];
2733         u8 reserved_at_50[0x4];
2734         u8 stat_rate[0x4];
2735         u8 hop_limit[0x8];
2736         u8 reserved_at_60[0x4];
2737         u8 tclass[0x8];
2738         u8 flow_label[0x14];
2739         u8 rgid_rip[16][0x8];
2740         u8 reserved_at_100[0x4];
2741         u8 f_dscp[0x1];
2742         u8 f_ecn[0x1];
2743         u8 reserved_at_106[0x1];
2744         u8 f_eth_prio[0x1];
2745         u8 ecn[0x2];
2746         u8 dscp[0x6];
2747         u8 udp_sport[0x10];
2748         u8 dei_cfi[0x1];
2749         u8 eth_prio[0x3];
2750         u8 sl[0x4];
2751         u8 vhca_port_num[0x8];
2752         u8 rmac_47_32[0x10];
2753         u8 rmac_31_0[0x20];
2754 };
2755
2756 struct mlx5_ifc_qpc_bits {
2757         u8 state[0x4];
2758         u8 lag_tx_port_affinity[0x4];
2759         u8 st[0x8];
2760         u8 reserved_at_10[0x3];
2761         u8 pm_state[0x2];
2762         u8 reserved_at_15[0x1];
2763         u8 req_e2e_credit_mode[0x2];
2764         u8 offload_type[0x4];
2765         u8 end_padding_mode[0x2];
2766         u8 reserved_at_1e[0x2];
2767         u8 wq_signature[0x1];
2768         u8 block_lb_mc[0x1];
2769         u8 atomic_like_write_en[0x1];
2770         u8 latency_sensitive[0x1];
2771         u8 reserved_at_24[0x1];
2772         u8 drain_sigerr[0x1];
2773         u8 reserved_at_26[0x2];
2774         u8 pd[0x18];
2775         u8 mtu[0x3];
2776         u8 log_msg_max[0x5];
2777         u8 reserved_at_48[0x1];
2778         u8 log_rq_size[0x4];
2779         u8 log_rq_stride[0x3];
2780         u8 no_sq[0x1];
2781         u8 log_sq_size[0x4];
2782         u8 reserved_at_55[0x3];
2783         u8 ts_format[0x2];
2784         u8 reserved_at_5a[0x1];
2785         u8 rlky[0x1];
2786         u8 ulp_stateless_offload_mode[0x4];
2787         u8 counter_set_id[0x8];
2788         u8 uar_page[0x18];
2789         u8 reserved_at_80[0x8];
2790         u8 user_index[0x18];
2791         u8 reserved_at_a0[0x3];
2792         u8 log_page_size[0x5];
2793         u8 remote_qpn[0x18];
2794         struct mlx5_ifc_ads_bits primary_address_path;
2795         struct mlx5_ifc_ads_bits secondary_address_path;
2796         u8 log_ack_req_freq[0x4];
2797         u8 reserved_at_384[0x4];
2798         u8 log_sra_max[0x3];
2799         u8 reserved_at_38b[0x2];
2800         u8 retry_count[0x3];
2801         u8 rnr_retry[0x3];
2802         u8 reserved_at_393[0x1];
2803         u8 fre[0x1];
2804         u8 cur_rnr_retry[0x3];
2805         u8 cur_retry_count[0x3];
2806         u8 reserved_at_39b[0x5];
2807         u8 reserved_at_3a0[0x20];
2808         u8 reserved_at_3c0[0x8];
2809         u8 next_send_psn[0x18];
2810         u8 reserved_at_3e0[0x8];
2811         u8 cqn_snd[0x18];
2812         u8 reserved_at_400[0x8];
2813         u8 deth_sqpn[0x18];
2814         u8 reserved_at_420[0x20];
2815         u8 reserved_at_440[0x8];
2816         u8 last_acked_psn[0x18];
2817         u8 reserved_at_460[0x8];
2818         u8 ssn[0x18];
2819         u8 reserved_at_480[0x8];
2820         u8 log_rra_max[0x3];
2821         u8 reserved_at_48b[0x1];
2822         u8 atomic_mode[0x4];
2823         u8 rre[0x1];
2824         u8 rwe[0x1];
2825         u8 rae[0x1];
2826         u8 reserved_at_493[0x1];
2827         u8 page_offset[0x6];
2828         u8 reserved_at_49a[0x3];
2829         u8 cd_slave_receive[0x1];
2830         u8 cd_slave_send[0x1];
2831         u8 cd_master[0x1];
2832         u8 reserved_at_4a0[0x3];
2833         u8 min_rnr_nak[0x5];
2834         u8 next_rcv_psn[0x18];
2835         u8 reserved_at_4c0[0x8];
2836         u8 xrcd[0x18];
2837         u8 reserved_at_4e0[0x8];
2838         u8 cqn_rcv[0x18];
2839         u8 dbr_addr[0x40];
2840         u8 q_key[0x20];
2841         u8 reserved_at_560[0x5];
2842         u8 rq_type[0x3];
2843         u8 srqn_rmpn_xrqn[0x18];
2844         u8 reserved_at_580[0x8];
2845         u8 rmsn[0x18];
2846         u8 hw_sq_wqebb_counter[0x10];
2847         u8 sw_sq_wqebb_counter[0x10];
2848         u8 hw_rq_counter[0x20];
2849         u8 sw_rq_counter[0x20];
2850         u8 reserved_at_600[0x20];
2851         u8 reserved_at_620[0xf];
2852         u8 cgs[0x1];
2853         u8 cs_req[0x8];
2854         u8 cs_res[0x8];
2855         u8 dc_access_key[0x40];
2856         u8 reserved_at_680[0x3];
2857         u8 dbr_umem_valid[0x1];
2858         u8 reserved_at_684[0x9c];
2859         u8 dbr_umem_id[0x20];
2860 };
2861
2862 struct mlx5_ifc_create_qp_out_bits {
2863         u8 status[0x8];
2864         u8 reserved_at_8[0x18];
2865         u8 syndrome[0x20];
2866         u8 reserved_at_40[0x8];
2867         u8 qpn[0x18];
2868         u8 reserved_at_60[0x20];
2869 };
2870
2871 #ifdef PEDANTIC
2872 #pragma GCC diagnostic ignored "-Wpedantic"
2873 #endif
2874 struct mlx5_ifc_create_qp_in_bits {
2875         u8 opcode[0x10];
2876         u8 uid[0x10];
2877         u8 reserved_at_20[0x10];
2878         u8 op_mod[0x10];
2879         u8 reserved_at_40[0x40];
2880         u8 opt_param_mask[0x20];
2881         u8 reserved_at_a0[0x20];
2882         struct mlx5_ifc_qpc_bits qpc;
2883         u8 wq_umem_offset[0x40];
2884         u8 wq_umem_id[0x20];
2885         u8 wq_umem_valid[0x1];
2886         u8 reserved_at_861[0x1f];
2887         u8 pas[0][0x40];
2888 };
2889 #ifdef PEDANTIC
2890 #pragma GCC diagnostic error "-Wpedantic"
2891 #endif
2892
2893 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2894         u8 status[0x8];
2895         u8 reserved_at_8[0x18];
2896         u8 syndrome[0x20];
2897         u8 reserved_at_40[0x40];
2898 };
2899
2900 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2901         u8 opcode[0x10];
2902         u8 uid[0x10];
2903         u8 reserved_at_20[0x10];
2904         u8 op_mod[0x10];
2905         u8 reserved_at_40[0x8];
2906         u8 qpn[0x18];
2907         u8 reserved_at_60[0x20];
2908         u8 opt_param_mask[0x20];
2909         u8 reserved_at_a0[0x20];
2910         struct mlx5_ifc_qpc_bits qpc;
2911         u8 reserved_at_800[0x80];
2912 };
2913
2914 struct mlx5_ifc_sqd2rts_qp_out_bits {
2915         u8 status[0x8];
2916         u8 reserved_at_8[0x18];
2917         u8 syndrome[0x20];
2918         u8 reserved_at_40[0x40];
2919 };
2920
2921 struct mlx5_ifc_sqd2rts_qp_in_bits {
2922         u8 opcode[0x10];
2923         u8 uid[0x10];
2924         u8 reserved_at_20[0x10];
2925         u8 op_mod[0x10];
2926         u8 reserved_at_40[0x8];
2927         u8 qpn[0x18];
2928         u8 reserved_at_60[0x20];
2929         u8 opt_param_mask[0x20];
2930         u8 reserved_at_a0[0x20];
2931         struct mlx5_ifc_qpc_bits qpc;
2932         u8 reserved_at_800[0x80];
2933 };
2934
2935 struct mlx5_ifc_rts2rts_qp_out_bits {
2936         u8 status[0x8];
2937         u8 reserved_at_8[0x18];
2938         u8 syndrome[0x20];
2939         u8 reserved_at_40[0x40];
2940 };
2941
2942 struct mlx5_ifc_rts2rts_qp_in_bits {
2943         u8 opcode[0x10];
2944         u8 uid[0x10];
2945         u8 reserved_at_20[0x10];
2946         u8 op_mod[0x10];
2947         u8 reserved_at_40[0x8];
2948         u8 qpn[0x18];
2949         u8 reserved_at_60[0x20];
2950         u8 opt_param_mask[0x20];
2951         u8 reserved_at_a0[0x20];
2952         struct mlx5_ifc_qpc_bits qpc;
2953         u8 reserved_at_800[0x80];
2954 };
2955
2956 struct mlx5_ifc_rtr2rts_qp_out_bits {
2957         u8 status[0x8];
2958         u8 reserved_at_8[0x18];
2959         u8 syndrome[0x20];
2960         u8 reserved_at_40[0x40];
2961 };
2962
2963 struct mlx5_ifc_rtr2rts_qp_in_bits {
2964         u8 opcode[0x10];
2965         u8 uid[0x10];
2966         u8 reserved_at_20[0x10];
2967         u8 op_mod[0x10];
2968         u8 reserved_at_40[0x8];
2969         u8 qpn[0x18];
2970         u8 reserved_at_60[0x20];
2971         u8 opt_param_mask[0x20];
2972         u8 reserved_at_a0[0x20];
2973         struct mlx5_ifc_qpc_bits qpc;
2974         u8 reserved_at_800[0x80];
2975 };
2976
2977 struct mlx5_ifc_rst2init_qp_out_bits {
2978         u8 status[0x8];
2979         u8 reserved_at_8[0x18];
2980         u8 syndrome[0x20];
2981         u8 reserved_at_40[0x40];
2982 };
2983
2984 struct mlx5_ifc_rst2init_qp_in_bits {
2985         u8 opcode[0x10];
2986         u8 uid[0x10];
2987         u8 reserved_at_20[0x10];
2988         u8 op_mod[0x10];
2989         u8 reserved_at_40[0x8];
2990         u8 qpn[0x18];
2991         u8 reserved_at_60[0x20];
2992         u8 opt_param_mask[0x20];
2993         u8 reserved_at_a0[0x20];
2994         struct mlx5_ifc_qpc_bits qpc;
2995         u8 reserved_at_800[0x80];
2996 };
2997
2998 struct mlx5_ifc_init2rtr_qp_out_bits {
2999         u8 status[0x8];
3000         u8 reserved_at_8[0x18];
3001         u8 syndrome[0x20];
3002         u8 reserved_at_40[0x40];
3003 };
3004
3005 struct mlx5_ifc_init2rtr_qp_in_bits {
3006         u8 opcode[0x10];
3007         u8 uid[0x10];
3008         u8 reserved_at_20[0x10];
3009         u8 op_mod[0x10];
3010         u8 reserved_at_40[0x8];
3011         u8 qpn[0x18];
3012         u8 reserved_at_60[0x20];
3013         u8 opt_param_mask[0x20];
3014         u8 reserved_at_a0[0x20];
3015         struct mlx5_ifc_qpc_bits qpc;
3016         u8 reserved_at_800[0x80];
3017 };
3018
3019 struct mlx5_ifc_init2init_qp_out_bits {
3020         u8 status[0x8];
3021         u8 reserved_at_8[0x18];
3022         u8 syndrome[0x20];
3023         u8 reserved_at_40[0x40];
3024 };
3025
3026 struct mlx5_ifc_init2init_qp_in_bits {
3027         u8 opcode[0x10];
3028         u8 uid[0x10];
3029         u8 reserved_at_20[0x10];
3030         u8 op_mod[0x10];
3031         u8 reserved_at_40[0x8];
3032         u8 qpn[0x18];
3033         u8 reserved_at_60[0x20];
3034         u8 opt_param_mask[0x20];
3035         u8 reserved_at_a0[0x20];
3036         struct mlx5_ifc_qpc_bits qpc;
3037         u8 reserved_at_800[0x80];
3038 };
3039
3040 struct mlx5_ifc_dealloc_pd_out_bits {
3041         u8 status[0x8];
3042         u8 reserved_0[0x18];
3043         u8 syndrome[0x20];
3044         u8 reserved_1[0x40];
3045 };
3046
3047 struct mlx5_ifc_dealloc_pd_in_bits {
3048         u8 opcode[0x10];
3049         u8 reserved_0[0x10];
3050         u8 reserved_1[0x10];
3051         u8 op_mod[0x10];
3052         u8 reserved_2[0x8];
3053         u8 pd[0x18];
3054         u8 reserved_3[0x20];
3055 };
3056
3057 struct mlx5_ifc_alloc_pd_out_bits {
3058         u8 status[0x8];
3059         u8 reserved_0[0x18];
3060         u8 syndrome[0x20];
3061         u8 reserved_1[0x8];
3062         u8 pd[0x18];
3063         u8 reserved_2[0x20];
3064 };
3065
3066 struct mlx5_ifc_alloc_pd_in_bits {
3067         u8 opcode[0x10];
3068         u8 reserved_0[0x10];
3069         u8 reserved_1[0x10];
3070         u8 op_mod[0x10];
3071         u8 reserved_2[0x40];
3072 };
3073
3074 #ifdef PEDANTIC
3075 #pragma GCC diagnostic ignored "-Wpedantic"
3076 #endif
3077 struct mlx5_ifc_query_qp_out_bits {
3078         u8 status[0x8];
3079         u8 reserved_at_8[0x18];
3080         u8 syndrome[0x20];
3081         u8 reserved_at_40[0x40];
3082         u8 opt_param_mask[0x20];
3083         u8 reserved_at_a0[0x20];
3084         struct mlx5_ifc_qpc_bits qpc;
3085         u8 reserved_at_800[0x80];
3086         u8 pas[0][0x40];
3087 };
3088 #ifdef PEDANTIC
3089 #pragma GCC diagnostic error "-Wpedantic"
3090 #endif
3091
3092 struct mlx5_ifc_query_qp_in_bits {
3093         u8 opcode[0x10];
3094         u8 reserved_at_10[0x10];
3095         u8 reserved_at_20[0x10];
3096         u8 op_mod[0x10];
3097         u8 reserved_at_40[0x8];
3098         u8 qpn[0x18];
3099         u8 reserved_at_60[0x20];
3100 };
3101
3102 enum {
3103         MLX5_DATA_RATE = 0x0,
3104         MLX5_WQE_RATE = 0x1,
3105 };
3106
3107 struct mlx5_ifc_set_pp_rate_limit_context_bits {
3108         u8 rate_limit[0x20];
3109         u8 burst_upper_bound[0x20];
3110         u8 reserved_at_40[0xC];
3111         u8 rate_mode[0x4];
3112         u8 typical_packet_size[0x10];
3113         u8 reserved_at_60[0x120];
3114 };
3115
3116 #define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u
3117
3118 #ifdef PEDANTIC
3119 #pragma GCC diagnostic ignored "-Wpedantic"
3120 #endif
3121 struct mlx5_ifc_access_register_out_bits {
3122         u8 status[0x8];
3123         u8 reserved_at_8[0x18];
3124         u8 syndrome[0x20];
3125         u8 reserved_at_40[0x40];
3126         u8 register_data[0][0x20];
3127 };
3128
3129 struct mlx5_ifc_access_register_in_bits {
3130         u8 opcode[0x10];
3131         u8 reserved_at_10[0x10];
3132         u8 reserved_at_20[0x10];
3133         u8 op_mod[0x10];
3134         u8 reserved_at_40[0x10];
3135         u8 register_id[0x10];
3136         u8 argument[0x20];
3137         u8 register_data[0][0x20];
3138 };
3139 #ifdef PEDANTIC
3140 #pragma GCC diagnostic error "-Wpedantic"
3141 #endif
3142
3143 enum {
3144         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
3145         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
3146 };
3147
3148 enum {
3149         MLX5_REGISTER_ID_MTUTC  = 0x9055,
3150 };
3151
3152 struct mlx5_ifc_register_mtutc_bits {
3153         u8 time_stamp_mode[0x2];
3154         u8 time_stamp_state[0x2];
3155         u8 reserved_at_4[0x18];
3156         u8 operation[0x4];
3157         u8 freq_adjustment[0x20];
3158         u8 reserved_at_40[0x40];
3159         u8 utc_sec[0x20];
3160         u8 utc_nsec[0x20];
3161         u8 time_adjustment[0x20];
3162 };
3163
3164 #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0
3165 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1
3166
3167 struct mlx5_ifc_parse_graph_arc_bits {
3168         u8 start_inner_tunnel[0x1];
3169         u8 reserved_at_1[0x7];
3170         u8 arc_parse_graph_node[0x8];
3171         u8 compare_condition_value[0x10];
3172         u8 parse_graph_node_handle[0x20];
3173         u8 reserved_at_40[0x40];
3174 };
3175
3176 struct mlx5_ifc_parse_graph_flow_match_sample_bits {
3177         u8 flow_match_sample_en[0x1];
3178         u8 reserved_at_1[0x3];
3179         u8 flow_match_sample_offset_mode[0x4];
3180         u8 reserved_at_5[0x8];
3181         u8 flow_match_sample_field_offset[0x10];
3182         u8 reserved_at_32[0x4];
3183         u8 flow_match_sample_field_offset_shift[0x4];
3184         u8 flow_match_sample_field_base_offset[0x8];
3185         u8 reserved_at_48[0xd];
3186         u8 flow_match_sample_tunnel_mode[0x3];
3187         u8 flow_match_sample_field_offset_mask[0x20];
3188         u8 flow_match_sample_field_id[0x20];
3189 };
3190
3191 struct mlx5_ifc_parse_graph_flex_bits {
3192         u8 modify_field_select[0x40];
3193         u8 reserved_at_64[0x20];
3194         u8 header_length_base_value[0x10];
3195         u8 reserved_at_112[0x4];
3196         u8 header_length_field_shift[0x4];
3197         u8 reserved_at_120[0x4];
3198         u8 header_length_mode[0x4];
3199         u8 header_length_field_offset[0x10];
3200         u8 next_header_field_offset[0x10];
3201         u8 reserved_at_160[0x1b];
3202         u8 next_header_field_size[0x5];
3203         u8 header_length_field_mask[0x20];
3204         u8 reserved_at_224[0x20];
3205         struct mlx5_ifc_parse_graph_flow_match_sample_bits sample_table[0x8];
3206         struct mlx5_ifc_parse_graph_arc_bits input_arc[0x8];
3207         struct mlx5_ifc_parse_graph_arc_bits output_arc[0x8];
3208 };
3209
3210 struct mlx5_ifc_create_flex_parser_in_bits {
3211         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3212         struct mlx5_ifc_parse_graph_flex_bits flex;
3213 };
3214
3215 struct mlx5_ifc_create_flex_parser_out_bits {
3216         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3217         struct mlx5_ifc_parse_graph_flex_bits flex;
3218 };
3219
3220 struct mlx5_ifc_parse_graph_flex_out_bits {
3221         u8 status[0x8];
3222         u8 reserved_at_8[0x18];
3223         u8 syndrome[0x20];
3224         u8 reserved_at_40[0x40];
3225         struct mlx5_ifc_parse_graph_flex_bits capability;
3226 };
3227
3228 struct regexp_params_field_select_bits {
3229         u8 reserved_at_0[0x1e];
3230         u8 stop_engine[0x1];
3231         u8 db_umem_id[0x1];
3232 };
3233
3234 struct mlx5_ifc_regexp_params_bits {
3235         u8 reserved_at_0[0x1f];
3236         u8 stop_engine[0x1];
3237         u8 db_umem_id[0x20];
3238         u8 db_umem_offset[0x40];
3239         u8 reserved_at_80[0x100];
3240 };
3241
3242 struct mlx5_ifc_set_regexp_params_in_bits {
3243         u8 opcode[0x10];
3244         u8 uid[0x10];
3245         u8 reserved_at_20[0x10];
3246         u8 op_mod[0x10];
3247         u8 reserved_at_40[0x18];
3248         u8 engine_id[0x8];
3249         struct regexp_params_field_select_bits field_select;
3250         struct mlx5_ifc_regexp_params_bits regexp_params;
3251 };
3252
3253 struct mlx5_ifc_set_regexp_params_out_bits {
3254         u8 status[0x8];
3255         u8 reserved_at_8[0x18];
3256         u8 syndrome[0x20];
3257         u8 reserved_at_18[0x40];
3258 };
3259
3260 struct mlx5_ifc_query_regexp_params_in_bits {
3261         u8 opcode[0x10];
3262         u8 uid[0x10];
3263         u8 reserved_at_20[0x10];
3264         u8 op_mod[0x10];
3265         u8 reserved_at_40[0x18];
3266         u8 engine_id[0x8];
3267         u8 reserved[0x20];
3268 };
3269
3270 struct mlx5_ifc_query_regexp_params_out_bits {
3271         u8 status[0x8];
3272         u8 reserved_at_8[0x18];
3273         u8 syndrome[0x20];
3274         u8 reserved[0x40];
3275         struct mlx5_ifc_regexp_params_bits regexp_params;
3276 };
3277
3278 struct mlx5_ifc_set_regexp_register_in_bits {
3279         u8 opcode[0x10];
3280         u8 uid[0x10];
3281         u8 reserved_at_20[0x10];
3282         u8 op_mod[0x10];
3283         u8 reserved_at_40[0x18];
3284         u8 engine_id[0x8];
3285         u8 register_address[0x20];
3286         u8 register_data[0x20];
3287         u8 reserved[0x60];
3288 };
3289
3290 struct mlx5_ifc_set_regexp_register_out_bits {
3291         u8 status[0x8];
3292         u8 reserved_at_8[0x18];
3293         u8 syndrome[0x20];
3294         u8 reserved[0x40];
3295 };
3296
3297 struct mlx5_ifc_query_regexp_register_in_bits {
3298         u8 opcode[0x10];
3299         u8 uid[0x10];
3300         u8 reserved_at_20[0x10];
3301         u8 op_mod[0x10];
3302         u8 reserved_at_40[0x18];
3303         u8 engine_id[0x8];
3304         u8 register_address[0x20];
3305 };
3306
3307 struct mlx5_ifc_query_regexp_register_out_bits {
3308         u8 status[0x8];
3309         u8 reserved_at_8[0x18];
3310         u8 syndrome[0x20];
3311         u8 reserved[0x20];
3312         u8 register_data[0x20];
3313 };
3314
3315 /* Queue counters. */
3316 struct mlx5_ifc_alloc_q_counter_out_bits {
3317         u8 status[0x8];
3318         u8 reserved_at_8[0x18];
3319         u8 syndrome[0x20];
3320         u8 reserved_at_40[0x18];
3321         u8 counter_set_id[0x8];
3322         u8 reserved_at_60[0x20];
3323 };
3324
3325 struct mlx5_ifc_alloc_q_counter_in_bits {
3326         u8 opcode[0x10];
3327         u8 uid[0x10];
3328         u8 reserved_at_20[0x10];
3329         u8 op_mod[0x10];
3330         u8 reserved_at_40[0x40];
3331 };
3332
3333 struct mlx5_ifc_query_q_counter_out_bits {
3334         u8 status[0x8];
3335         u8 reserved_at_8[0x18];
3336         u8 syndrome[0x20];
3337         u8 reserved_at_40[0x40];
3338         u8 rx_write_requests[0x20];
3339         u8 reserved_at_a0[0x20];
3340         u8 rx_read_requests[0x20];
3341         u8 reserved_at_e0[0x20];
3342         u8 rx_atomic_requests[0x20];
3343         u8 reserved_at_120[0x20];
3344         u8 rx_dct_connect[0x20];
3345         u8 reserved_at_160[0x20];
3346         u8 out_of_buffer[0x20];
3347         u8 reserved_at_1a0[0x20];
3348         u8 out_of_sequence[0x20];
3349         u8 reserved_at_1e0[0x20];
3350         u8 duplicate_request[0x20];
3351         u8 reserved_at_220[0x20];
3352         u8 rnr_nak_retry_err[0x20];
3353         u8 reserved_at_260[0x20];
3354         u8 packet_seq_err[0x20];
3355         u8 reserved_at_2a0[0x20];
3356         u8 implied_nak_seq_err[0x20];
3357         u8 reserved_at_2e0[0x20];
3358         u8 local_ack_timeout_err[0x20];
3359         u8 reserved_at_320[0xa0];
3360         u8 resp_local_length_error[0x20];
3361         u8 req_local_length_error[0x20];
3362         u8 resp_local_qp_error[0x20];
3363         u8 local_operation_error[0x20];
3364         u8 resp_local_protection[0x20];
3365         u8 req_local_protection[0x20];
3366         u8 resp_cqe_error[0x20];
3367         u8 req_cqe_error[0x20];
3368         u8 req_mw_binding[0x20];
3369         u8 req_bad_response[0x20];
3370         u8 req_remote_invalid_request[0x20];
3371         u8 resp_remote_invalid_request[0x20];
3372         u8 req_remote_access_errors[0x20];
3373         u8 resp_remote_access_errors[0x20];
3374         u8 req_remote_operation_errors[0x20];
3375         u8 req_transport_retries_exceeded[0x20];
3376         u8 cq_overflow[0x20];
3377         u8 resp_cqe_flush_error[0x20];
3378         u8 req_cqe_flush_error[0x20];
3379         u8 reserved_at_620[0x1e0];
3380 };
3381
3382 struct mlx5_ifc_query_q_counter_in_bits {
3383         u8 opcode[0x10];
3384         u8 uid[0x10];
3385         u8 reserved_at_20[0x10];
3386         u8 op_mod[0x10];
3387         u8 reserved_at_40[0x80];
3388         u8 clear[0x1];
3389         u8 reserved_at_c1[0x1f];
3390         u8 reserved_at_e0[0x18];
3391         u8 counter_set_id[0x8];
3392 };
3393
3394 /* CQE format mask. */
3395 #define MLX5E_CQE_FORMAT_MASK 0xc
3396
3397 /* MPW opcode. */
3398 #define MLX5_OPC_MOD_MPW 0x01
3399
3400 /* Compressed Rx CQE structure. */
3401 struct mlx5_mini_cqe8 {
3402         union {
3403                 uint32_t rx_hash_result;
3404                 struct {
3405                         union {
3406                                 uint16_t checksum;
3407                                 uint16_t flow_tag_high;
3408                                 struct {
3409                                         uint8_t reserved;
3410                                         uint8_t hdr_type;
3411                                 };
3412                         };
3413                         uint16_t stride_idx;
3414                 };
3415                 struct {
3416                         uint16_t wqe_counter;
3417                         uint8_t  s_wqe_opcode;
3418                         uint8_t  reserved;
3419                 } s_wqe_info;
3420         };
3421         union {
3422                 uint32_t byte_cnt_flow;
3423                 uint32_t byte_cnt;
3424         };
3425 };
3426
3427 /* Mini CQE responder format. */
3428 enum {
3429         MLX5_CQE_RESP_FORMAT_HASH = 0x0,
3430         MLX5_CQE_RESP_FORMAT_CSUM = 0x1,
3431         MLX5_CQE_RESP_FORMAT_FTAG_STRIDX = 0x2,
3432         MLX5_CQE_RESP_FORMAT_CSUM_STRIDX = 0x3,
3433         MLX5_CQE_RESP_FORMAT_L34H_STRIDX = 0x4,
3434 };
3435
3436 /* srTCM PRM flow meter parameters. */
3437 enum {
3438         MLX5_FLOW_COLOR_RED = 0,
3439         MLX5_FLOW_COLOR_YELLOW,
3440         MLX5_FLOW_COLOR_GREEN,
3441         MLX5_FLOW_COLOR_UNDEFINED,
3442 };
3443
3444 /* Maximum value of srTCM metering parameters. */
3445 #define MLX5_SRTCM_CBS_MAX (0xFF * (1ULL << 0x1F))
3446 #define MLX5_SRTCM_CIR_MAX (8 * (1ULL << 30) * 0xFF)
3447 #define MLX5_SRTCM_EBS_MAX 0
3448
3449 /* The bits meter color use. */
3450 #define MLX5_MTR_COLOR_BITS 8
3451
3452 /* The bit size of one register. */
3453 #define MLX5_REG_BITS 32
3454
3455 /* Idle bits for non-color usage in color register. */
3456 #define MLX5_MTR_IDLE_BITS_IN_COLOR_REG (MLX5_REG_BITS - MLX5_MTR_COLOR_BITS)
3457
3458 /* Length mode of dynamic flex parser graph node. */
3459 enum mlx5_parse_graph_node_len_mode {
3460         MLX5_GRAPH_NODE_LEN_FIXED = 0x0,
3461         MLX5_GRAPH_NODE_LEN_FIELD = 0x1,
3462         MLX5_GRAPH_NODE_LEN_BITMASK = 0x2,
3463 };
3464
3465 /* Offset mode of the samples of flex parser. */
3466 enum mlx5_parse_graph_flow_match_sample_offset_mode {
3467         MLX5_GRAPH_SAMPLE_OFFSET_FIXED = 0x0,
3468         MLX5_GRAPH_SAMPLE_OFFSET_FIELD = 0x1,
3469         MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2,
3470 };
3471
3472 /* Node index for an input / output arc of the flex parser graph. */
3473 enum mlx5_parse_graph_arc_node_index {
3474         MLX5_GRAPH_ARC_NODE_NULL = 0x0,
3475         MLX5_GRAPH_ARC_NODE_HEAD = 0x1,
3476         MLX5_GRAPH_ARC_NODE_MAC = 0x2,
3477         MLX5_GRAPH_ARC_NODE_IP = 0x3,
3478         MLX5_GRAPH_ARC_NODE_GRE = 0x4,
3479         MLX5_GRAPH_ARC_NODE_UDP = 0x5,
3480         MLX5_GRAPH_ARC_NODE_MPLS = 0x6,
3481         MLX5_GRAPH_ARC_NODE_TCP = 0x7,
3482         MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8,
3483         MLX5_GRAPH_ARC_NODE_GENEVE = 0x9,
3484         MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa,
3485         MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f,
3486 };
3487
3488 /**
3489  * Convert a user mark to flow mark.
3490  *
3491  * @param val
3492  *   Mark value to convert.
3493  *
3494  * @return
3495  *   Converted mark value.
3496  */
3497 static inline uint32_t
3498 mlx5_flow_mark_set(uint32_t val)
3499 {
3500         uint32_t ret;
3501
3502         /*
3503          * Add one to the user value to differentiate un-marked flows from
3504          * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
3505          * remains untouched.
3506          */
3507         if (val != MLX5_FLOW_MARK_DEFAULT)
3508                 ++val;
3509 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
3510         /*
3511          * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
3512          * word, byte-swapped by the kernel on little-endian systems. In this
3513          * case, left-shifting the resulting big-endian value ensures the
3514          * least significant 24 bits are retained when converting it back.
3515          */
3516         ret = rte_cpu_to_be_32(val) >> 8;
3517 #else
3518         ret = val;
3519 #endif
3520         return ret;
3521 }
3522
3523 /**
3524  * Convert a mark to user mark.
3525  *
3526  * @param val
3527  *   Mark value to convert.
3528  *
3529  * @return
3530  *   Converted mark value.
3531  */
3532 static inline uint32_t
3533 mlx5_flow_mark_get(uint32_t val)
3534 {
3535         /*
3536          * Subtract one from the retrieved value. It was added by
3537          * mlx5_flow_mark_set() to distinguish unmarked flows.
3538          */
3539 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
3540         return (val >> 8) - 1;
3541 #else
3542         return val - 1;
3543 #endif
3544 }
3545
3546 /**
3547  * Convert a timestamp format to configure settings in the queue context.
3548  *
3549  * @param val
3550  *   timestamp format supported by the queue.
3551  *
3552  * @return
3553  *   Converted timstamp format settings.
3554  */
3555 static inline uint32_t
3556 mlx5_ts_format_conv(uint32_t ts_format)
3557 {
3558         return ts_format == MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR ?
3559                         MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING :
3560                         MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;
3561 }
3562
3563 #endif /* RTE_PMD_MLX5_PRM_H_ */