drivers/common/mlx5/rte_common_mlx5_version.map

   1 INTERNAL {
   2         global:
   3
   4         mlx5_class_get;
   5
   6         mlx5_common_verbs_reg_mr;
   7         mlx5_common_verbs_dereg_mr;
   8
   9         mlx5_create_mr_ext;
  10
  11         mlx5_dev_to_pci_addr;
  12
  13         mlx5_devx_cmd_create_cq;
  14         mlx5_devx_cmd_create_qp;
  15         mlx5_devx_cmd_create_rq;
  16         mlx5_devx_cmd_create_rqt;
  17         mlx5_devx_cmd_create_sq;
  18         mlx5_devx_cmd_create_tir;
  19         mlx5_devx_cmd_create_td;
  20         mlx5_devx_cmd_create_tis;
  21         mlx5_devx_cmd_create_virtio_q_counters;
  22         mlx5_devx_cmd_create_virtq;
  23         mlx5_devx_cmd_destroy;
  24         mlx5_devx_cmd_flow_counter_alloc;
  25         mlx5_devx_cmd_flow_counter_query;
  26         mlx5_devx_cmd_flow_dump;
  27         mlx5_devx_cmd_mkey_create;
  28         mlx5_devx_cmd_modify_qp_state;
  29         mlx5_devx_cmd_modify_rq;
  30         mlx5_devx_cmd_modify_rqt;
  31         mlx5_devx_cmd_modify_sq;
  32         mlx5_devx_cmd_modify_virtq;
  33         mlx5_devx_cmd_qp_query_tis_td;
  34         mlx5_devx_cmd_query_hca_attr;
  35         mlx5_devx_cmd_query_virtio_q_counters;
  36         mlx5_devx_cmd_query_virtq;
  37         mlx5_devx_get_out_command_status;
  38
  39         mlx5_mp_init_primary;
  40         mlx5_mp_uninit_primary;
  41         mlx5_mp_init_secondary;
  42         mlx5_mp_uninit_secondary;
  43         mlx5_mp_req_mr_create;
  44         mlx5_mp_req_queue_state_modify;
  45         mlx5_mp_req_verbs_cmd_fd;
  46
  47         mlx5_mr_btree_init;
  48         mlx5_mr_btree_free;
  49         mlx5_mr_btree_dump;
  50         mlx5_mr_addr2mr_bh;
  51         mlx5_mr_release_cache;
  52         mlx5_mr_dump_cache;
  53         mlx5_mr_rebuild_cache;
  54         mlx5_mr_insert_cache;
  55         mlx5_mr_lookup_cache;
  56         mlx5_mr_lookup_list;
  57         mlx5_mr_create_primary;
  58         mlx5_mr_flush_local_cache;
  59
  60         mlx5_nl_allmulti;
  61         mlx5_nl_devlink_family_id_get;
  62         mlx5_nl_driver_reload;
  63         mlx5_nl_enable_roce_get;
  64         mlx5_nl_enable_roce_set;
  65         mlx5_nl_ifindex;
  66         mlx5_nl_init;
  67         mlx5_nl_mac_addr_add;
  68         mlx5_nl_mac_addr_flush;
  69         mlx5_nl_mac_addr_remove;
  70         mlx5_nl_mac_addr_sync;
  71         mlx5_nl_portnum;
  72         mlx5_nl_promisc;
  73         mlx5_nl_switch_info;
  74         mlx5_nl_vf_mac_addr_modify;
  75         mlx5_nl_vlan_vmwa_create;
  76         mlx5_nl_vlan_vmwa_delete;
  77
  78         mlx5_translate_port_name;
  79 };
  80