drivers/common/mlx5/windows/mlx5_win_defs.h

   1 /*
   2  * Copyright (C) Mellanox Technologies, Ltd. 2001-2020.
   3  *
   4  */
   5 #ifndef __MLX5_WIN_DEFS_H__
   6 #define __MLX5_WIN_DEFS_H__
   7
   8 #ifdef __cplusplus
   9 extern "C" {
  10 #endif
  11
  12 enum {
  13         MLX5_CQE_OWNER_MASK     = 1,
  14         MLX5_CQE_REQ            = 0,
  15         MLX5_CQE_RESP_WR_IMM    = 1,
  16         MLX5_CQE_RESP_SEND      = 2,
  17         MLX5_CQE_RESP_SEND_IMM  = 3,
  18         MLX5_CQE_RESP_SEND_INV  = 4,
  19         MLX5_CQE_RESIZE_CQ      = 5,
  20         MLX5_CQE_NO_PACKET      = 6,
  21         MLX5_CQE_REQ_ERR        = 13,
  22         MLX5_CQE_RESP_ERR       = 14,
  23         MLX5_CQE_INVALID        = 15,
  24 };
  25
  26 enum {
  27         MLX5_OPCODE_NOP                 = 0x00,
  28         MLX5_OPCODE_SEND_INVAL          = 0x01,
  29         MLX5_OPCODE_RDMA_WRITE          = 0x08,
  30         MLX5_OPCODE_RDMA_WRITE_IMM      = 0x09,
  31         MLX5_OPCODE_SEND                = 0x0a,
  32         MLX5_OPCODE_SEND_IMM            = 0x0b,
  33         MLX5_OPCODE_TSO                 = 0x0e,
  34         MLX5_OPCODE_RDMA_READ           = 0x10,
  35         MLX5_OPCODE_ATOMIC_CS           = 0x11,
  36         MLX5_OPCODE_ATOMIC_FA           = 0x12,
  37         MLX5_OPCODE_ATOMIC_MASKED_CS    = 0x14,
  38         MLX5_OPCODE_ATOMIC_MASKED_FA    = 0x15,
  39         MLX5_OPCODE_FMR                 = 0x19,
  40         MLX5_OPCODE_LOCAL_INVAL         = 0x1b,
  41         MLX5_OPCODE_CONFIG_CMD          = 0x1f,
  42         MLX5_OPCODE_UMR                 = 0x25,
  43         MLX5_OPCODE_TAG_MATCHING        = 0x28
  44 };
  45
  46 enum mlx5dv_cq_init_attr_mask {
  47         MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE = 1 << 0,
  48         MLX5DV_CQ_INIT_ATTR_MASK_FLAGS          = 1 << 1,
  49         MLX5DV_CQ_INIT_ATTR_MASK_CQE_SIZE = 1 << 2,
  50 };
  51
  52 enum mlx5dv_cqe_comp_res_format {
  53         MLX5DV_CQE_RES_FORMAT_HASH              = 1 << 0,
  54         MLX5DV_CQE_RES_FORMAT_CSUM              = 1 << 1,
  55         MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX       = 1 << 2,
  56 };
  57
  58 enum ibv_access_flags {
  59         IBV_ACCESS_LOCAL_WRITE          = 1,
  60         IBV_ACCESS_REMOTE_WRITE         = 1 << 1,
  61         IBV_ACCESS_REMOTE_READ          = 1 << 2,
  62         IBV_ACCESS_REMOTE_ATOMIC        = 1 << 3,
  63         IBV_ACCESS_MW_BIND              = 1 << 4,
  64         IBV_ACCESS_ZERO_BASED           = 1 << 5,
  65         IBV_ACCESS_ON_DEMAND            = 1 << 6,
  66 };
  67
  68 enum mlx5_ib_uapi_devx_create_event_channel_flags {
  69         MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA = 1 << 0,
  70 };
  71
  72 #define MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA \
  73         MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA
  74
  75 enum {
  76         MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR              = 0x01,
  77         MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR               = 0x02,
  78         MLX5_CQE_SYNDROME_LOCAL_PROT_ERR                = 0x04,
  79         MLX5_CQE_SYNDROME_WR_FLUSH_ERR                  = 0x05,
  80         MLX5_CQE_SYNDROME_MW_BIND_ERR                   = 0x06,
  81         MLX5_CQE_SYNDROME_BAD_RESP_ERR                  = 0x10,
  82         MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR              = 0x11,
  83         MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR          = 0x12,
  84         MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR             = 0x13,
  85         MLX5_CQE_SYNDROME_REMOTE_OP_ERR                 = 0x14,
  86         MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR       = 0x15,
  87         MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR             = 0x16,
  88         MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR            = 0x22,
  89 };
  90
  91 enum {
  92         MLX5_ETH_WQE_L3_CSUM = (1 << 6),
  93         MLX5_ETH_WQE_L4_CSUM = (1 << 7),
  94 };
  95
  96 /*
  97  * RX Hash fields enable to set which incoming packet's field should
  98  * participates in RX Hash. Each flag represent certain packet's field,
  99  * when the flag is set the field that is represented by the flag will
 100  * participate in RX Hash calculation.
 101  * Note: IPV4 and IPV6 flags can't be enabled together on the same QP,
 102  * TCP and UDP flags can't be enabled together on the same QP.
 103  */
 104 enum ibv_rx_hash_fields {
 105         IBV_RX_HASH_SRC_IPV4    = 1 << 0,
 106         IBV_RX_HASH_DST_IPV4    = 1 << 1,
 107         IBV_RX_HASH_SRC_IPV6    = 1 << 2,
 108         IBV_RX_HASH_DST_IPV6    = 1 << 3,
 109         IBV_RX_HASH_SRC_PORT_TCP        = 1 << 4,
 110         IBV_RX_HASH_DST_PORT_TCP        = 1 << 5,
 111         IBV_RX_HASH_SRC_PORT_UDP        = 1 << 6,
 112         IBV_RX_HASH_DST_PORT_UDP        = 1 << 7,
 113         IBV_RX_HASH_IPSEC_SPI           = 1 << 8,
 114         IBV_RX_HASH_INNER               = (1 << 31),
 115 };
 116
 117 enum {
 118         MLX5_RCV_DBR    = 0,
 119         MLX5_SND_DBR    = 1,
 120 };
 121
 122 #ifndef MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2
 123 #define MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 0x0
 124 #endif
 125 #ifndef MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL
 126 #define MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL 0x1
 127 #endif
 128 #ifndef MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2
 129 #define MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 0x2
 130 #endif
 131 #ifndef MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL
 132 #define MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL 0x3
 133 #endif
 134
 135 struct mlx5_err_cqe {
 136         uint8_t         rsvd0[32];
 137         uint32_t        srqn;
 138         uint8_t         rsvd1[18];
 139         uint8_t         vendor_err_synd;
 140         uint8_t         syndrome;
 141         uint32_t        s_wqe_opcode_qpn;
 142         uint16_t        wqe_counter;
 143         uint8_t         signature;
 144         uint8_t         op_own;
 145 };
 146
 147 struct mlx5_wqe_srq_next_seg {
 148         uint8_t                 rsvd0[2];
 149         rte_be16_t              next_wqe_index;
 150         uint8_t                 signature;
 151         uint8_t                 rsvd1[11];
 152 };
 153
 154 enum ibv_wq_state {
 155         IBV_WQS_RESET,
 156         IBV_WQS_RDY,
 157         IBV_WQS_ERR,
 158         IBV_WQS_UNKNOWN
 159 };
 160
 161 struct mlx5_wqe_data_seg {
 162         rte_be32_t              byte_count;
 163         rte_be32_t              lkey;
 164         rte_be64_t              addr;
 165 };
 166
 167 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP      (1 << 4)
 168 #define IBV_DEVICE_RAW_IP_CSUM                  (1 << 26)
 169 #define IBV_RAW_PACKET_CAP_CVLAN_STRIPPING      (1 << 0)
 170 #define IBV_RAW_PACKET_CAP_SCATTER_FCS          (1 << 1)
 171 #define IBV_QPT_RAW_PACKET                      8
 172
 173 enum {
 174         MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT                    = 0x0,
 175         MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE               = 0x1,
 176         MLX5_FLOW_CONTEXT_DEST_TYPE_TIR                      = 0x2,
 177         MLX5_FLOW_CONTEXT_DEST_TYPE_QP                       = 0x3,
 178 };
 179 #endif /* __MLX5_WIN_DEFS_H__ */