1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2006-2019 Solarflare Communications Inc.
10 #include "efx_annote.h"
12 #include "efx_types.h"
13 #include "efx_check.h"
14 #include "efx_phy_ids.h"
20 #define EFX_STATIC_ASSERT(_cond) \
21 ((void)sizeof (char[(_cond) ? 1 : -1]))
23 #define EFX_ARRAY_SIZE(_array) \
24 (sizeof (_array) / sizeof ((_array)[0]))
26 #define EFX_FIELD_OFFSET(_type, _field) \
27 ((size_t)&(((_type *)0)->_field))
29 /* The macro expands divider twice */
30 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 /* Round value up to the nearest power of two. */
33 #define EFX_P2ROUNDUP(_type, _value, _align) \
34 (-(-(_type)(_value) & -(_type)(_align)))
36 /* Align value down to the nearest power of two. */
37 #define EFX_P2ALIGN(_type, _value, _align) \
38 ((_type)(_value) & -(_type)(_align))
40 /* Test if value is power of 2 aligned. */
41 #define EFX_IS_P2ALIGNED(_type, _value, _align) \
42 ((((_type)(_value)) & ((_type)(_align) - 1)) == 0)
46 typedef __success(return == 0) int efx_rc_t;
51 typedef enum efx_family_e {
53 EFX_FAMILY_FALCON, /* Obsolete and not supported */
55 EFX_FAMILY_HUNTINGTON,
62 typedef enum efx_bar_type_e {
67 typedef struct efx_bar_region_s {
68 efx_bar_type_t ebr_type;
70 efsys_dma_addr_t ebr_offset;
71 efsys_dma_addr_t ebr_length;
74 /* The function is deprecated. It is used only if Riverhead is not supported. */
76 extern __checkReturn efx_rc_t
80 __out efx_family_t *efp,
81 __out unsigned int *membarp);
85 /* PCIe interface numbers for multi-host configurations. */
86 typedef enum efx_pcie_interface_e {
87 EFX_PCIE_INTERFACE_CALLER = 1000,
88 EFX_PCIE_INTERFACE_HOST_PRIMARY,
89 EFX_PCIE_INTERFACE_NIC_EMBEDDED,
90 } efx_pcie_interface_t;
92 typedef struct efx_pci_ops_s {
94 * Function for reading PCIe configuration space.
96 * espcp System-specific PCIe device handle;
97 * offset Offset inside PCIe configuration space to start reading
99 * edp EFX DWORD structure that should be populated by function
100 * in little-endian order;
102 * Returns status code, 0 on success, any other value on error.
104 efx_rc_t (*epo_config_readd)(efsys_pci_config_t *espcp,
105 uint32_t offset, efx_dword_t *edp);
107 * Function for finding PCIe memory bar handle by its index from a PCIe
108 * device handle. The found memory bar is available in read-only mode.
110 * configp System-specific PCIe device handle;
111 * index Memory bar index;
112 * memp Pointer to the found memory bar handle;
114 * Returns status code, 0 on success, any other value on error.
116 efx_rc_t (*epo_find_mem_bar)(efsys_pci_config_t *configp,
117 int index, efsys_bar_t *memp);
120 /* Determine EFX family and perform lookup of the function control window
122 * The function requires PCI config handle from which all memory bars can
124 * A user of the API must be aware of memory bars indexes (not available
128 extern __checkReturn efx_rc_t
129 efx_family_probe_bar(
132 __in efsys_pci_config_t *espcp,
133 __in const efx_pci_ops_t *epop,
134 __out efx_family_t *efp,
135 __out efx_bar_region_t *ebrp);
137 #endif /* EFSYS_OPT_PCI */
140 #define EFX_PCI_VENID_SFC 0x1924
141 #define EFX_PCI_VENID_XILINX 0x10EE
143 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
145 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
146 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
147 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
149 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
150 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
151 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
153 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
154 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
156 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
157 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
158 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
160 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
161 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
162 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
164 #define EFX_PCI_DEVID_RIVERHEAD 0x0100
165 #define EFX_PCI_DEVID_RIVERHEAD_VF 0x1100
167 #define EFX_MEM_BAR_SIENA 2
169 #define EFX_MEM_BAR_HUNTINGTON_PF 2
170 #define EFX_MEM_BAR_HUNTINGTON_VF 0
172 #define EFX_MEM_BAR_MEDFORD_PF 2
173 #define EFX_MEM_BAR_MEDFORD_VF 0
175 #define EFX_MEM_BAR_MEDFORD2 0
177 /* FIXME Fix it when memory bar is fixed in FPGA image. It must be 0. */
178 #define EFX_MEM_BAR_RIVERHEAD 2
186 EFX_ERR_BUFID_DC_OOB,
199 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
201 extern __checkReturn uint32_t
203 __in uint32_t crc_init,
204 __in_ecount(length) uint8_t const *input,
208 /* Type prototypes */
210 typedef struct efx_rxq_s efx_rxq_t;
214 typedef struct efx_nic_s efx_nic_t;
217 extern __checkReturn efx_rc_t
219 __in efx_family_t family,
220 __in efsys_identifier_t *esip,
221 __in efsys_bar_t *esbp,
222 __in uint32_t fcw_offset,
223 __in efsys_lock_t *eslp,
224 __deref_out efx_nic_t **enpp);
226 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
227 typedef enum efx_fw_variant_e {
228 EFX_FW_VARIANT_FULL_FEATURED,
229 EFX_FW_VARIANT_LOW_LATENCY,
230 EFX_FW_VARIANT_PACKED_STREAM,
231 EFX_FW_VARIANT_HIGH_TX_RATE,
232 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
233 EFX_FW_VARIANT_RULES_ENGINE,
235 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
239 extern __checkReturn efx_rc_t
242 __in efx_fw_variant_t efv);
245 extern __checkReturn efx_rc_t
247 __in efx_nic_t *enp);
250 extern __checkReturn efx_rc_t
252 __in efx_nic_t *enp);
255 extern __checkReturn boolean_t
256 efx_nic_hw_unavailable(
257 __in efx_nic_t *enp);
261 efx_nic_set_hw_unavailable(
262 __in efx_nic_t *enp);
267 extern __checkReturn efx_rc_t
268 efx_nic_register_test(
269 __in efx_nic_t *enp);
271 #endif /* EFSYS_OPT_DIAG */
276 __in efx_nic_t *enp);
281 __in efx_nic_t *enp);
286 __in efx_nic_t *enp);
288 #define EFX_PCIE_LINK_SPEED_GEN1 1
289 #define EFX_PCIE_LINK_SPEED_GEN2 2
290 #define EFX_PCIE_LINK_SPEED_GEN3 3
292 typedef enum efx_pcie_link_performance_e {
293 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
294 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
295 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
296 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
297 } efx_pcie_link_performance_t;
300 extern __checkReturn efx_rc_t
301 efx_nic_calculate_pcie_link_bandwidth(
302 __in uint32_t pcie_link_width,
303 __in uint32_t pcie_link_gen,
304 __out uint32_t *bandwidth_mbpsp);
307 extern __checkReturn efx_rc_t
308 efx_nic_check_pcie_link_speed(
310 __in uint32_t pcie_link_width,
311 __in uint32_t pcie_link_gen,
312 __out efx_pcie_link_performance_t *resultp);
316 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
317 /* EF10 architecture and Riverhead NICs require MCDIv2 commands */
318 #define WITH_MCDI_V2 1
321 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
323 typedef enum efx_mcdi_exception_e {
324 EFX_MCDI_EXCEPTION_MC_REBOOT,
325 EFX_MCDI_EXCEPTION_MC_BADASSERT,
326 } efx_mcdi_exception_t;
328 #if EFSYS_OPT_MCDI_LOGGING
329 typedef enum efx_log_msg_e {
331 EFX_LOG_MCDI_REQUEST,
332 EFX_LOG_MCDI_RESPONSE,
334 #endif /* EFSYS_OPT_MCDI_LOGGING */
336 typedef struct efx_mcdi_transport_s {
338 efsys_mem_t *emt_dma_mem;
339 void (*emt_execute)(void *, efx_mcdi_req_t *);
340 void (*emt_ev_cpl)(void *);
341 void (*emt_exception)(void *, efx_mcdi_exception_t);
342 #if EFSYS_OPT_MCDI_LOGGING
343 void (*emt_logger)(void *, efx_log_msg_t,
344 void *, size_t, void *, size_t);
345 #endif /* EFSYS_OPT_MCDI_LOGGING */
346 #if EFSYS_OPT_MCDI_PROXY_AUTH
347 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
348 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
349 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
350 void (*emt_ev_proxy_request)(void *, uint32_t);
351 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
352 } efx_mcdi_transport_t;
355 extern __checkReturn efx_rc_t
358 __in const efx_mcdi_transport_t *mtp);
361 extern __checkReturn efx_rc_t
363 __in efx_nic_t *enp);
368 __in efx_nic_t *enp);
372 efx_mcdi_get_timeout(
374 __in efx_mcdi_req_t *emrp,
375 __out uint32_t *usec_timeoutp);
379 efx_mcdi_request_start(
381 __in efx_mcdi_req_t *emrp,
382 __in boolean_t ev_cpl);
385 extern __checkReturn boolean_t
386 efx_mcdi_request_poll(
387 __in efx_nic_t *enp);
390 extern __checkReturn boolean_t
391 efx_mcdi_request_abort(
392 __in efx_nic_t *enp);
395 extern __checkReturn efx_rc_t
396 efx_mcdi_get_client_handle(
398 __in efx_pcie_interface_t intf,
401 __out uint32_t *handle);
404 extern __checkReturn efx_rc_t
405 efx_mcdi_get_own_client_handle(
407 __out uint32_t *handle);
412 __in efx_nic_t *enp);
414 #endif /* EFSYS_OPT_MCDI */
418 #define EFX_NINTR_SIENA 1024
420 typedef enum efx_intr_type_e {
421 EFX_INTR_INVALID = 0,
427 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
430 extern __checkReturn efx_rc_t
433 __in efx_intr_type_t type,
434 __in_opt efsys_mem_t *esmp);
439 __in efx_nic_t *enp);
444 __in efx_nic_t *enp);
448 efx_intr_disable_unlocked(
449 __in efx_nic_t *enp);
451 #define EFX_INTR_NEVQS 32
454 extern __checkReturn efx_rc_t
457 __in unsigned int level);
461 efx_intr_status_line(
463 __out boolean_t *fatalp,
464 __out uint32_t *maskp);
468 efx_intr_status_message(
470 __in unsigned int message,
471 __out boolean_t *fatalp);
476 __in efx_nic_t *enp);
481 __in efx_nic_t *enp);
485 #if EFSYS_OPT_MAC_STATS
487 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
488 typedef enum efx_mac_stat_e {
491 EFX_MAC_RX_UNICST_PKTS,
492 EFX_MAC_RX_MULTICST_PKTS,
493 EFX_MAC_RX_BRDCST_PKTS,
494 EFX_MAC_RX_PAUSE_PKTS,
495 EFX_MAC_RX_LE_64_PKTS,
496 EFX_MAC_RX_65_TO_127_PKTS,
497 EFX_MAC_RX_128_TO_255_PKTS,
498 EFX_MAC_RX_256_TO_511_PKTS,
499 EFX_MAC_RX_512_TO_1023_PKTS,
500 EFX_MAC_RX_1024_TO_15XX_PKTS,
501 EFX_MAC_RX_GE_15XX_PKTS,
503 EFX_MAC_RX_FCS_ERRORS,
504 EFX_MAC_RX_DROP_EVENTS,
505 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
506 EFX_MAC_RX_SYMBOL_ERRORS,
507 EFX_MAC_RX_ALIGN_ERRORS,
508 EFX_MAC_RX_INTERNAL_ERRORS,
509 EFX_MAC_RX_JABBER_PKTS,
510 EFX_MAC_RX_LANE0_CHAR_ERR,
511 EFX_MAC_RX_LANE1_CHAR_ERR,
512 EFX_MAC_RX_LANE2_CHAR_ERR,
513 EFX_MAC_RX_LANE3_CHAR_ERR,
514 EFX_MAC_RX_LANE0_DISP_ERR,
515 EFX_MAC_RX_LANE1_DISP_ERR,
516 EFX_MAC_RX_LANE2_DISP_ERR,
517 EFX_MAC_RX_LANE3_DISP_ERR,
518 EFX_MAC_RX_MATCH_FAULT,
519 EFX_MAC_RX_NODESC_DROP_CNT,
522 EFX_MAC_TX_UNICST_PKTS,
523 EFX_MAC_TX_MULTICST_PKTS,
524 EFX_MAC_TX_BRDCST_PKTS,
525 EFX_MAC_TX_PAUSE_PKTS,
526 EFX_MAC_TX_LE_64_PKTS,
527 EFX_MAC_TX_65_TO_127_PKTS,
528 EFX_MAC_TX_128_TO_255_PKTS,
529 EFX_MAC_TX_256_TO_511_PKTS,
530 EFX_MAC_TX_512_TO_1023_PKTS,
531 EFX_MAC_TX_1024_TO_15XX_PKTS,
532 EFX_MAC_TX_GE_15XX_PKTS,
534 EFX_MAC_TX_SGL_COL_PKTS,
535 EFX_MAC_TX_MULT_COL_PKTS,
536 EFX_MAC_TX_EX_COL_PKTS,
537 EFX_MAC_TX_LATE_COL_PKTS,
539 EFX_MAC_TX_EX_DEF_PKTS,
540 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
541 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
542 EFX_MAC_PM_TRUNC_VFIFO_FULL,
543 EFX_MAC_PM_DISCARD_VFIFO_FULL,
544 EFX_MAC_PM_TRUNC_QBB,
545 EFX_MAC_PM_DISCARD_QBB,
546 EFX_MAC_PM_DISCARD_MAPPING,
547 EFX_MAC_RXDP_Q_DISABLED_PKTS,
548 EFX_MAC_RXDP_DI_DROPPED_PKTS,
549 EFX_MAC_RXDP_STREAMING_PKTS,
550 EFX_MAC_RXDP_HLB_FETCH,
551 EFX_MAC_RXDP_HLB_WAIT,
552 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
553 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
554 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
555 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
556 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
557 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
558 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
559 EFX_MAC_VADAPTER_RX_BAD_BYTES,
560 EFX_MAC_VADAPTER_RX_OVERFLOW,
561 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
562 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
563 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
564 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
565 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
566 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
567 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
568 EFX_MAC_VADAPTER_TX_BAD_BYTES,
569 EFX_MAC_VADAPTER_TX_OVERFLOW,
570 EFX_MAC_FEC_UNCORRECTED_ERRORS,
571 EFX_MAC_FEC_CORRECTED_ERRORS,
572 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
573 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
574 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
575 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
576 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
577 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
578 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
579 EFX_MAC_CTPIO_OVERFLOW_FAIL,
580 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
581 EFX_MAC_CTPIO_TIMEOUT_FAIL,
582 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
583 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
584 EFX_MAC_CTPIO_INVALID_WR_FAIL,
585 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
586 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
587 EFX_MAC_CTPIO_RUNT_FALLBACK,
588 EFX_MAC_CTPIO_SUCCESS,
589 EFX_MAC_CTPIO_FALLBACK,
590 EFX_MAC_CTPIO_POISON,
592 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
593 EFX_MAC_RXDP_HLB_IDLE,
594 EFX_MAC_RXDP_HLB_TIMEOUT,
598 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
600 #endif /* EFSYS_OPT_MAC_STATS */
602 typedef enum efx_link_mode_e {
603 EFX_LINK_UNKNOWN = 0,
619 #define EFX_MAC_ADDR_LEN 6
621 #define EFX_VNI_OR_VSID_LEN 3
623 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
625 #define EFX_MAC_MULTICAST_LIST_MAX 256
627 #define EFX_MAC_SDU_MAX 9202
629 #define EFX_MAC_PDU_ADJUSTMENT \
633 + /* bug16011 */ 16) \
635 #define EFX_MAC_PDU(_sdu) \
636 EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
639 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
640 * the SDU rounded up slightly.
642 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
644 #define EFX_MAC_PDU_MIN 60
645 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
648 extern __checkReturn efx_rc_t
654 extern __checkReturn efx_rc_t
660 extern __checkReturn efx_rc_t
666 extern __checkReturn efx_rc_t
669 __in boolean_t all_unicst,
670 __in boolean_t mulcst,
671 __in boolean_t all_mulcst,
672 __in boolean_t brdcst);
676 efx_mac_filter_get_all_ucast_mcast(
678 __out boolean_t *all_unicst,
679 __out boolean_t *all_mulcst);
682 extern __checkReturn efx_rc_t
683 efx_mac_multicast_list_set(
685 __in_ecount(6*count) uint8_t const *addrs,
689 extern __checkReturn efx_rc_t
690 efx_mac_filter_default_rxq_set(
693 __in boolean_t using_rss);
697 efx_mac_filter_default_rxq_clear(
698 __in efx_nic_t *enp);
701 extern __checkReturn efx_rc_t
704 __in boolean_t enabled);
707 extern __checkReturn efx_rc_t
710 __out boolean_t *mac_upp);
712 #define EFX_FCNTL_RESPOND 0x00000001
713 #define EFX_FCNTL_GENERATE 0x00000002
716 extern __checkReturn efx_rc_t
719 __in unsigned int fcntl,
720 __in boolean_t autoneg);
726 __out unsigned int *fcntl_wantedp,
727 __out unsigned int *fcntl_linkp);
730 #if EFSYS_OPT_MAC_STATS
735 extern __checkReturn const char *
738 __in unsigned int id);
740 #endif /* EFSYS_OPT_NAMES */
742 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
744 #define EFX_MAC_STATS_MASK_NPAGES \
745 (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \
746 EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
747 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
750 * Get mask of MAC statistics supported by the hardware.
752 * If mask_size is insufficient to return the mask, EINVAL error is
753 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
754 * (which is sizeof (uint32_t)) is sufficient.
757 extern __checkReturn efx_rc_t
758 efx_mac_stats_get_mask(
760 __out_bcount(mask_size) uint32_t *maskp,
761 __in size_t mask_size);
763 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
764 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
765 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
769 extern __checkReturn efx_rc_t
771 __in efx_nic_t *enp);
774 * Upload mac statistics supported by the hardware into the given buffer.
776 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
777 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
779 * The hardware will only DMA statistics that it understands (of course).
780 * Drivers should not make any assumptions about which statistics are
781 * supported, especially when the statistics are generated by firmware.
783 * Thus, drivers should zero this buffer before use, so that not-understood
784 * statistics read back as zero.
787 extern __checkReturn efx_rc_t
788 efx_mac_stats_upload(
790 __in efsys_mem_t *esmp);
793 extern __checkReturn efx_rc_t
794 efx_mac_stats_periodic(
796 __in efsys_mem_t *esmp,
797 __in uint16_t period_ms,
798 __in boolean_t events);
801 extern __checkReturn efx_rc_t
802 efx_mac_stats_update(
804 __in efsys_mem_t *esmp,
805 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
806 __inout_opt uint32_t *generationp);
808 #endif /* EFSYS_OPT_MAC_STATS */
812 typedef enum efx_mon_type_e {
825 __in efx_nic_t *enp);
827 #endif /* EFSYS_OPT_NAMES */
830 extern __checkReturn efx_rc_t
832 __in efx_nic_t *enp);
834 #if EFSYS_OPT_MON_STATS
836 #define EFX_MON_STATS_PAGE_SIZE 0x100
837 #define EFX_MON_MASK_ELEMENT_SIZE 32
839 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
840 typedef enum efx_mon_stat_e {
841 EFX_MON_STAT_CONTROLLER_TEMP,
842 EFX_MON_STAT_PHY_COMMON_TEMP,
843 EFX_MON_STAT_CONTROLLER_COOLING,
844 EFX_MON_STAT_PHY0_TEMP,
845 EFX_MON_STAT_PHY0_COOLING,
846 EFX_MON_STAT_PHY1_TEMP,
847 EFX_MON_STAT_PHY1_COOLING,
853 EFX_MON_STAT_IN_12V0,
854 EFX_MON_STAT_IN_1V2A,
855 EFX_MON_STAT_IN_VREF,
856 EFX_MON_STAT_OUT_VAOE,
857 EFX_MON_STAT_AOE_TEMP,
858 EFX_MON_STAT_PSU_AOE_TEMP,
859 EFX_MON_STAT_PSU_TEMP,
865 EFX_MON_STAT_IN_VAOE,
866 EFX_MON_STAT_OUT_IAOE,
867 EFX_MON_STAT_IN_IAOE,
868 EFX_MON_STAT_NIC_POWER,
870 EFX_MON_STAT_IN_I0V9,
871 EFX_MON_STAT_IN_I1V2,
872 EFX_MON_STAT_IN_0V9_ADC,
873 EFX_MON_STAT_CONTROLLER_2_TEMP,
874 EFX_MON_STAT_VREG_INTERNAL_TEMP,
875 EFX_MON_STAT_VREG_0V9_TEMP,
876 EFX_MON_STAT_VREG_1V2_TEMP,
877 EFX_MON_STAT_CONTROLLER_VPTAT,
878 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
879 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
880 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
881 EFX_MON_STAT_AMBIENT_TEMP,
882 EFX_MON_STAT_AIRFLOW,
883 EFX_MON_STAT_VDD08D_VSS08D_CSR,
884 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
885 EFX_MON_STAT_HOTPOINT_TEMP,
886 EFX_MON_STAT_PHY_POWER_PORT0,
887 EFX_MON_STAT_PHY_POWER_PORT1,
888 EFX_MON_STAT_MUM_VCC,
889 EFX_MON_STAT_IN_0V9_A,
890 EFX_MON_STAT_IN_I0V9_A,
891 EFX_MON_STAT_VREG_0V9_A_TEMP,
892 EFX_MON_STAT_IN_0V9_B,
893 EFX_MON_STAT_IN_I0V9_B,
894 EFX_MON_STAT_VREG_0V9_B_TEMP,
895 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
896 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
897 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
898 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
899 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
900 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
901 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
902 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
903 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
904 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
905 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
906 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
907 EFX_MON_STAT_SODIMM_VOUT,
908 EFX_MON_STAT_SODIMM_0_TEMP,
909 EFX_MON_STAT_SODIMM_1_TEMP,
910 EFX_MON_STAT_PHY0_VCC,
911 EFX_MON_STAT_PHY1_VCC,
912 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
913 EFX_MON_STAT_BOARD_FRONT_TEMP,
914 EFX_MON_STAT_BOARD_BACK_TEMP,
915 EFX_MON_STAT_IN_I1V8,
916 EFX_MON_STAT_IN_I2V5,
917 EFX_MON_STAT_IN_I3V3,
918 EFX_MON_STAT_IN_I12V0,
920 EFX_MON_STAT_IN_I1V3,
924 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
926 typedef enum efx_mon_stat_state_e {
927 EFX_MON_STAT_STATE_OK = 0,
928 EFX_MON_STAT_STATE_WARNING = 1,
929 EFX_MON_STAT_STATE_FATAL = 2,
930 EFX_MON_STAT_STATE_BROKEN = 3,
931 EFX_MON_STAT_STATE_NO_READING = 4,
932 } efx_mon_stat_state_t;
934 typedef enum efx_mon_stat_unit_e {
935 EFX_MON_STAT_UNIT_UNKNOWN = 0,
936 EFX_MON_STAT_UNIT_BOOL,
937 EFX_MON_STAT_UNIT_TEMP_C,
938 EFX_MON_STAT_UNIT_VOLTAGE_MV,
939 EFX_MON_STAT_UNIT_CURRENT_MA,
940 EFX_MON_STAT_UNIT_POWER_W,
941 EFX_MON_STAT_UNIT_RPM,
943 } efx_mon_stat_unit_t;
945 typedef struct efx_mon_stat_value_s {
947 efx_mon_stat_state_t emsv_state;
948 efx_mon_stat_unit_t emsv_unit;
949 } efx_mon_stat_value_t;
951 typedef struct efx_mon_limit_value_s {
952 uint16_t emlv_warning_min;
953 uint16_t emlv_warning_max;
954 uint16_t emlv_fatal_min;
955 uint16_t emlv_fatal_max;
956 } efx_mon_stat_limits_t;
958 typedef enum efx_mon_stat_portmask_e {
959 EFX_MON_STAT_PORTMAP_NONE = 0,
960 EFX_MON_STAT_PORTMAP_PORT0 = 1,
961 EFX_MON_STAT_PORTMAP_PORT1 = 2,
962 EFX_MON_STAT_PORTMAP_PORT2 = 3,
963 EFX_MON_STAT_PORTMAP_PORT3 = 4,
964 EFX_MON_STAT_PORTMAP_ALL = (-1),
965 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
966 } efx_mon_stat_portmask_t;
974 __in efx_mon_stat_t id);
978 efx_mon_stat_description(
980 __in efx_mon_stat_t id);
982 #endif /* EFSYS_OPT_NAMES */
985 extern __checkReturn boolean_t
986 efx_mon_mcdi_to_efx_stat(
988 __out efx_mon_stat_t *statp);
991 extern __checkReturn boolean_t
992 efx_mon_get_stat_unit(
993 __in efx_mon_stat_t stat,
994 __out efx_mon_stat_unit_t *unitp);
997 extern __checkReturn boolean_t
998 efx_mon_get_stat_portmap(
999 __in efx_mon_stat_t stat,
1000 __out efx_mon_stat_portmask_t *maskp);
1003 extern __checkReturn efx_rc_t
1004 efx_mon_stats_update(
1005 __in efx_nic_t *enp,
1006 __in efsys_mem_t *esmp,
1007 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
1010 extern __checkReturn efx_rc_t
1011 efx_mon_limits_update(
1012 __in efx_nic_t *enp,
1013 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values);
1015 #endif /* EFSYS_OPT_MON_STATS */
1020 __in efx_nic_t *enp);
1025 extern __checkReturn efx_rc_t
1027 __in efx_nic_t *enp);
1029 typedef enum efx_phy_led_mode_e {
1030 EFX_PHY_LED_DEFAULT = 0,
1035 } efx_phy_led_mode_t;
1037 #if EFSYS_OPT_PHY_LED_CONTROL
1040 extern __checkReturn efx_rc_t
1042 __in efx_nic_t *enp,
1043 __in efx_phy_led_mode_t mode);
1045 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1048 extern __checkReturn efx_rc_t
1050 __in efx_nic_t *enp);
1052 #if EFSYS_OPT_LOOPBACK
1054 typedef enum efx_loopback_type_e {
1055 EFX_LOOPBACK_OFF = 0,
1056 EFX_LOOPBACK_DATA = 1,
1057 EFX_LOOPBACK_GMAC = 2,
1058 EFX_LOOPBACK_XGMII = 3,
1059 EFX_LOOPBACK_XGXS = 4,
1060 EFX_LOOPBACK_XAUI = 5,
1061 EFX_LOOPBACK_GMII = 6,
1062 EFX_LOOPBACK_SGMII = 7,
1063 EFX_LOOPBACK_XGBR = 8,
1064 EFX_LOOPBACK_XFI = 9,
1065 EFX_LOOPBACK_XAUI_FAR = 10,
1066 EFX_LOOPBACK_GMII_FAR = 11,
1067 EFX_LOOPBACK_SGMII_FAR = 12,
1068 EFX_LOOPBACK_XFI_FAR = 13,
1069 EFX_LOOPBACK_GPHY = 14,
1070 EFX_LOOPBACK_PHY_XS = 15,
1071 EFX_LOOPBACK_PCS = 16,
1072 EFX_LOOPBACK_PMA_PMD = 17,
1073 EFX_LOOPBACK_XPORT = 18,
1074 EFX_LOOPBACK_XGMII_WS = 19,
1075 EFX_LOOPBACK_XAUI_WS = 20,
1076 EFX_LOOPBACK_XAUI_WS_FAR = 21,
1077 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
1078 EFX_LOOPBACK_GMII_WS = 23,
1079 EFX_LOOPBACK_XFI_WS = 24,
1080 EFX_LOOPBACK_XFI_WS_FAR = 25,
1081 EFX_LOOPBACK_PHYXS_WS = 26,
1082 EFX_LOOPBACK_PMA_INT = 27,
1083 EFX_LOOPBACK_SD_NEAR = 28,
1084 EFX_LOOPBACK_SD_FAR = 29,
1085 EFX_LOOPBACK_PMA_INT_WS = 30,
1086 EFX_LOOPBACK_SD_FEP2_WS = 31,
1087 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
1088 EFX_LOOPBACK_SD_FEP_WS = 33,
1089 EFX_LOOPBACK_SD_FES_WS = 34,
1090 EFX_LOOPBACK_AOE_INT_NEAR = 35,
1091 EFX_LOOPBACK_DATA_WS = 36,
1092 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
1094 } efx_loopback_type_t;
1096 typedef enum efx_loopback_kind_e {
1097 EFX_LOOPBACK_KIND_OFF = 0,
1098 EFX_LOOPBACK_KIND_ALL,
1099 EFX_LOOPBACK_KIND_MAC,
1100 EFX_LOOPBACK_KIND_PHY,
1102 } efx_loopback_kind_t;
1107 __in efx_loopback_kind_t loopback_kind,
1108 __out efx_qword_t *maskp);
1111 extern __checkReturn efx_rc_t
1112 efx_port_loopback_set(
1113 __in efx_nic_t *enp,
1114 __in efx_link_mode_t link_mode,
1115 __in efx_loopback_type_t type);
1120 extern __checkReturn const char *
1121 efx_loopback_type_name(
1122 __in efx_nic_t *enp,
1123 __in efx_loopback_type_t type);
1125 #endif /* EFSYS_OPT_NAMES */
1127 #endif /* EFSYS_OPT_LOOPBACK */
1130 extern __checkReturn efx_rc_t
1132 __in efx_nic_t *enp,
1133 __out_opt efx_link_mode_t *link_modep);
1138 __in efx_nic_t *enp);
1140 typedef enum efx_phy_cap_type_e {
1141 EFX_PHY_CAP_INVALID = 0,
1146 EFX_PHY_CAP_1000HDX,
1147 EFX_PHY_CAP_1000FDX,
1148 EFX_PHY_CAP_10000FDX,
1152 EFX_PHY_CAP_40000FDX,
1154 EFX_PHY_CAP_100000FDX,
1155 EFX_PHY_CAP_25000FDX,
1156 EFX_PHY_CAP_50000FDX,
1157 EFX_PHY_CAP_BASER_FEC,
1158 EFX_PHY_CAP_BASER_FEC_REQUESTED,
1160 EFX_PHY_CAP_RS_FEC_REQUESTED,
1161 EFX_PHY_CAP_25G_BASER_FEC,
1162 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
1164 } efx_phy_cap_type_t;
1167 #define EFX_PHY_CAP_CURRENT 0x00000000
1168 #define EFX_PHY_CAP_DEFAULT 0x00000001
1169 #define EFX_PHY_CAP_PERM 0x00000002
1173 efx_phy_adv_cap_get(
1174 __in efx_nic_t *enp,
1176 __out uint32_t *maskp);
1179 extern __checkReturn efx_rc_t
1180 efx_phy_adv_cap_set(
1181 __in efx_nic_t *enp,
1182 __in uint32_t mask);
1187 __in efx_nic_t *enp,
1188 __out uint32_t *maskp);
1191 extern __checkReturn efx_rc_t
1193 __in efx_nic_t *enp,
1194 __out uint32_t *ouip);
1196 typedef enum efx_phy_media_type_e {
1197 EFX_PHY_MEDIA_INVALID = 0,
1202 EFX_PHY_MEDIA_SFP_PLUS,
1203 EFX_PHY_MEDIA_BASE_T,
1204 EFX_PHY_MEDIA_QSFP_PLUS,
1205 EFX_PHY_MEDIA_NTYPES
1206 } efx_phy_media_type_t;
1209 * Get the type of medium currently used. If the board has ports for
1210 * modules, a module is present, and we recognise the media type of
1211 * the module, then this will be the media type of the module.
1212 * Otherwise it will be the media type of the port.
1216 efx_phy_media_type_get(
1217 __in efx_nic_t *enp,
1218 __out efx_phy_media_type_t *typep);
1221 * 2-wire device address of the base information in accordance with SFF-8472
1222 * Diagnostic Monitoring Interface for Optical Transceivers section
1223 * 4 Memory Organization.
1225 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0
1228 * 2-wire device address of the digital diagnostics monitoring interface
1229 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical
1230 * Transceivers section 4 Memory Organization.
1232 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2
1235 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436
1236 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and
1239 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0
1242 * Maximum accessible data offset for PHY module information.
1244 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100
1248 extern __checkReturn efx_rc_t
1249 efx_phy_module_get_info(
1250 __in efx_nic_t *enp,
1251 __in uint8_t dev_addr,
1254 __out_bcount(len) uint8_t *data);
1256 #if EFSYS_OPT_PHY_STATS
1258 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1259 typedef enum efx_phy_stat_e {
1261 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1262 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1263 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1264 EFX_PHY_STAT_PMA_PMD_REV_A,
1265 EFX_PHY_STAT_PMA_PMD_REV_B,
1266 EFX_PHY_STAT_PMA_PMD_REV_C,
1267 EFX_PHY_STAT_PMA_PMD_REV_D,
1268 EFX_PHY_STAT_PCS_LINK_UP,
1269 EFX_PHY_STAT_PCS_RX_FAULT,
1270 EFX_PHY_STAT_PCS_TX_FAULT,
1271 EFX_PHY_STAT_PCS_BER,
1272 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1273 EFX_PHY_STAT_PHY_XS_LINK_UP,
1274 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1275 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1276 EFX_PHY_STAT_PHY_XS_ALIGN,
1277 EFX_PHY_STAT_PHY_XS_SYNC_A,
1278 EFX_PHY_STAT_PHY_XS_SYNC_B,
1279 EFX_PHY_STAT_PHY_XS_SYNC_C,
1280 EFX_PHY_STAT_PHY_XS_SYNC_D,
1281 EFX_PHY_STAT_AN_LINK_UP,
1282 EFX_PHY_STAT_AN_MASTER,
1283 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1284 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1285 EFX_PHY_STAT_CL22EXT_LINK_UP,
1290 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1291 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1292 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1293 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1294 EFX_PHY_STAT_AN_COMPLETE,
1295 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1296 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1297 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1298 EFX_PHY_STAT_PCS_FW_VERSION_0,
1299 EFX_PHY_STAT_PCS_FW_VERSION_1,
1300 EFX_PHY_STAT_PCS_FW_VERSION_2,
1301 EFX_PHY_STAT_PCS_FW_VERSION_3,
1302 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1303 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1304 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1305 EFX_PHY_STAT_PCS_OP_MODE,
1309 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1316 __in efx_nic_t *enp,
1317 __in efx_phy_stat_t stat);
1319 #endif /* EFSYS_OPT_NAMES */
1321 #define EFX_PHY_STATS_SIZE 0x100
1324 extern __checkReturn efx_rc_t
1325 efx_phy_stats_update(
1326 __in efx_nic_t *enp,
1327 __in efsys_mem_t *esmp,
1328 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1330 #endif /* EFSYS_OPT_PHY_STATS */
1335 typedef enum efx_bist_type_e {
1336 EFX_BIST_TYPE_UNKNOWN,
1337 EFX_BIST_TYPE_PHY_NORMAL,
1338 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1339 EFX_BIST_TYPE_PHY_CABLE_LONG,
1340 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1341 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1342 EFX_BIST_TYPE_REG, /* Test the register memories */
1343 EFX_BIST_TYPE_NTYPES,
1346 typedef enum efx_bist_result_e {
1347 EFX_BIST_RESULT_UNKNOWN,
1348 EFX_BIST_RESULT_RUNNING,
1349 EFX_BIST_RESULT_PASSED,
1350 EFX_BIST_RESULT_FAILED,
1351 } efx_bist_result_t;
1353 typedef enum efx_phy_cable_status_e {
1354 EFX_PHY_CABLE_STATUS_OK,
1355 EFX_PHY_CABLE_STATUS_INVALID,
1356 EFX_PHY_CABLE_STATUS_OPEN,
1357 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1358 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1359 EFX_PHY_CABLE_STATUS_BUSY,
1360 } efx_phy_cable_status_t;
1362 typedef enum efx_bist_value_e {
1363 EFX_BIST_PHY_CABLE_LENGTH_A,
1364 EFX_BIST_PHY_CABLE_LENGTH_B,
1365 EFX_BIST_PHY_CABLE_LENGTH_C,
1366 EFX_BIST_PHY_CABLE_LENGTH_D,
1367 EFX_BIST_PHY_CABLE_STATUS_A,
1368 EFX_BIST_PHY_CABLE_STATUS_B,
1369 EFX_BIST_PHY_CABLE_STATUS_C,
1370 EFX_BIST_PHY_CABLE_STATUS_D,
1371 EFX_BIST_FAULT_CODE,
1373 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1379 EFX_BIST_MEM_EXPECT,
1380 EFX_BIST_MEM_ACTUAL,
1382 EFX_BIST_MEM_ECC_PARITY,
1383 EFX_BIST_MEM_ECC_FATAL,
1388 extern __checkReturn efx_rc_t
1389 efx_bist_enable_offline(
1390 __in efx_nic_t *enp);
1393 extern __checkReturn efx_rc_t
1395 __in efx_nic_t *enp,
1396 __in efx_bist_type_t type);
1399 extern __checkReturn efx_rc_t
1401 __in efx_nic_t *enp,
1402 __in efx_bist_type_t type,
1403 __out efx_bist_result_t *resultp,
1404 __out_opt uint32_t *value_maskp,
1405 __out_ecount_opt(count) unsigned long *valuesp,
1411 __in efx_nic_t *enp,
1412 __in efx_bist_type_t type);
1414 #endif /* EFSYS_OPT_BIST */
1416 #define EFX_FEATURE_IPV6 0x00000001
1417 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1418 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1419 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1420 #define EFX_FEATURE_MCDI 0x00000020
1421 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1422 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1423 #define EFX_FEATURE_TURBO 0x00000100
1424 #define EFX_FEATURE_MCDI_DMA 0x00000200
1425 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1426 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1427 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1428 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1429 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1430 #define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000
1432 typedef enum efx_tunnel_protocol_e {
1433 EFX_TUNNEL_PROTOCOL_NONE = 0,
1434 EFX_TUNNEL_PROTOCOL_VXLAN,
1435 EFX_TUNNEL_PROTOCOL_GENEVE,
1436 EFX_TUNNEL_PROTOCOL_NVGRE,
1438 } efx_tunnel_protocol_t;
1440 typedef enum efx_vi_window_shift_e {
1441 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1442 EFX_VI_WINDOW_SHIFT_8K = 13,
1443 EFX_VI_WINDOW_SHIFT_16K = 14,
1444 EFX_VI_WINDOW_SHIFT_64K = 16,
1445 } efx_vi_window_shift_t;
1447 typedef enum efx_nic_dma_mapping_e {
1448 EFX_NIC_DMA_MAPPING_UNKNOWN = 0,
1449 EFX_NIC_DMA_MAPPING_FLAT,
1450 EFX_NIC_DMA_MAPPING_REGIONED,
1452 EFX_NIC_DMA_MAPPING_NTYPES
1453 } efx_nic_dma_mapping_t;
1455 typedef struct efx_nic_cfg_s {
1456 uint32_t enc_board_type;
1457 uint32_t enc_phy_type;
1459 char enc_phy_name[21];
1461 char enc_phy_revision[21];
1462 efx_mon_type_t enc_mon_type;
1463 #if EFSYS_OPT_MON_STATS
1464 uint32_t enc_mon_stat_dma_buf_size;
1465 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1467 unsigned int enc_features;
1468 efx_vi_window_shift_t enc_vi_window_shift;
1469 uint8_t enc_mac_addr[6];
1470 uint8_t enc_port; /* PHY port number */
1471 uint32_t enc_intr_vec_base;
1472 uint32_t enc_intr_limit;
1473 uint32_t enc_evq_limit;
1474 uint32_t enc_txq_limit;
1475 uint32_t enc_rxq_limit;
1476 uint32_t enc_evq_max_nevs;
1477 uint32_t enc_evq_min_nevs;
1478 uint32_t enc_rxq_max_ndescs;
1479 uint32_t enc_rxq_min_ndescs;
1480 uint32_t enc_txq_max_ndescs;
1481 uint32_t enc_txq_min_ndescs;
1482 uint32_t enc_buftbl_limit;
1483 uint32_t enc_piobuf_limit;
1484 uint32_t enc_piobuf_size;
1485 uint32_t enc_piobuf_min_alloc_size;
1486 uint32_t enc_evq_timer_quantum_ns;
1487 uint32_t enc_evq_timer_max_us;
1488 uint32_t enc_clk_mult;
1489 uint32_t enc_ev_ew_desc_size;
1490 uint32_t enc_ev_desc_size;
1491 uint32_t enc_rx_desc_size;
1492 uint32_t enc_tx_desc_size;
1493 /* Maximum Rx prefix size if many Rx prefixes are supported */
1494 uint32_t enc_rx_prefix_size;
1495 uint32_t enc_rx_buf_align_start;
1496 uint32_t enc_rx_buf_align_end;
1497 #if EFSYS_OPT_RX_SCALE
1498 uint32_t enc_rx_scale_max_exclusive_contexts;
1500 * Mask of supported hash algorithms.
1501 * Hash algorithm types are used as the bit indices.
1503 uint32_t enc_rx_scale_hash_alg_mask;
1505 * Indicates whether port numbers can be included to the
1506 * input data for hash computation.
1508 boolean_t enc_rx_scale_l4_hash_supported;
1509 boolean_t enc_rx_scale_additional_modes_supported;
1510 #endif /* EFSYS_OPT_RX_SCALE */
1511 #if EFSYS_OPT_LOOPBACK
1512 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1513 #endif /* EFSYS_OPT_LOOPBACK */
1514 #if EFSYS_OPT_PHY_FLAGS
1515 uint32_t enc_phy_flags_mask;
1516 #endif /* EFSYS_OPT_PHY_FLAGS */
1517 #if EFSYS_OPT_PHY_LED_CONTROL
1518 uint32_t enc_led_mask;
1519 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1520 #if EFSYS_OPT_PHY_STATS
1521 uint64_t enc_phy_stat_mask;
1522 #endif /* EFSYS_OPT_PHY_STATS */
1524 uint8_t enc_mcdi_mdio_channel;
1525 #if EFSYS_OPT_PHY_STATS
1526 uint32_t enc_mcdi_phy_stat_mask;
1527 #endif /* EFSYS_OPT_PHY_STATS */
1528 #if EFSYS_OPT_MON_STATS
1529 uint32_t *enc_mcdi_sensor_maskp;
1530 uint32_t enc_mcdi_sensor_mask_size;
1531 #endif /* EFSYS_OPT_MON_STATS */
1532 #endif /* EFSYS_OPT_MCDI */
1534 uint32_t enc_bist_mask;
1535 #endif /* EFSYS_OPT_BIST */
1536 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
1537 efx_pcie_interface_t enc_intf;
1540 uint32_t enc_privilege_mask;
1541 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
1542 boolean_t enc_evq_init_done_ev_supported;
1543 boolean_t enc_bug26807_workaround;
1544 boolean_t enc_bug35388_workaround;
1545 boolean_t enc_bug41750_workaround;
1546 boolean_t enc_bug61265_workaround;
1547 boolean_t enc_bug61297_workaround;
1548 boolean_t enc_rx_batching_enabled;
1549 /* Maximum number of descriptors completed in an rx event. */
1550 uint32_t enc_rx_batch_max;
1551 /* Number of rx descriptors the hardware requires for a push. */
1552 uint32_t enc_rx_push_align;
1553 /* Maximum amount of data in DMA descriptor */
1554 uint32_t enc_tx_dma_desc_size_max;
1556 * Boundary which DMA descriptor data must not cross or 0 if no
1559 uint32_t enc_tx_dma_desc_boundary;
1561 * Maximum number of bytes into the packet the TCP header can start for
1562 * the hardware to apply TSO packet edits.
1564 uint32_t enc_tx_tso_tcp_header_offset_limit;
1565 /* Maximum number of header DMA descriptors per TSO transaction. */
1566 uint32_t enc_tx_tso_max_header_ndescs;
1567 /* Maximum header length acceptable by TSO transaction. */
1568 uint32_t enc_tx_tso_max_header_length;
1569 /* Maximum number of payload DMA descriptors per TSO transaction. */
1570 uint32_t enc_tx_tso_max_payload_ndescs;
1571 /* Maximum payload length per TSO transaction. */
1572 uint32_t enc_tx_tso_max_payload_length;
1573 /* Maximum number of frames to be generated per TSO transaction. */
1574 uint32_t enc_tx_tso_max_nframes;
1575 boolean_t enc_fw_assisted_tso_enabled;
1576 boolean_t enc_fw_assisted_tso_v2_enabled;
1577 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1578 boolean_t enc_tso_v3_enabled;
1579 /* Number of TSO contexts on the NIC (FATSOv2) */
1580 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1581 boolean_t enc_hw_tx_insert_vlan_enabled;
1582 /* Number of PFs on the NIC */
1583 uint32_t enc_hw_pf_count;
1584 /* Datapath firmware vadapter/vport/vswitch support */
1585 boolean_t enc_datapath_cap_evb;
1586 /* Datapath firmware vport reconfigure support */
1587 boolean_t enc_vport_reconfigure_supported;
1588 boolean_t enc_rx_disable_scatter_supported;
1589 /* Maximum number of Rx scatter segments supported by HW */
1590 uint32_t enc_rx_scatter_max;
1591 boolean_t enc_allow_set_mac_with_installed_filters;
1592 boolean_t enc_enhanced_set_mac_supported;
1593 boolean_t enc_init_evq_v2_supported;
1594 boolean_t enc_init_evq_extended_width_supported;
1595 boolean_t enc_no_cont_ev_mode_supported;
1596 boolean_t enc_init_rxq_with_buffer_size;
1597 boolean_t enc_rx_packed_stream_supported;
1598 boolean_t enc_rx_var_packed_stream_supported;
1599 boolean_t enc_rx_es_super_buffer_supported;
1600 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1601 boolean_t enc_pm_and_rxdp_counters;
1602 boolean_t enc_mac_stats_40g_tx_size_bins;
1603 uint32_t enc_tunnel_encapsulations_supported;
1605 * NIC global maximum for unique UDP tunnel ports shared by all
1608 uint32_t enc_tunnel_config_udp_entries_max;
1609 /* External port identifier */
1610 uint8_t enc_external_port;
1611 uint32_t enc_mcdi_max_payload_length;
1612 /* VPD may be per-PF or global */
1613 boolean_t enc_vpd_is_global;
1614 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1615 uint32_t enc_required_pcie_bandwidth_mbps;
1616 uint32_t enc_max_pcie_link_gen;
1617 /* Firmware verifies integrity of NVRAM updates */
1618 boolean_t enc_nvram_update_verify_result_supported;
1619 /* Firmware supports polled NVRAM updates on select partitions */
1620 boolean_t enc_nvram_update_poll_verify_result_supported;
1621 /* Firmware accepts updates via the BUNDLE partition */
1622 boolean_t enc_nvram_bundle_update_supported;
1623 /* Firmware support for extended MAC_STATS buffer */
1624 uint32_t enc_mac_stats_nstats;
1625 boolean_t enc_fec_counters;
1626 boolean_t enc_hlb_counters;
1627 /* NIC support for Match-Action Engine (MAE). */
1628 boolean_t enc_mae_supported;
1630 * NIC is privileged, i.e. it is the MAE admin.
1631 * Only privileged MAE clients can manage MAE flow rules,
1632 * for example, modify, count and route traffic to selected
1633 * destination (a MAE client or network port).
1635 boolean_t enc_mae_admin;
1636 /* NIC support for MAE action set v2 features. */
1637 boolean_t enc_mae_aset_v2_supported;
1638 /* Firmware support for "FLAG" and "MARK" filter actions */
1639 boolean_t enc_filter_action_flag_supported;
1640 boolean_t enc_filter_action_mark_supported;
1641 uint32_t enc_filter_action_mark_max;
1642 /* Port assigned to this PCI function */
1643 uint32_t enc_assigned_port;
1644 /* NIC DMA mapping type */
1645 efx_nic_dma_mapping_t enc_dma_mapping;
1648 #define EFX_PCI_VF_INVALID 0xffff
1650 #define EFX_VPORT_PCI_FUNCTION_IS_PF(configp) \
1651 ((configp)->evc_function == EFX_PCI_VF_INVALID)
1653 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == EFX_PCI_VF_INVALID)
1654 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != EFX_PCI_VF_INVALID)
1656 #define EFX_PCI_FUNCTION(_encp) \
1657 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1659 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1662 extern const efx_nic_cfg_t *
1664 __in const efx_nic_t *enp);
1666 /* RxDPCPU firmware id values by which FW variant can be identified */
1667 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1668 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1669 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1670 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1671 #define EFX_RXDP_DPDK_FW_ID 0x6
1673 typedef struct efx_nic_fw_info_s {
1674 /* Basic FW version information */
1675 uint16_t enfi_mc_fw_version[4];
1677 * If datapath capabilities can be detected,
1678 * additional FW information is to be shown
1680 boolean_t enfi_dpcpu_fw_ids_valid;
1681 /* Rx and Tx datapath CPU FW IDs */
1682 uint16_t enfi_rx_dpcpu_fw_id;
1683 uint16_t enfi_tx_dpcpu_fw_id;
1684 } efx_nic_fw_info_t;
1687 extern __checkReturn efx_rc_t
1688 efx_nic_get_fw_version(
1689 __in efx_nic_t *enp,
1690 __out efx_nic_fw_info_t *enfip);
1692 #define EFX_NIC_BOARD_INFO_SERIAL_LEN (64)
1693 #define EFX_NIC_BOARD_INFO_NAME_LEN (16)
1695 typedef struct efx_nic_board_info_s {
1696 /* The following two fields are NUL-terminated ASCII strings. */
1697 char enbi_serial[EFX_NIC_BOARD_INFO_SERIAL_LEN];
1698 char enbi_name[EFX_NIC_BOARD_INFO_NAME_LEN];
1699 uint32_t enbi_revision;
1700 } efx_nic_board_info_t;
1703 extern __checkReturn efx_rc_t
1704 efx_nic_get_board_info(
1705 __in efx_nic_t *enp,
1706 __out efx_nic_board_info_t *board_infop);
1708 /* Driver resource limits (minimum required/maximum usable). */
1709 typedef struct efx_drv_limits_s {
1710 uint32_t edl_min_evq_count;
1711 uint32_t edl_max_evq_count;
1713 uint32_t edl_min_rxq_count;
1714 uint32_t edl_max_rxq_count;
1716 uint32_t edl_min_txq_count;
1717 uint32_t edl_max_txq_count;
1719 /* PIO blocks (sub-allocated from piobuf) */
1720 uint32_t edl_min_pio_alloc_size;
1721 uint32_t edl_max_pio_alloc_count;
1725 extern __checkReturn efx_rc_t
1726 efx_nic_set_drv_limits(
1727 __inout efx_nic_t *enp,
1728 __in efx_drv_limits_t *edlp);
1731 * Register the OS driver version string for management agents
1732 * (e.g. via NC-SI). The content length is provided (i.e. no
1733 * NUL terminator). Use length 0 to indicate no version string
1734 * should be advertised. It is valid to set the version string
1735 * only before efx_nic_probe() is called.
1738 extern __checkReturn efx_rc_t
1739 efx_nic_set_drv_version(
1740 __inout efx_nic_t *enp,
1741 __in_ecount(length) char const *verp,
1742 __in size_t length);
1744 typedef enum efx_nic_region_e {
1745 EFX_REGION_VI, /* Memory BAR UC mapping */
1746 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1750 extern __checkReturn efx_rc_t
1751 efx_nic_get_bar_region(
1752 __in efx_nic_t *enp,
1753 __in efx_nic_region_t region,
1754 __out uint32_t *offsetp,
1755 __out size_t *sizep);
1758 extern __checkReturn efx_rc_t
1759 efx_nic_get_vi_pool(
1760 __in efx_nic_t *enp,
1761 __out uint32_t *evq_countp,
1762 __out uint32_t *rxq_countp,
1763 __out uint32_t *txq_countp);
1768 typedef enum efx_vpd_tag_e {
1775 typedef uint16_t efx_vpd_keyword_t;
1777 typedef struct efx_vpd_value_s {
1778 efx_vpd_tag_t evv_tag;
1779 efx_vpd_keyword_t evv_keyword;
1781 uint8_t evv_value[0x100];
1785 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1788 extern __checkReturn efx_rc_t
1790 __in efx_nic_t *enp);
1793 extern __checkReturn efx_rc_t
1795 __in efx_nic_t *enp,
1796 __out size_t *sizep);
1799 extern __checkReturn efx_rc_t
1801 __in efx_nic_t *enp,
1802 __out_bcount(size) caddr_t data,
1806 extern __checkReturn efx_rc_t
1808 __in efx_nic_t *enp,
1809 __in_bcount(size) caddr_t data,
1813 extern __checkReturn efx_rc_t
1815 __in efx_nic_t *enp,
1816 __in_bcount(size) caddr_t data,
1820 extern __checkReturn efx_rc_t
1822 __in efx_nic_t *enp,
1823 __in_bcount(size) caddr_t data,
1825 __inout efx_vpd_value_t *evvp);
1828 extern __checkReturn efx_rc_t
1830 __in efx_nic_t *enp,
1831 __inout_bcount(size) caddr_t data,
1833 __in efx_vpd_value_t *evvp);
1836 extern __checkReturn efx_rc_t
1838 __in efx_nic_t *enp,
1839 __inout_bcount(size) caddr_t data,
1841 __out efx_vpd_value_t *evvp,
1842 __inout unsigned int *contp);
1845 extern __checkReturn efx_rc_t
1847 __in efx_nic_t *enp,
1848 __in_bcount(size) caddr_t data,
1854 __in efx_nic_t *enp);
1856 #endif /* EFSYS_OPT_VPD */
1862 typedef enum efx_nvram_type_e {
1863 EFX_NVRAM_INVALID = 0,
1865 EFX_NVRAM_BOOTROM_CFG,
1866 EFX_NVRAM_MC_FIRMWARE,
1867 EFX_NVRAM_MC_GOLDEN,
1873 EFX_NVRAM_FPGA_BACKUP,
1874 EFX_NVRAM_DYNAMIC_CFG,
1877 EFX_NVRAM_MUM_FIRMWARE,
1878 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1879 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1881 EFX_NVRAM_BUNDLE_METADATA,
1885 typedef struct efx_nvram_info_s {
1887 uint32_t eni_partn_size;
1888 uint32_t eni_address;
1889 uint32_t eni_erase_size;
1890 uint32_t eni_write_size;
1893 #define EFX_NVRAM_FLAG_READ_ONLY (1 << 0)
1896 extern __checkReturn efx_rc_t
1898 __in efx_nic_t *enp);
1903 extern __checkReturn efx_rc_t
1905 __in efx_nic_t *enp);
1907 #endif /* EFSYS_OPT_DIAG */
1910 extern __checkReturn efx_rc_t
1912 __in efx_nic_t *enp,
1913 __in efx_nvram_type_t type,
1914 __out size_t *sizep);
1917 extern __checkReturn efx_rc_t
1919 __in efx_nic_t *enp,
1920 __in efx_nvram_type_t type,
1921 __out efx_nvram_info_t *enip);
1924 extern __checkReturn efx_rc_t
1926 __in efx_nic_t *enp,
1927 __in efx_nvram_type_t type,
1928 __out_opt size_t *pref_chunkp);
1931 extern __checkReturn efx_rc_t
1932 efx_nvram_rw_finish(
1933 __in efx_nic_t *enp,
1934 __in efx_nvram_type_t type,
1935 __out_opt uint32_t *verify_resultp);
1938 extern __checkReturn efx_rc_t
1939 efx_nvram_get_version(
1940 __in efx_nic_t *enp,
1941 __in efx_nvram_type_t type,
1942 __out uint32_t *subtypep,
1943 __out_ecount(4) uint16_t version[4]);
1946 extern __checkReturn efx_rc_t
1947 efx_nvram_read_chunk(
1948 __in efx_nic_t *enp,
1949 __in efx_nvram_type_t type,
1950 __in unsigned int offset,
1951 __out_bcount(size) caddr_t data,
1955 extern __checkReturn efx_rc_t
1956 efx_nvram_read_backup(
1957 __in efx_nic_t *enp,
1958 __in efx_nvram_type_t type,
1959 __in unsigned int offset,
1960 __out_bcount(size) caddr_t data,
1964 extern __checkReturn efx_rc_t
1965 efx_nvram_set_version(
1966 __in efx_nic_t *enp,
1967 __in efx_nvram_type_t type,
1968 __in_ecount(4) uint16_t version[4]);
1971 extern __checkReturn efx_rc_t
1973 __in efx_nic_t *enp,
1974 __in efx_nvram_type_t type,
1975 __in_bcount(partn_size) caddr_t partn_data,
1976 __in size_t partn_size);
1979 extern __checkReturn efx_rc_t
1981 __in efx_nic_t *enp,
1982 __in efx_nvram_type_t type);
1985 extern __checkReturn efx_rc_t
1986 efx_nvram_write_chunk(
1987 __in efx_nic_t *enp,
1988 __in efx_nvram_type_t type,
1989 __in unsigned int offset,
1990 __in_bcount(size) caddr_t data,
1996 __in efx_nic_t *enp);
1998 #endif /* EFSYS_OPT_NVRAM */
2000 #if EFSYS_OPT_BOOTCFG
2002 /* Report size and offset of bootcfg sector in NVRAM partition. */
2004 extern __checkReturn efx_rc_t
2005 efx_bootcfg_sector_info(
2006 __in efx_nic_t *enp,
2008 __out_opt uint32_t *sector_countp,
2009 __out size_t *offsetp,
2010 __out size_t *max_sizep);
2013 * Copy bootcfg sector data to a target buffer which may differ in size.
2014 * Optionally corrects format errors in source buffer.
2018 efx_bootcfg_copy_sector(
2019 __in efx_nic_t *enp,
2020 __inout_bcount(sector_length)
2022 __in size_t sector_length,
2023 __out_bcount(data_size) uint8_t *data,
2024 __in size_t data_size,
2025 __in boolean_t handle_format_errors);
2030 __in efx_nic_t *enp,
2031 __out_bcount(size) uint8_t *data,
2037 __in efx_nic_t *enp,
2038 __in_bcount(size) uint8_t *data,
2043 * Processing routines for buffers arranged in the DHCP/BOOTP option format
2044 * (see https://tools.ietf.org/html/rfc1533)
2046 * Summarising the format: the buffer is a sequence of options. All options
2047 * begin with a tag octet, which uniquely identifies the option. Fixed-
2048 * length options without data consist of only a tag octet. Only options PAD
2049 * (0) and END (255) are fixed length. All other options are variable-length
2050 * with a length octet following the tag octet. The value of the length
2051 * octet does not include the two octets specifying the tag and length. The
2052 * length octet is followed by "length" octets of data.
2054 * Option data may be a sequence of sub-options in the same format. The data
2055 * content of the encapsulating option is one or more encapsulated sub-options,
2056 * with no terminating END tag is required.
2058 * To be valid, the top-level sequence of options should be terminated by an
2059 * END tag. The buffer should be padded with the PAD byte.
2061 * When stored to NVRAM, the DHCP option format buffer is preceded by a
2062 * checksum octet. The full buffer (including after the END tag) contributes
2063 * to the checksum, hence the need to fill the buffer to the end with PAD.
2066 #define EFX_DHCP_END ((uint8_t)0xff)
2067 #define EFX_DHCP_PAD ((uint8_t)0)
2069 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \
2070 (uint16_t)(((encapsulator) << 8) | (encapsulated))
2073 extern __checkReturn uint8_t
2075 __in_bcount(size) uint8_t const *data,
2079 extern __checkReturn efx_rc_t
2081 __in_bcount(size) uint8_t const *data,
2083 __out_opt size_t *usedp);
2086 extern __checkReturn efx_rc_t
2088 __in_bcount(buffer_length) uint8_t *bufferp,
2089 __in size_t buffer_length,
2091 __deref_out uint8_t **valuepp,
2092 __out size_t *value_lengthp);
2095 extern __checkReturn efx_rc_t
2097 __in_bcount(buffer_length) uint8_t *bufferp,
2098 __in size_t buffer_length,
2099 __deref_out uint8_t **endpp);
2103 extern __checkReturn efx_rc_t
2104 efx_dhcp_delete_tag(
2105 __inout_bcount(buffer_length) uint8_t *bufferp,
2106 __in size_t buffer_length,
2110 extern __checkReturn efx_rc_t
2112 __inout_bcount(buffer_length) uint8_t *bufferp,
2113 __in size_t buffer_length,
2115 __in_bcount_opt(value_length) uint8_t *valuep,
2116 __in size_t value_length);
2119 extern __checkReturn efx_rc_t
2120 efx_dhcp_update_tag(
2121 __inout_bcount(buffer_length) uint8_t *bufferp,
2122 __in size_t buffer_length,
2124 __in uint8_t *value_locationp,
2125 __in_bcount_opt(value_length) uint8_t *valuep,
2126 __in size_t value_length);
2129 #endif /* EFSYS_OPT_BOOTCFG */
2131 #if EFSYS_OPT_IMAGE_LAYOUT
2133 #include "ef10_signed_image_layout.h"
2136 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
2139 * The image header format is extensible. However, older drivers require an
2140 * exact match of image header version and header length when validating and
2141 * writing firmware images.
2143 * To avoid breaking backward compatibility, we use the upper bits of the
2144 * controller version fields to contain an extra version number used for
2145 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
2146 * version). See bug39254 and SF-102785-PS for details.
2148 typedef struct efx_image_header_s {
2150 uint32_t eih_version;
2152 uint32_t eih_subtype;
2153 uint32_t eih_code_size;
2156 uint32_t eih_controller_version_min;
2158 uint16_t eih_controller_version_min_short;
2159 uint8_t eih_extra_version_a;
2160 uint8_t eih_extra_version_b;
2164 uint32_t eih_controller_version_max;
2166 uint16_t eih_controller_version_max_short;
2167 uint8_t eih_extra_version_c;
2168 uint8_t eih_extra_version_d;
2171 uint16_t eih_code_version_a;
2172 uint16_t eih_code_version_b;
2173 uint16_t eih_code_version_c;
2174 uint16_t eih_code_version_d;
2175 } efx_image_header_t;
2177 #define EFX_IMAGE_HEADER_SIZE (40)
2178 #define EFX_IMAGE_HEADER_VERSION (4)
2179 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
2182 typedef struct efx_image_trailer_s {
2184 } efx_image_trailer_t;
2186 #define EFX_IMAGE_TRAILER_SIZE (4)
2188 typedef enum efx_image_format_e {
2189 EFX_IMAGE_FORMAT_NO_IMAGE,
2190 EFX_IMAGE_FORMAT_INVALID,
2191 EFX_IMAGE_FORMAT_UNSIGNED,
2192 EFX_IMAGE_FORMAT_SIGNED,
2193 EFX_IMAGE_FORMAT_SIGNED_PACKAGE
2194 } efx_image_format_t;
2196 typedef struct efx_image_info_s {
2197 efx_image_format_t eii_format;
2198 uint8_t * eii_imagep;
2199 size_t eii_image_size;
2200 efx_image_header_t * eii_headerp;
2204 extern __checkReturn efx_rc_t
2205 efx_check_reflash_image(
2207 __in uint32_t buffer_size,
2208 __out efx_image_info_t *infop);
2211 extern __checkReturn efx_rc_t
2212 efx_build_signed_image_write_buffer(
2213 __out_bcount(buffer_size)
2215 __in uint32_t buffer_size,
2216 __in efx_image_info_t *infop,
2217 __out efx_image_header_t **headerpp);
2219 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
2223 typedef enum efx_pattern_type_t {
2224 EFX_PATTERN_BYTE_INCREMENT = 0,
2225 EFX_PATTERN_ALL_THE_SAME,
2226 EFX_PATTERN_BIT_ALTERNATE,
2227 EFX_PATTERN_BYTE_ALTERNATE,
2228 EFX_PATTERN_BYTE_CHANGING,
2229 EFX_PATTERN_BIT_SWEEP,
2231 } efx_pattern_type_t;
2234 (*efx_sram_pattern_fn_t)(
2236 __in boolean_t negate,
2237 __out efx_qword_t *eqp);
2240 extern __checkReturn efx_rc_t
2242 __in efx_nic_t *enp,
2243 __in efx_pattern_type_t type);
2245 #endif /* EFSYS_OPT_DIAG */
2248 extern __checkReturn efx_rc_t
2249 efx_sram_buf_tbl_set(
2250 __in efx_nic_t *enp,
2252 __in efsys_mem_t *esmp,
2257 efx_sram_buf_tbl_clear(
2258 __in efx_nic_t *enp,
2262 #define EFX_BUF_TBL_SIZE 0x20000
2264 #define EFX_BUF_SIZE 4096
2268 typedef struct efx_evq_s efx_evq_t;
2270 #if EFSYS_OPT_QSTATS
2272 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 0a147ace40844969 */
2273 typedef enum efx_ev_qstat_e {
2279 EV_RX_PAUSE_FRM_ERR,
2280 EV_RX_BUF_OWNER_ID_ERR,
2281 EV_RX_IPV4_HDR_CHKSUM_ERR,
2282 EV_RX_TCP_UDP_CHKSUM_ERR,
2286 EV_RX_MCAST_HASH_MATCH,
2303 EV_DRIVER_SRM_UPD_DONE,
2304 EV_DRIVER_TX_DESCQ_FLS_DONE,
2305 EV_DRIVER_RX_DESCQ_FLS_DONE,
2306 EV_DRIVER_RX_DESCQ_FLS_FAILED,
2307 EV_DRIVER_RX_DSC_ERROR,
2308 EV_DRIVER_TX_DSC_ERROR,
2311 EV_RX_PARSE_INCOMPLETE,
2315 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
2317 #endif /* EFSYS_OPT_QSTATS */
2320 extern __checkReturn efx_rc_t
2322 __in efx_nic_t *enp);
2327 __in efx_nic_t *enp);
2330 extern __checkReturn size_t
2332 __in const efx_nic_t *enp,
2333 __in unsigned int ndescs,
2334 __in uint32_t flags);
2337 extern __checkReturn unsigned int
2339 __in const efx_nic_t *enp,
2340 __in unsigned int ndescs,
2341 __in uint32_t flags);
2343 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
2344 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
2345 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
2346 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
2348 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
2349 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
2350 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
2353 * Use the NO_CONT_EV RX event format, which allows the firmware to operate more
2354 * efficiently at high data rates. See SF-109306-TC 5.11 "Events for RXQs in
2357 * NO_CONT_EV requires EVQ_RX_MERGE and RXQ_FORCED_EV_MERGING to both be set,
2358 * which is the case when an event queue is set to THROUGHPUT mode.
2360 #define EFX_EVQ_FLAGS_NO_CONT_EV (0x10)
2362 /* Configure EVQ for extended width events (EF100 only) */
2363 #define EFX_EVQ_FLAGS_EXTENDED_WIDTH (0x20)
2367 extern __checkReturn efx_rc_t
2369 __in efx_nic_t *enp,
2370 __in unsigned int index,
2371 __in efsys_mem_t *esmp,
2375 __in uint32_t flags,
2376 __deref_out efx_evq_t **eepp);
2379 extern __checkReturn efx_rc_t
2381 __in efx_nic_t *enp,
2382 __in unsigned int index,
2383 __in efsys_mem_t *esmp,
2387 __in uint32_t flags,
2389 __deref_out efx_evq_t **eepp);
2394 __in efx_evq_t *eep,
2395 __in uint16_t data);
2397 typedef __checkReturn boolean_t
2398 (*efx_initialized_ev_t)(
2399 __in_opt void *arg);
2401 #define EFX_PKT_UNICAST 0x0004
2402 #define EFX_PKT_START 0x0008
2404 #define EFX_PKT_VLAN_TAGGED 0x0010
2405 #define EFX_CKSUM_TCPUDP 0x0020
2406 #define EFX_CKSUM_IPV4 0x0040
2407 #define EFX_PKT_CONT 0x0080
2409 #define EFX_CHECK_VLAN 0x0100
2410 #define EFX_PKT_TCP 0x0200
2411 #define EFX_PKT_UDP 0x0400
2412 #define EFX_PKT_IPV4 0x0800
2414 #define EFX_PKT_IPV6 0x1000
2415 #define EFX_PKT_PREFIX_LEN 0x2000
2416 #define EFX_ADDR_MISMATCH 0x4000
2417 #define EFX_DISCARD 0x8000
2420 * The following flags are used only for packed stream
2421 * mode. The values for the flags are reused to fit into 16 bit,
2422 * since EFX_PKT_START and EFX_PKT_CONT are never used in
2423 * packed stream mode
2425 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
2426 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
2429 #define EFX_EV_RX_NLABELS 32
2430 #define EFX_EV_TX_NLABELS 32
2432 typedef __checkReturn boolean_t
2435 __in uint32_t label,
2438 __in uint16_t flags);
2440 typedef __checkReturn boolean_t
2441 (*efx_rx_packets_ev_t)(
2443 __in uint32_t label,
2444 __in unsigned int num_packets,
2445 __in uint32_t flags);
2447 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2450 * Packed stream mode is documented in SF-112241-TC.
2451 * The general idea is that, instead of putting each incoming
2452 * packet into a separate buffer which is specified in a RX
2453 * descriptor, a large buffer is provided to the hardware and
2454 * packets are put there in a continuous stream.
2455 * The main advantage of such an approach is that RX queue refilling
2456 * happens much less frequently.
2458 * Equal stride packed stream mode is documented in SF-119419-TC.
2459 * The general idea is to utilize advantages of the packed stream,
2460 * but avoid indirection in packets representation.
2461 * The main advantage of such an approach is that RX queue refilling
2462 * happens much less frequently and packets buffers are independent
2463 * from upper layers point of view.
2466 typedef __checkReturn boolean_t
2469 __in uint32_t label,
2471 __in uint32_t pkt_count,
2472 __in uint16_t flags);
2476 typedef __checkReturn boolean_t
2479 __in uint32_t label,
2482 typedef __checkReturn boolean_t
2483 (*efx_tx_ndescs_ev_t)(
2485 __in uint32_t label,
2486 __in unsigned int ndescs);
2488 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
2489 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
2490 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
2491 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
2492 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
2493 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
2494 #define EFX_EXCEPTION_RX_ERROR 0x00000007
2495 #define EFX_EXCEPTION_TX_ERROR 0x00000008
2496 #define EFX_EXCEPTION_EV_ERROR 0x00000009
2498 typedef __checkReturn boolean_t
2499 (*efx_exception_ev_t)(
2501 __in uint32_t label,
2502 __in uint32_t data);
2504 typedef __checkReturn boolean_t
2505 (*efx_rxq_flush_done_ev_t)(
2507 __in uint32_t rxq_index);
2509 typedef __checkReturn boolean_t
2510 (*efx_rxq_flush_failed_ev_t)(
2512 __in uint32_t rxq_index);
2514 typedef __checkReturn boolean_t
2515 (*efx_txq_flush_done_ev_t)(
2517 __in uint32_t txq_index);
2519 typedef __checkReturn boolean_t
2520 (*efx_software_ev_t)(
2522 __in uint16_t magic);
2524 typedef __checkReturn boolean_t
2527 __in uint32_t code);
2529 #define EFX_SRAM_CLEAR 0
2530 #define EFX_SRAM_UPDATE 1
2531 #define EFX_SRAM_ILLEGAL_CLEAR 2
2533 typedef __checkReturn boolean_t
2534 (*efx_wake_up_ev_t)(
2536 __in uint32_t label);
2538 typedef __checkReturn boolean_t
2541 __in uint32_t label);
2543 typedef __checkReturn boolean_t
2544 (*efx_link_change_ev_t)(
2546 __in efx_link_mode_t link_mode);
2548 #if EFSYS_OPT_MON_STATS
2550 typedef __checkReturn boolean_t
2551 (*efx_monitor_ev_t)(
2553 __in efx_mon_stat_t id,
2554 __in efx_mon_stat_value_t value);
2556 #endif /* EFSYS_OPT_MON_STATS */
2558 #if EFSYS_OPT_MAC_STATS
2560 typedef __checkReturn boolean_t
2561 (*efx_mac_stats_ev_t)(
2563 __in uint32_t generation);
2565 #endif /* EFSYS_OPT_MAC_STATS */
2567 #if EFSYS_OPT_DESC_PROXY
2570 * NOTE: This callback returns the raw descriptor data, which has not been
2571 * converted to host endian. The callback must use the EFX_OWORD macros
2572 * to extract the descriptor fields as host endian values.
2574 typedef __checkReturn boolean_t
2575 (*efx_desc_proxy_txq_desc_ev_t)(
2577 __in uint16_t vi_id,
2578 __in efx_oword_t txq_desc);
2581 * NOTE: This callback returns the raw descriptor data, which has not been
2582 * converted to host endian. The callback must use the EFX_OWORD macros
2583 * to extract the descriptor fields as host endian values.
2585 typedef __checkReturn boolean_t
2586 (*efx_desc_proxy_virtq_desc_ev_t)(
2588 __in uint16_t vi_id,
2589 __in uint16_t avail,
2590 __in efx_oword_t virtq_desc);
2592 #endif /* EFSYS_OPT_DESC_PROXY */
2594 typedef struct efx_ev_callbacks_s {
2595 efx_initialized_ev_t eec_initialized;
2597 efx_rx_packets_ev_t eec_rx_packets;
2598 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2599 efx_rx_ps_ev_t eec_rx_ps;
2602 efx_tx_ndescs_ev_t eec_tx_ndescs;
2603 efx_exception_ev_t eec_exception;
2604 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2605 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2606 efx_txq_flush_done_ev_t eec_txq_flush_done;
2607 efx_software_ev_t eec_software;
2608 efx_sram_ev_t eec_sram;
2609 efx_wake_up_ev_t eec_wake_up;
2610 efx_timer_ev_t eec_timer;
2611 efx_link_change_ev_t eec_link_change;
2612 #if EFSYS_OPT_MON_STATS
2613 efx_monitor_ev_t eec_monitor;
2614 #endif /* EFSYS_OPT_MON_STATS */
2615 #if EFSYS_OPT_MAC_STATS
2616 efx_mac_stats_ev_t eec_mac_stats;
2617 #endif /* EFSYS_OPT_MAC_STATS */
2618 #if EFSYS_OPT_DESC_PROXY
2619 efx_desc_proxy_txq_desc_ev_t eec_desc_proxy_txq_desc;
2620 efx_desc_proxy_virtq_desc_ev_t eec_desc_proxy_virtq_desc;
2621 #endif /* EFSYS_OPT_DESC_PROXY */
2623 } efx_ev_callbacks_t;
2626 extern __checkReturn boolean_t
2628 __in efx_evq_t *eep,
2629 __in unsigned int count);
2631 #if EFSYS_OPT_EV_PREFETCH
2636 __in efx_evq_t *eep,
2637 __in unsigned int count);
2639 #endif /* EFSYS_OPT_EV_PREFETCH */
2643 efx_ev_qcreate_check_init_done(
2644 __in efx_evq_t *eep,
2645 __in const efx_ev_callbacks_t *eecp,
2646 __in_opt void *arg);
2651 __in efx_evq_t *eep,
2652 __inout unsigned int *countp,
2653 __in const efx_ev_callbacks_t *eecp,
2654 __in_opt void *arg);
2657 extern __checkReturn efx_rc_t
2658 efx_ev_usecs_to_ticks(
2659 __in efx_nic_t *enp,
2660 __in unsigned int usecs,
2661 __out unsigned int *ticksp);
2664 extern __checkReturn efx_rc_t
2666 __in efx_evq_t *eep,
2667 __in unsigned int us);
2670 extern __checkReturn efx_rc_t
2672 __in efx_evq_t *eep,
2673 __in unsigned int count);
2675 #if EFSYS_OPT_QSTATS
2682 __in efx_nic_t *enp,
2683 __in unsigned int id);
2685 #endif /* EFSYS_OPT_NAMES */
2689 efx_ev_qstats_update(
2690 __in efx_evq_t *eep,
2691 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2693 #endif /* EFSYS_OPT_QSTATS */
2698 __in efx_evq_t *eep);
2703 extern __checkReturn efx_rc_t
2705 __inout efx_nic_t *enp);
2710 __in efx_nic_t *enp);
2712 #if EFSYS_OPT_RX_SCATTER
2714 extern __checkReturn efx_rc_t
2715 efx_rx_scatter_enable(
2716 __in efx_nic_t *enp,
2717 __in unsigned int buf_size);
2718 #endif /* EFSYS_OPT_RX_SCATTER */
2720 /* Handle to represent use of the default RSS context. */
2721 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2723 #if EFSYS_OPT_RX_SCALE
2725 typedef enum efx_rx_hash_alg_e {
2726 EFX_RX_HASHALG_LFSR = 0,
2727 EFX_RX_HASHALG_TOEPLITZ,
2728 EFX_RX_HASHALG_PACKED_STREAM,
2730 } efx_rx_hash_alg_t;
2733 * Legacy hash type flags.
2735 * They represent standard tuples for distinct traffic classes.
2737 #define EFX_RX_HASH_IPV4 (1U << 0)
2738 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2739 #define EFX_RX_HASH_IPV6 (1U << 2)
2740 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2742 #define EFX_RX_HASH_LEGACY_MASK \
2743 (EFX_RX_HASH_IPV4 | \
2744 EFX_RX_HASH_TCPIPV4 | \
2745 EFX_RX_HASH_IPV6 | \
2746 EFX_RX_HASH_TCPIPV6)
2749 * The type of the argument used by efx_rx_scale_mode_set() to
2750 * provide a means for the client drivers to configure hashing.
2752 * A properly constructed value can either be:
2753 * - a combination of legacy flags
2754 * - a combination of EFX_RX_HASH() flags
2756 typedef uint32_t efx_rx_hash_type_t;
2758 typedef enum efx_rx_hash_support_e {
2759 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2760 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2761 } efx_rx_hash_support_t;
2763 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2764 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2765 #define EFX_MAXRSS 64 /* RX indirection entry range */
2766 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2768 typedef enum efx_rx_scale_context_type_e {
2769 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2770 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2771 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2772 } efx_rx_scale_context_type_t;
2775 * Traffic classes eligible for hash computation.
2777 * Select packet headers used in computing the receive hash.
2778 * This uses the same encoding as the RSS_MODES field of
2779 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2781 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2782 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2783 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2784 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2785 #define EFX_RX_CLASS_IPV4_LBN 16
2786 #define EFX_RX_CLASS_IPV4_WIDTH 4
2787 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2788 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2789 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2790 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2791 #define EFX_RX_CLASS_IPV6_LBN 28
2792 #define EFX_RX_CLASS_IPV6_WIDTH 4
2794 #define EFX_RX_NCLASSES 6
2797 * Ancillary flags used to construct generic hash tuples.
2798 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2800 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2801 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2802 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2803 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2806 * Generic hash tuples.
2808 * They express combinations of packet fields
2809 * which can contribute to the hash value for
2810 * a particular traffic class.
2812 #define EFX_RX_CLASS_HASH_DISABLE 0
2814 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2815 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2817 #define EFX_RX_CLASS_HASH_2TUPLE \
2818 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2819 EFX_RX_CLASS_HASH_DST_ADDR)
2821 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2822 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2823 EFX_RX_CLASS_HASH_SRC_PORT)
2825 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2826 (EFX_RX_CLASS_HASH_DST_ADDR | \
2827 EFX_RX_CLASS_HASH_DST_PORT)
2829 #define EFX_RX_CLASS_HASH_4TUPLE \
2830 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2831 EFX_RX_CLASS_HASH_DST_ADDR | \
2832 EFX_RX_CLASS_HASH_SRC_PORT | \
2833 EFX_RX_CLASS_HASH_DST_PORT)
2835 #define EFX_RX_CLASS_HASH_NTUPLES 7
2838 * Hash flag constructor.
2840 * Resulting flags encode hash tuples for specific traffic classes.
2841 * The client drivers are encouraged to use these flags to form
2842 * a hash type value.
2844 #define EFX_RX_HASH(_class, _tuple) \
2845 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2846 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2849 * The maximum number of EFX_RX_HASH() flags.
2851 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2854 extern __checkReturn efx_rc_t
2855 efx_rx_scale_hash_flags_get(
2856 __in efx_nic_t *enp,
2857 __in efx_rx_hash_alg_t hash_alg,
2858 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
2859 __in unsigned int max_nflags,
2860 __out unsigned int *nflagsp);
2863 extern __checkReturn efx_rc_t
2864 efx_rx_hash_default_support_get(
2865 __in efx_nic_t *enp,
2866 __out efx_rx_hash_support_t *supportp);
2870 extern __checkReturn efx_rc_t
2871 efx_rx_scale_default_support_get(
2872 __in efx_nic_t *enp,
2873 __out efx_rx_scale_context_type_t *typep);
2876 extern __checkReturn efx_rc_t
2877 efx_rx_scale_context_alloc(
2878 __in efx_nic_t *enp,
2879 __in efx_rx_scale_context_type_t type,
2880 __in uint32_t num_queues,
2881 __out uint32_t *rss_contextp);
2884 extern __checkReturn efx_rc_t
2885 efx_rx_scale_context_free(
2886 __in efx_nic_t *enp,
2887 __in uint32_t rss_context);
2890 extern __checkReturn efx_rc_t
2891 efx_rx_scale_mode_set(
2892 __in efx_nic_t *enp,
2893 __in uint32_t rss_context,
2894 __in efx_rx_hash_alg_t alg,
2895 __in efx_rx_hash_type_t type,
2896 __in boolean_t insert);
2899 extern __checkReturn efx_rc_t
2900 efx_rx_scale_tbl_set(
2901 __in efx_nic_t *enp,
2902 __in uint32_t rss_context,
2903 __in_ecount(n) unsigned int *table,
2907 extern __checkReturn efx_rc_t
2908 efx_rx_scale_key_set(
2909 __in efx_nic_t *enp,
2910 __in uint32_t rss_context,
2911 __in_ecount(n) uint8_t *key,
2915 extern __checkReturn uint32_t
2916 efx_pseudo_hdr_hash_get(
2917 __in efx_rxq_t *erp,
2918 __in efx_rx_hash_alg_t func,
2919 __in uint8_t *buffer);
2921 #endif /* EFSYS_OPT_RX_SCALE */
2924 extern __checkReturn efx_rc_t
2925 efx_pseudo_hdr_pkt_length_get(
2926 __in efx_rxq_t *erp,
2927 __in uint8_t *buffer,
2928 __out uint16_t *pkt_lengthp);
2931 extern __checkReturn size_t
2933 __in const efx_nic_t *enp,
2934 __in unsigned int ndescs);
2937 extern __checkReturn unsigned int
2939 __in const efx_nic_t *enp,
2940 __in unsigned int ndescs);
2942 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2945 * libefx representation of the Rx prefix layout information.
2947 * The information may be used inside libefx to implement Rx prefix fields
2948 * accessors and by drivers which process Rx prefix itself.
2952 * All known Rx prefix fields.
2954 * An Rx prefix may have a subset of these fields.
2956 typedef enum efx_rx_prefix_field_e {
2957 EFX_RX_PREFIX_FIELD_LENGTH = 0,
2958 EFX_RX_PREFIX_FIELD_ORIG_LENGTH,
2959 EFX_RX_PREFIX_FIELD_CLASS,
2960 EFX_RX_PREFIX_FIELD_RSS_HASH,
2961 EFX_RX_PREFIX_FIELD_RSS_HASH_VALID,
2962 EFX_RX_PREFIX_FIELD_PARTIAL_TSTAMP,
2963 EFX_RX_PREFIX_FIELD_VLAN_STRIP_TCI,
2964 EFX_RX_PREFIX_FIELD_INNER_VLAN_STRIP_TCI,
2965 EFX_RX_PREFIX_FIELD_USER_FLAG,
2966 EFX_RX_PREFIX_FIELD_USER_MARK,
2967 EFX_RX_PREFIX_FIELD_USER_MARK_VALID,
2968 EFX_RX_PREFIX_FIELD_CSUM_FRAME,
2969 EFX_RX_PREFIX_FIELD_INGRESS_VPORT,
2970 EFX_RX_PREFIX_FIELD_INGRESS_MPORT = EFX_RX_PREFIX_FIELD_INGRESS_VPORT,
2971 EFX_RX_PREFIX_NFIELDS
2972 } efx_rx_prefix_field_t;
2975 * Location and endianness of a field in Rx prefix.
2977 * If width is zero, the field is not present.
2979 typedef struct efx_rx_prefix_field_info_s {
2980 uint16_t erpfi_offset_bits;
2981 uint8_t erpfi_width_bits;
2982 boolean_t erpfi_big_endian;
2983 } efx_rx_prefix_field_info_t;
2985 /* Helper macro to define Rx prefix fields */
2986 #define EFX_RX_PREFIX_FIELD(_efx, _field, _big_endian) \
2987 [EFX_RX_PREFIX_FIELD_ ## _efx] = { \
2988 .erpfi_offset_bits = EFX_LOW_BIT(_field), \
2989 .erpfi_width_bits = EFX_WIDTH(_field), \
2990 .erpfi_big_endian = (_big_endian), \
2993 typedef struct efx_rx_prefix_layout_s {
2995 uint8_t erpl_length;
2996 efx_rx_prefix_field_info_t erpl_fields[EFX_RX_PREFIX_NFIELDS];
2997 } efx_rx_prefix_layout_t;
3000 * Helper function to find out a bit mask of wanted but not available
3003 * A field is considered as not available if any parameter mismatch.
3006 extern __checkReturn uint32_t
3007 efx_rx_prefix_layout_check(
3008 __in const efx_rx_prefix_layout_t *available,
3009 __in const efx_rx_prefix_layout_t *wanted);
3012 extern __checkReturn efx_rc_t
3013 efx_rx_prefix_get_layout(
3014 __in const efx_rxq_t *erp,
3015 __out efx_rx_prefix_layout_t *erplp);
3017 typedef enum efx_rxq_type_e {
3018 EFX_RXQ_TYPE_DEFAULT,
3019 EFX_RXQ_TYPE_PACKED_STREAM,
3020 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
3025 * Dummy flag to be used instead of 0 to make it clear that the argument
3026 * is receive queue flags.
3028 #define EFX_RXQ_FLAG_NONE 0x0
3029 #define EFX_RXQ_FLAG_SCATTER 0x1
3031 * If tunnels are supported and Rx event can provide information about
3032 * either outer or inner packet classes (e.g. SFN8xxx adapters with
3033 * full-feature firmware variant running), outer classes are requested by
3034 * default. However, if the driver supports tunnels, the flag allows to
3035 * request inner classes which are required to be able to interpret inner
3036 * Rx checksum offload results.
3038 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
3040 * Request delivery of the RSS hash calculated by HW to be used by
3043 #define EFX_RXQ_FLAG_RSS_HASH 0x4
3045 * Request ingress mport field in the Rx prefix of a queue.
3047 #define EFX_RXQ_FLAG_INGRESS_MPORT 0x8
3049 * Request user mark field in the Rx prefix of a queue.
3051 #define EFX_RXQ_FLAG_USER_MARK 0x10
3053 * Request user flag field in the Rx prefix of a queue.
3055 #define EFX_RXQ_FLAG_USER_FLAG 0x20
3058 extern __checkReturn efx_rc_t
3060 __in efx_nic_t *enp,
3061 __in unsigned int index,
3062 __in unsigned int label,
3063 __in efx_rxq_type_t type,
3064 __in size_t buf_size,
3065 __in efsys_mem_t *esmp,
3068 __in unsigned int flags,
3069 __in efx_evq_t *eep,
3070 __deref_out efx_rxq_t **erpp);
3072 #if EFSYS_OPT_RX_PACKED_STREAM
3074 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
3075 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
3076 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
3077 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
3078 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
3081 extern __checkReturn efx_rc_t
3082 efx_rx_qcreate_packed_stream(
3083 __in efx_nic_t *enp,
3084 __in unsigned int index,
3085 __in unsigned int label,
3086 __in uint32_t ps_buf_size,
3087 __in efsys_mem_t *esmp,
3089 __in efx_evq_t *eep,
3090 __deref_out efx_rxq_t **erpp);
3094 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
3096 /* Maximum head-of-line block timeout in nanoseconds */
3097 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
3100 extern __checkReturn efx_rc_t
3101 efx_rx_qcreate_es_super_buffer(
3102 __in efx_nic_t *enp,
3103 __in unsigned int index,
3104 __in unsigned int label,
3105 __in uint32_t n_bufs_per_desc,
3106 __in uint32_t max_dma_len,
3107 __in uint32_t buf_stride,
3108 __in uint32_t hol_block_timeout,
3109 __in efsys_mem_t *esmp,
3111 __in unsigned int flags,
3112 __in efx_evq_t *eep,
3113 __deref_out efx_rxq_t **erpp);
3117 typedef struct efx_buffer_s {
3118 efsys_dma_addr_t eb_addr;
3123 typedef struct efx_desc_s {
3130 __in efx_rxq_t *erp,
3131 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
3133 __in unsigned int ndescs,
3134 __in unsigned int completed,
3135 __in unsigned int added);
3140 __in efx_rxq_t *erp,
3141 __in unsigned int added,
3142 __inout unsigned int *pushedp);
3144 #if EFSYS_OPT_RX_PACKED_STREAM
3148 efx_rx_qpush_ps_credits(
3149 __in efx_rxq_t *erp);
3152 extern __checkReturn uint8_t *
3153 efx_rx_qps_packet_info(
3154 __in efx_rxq_t *erp,
3155 __in uint8_t *buffer,
3156 __in uint32_t buffer_length,
3157 __in uint32_t current_offset,
3158 __out uint16_t *lengthp,
3159 __out uint32_t *next_offsetp,
3160 __out uint32_t *timestamp);
3164 extern __checkReturn efx_rc_t
3166 __in efx_rxq_t *erp);
3171 __in efx_rxq_t *erp);
3176 __in efx_rxq_t *erp);
3180 typedef struct efx_txq_s efx_txq_t;
3182 #if EFSYS_OPT_QSTATS
3184 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
3185 typedef enum efx_tx_qstat_e {
3191 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
3193 #endif /* EFSYS_OPT_QSTATS */
3196 extern __checkReturn efx_rc_t
3198 __in efx_nic_t *enp);
3203 __in efx_nic_t *enp);
3206 extern __checkReturn size_t
3208 __in const efx_nic_t *enp,
3209 __in unsigned int ndescs);
3212 extern __checkReturn unsigned int
3214 __in const efx_nic_t *enp,
3215 __in unsigned int ndescs);
3217 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
3219 #define EFX_TXQ_CKSUM_IPV4 0x0001
3220 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
3221 #define EFX_TXQ_FATSOV2 0x0004
3222 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
3223 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
3226 extern __checkReturn efx_rc_t
3228 __in efx_nic_t *enp,
3229 __in unsigned int index,
3230 __in unsigned int label,
3231 __in efsys_mem_t *esmp,
3234 __in uint16_t flags,
3235 __in efx_evq_t *eep,
3236 __deref_out efx_txq_t **etpp,
3237 __out unsigned int *addedp);
3240 extern __checkReturn efx_rc_t
3242 __in efx_txq_t *etp,
3243 __in_ecount(ndescs) efx_buffer_t *eb,
3244 __in unsigned int ndescs,
3245 __in unsigned int completed,
3246 __inout unsigned int *addedp);
3249 extern __checkReturn efx_rc_t
3251 __in efx_txq_t *etp,
3252 __in unsigned int ns);
3257 __in efx_txq_t *etp,
3258 __in unsigned int added,
3259 __in unsigned int pushed);
3262 extern __checkReturn efx_rc_t
3264 __in efx_txq_t *etp);
3269 __in efx_txq_t *etp);
3272 extern __checkReturn efx_rc_t
3274 __in efx_txq_t *etp);
3278 efx_tx_qpio_disable(
3279 __in efx_txq_t *etp);
3282 extern __checkReturn efx_rc_t
3284 __in efx_txq_t *etp,
3285 __in_ecount(buf_length) uint8_t *buffer,
3286 __in size_t buf_length,
3287 __in size_t pio_buf_offset);
3290 extern __checkReturn efx_rc_t
3292 __in efx_txq_t *etp,
3293 __in size_t pkt_length,
3294 __in unsigned int completed,
3295 __inout unsigned int *addedp);
3298 extern __checkReturn efx_rc_t
3300 __in efx_txq_t *etp,
3301 __in_ecount(n) efx_desc_t *ed,
3302 __in unsigned int n,
3303 __in unsigned int completed,
3304 __inout unsigned int *addedp);
3308 efx_tx_qdesc_dma_create(
3309 __in efx_txq_t *etp,
3310 __in efsys_dma_addr_t addr,
3313 __out efx_desc_t *edp);
3317 efx_tx_qdesc_tso_create(
3318 __in efx_txq_t *etp,
3319 __in uint16_t ipv4_id,
3320 __in uint32_t tcp_seq,
3321 __in uint8_t tcp_flags,
3322 __out efx_desc_t *edp);
3324 /* Number of FATSOv2 option descriptors */
3325 #define EFX_TX_FATSOV2_OPT_NDESCS 2
3327 /* Maximum number of DMA segments per TSO packet (not superframe) */
3328 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
3332 efx_tx_qdesc_tso2_create(
3333 __in efx_txq_t *etp,
3334 __in uint16_t ipv4_id,
3335 __in uint16_t outer_ipv4_id,
3336 __in uint32_t tcp_seq,
3337 __in uint16_t tcp_mss,
3338 __out_ecount(count) efx_desc_t *edp,
3343 efx_tx_qdesc_vlantci_create(
3344 __in efx_txq_t *etp,
3346 __out efx_desc_t *edp);
3350 efx_tx_qdesc_checksum_create(
3351 __in efx_txq_t *etp,
3352 __in uint16_t flags,
3353 __out efx_desc_t *edp);
3355 #if EFSYS_OPT_QSTATS
3362 __in efx_nic_t *etp,
3363 __in unsigned int id);
3365 #endif /* EFSYS_OPT_NAMES */
3369 efx_tx_qstats_update(
3370 __in efx_txq_t *etp,
3371 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
3373 #endif /* EFSYS_OPT_QSTATS */
3378 __in efx_txq_t *etp);
3383 #if EFSYS_OPT_FILTER
3385 #define EFX_ETHER_TYPE_IPV4 0x0800
3386 #define EFX_ETHER_TYPE_IPV6 0x86DD
3388 #define EFX_IPPROTO_TCP 6
3389 #define EFX_IPPROTO_UDP 17
3390 #define EFX_IPPROTO_GRE 47
3392 /* Use RSS to spread across multiple queues */
3393 #define EFX_FILTER_FLAG_RX_RSS 0x01
3394 /* Enable RX scatter */
3395 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
3397 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
3398 * May only be set by the filter implementation for each type.
3399 * A removal request will restore the automatic filter in its place.
3401 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
3402 /* Filter is for RX */
3403 #define EFX_FILTER_FLAG_RX 0x08
3404 /* Filter is for TX */
3405 #define EFX_FILTER_FLAG_TX 0x10
3406 /* Set match flag on the received packet */
3407 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
3408 /* Set match mark on the received packet */
3409 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
3411 typedef uint8_t efx_filter_flags_t;
3414 * Flags which specify the fields to match on. The values are the same as in the
3415 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
3418 /* Match by remote IP host address */
3419 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
3420 /* Match by local IP host address */
3421 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
3422 /* Match by remote MAC address */
3423 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
3424 /* Match by remote TCP/UDP port */
3425 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
3426 /* Match by remote TCP/UDP port */
3427 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
3428 /* Match by local TCP/UDP port */
3429 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
3430 /* Match by Ether-type */
3431 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
3432 /* Match by inner VLAN ID */
3433 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
3434 /* Match by outer VLAN ID */
3435 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
3436 /* Match by IP transport protocol */
3437 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
3438 /* Match by ingress MPORT */
3439 #define EFX_FILTER_MATCH_MPORT 0x00000400
3440 /* Match by VNI or VSID */
3441 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
3442 /* For encapsulated packets, match by inner frame local MAC address */
3443 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
3444 /* For encapsulated packets, match all multicast inner frames */
3445 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
3446 /* For encapsulated packets, match all unicast inner frames */
3447 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
3449 * Match by encap type, this flag does not correspond to
3450 * the MCDI match flags and any unoccupied value may be used
3452 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
3453 /* Match otherwise-unmatched multicast and broadcast packets */
3454 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
3455 /* Match otherwise-unmatched unicast packets */
3456 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
3458 typedef uint32_t efx_filter_match_flags_t;
3460 /* Filter priority from lowest to highest */
3461 typedef enum efx_filter_priority_s {
3462 EFX_FILTER_PRI_AUTO = 0, /* Automatic filter based on device
3463 * address list or hardware
3464 * requirements. This may only be used
3465 * by the filter implementation for
3467 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
3469 } efx_filter_priority_t;
3472 * FIXME: All these fields are assumed to be in little-endian byte order.
3473 * It may be better for some to be big-endian. See bug42804.
3476 typedef struct efx_filter_spec_s {
3477 efx_filter_match_flags_t efs_match_flags;
3478 uint8_t efs_priority;
3479 efx_filter_flags_t efs_flags;
3480 uint16_t efs_dmaq_id;
3481 uint32_t efs_rss_context;
3484 * Saved lower-priority filter. If it is set, it is restored on
3485 * filter delete operation.
3487 struct efx_filter_spec_s *efs_overridden_spec;
3488 /* Fields below here are hashed for software filter lookup */
3489 uint16_t efs_outer_vid;
3490 uint16_t efs_inner_vid;
3491 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
3492 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
3493 uint16_t efs_ether_type;
3494 uint8_t efs_ip_proto;
3495 efx_tunnel_protocol_t efs_encap_type;
3496 uint16_t efs_loc_port;
3497 uint16_t efs_rem_port;
3498 efx_oword_t efs_rem_host;
3499 efx_oword_t efs_loc_host;
3500 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
3501 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
3502 uint32_t efs_ingress_mport;
3503 } efx_filter_spec_t;
3506 /* Default values for use in filter specifications */
3507 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
3508 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
3511 extern __checkReturn efx_rc_t
3513 __in efx_nic_t *enp);
3518 __in efx_nic_t *enp);
3521 extern __checkReturn efx_rc_t
3523 __in efx_nic_t *enp,
3524 __inout efx_filter_spec_t *spec);
3527 extern __checkReturn efx_rc_t
3529 __in efx_nic_t *enp,
3530 __inout efx_filter_spec_t *spec);
3533 extern __checkReturn efx_rc_t
3535 __in efx_nic_t *enp);
3538 extern __checkReturn efx_rc_t
3539 efx_filter_supported_filters(
3540 __in efx_nic_t *enp,
3541 __out_ecount(buffer_length) uint32_t *buffer,
3542 __in size_t buffer_length,
3543 __out size_t *list_lengthp);
3547 efx_filter_spec_init_rx(
3548 __out efx_filter_spec_t *spec,
3549 __in efx_filter_priority_t priority,
3550 __in efx_filter_flags_t flags,
3551 __in efx_rxq_t *erp);
3555 efx_filter_spec_init_tx(
3556 __out efx_filter_spec_t *spec,
3557 __in efx_txq_t *etp);
3560 extern __checkReturn efx_rc_t
3561 efx_filter_spec_set_ipv4_local(
3562 __inout efx_filter_spec_t *spec,
3565 __in uint16_t port);
3568 extern __checkReturn efx_rc_t
3569 efx_filter_spec_set_ipv4_full(
3570 __inout efx_filter_spec_t *spec,
3572 __in uint32_t lhost,
3573 __in uint16_t lport,
3574 __in uint32_t rhost,
3575 __in uint16_t rport);
3578 extern __checkReturn efx_rc_t
3579 efx_filter_spec_set_eth_local(
3580 __inout efx_filter_spec_t *spec,
3582 __in const uint8_t *addr);
3586 efx_filter_spec_set_ether_type(
3587 __inout efx_filter_spec_t *spec,
3588 __in uint16_t ether_type);
3591 extern __checkReturn efx_rc_t
3592 efx_filter_spec_set_uc_def(
3593 __inout efx_filter_spec_t *spec);
3596 extern __checkReturn efx_rc_t
3597 efx_filter_spec_set_mc_def(
3598 __inout efx_filter_spec_t *spec);
3600 typedef enum efx_filter_inner_frame_match_e {
3601 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
3602 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
3603 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
3604 } efx_filter_inner_frame_match_t;
3607 extern __checkReturn efx_rc_t
3608 efx_filter_spec_set_encap_type(
3609 __inout efx_filter_spec_t *spec,
3610 __in efx_tunnel_protocol_t encap_type,
3611 __in efx_filter_inner_frame_match_t inner_frame_match);
3614 extern __checkReturn efx_rc_t
3615 efx_filter_spec_set_vxlan(
3616 __inout efx_filter_spec_t *spec,
3617 __in const uint8_t *vni,
3618 __in const uint8_t *inner_addr,
3619 __in const uint8_t *outer_addr);
3622 extern __checkReturn efx_rc_t
3623 efx_filter_spec_set_geneve(
3624 __inout efx_filter_spec_t *spec,
3625 __in const uint8_t *vni,
3626 __in const uint8_t *inner_addr,
3627 __in const uint8_t *outer_addr);
3630 extern __checkReturn efx_rc_t
3631 efx_filter_spec_set_nvgre(
3632 __inout efx_filter_spec_t *spec,
3633 __in const uint8_t *vsid,
3634 __in const uint8_t *inner_addr,
3635 __in const uint8_t *outer_addr);
3637 #if EFSYS_OPT_RX_SCALE
3639 extern __checkReturn efx_rc_t
3640 efx_filter_spec_set_rss_context(
3641 __inout efx_filter_spec_t *spec,
3642 __in uint32_t rss_context);
3644 #endif /* EFSYS_OPT_FILTER */
3649 extern __checkReturn uint32_t
3651 __in_ecount(count) uint32_t const *input,
3653 __in uint32_t init);
3656 extern __checkReturn uint32_t
3658 __in_ecount(length) uint8_t const *input,
3660 __in uint32_t init);
3662 #if EFSYS_OPT_LICENSING
3666 typedef struct efx_key_stats_s {
3668 uint32_t eks_invalid;
3669 uint32_t eks_blacklisted;
3670 uint32_t eks_unverifiable;
3671 uint32_t eks_wrong_node;
3672 uint32_t eks_licensed_apps_lo;
3673 uint32_t eks_licensed_apps_hi;
3674 uint32_t eks_licensed_features_lo;
3675 uint32_t eks_licensed_features_hi;
3679 extern __checkReturn efx_rc_t
3681 __in efx_nic_t *enp);
3686 __in efx_nic_t *enp);
3689 extern __checkReturn boolean_t
3690 efx_lic_check_support(
3691 __in efx_nic_t *enp);
3694 extern __checkReturn efx_rc_t
3695 efx_lic_update_licenses(
3696 __in efx_nic_t *enp);
3699 extern __checkReturn efx_rc_t
3700 efx_lic_get_key_stats(
3701 __in efx_nic_t *enp,
3702 __out efx_key_stats_t *ksp);
3705 extern __checkReturn efx_rc_t
3707 __in efx_nic_t *enp,
3708 __in uint64_t app_id,
3709 __out boolean_t *licensedp);
3712 extern __checkReturn efx_rc_t
3714 __in efx_nic_t *enp,
3715 __in size_t buffer_size,
3716 __out uint32_t *typep,
3717 __out size_t *lengthp,
3718 __out_opt uint8_t *bufferp);
3722 extern __checkReturn efx_rc_t
3724 __in efx_nic_t *enp,
3725 __in_bcount(buffer_size)
3727 __in size_t buffer_size,
3728 __out uint32_t *startp);
3731 extern __checkReturn efx_rc_t
3733 __in efx_nic_t *enp,
3734 __in_bcount(buffer_size)
3736 __in size_t buffer_size,
3737 __in uint32_t offset,
3738 __out uint32_t *endp);
3741 extern __checkReturn __success(return != B_FALSE) boolean_t
3743 __in efx_nic_t *enp,
3744 __in_bcount(buffer_size)
3746 __in size_t buffer_size,
3747 __in uint32_t offset,
3748 __out uint32_t *startp,
3749 __out uint32_t *lengthp);
3752 extern __checkReturn __success(return != B_FALSE) boolean_t
3753 efx_lic_validate_key(
3754 __in efx_nic_t *enp,
3755 __in_bcount(length) caddr_t keyp,
3756 __in uint32_t length);
3759 extern __checkReturn efx_rc_t
3761 __in efx_nic_t *enp,
3762 __in_bcount(buffer_size)
3764 __in size_t buffer_size,
3765 __in uint32_t offset,
3766 __in uint32_t length,
3767 __out_bcount_part(key_max_size, *lengthp)
3769 __in size_t key_max_size,
3770 __out uint32_t *lengthp);
3773 extern __checkReturn efx_rc_t
3775 __in efx_nic_t *enp,
3776 __in_bcount(buffer_size)
3778 __in size_t buffer_size,
3779 __in uint32_t offset,
3780 __in_bcount(length) caddr_t keyp,
3781 __in uint32_t length,
3782 __out uint32_t *lengthp);
3785 extern __checkReturn efx_rc_t
3787 __in efx_nic_t *enp,
3788 __in_bcount(buffer_size)
3790 __in size_t buffer_size,
3791 __in uint32_t offset,
3792 __in uint32_t length,
3794 __out uint32_t *deltap);
3797 extern __checkReturn efx_rc_t
3798 efx_lic_create_partition(
3799 __in efx_nic_t *enp,
3800 __in_bcount(buffer_size)
3802 __in size_t buffer_size);
3804 extern __checkReturn efx_rc_t
3805 efx_lic_finish_partition(
3806 __in efx_nic_t *enp,
3807 __in_bcount(buffer_size)
3809 __in size_t buffer_size);
3811 #endif /* EFSYS_OPT_LICENSING */
3815 #if EFSYS_OPT_TUNNEL
3818 extern __checkReturn efx_rc_t
3820 __in efx_nic_t *enp);
3825 __in efx_nic_t *enp);
3828 * For overlay network encapsulation using UDP, the firmware needs to know
3829 * the configured UDP port for the overlay so it can decode encapsulated
3831 * The UDP port/protocol list is global.
3835 extern __checkReturn efx_rc_t
3836 efx_tunnel_config_udp_add(
3837 __in efx_nic_t *enp,
3838 __in uint16_t port /* host/cpu-endian */,
3839 __in efx_tunnel_protocol_t protocol);
3842 * Returns EBUSY if reconfiguration of the port is in progress in other thread.
3845 extern __checkReturn efx_rc_t
3846 efx_tunnel_config_udp_remove(
3847 __in efx_nic_t *enp,
3848 __in uint16_t port /* host/cpu-endian */,
3849 __in efx_tunnel_protocol_t protocol);
3852 * Returns EBUSY if reconfiguration of any of the tunnel entries
3853 * is in progress in other thread.
3856 extern __checkReturn efx_rc_t
3857 efx_tunnel_config_clear(
3858 __in efx_nic_t *enp);
3861 * Apply tunnel UDP ports configuration to hardware.
3863 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
3867 extern __checkReturn efx_rc_t
3868 efx_tunnel_reconfigure(
3869 __in efx_nic_t *enp);
3871 #endif /* EFSYS_OPT_TUNNEL */
3873 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3876 * Firmware subvariant choice options.
3878 * It may be switched to no Tx checksum if attached drivers are either
3879 * preboot or firmware subvariant aware and no VIS are allocated.
3880 * If may be always switched to default explicitly using set request or
3881 * implicitly if unaware driver is attaching. If switching is done when
3882 * a driver is attached, it gets MC_REBOOT event and should recreate its
3885 * See SF-119419-TC DPDK Firmware Driver Interface and
3886 * SF-109306-TC EF10 for Driver Writers for details.
3888 typedef enum efx_nic_fw_subvariant_e {
3889 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3890 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3891 EFX_NIC_FW_SUBVARIANT_NTYPES
3892 } efx_nic_fw_subvariant_t;
3895 extern __checkReturn efx_rc_t
3896 efx_nic_get_fw_subvariant(
3897 __in efx_nic_t *enp,
3898 __out efx_nic_fw_subvariant_t *subvariantp);
3901 extern __checkReturn efx_rc_t
3902 efx_nic_set_fw_subvariant(
3903 __in efx_nic_t *enp,
3904 __in efx_nic_fw_subvariant_t subvariant);
3906 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3908 typedef enum efx_phy_fec_type_e {
3909 EFX_PHY_FEC_NONE = 0,
3912 } efx_phy_fec_type_t;
3915 extern __checkReturn efx_rc_t
3916 efx_phy_fec_type_get(
3917 __in efx_nic_t *enp,
3918 __out efx_phy_fec_type_t *typep);
3920 typedef struct efx_phy_link_state_s {
3921 uint32_t epls_adv_cap_mask;
3922 uint32_t epls_lp_cap_mask;
3923 uint32_t epls_ld_cap_mask;
3924 unsigned int epls_fcntl;
3925 efx_phy_fec_type_t epls_fec;
3926 efx_link_mode_t epls_link_mode;
3927 } efx_phy_link_state_t;
3930 extern __checkReturn efx_rc_t
3931 efx_phy_link_state_get(
3932 __in efx_nic_t *enp,
3933 __out efx_phy_link_state_t *eplsp);
3938 typedef uint32_t efx_vswitch_id_t;
3939 typedef uint32_t efx_vport_id_t;
3941 typedef enum efx_vswitch_type_e {
3942 EFX_VSWITCH_TYPE_VLAN = 1,
3943 EFX_VSWITCH_TYPE_VEB,
3944 /* VSWITCH_TYPE_VEPA: obsolete */
3945 EFX_VSWITCH_TYPE_MUX = 4,
3946 } efx_vswitch_type_t;
3948 typedef enum efx_vport_type_e {
3949 EFX_VPORT_TYPE_NORMAL = 4,
3950 EFX_VPORT_TYPE_EXPANSION,
3951 EFX_VPORT_TYPE_TEST,
3954 /* Unspecified VLAN ID to support disabling of VLAN filtering */
3955 #define EFX_FILTER_VID_UNSPEC 0xffff
3956 #define EFX_DEFAULT_VSWITCH_ID 1
3958 /* Default VF VLAN ID on creation */
3959 #define EFX_VF_VID_DEFAULT EFX_FILTER_VID_UNSPEC
3960 #define EFX_VPORT_ID_INVALID 0
3962 typedef struct efx_vport_config_s {
3963 /* Either VF index or EFX_PCI_VF_INVALID for PF */
3964 uint16_t evc_function;
3965 /* VLAN ID of the associated function */
3967 /* vport id shared with client driver */
3968 efx_vport_id_t evc_vport_id;
3969 /* MAC address of the associated function */
3970 uint8_t evc_mac_addr[EFX_MAC_ADDR_LEN];
3972 * vports created with this flag set may only transfer traffic on the
3973 * VLANs permitted by the vport. Also, an attempt to install filter with
3974 * VLAN will be refused unless requesting function has VLAN privilege.
3976 boolean_t evc_vlan_restrict;
3977 /* Whether this function is assigned or not */
3978 boolean_t evc_vport_assigned;
3979 } efx_vport_config_t;
3981 typedef struct efx_vswitch_s efx_vswitch_t;
3984 extern __checkReturn efx_rc_t
3986 __in efx_nic_t *enp);
3991 __in efx_nic_t *enp);
3994 extern __checkReturn efx_rc_t
3995 efx_evb_vswitch_create(
3996 __in efx_nic_t *enp,
3997 __in uint32_t num_vports,
3998 __inout_ecount(num_vports) efx_vport_config_t *vport_configp,
3999 __deref_out efx_vswitch_t **evpp);
4002 extern __checkReturn efx_rc_t
4003 efx_evb_vswitch_destroy(
4004 __in efx_nic_t *enp,
4005 __in efx_vswitch_t *evp);
4008 extern __checkReturn efx_rc_t
4009 efx_evb_vport_mac_set(
4010 __in efx_nic_t *enp,
4011 __in efx_vswitch_t *evp,
4012 __in efx_vport_id_t vport_id,
4013 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp);
4016 extern __checkReturn efx_rc_t
4017 efx_evb_vport_vlan_set(
4018 __in efx_nic_t *enp,
4019 __in efx_vswitch_t *evp,
4020 __in efx_vport_id_t vport_id,
4024 extern __checkReturn efx_rc_t
4025 efx_evb_vport_reset(
4026 __in efx_nic_t *enp,
4027 __in efx_vswitch_t *evp,
4028 __in efx_vport_id_t vport_id,
4029 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp,
4031 __out boolean_t *is_fn_resetp);
4034 extern __checkReturn efx_rc_t
4035 efx_evb_vport_stats(
4036 __in efx_nic_t *enp,
4037 __in efx_vswitch_t *evp,
4038 __in efx_vport_id_t vport_id,
4039 __out efsys_mem_t *stats_bufferp);
4041 #endif /* EFSYS_OPT_EVB */
4043 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
4045 typedef struct efx_proxy_auth_config_s {
4046 efsys_mem_t *request_bufferp;
4047 efsys_mem_t *response_bufferp;
4048 efsys_mem_t *status_bufferp;
4052 uint32_t handled_privileges;
4053 } efx_proxy_auth_config_t;
4055 typedef struct efx_proxy_cmd_params_s {
4058 uint8_t *request_bufferp;
4059 size_t request_size;
4060 uint8_t *response_bufferp;
4061 size_t response_size;
4062 size_t *response_size_actualp;
4063 } efx_proxy_cmd_params_t;
4066 extern __checkReturn efx_rc_t
4067 efx_proxy_auth_init(
4068 __in efx_nic_t *enp);
4072 efx_proxy_auth_fini(
4073 __in efx_nic_t *enp);
4076 extern __checkReturn efx_rc_t
4077 efx_proxy_auth_configure(
4078 __in efx_nic_t *enp,
4079 __in efx_proxy_auth_config_t *configp);
4082 extern __checkReturn efx_rc_t
4083 efx_proxy_auth_destroy(
4084 __in efx_nic_t *enp,
4085 __in uint32_t handled_privileges);
4088 extern __checkReturn efx_rc_t
4089 efx_proxy_auth_complete_request(
4090 __in efx_nic_t *enp,
4091 __in uint32_t fn_index,
4092 __in uint32_t proxy_result,
4093 __in uint32_t handle);
4096 extern __checkReturn efx_rc_t
4097 efx_proxy_auth_exec_cmd(
4098 __in efx_nic_t *enp,
4099 __inout efx_proxy_cmd_params_t *paramsp);
4102 extern __checkReturn efx_rc_t
4103 efx_proxy_auth_set_privilege_mask(
4104 __in efx_nic_t *enp,
4105 __in uint32_t vf_index,
4107 __in uint32_t value);
4110 extern __checkReturn efx_rc_t
4111 efx_proxy_auth_privilege_mask_get(
4112 __in efx_nic_t *enp,
4113 __in uint32_t pf_index,
4114 __in uint32_t vf_index,
4115 __out uint32_t *maskp);
4118 extern __checkReturn efx_rc_t
4119 efx_proxy_auth_privilege_modify(
4120 __in efx_nic_t *enp,
4121 __in uint32_t pf_index,
4122 __in uint32_t vf_index,
4123 __in uint32_t add_privileges_mask,
4124 __in uint32_t remove_privileges_mask);
4126 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
4131 extern __checkReturn efx_rc_t
4133 __in efx_nic_t *enp);
4138 __in efx_nic_t *enp);
4140 typedef struct efx_mae_limits_s {
4141 uint32_t eml_max_n_action_prios;
4142 uint32_t eml_max_n_outer_prios;
4143 uint32_t eml_encap_types_supported;
4144 uint32_t eml_encap_header_size_limit;
4145 uint32_t eml_max_n_counters;
4149 extern __checkReturn efx_rc_t
4151 __in efx_nic_t *enp,
4152 __out efx_mae_limits_t *emlp);
4154 typedef enum efx_mae_rule_type_e {
4155 EFX_MAE_RULE_ACTION = 0,
4159 } efx_mae_rule_type_t;
4161 typedef struct efx_mae_match_spec_s efx_mae_match_spec_t;
4164 extern __checkReturn efx_rc_t
4165 efx_mae_match_spec_init(
4166 __in efx_nic_t *enp,
4167 __in efx_mae_rule_type_t type,
4169 __out efx_mae_match_spec_t **specp);
4173 efx_mae_match_spec_fini(
4174 __in efx_nic_t *enp,
4175 __in efx_mae_match_spec_t *spec);
4177 typedef enum efx_mae_field_id_e {
4179 * Fields which can be set by efx_mae_match_spec_field_set()
4180 * or by using dedicated field-specific helper APIs.
4182 EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR = 0,
4183 EFX_MAE_FIELD_ETHER_TYPE_BE,
4184 EFX_MAE_FIELD_ETH_SADDR_BE,
4185 EFX_MAE_FIELD_ETH_DADDR_BE,
4186 EFX_MAE_FIELD_VLAN0_TCI_BE,
4187 EFX_MAE_FIELD_VLAN0_PROTO_BE,
4188 EFX_MAE_FIELD_VLAN1_TCI_BE,
4189 EFX_MAE_FIELD_VLAN1_PROTO_BE,
4190 EFX_MAE_FIELD_SRC_IP4_BE,
4191 EFX_MAE_FIELD_DST_IP4_BE,
4192 EFX_MAE_FIELD_IP_PROTO,
4193 EFX_MAE_FIELD_IP_TOS,
4194 EFX_MAE_FIELD_IP_TTL,
4195 EFX_MAE_FIELD_SRC_IP6_BE,
4196 EFX_MAE_FIELD_DST_IP6_BE,
4197 EFX_MAE_FIELD_L4_SPORT_BE,
4198 EFX_MAE_FIELD_L4_DPORT_BE,
4199 EFX_MAE_FIELD_TCP_FLAGS_BE,
4200 EFX_MAE_FIELD_ENC_ETHER_TYPE_BE,
4201 EFX_MAE_FIELD_ENC_ETH_SADDR_BE,
4202 EFX_MAE_FIELD_ENC_ETH_DADDR_BE,
4203 EFX_MAE_FIELD_ENC_VLAN0_TCI_BE,
4204 EFX_MAE_FIELD_ENC_VLAN0_PROTO_BE,
4205 EFX_MAE_FIELD_ENC_VLAN1_TCI_BE,
4206 EFX_MAE_FIELD_ENC_VLAN1_PROTO_BE,
4207 EFX_MAE_FIELD_ENC_SRC_IP4_BE,
4208 EFX_MAE_FIELD_ENC_DST_IP4_BE,
4209 EFX_MAE_FIELD_ENC_IP_PROTO,
4210 EFX_MAE_FIELD_ENC_IP_TOS,
4211 EFX_MAE_FIELD_ENC_IP_TTL,
4212 EFX_MAE_FIELD_ENC_SRC_IP6_BE,
4213 EFX_MAE_FIELD_ENC_DST_IP6_BE,
4214 EFX_MAE_FIELD_ENC_L4_SPORT_BE,
4215 EFX_MAE_FIELD_ENC_L4_DPORT_BE,
4216 EFX_MAE_FIELD_ENC_VNET_ID_BE,
4217 EFX_MAE_FIELD_OUTER_RULE_ID,
4219 /* Single bits which can be set by efx_mae_match_spec_bit_set(). */
4220 EFX_MAE_FIELD_HAS_OVLAN,
4221 EFX_MAE_FIELD_HAS_IVLAN,
4222 EFX_MAE_FIELD_ENC_HAS_OVLAN,
4223 EFX_MAE_FIELD_ENC_HAS_IVLAN,
4226 * Fields which can be set by efx_mae_match_spec_field_set()
4227 * or by using dedicated field-specific helper APIs.
4229 EFX_MAE_FIELD_RECIRC_ID,
4231 } efx_mae_field_id_t;
4233 /* MPORT selector. Used to refer to MPORTs in match/action rules. */
4234 typedef struct efx_mport_sel_s {
4239 * MPORT ID. Used to refer dynamically to a specific MPORT.
4240 * The difference between MPORT selector and MPORT ID is that
4241 * selector can specify an exact MPORT ID or it can specify a
4242 * pattern by which an exact MPORT ID can be selected. For example,
4243 * static MPORT selector can specify MPORT of a current PF, which
4244 * will be translated to the dynamic MPORT ID based on which PF is
4245 * using that MPORT selector.
4247 typedef struct efx_mport_id_s {
4251 typedef enum efx_mport_type_e {
4252 EFX_MPORT_TYPE_NET_PORT = 0,
4253 EFX_MPORT_TYPE_ALIAS,
4254 EFX_MPORT_TYPE_VNIC,
4257 typedef enum efx_mport_vnic_client_type_e {
4258 EFX_MPORT_VNIC_CLIENT_FUNCTION = 1,
4259 EFX_MPORT_VNIC_CLIENT_PLUGIN,
4260 } efx_mport_vnic_client_type_t;
4262 typedef struct efx_mport_desc_s {
4263 efx_mport_id_t emd_id;
4264 boolean_t emd_can_receive_on;
4265 boolean_t emd_can_deliver_to;
4266 boolean_t emd_can_delete;
4267 boolean_t emd_zombie;
4268 efx_mport_type_t emd_type;
4274 efx_mport_id_t ea_target_mport_id;
4277 efx_mport_vnic_client_type_t ev_client_type;
4278 efx_pcie_interface_t ev_intf;
4281 /* MCDI client handle for this VNIC. */
4287 #define EFX_MPORT_NULL (0U)
4290 * Generate an invalid MPORT selector.
4292 * The resulting MPORT selector is opaque to the caller. Requests
4293 * that attempt to use it will be rejected.
4296 extern __checkReturn efx_rc_t
4297 efx_mae_mport_invalid(
4298 __out efx_mport_sel_t *mportp);
4301 * Get MPORT selector of a physical port.
4303 * The resulting MPORT selector is opaque to the caller and can be
4304 * passed as an argument to efx_mae_match_spec_mport_set()
4305 * and efx_mae_action_set_populate_deliver().
4308 extern __checkReturn efx_rc_t
4309 efx_mae_mport_by_phy_port(
4310 __in uint32_t phy_port,
4311 __out efx_mport_sel_t *mportp);
4314 * Get MPORT selector of a PCIe function.
4316 * The resulting MPORT selector is opaque to the caller and can be
4317 * passed as an argument to efx_mae_match_spec_mport_set()
4318 * and efx_mae_action_set_populate_deliver().
4321 extern __checkReturn efx_rc_t
4322 efx_mae_mport_by_pcie_function(
4325 __out efx_mport_sel_t *mportp);
4328 * Get MPORT selector of a multi-host PCIe function.
4330 * The resulting MPORT selector is opaque to the caller and can be
4331 * passed as an argument to efx_mae_match_spec_mport_set()
4332 * and efx_mae_action_set_populate_deliver().
4335 extern __checkReturn efx_rc_t
4336 efx_mae_mport_by_pcie_mh_function(
4337 __in efx_pcie_interface_t intf,
4340 __out efx_mport_sel_t *mportp);
4343 * Get MPORT selector by an MPORT ID
4345 * The resulting MPORT selector is opaque to the caller and can be
4346 * passed as an argument to efx_mae_match_spec_mport_set()
4347 * and efx_mae_action_set_populate_deliver().
4350 extern __checkReturn efx_rc_t
4351 efx_mae_mport_by_id(
4352 __in const efx_mport_id_t *mport_idp,
4353 __out efx_mport_sel_t *mportp);
4355 /* Get MPORT ID by an MPORT selector */
4357 extern __checkReturn efx_rc_t
4358 efx_mae_mport_id_by_selector(
4359 __in efx_nic_t *enp,
4360 __in const efx_mport_sel_t *mport_selectorp,
4361 __out efx_mport_id_t *mport_idp);
4364 * Fields which have BE postfix in their named constants are expected
4365 * to be passed by callers in big-endian byte order. They will appear
4366 * in the MCDI buffer, which is a part of the match specification, in
4367 * the very same byte order, that is, no conversion will be performed.
4369 * Fields which don't have BE postfix in their named constants are in
4370 * host byte order. MCDI expects them to be little-endian, so the API
4371 * will take care to carry out conversion to little-endian byte order.
4372 * At the moment, the only field in host byte order is MPORT selector.
4375 extern __checkReturn efx_rc_t
4376 efx_mae_match_spec_field_set(
4377 __in efx_mae_match_spec_t *spec,
4378 __in efx_mae_field_id_t field_id,
4379 __in size_t value_size,
4380 __in_bcount(value_size) const uint8_t *value,
4381 __in size_t mask_size,
4382 __in_bcount(mask_size) const uint8_t *mask);
4384 /* The corresponding mask will be set to B_TRUE. */
4386 extern __checkReturn efx_rc_t
4387 efx_mae_match_spec_bit_set(
4388 __in efx_mae_match_spec_t *spec,
4389 __in efx_mae_field_id_t field_id,
4390 __in boolean_t value);
4392 /* If the mask argument is NULL, the API will use full mask by default. */
4394 extern __checkReturn efx_rc_t
4395 efx_mae_match_spec_mport_set(
4396 __in efx_mae_match_spec_t *spec,
4397 __in const efx_mport_sel_t *valuep,
4398 __in_opt const efx_mport_sel_t *maskp);
4401 extern __checkReturn efx_rc_t
4402 efx_mae_match_spec_recirc_id_set(
4403 __in efx_mae_match_spec_t *spec,
4404 __in uint8_t recirc_id);
4407 extern __checkReturn boolean_t
4408 efx_mae_match_specs_equal(
4409 __in const efx_mae_match_spec_t *left,
4410 __in const efx_mae_match_spec_t *right);
4413 * Make sure that match fields known by EFX have proper masks set
4414 * in the match specification as per requirements of SF-122526-TC.
4416 * In the case efx_mae_field_id_t lacks named identifiers for any
4417 * fields which the FW maintains with support status MATCH_ALWAYS,
4418 * the validation result may not be accurate.
4421 extern __checkReturn boolean_t
4422 efx_mae_match_spec_is_valid(
4423 __in efx_nic_t *enp,
4424 __in const efx_mae_match_spec_t *spec);
4426 typedef struct efx_mae_actions_s efx_mae_actions_t;
4429 extern __checkReturn efx_rc_t
4430 efx_mae_action_set_spec_init(
4431 __in efx_nic_t *enp,
4432 __out efx_mae_actions_t **specp);
4436 efx_mae_action_set_spec_fini(
4437 __in efx_nic_t *enp,
4438 __in efx_mae_actions_t *spec);
4441 extern __checkReturn efx_rc_t
4442 efx_mae_action_set_populate_decap(
4443 __in efx_mae_actions_t *spec);
4446 extern __checkReturn efx_rc_t
4447 efx_mae_action_set_populate_vlan_pop(
4448 __in efx_mae_actions_t *spec);
4451 * This always amends the outermost header. This way, for a tunnel
4452 * packet, if action DECAP is not requested, this will affect the
4453 * outer header; otherwise, the inner header will be updated.
4455 * Use efx_mae_action_set_fill_in_dst_mac_id() to set ID of
4456 * the allocated MAC address entry in the specification
4457 * prior to action set allocation.
4460 extern __checkReturn efx_rc_t
4461 efx_mae_action_set_populate_set_dst_mac(
4462 __in efx_mae_actions_t *spec);
4465 * This always amends the outermost header. This way, for a tunnel
4466 * packet, if action DECAP is not requested, this will affect the
4467 * outer header; otherwise, the inner header will be updated.
4469 * Use efx_mae_action_set_fill_in_src_mac_id() to set ID of
4470 * the allocated MAC address entry in the specification
4471 * prior to action set allocation.
4474 extern __checkReturn efx_rc_t
4475 efx_mae_action_set_populate_set_src_mac(
4476 __in efx_mae_actions_t *spec);
4479 * This always amends the outermost header. This way, for a tunnel
4480 * packet, if action DECAP is not requested, this will affect the
4481 * outer header; otherwise, the inner header will be updated.
4483 * This will also take care to update IPv4 checksum accordingly.
4486 extern __checkReturn efx_rc_t
4487 efx_mae_action_set_populate_decr_ip_ttl(
4488 __in efx_mae_actions_t *spec);
4491 extern __checkReturn efx_rc_t
4492 efx_mae_action_set_populate_vlan_push(
4493 __in efx_mae_actions_t *spec,
4494 __in uint16_t tpid_be,
4495 __in uint16_t tci_be);
4498 * Use efx_mae_action_set_fill_in_eh_id() to set ID of the allocated
4499 * encap. header in the specification prior to action set allocation.
4502 extern __checkReturn efx_rc_t
4503 efx_mae_action_set_populate_encap(
4504 __in efx_mae_actions_t *spec);
4507 * Use efx_mae_action_set_fill_in_counter_id() to set ID of a counter
4508 * in the specification prior to action set allocation.
4510 * NOTICE: the HW will conduct action COUNT after actions DECAP,
4511 * VLAN_POP, VLAN_PUSH (if any) have been applied to the packet,
4512 * but, as a workaround, this order is not validated by the API.
4514 * The workaround helps to unblock DPDK + Open vSwitch use case.
4515 * In Open vSwitch, this action is always the first to be added,
4516 * in particular, it's known to be inserted before action DECAP,
4517 * so enforcing the right order here would cause runtime errors.
4518 * The existing behaviour in Open vSwitch is unlikely to change
4519 * any time soon, and the workaround is a good solution because
4520 * in fact the real COUNT order is a don't care to Open vSwitch.
4523 extern __checkReturn efx_rc_t
4524 efx_mae_action_set_populate_count(
4525 __in efx_mae_actions_t *spec);
4528 extern __checkReturn efx_rc_t
4529 efx_mae_action_set_populate_flag(
4530 __in efx_mae_actions_t *spec);
4533 extern __checkReturn efx_rc_t
4534 efx_mae_action_set_populate_mark(
4535 __in efx_mae_actions_t *spec,
4536 __in uint32_t mark_value);
4539 extern __checkReturn efx_rc_t
4540 efx_mae_action_set_populate_deliver(
4541 __in efx_mae_actions_t *spec,
4542 __in const efx_mport_sel_t *mportp);
4545 extern __checkReturn efx_rc_t
4546 efx_mae_action_set_populate_drop(
4547 __in efx_mae_actions_t *spec);
4550 extern __checkReturn boolean_t
4551 efx_mae_action_set_specs_equal(
4552 __in const efx_mae_actions_t *left,
4553 __in const efx_mae_actions_t *right);
4556 * Conduct a comparison to check whether two match specifications
4557 * of equal rule type (action / outer) and priority would map to
4558 * the very same rule class from the firmware's standpoint.
4560 * For match specification fields that are not supported by firmware,
4561 * the rule class only matches if the mask/value pairs for that field
4562 * are equal. Clients should use efx_mae_match_spec_is_valid() before
4563 * calling this API to detect usage of unsupported fields.
4566 extern __checkReturn efx_rc_t
4567 efx_mae_match_specs_class_cmp(
4568 __in efx_nic_t *enp,
4569 __in const efx_mae_match_spec_t *left,
4570 __in const efx_mae_match_spec_t *right,
4571 __out boolean_t *have_same_classp);
4573 #define EFX_MAE_RSRC_ID_INVALID UINT32_MAX
4576 typedef struct efx_mae_rule_id_s {
4578 } efx_mae_rule_id_t;
4581 * Set the initial recirculation ID. It goes to action rule (AR) lookup.
4583 * To match on this ID in an AR, use efx_mae_match_spec_recirc_id_set().
4586 extern __checkReturn efx_rc_t
4587 efx_mae_outer_rule_recirc_id_set(
4588 __in efx_mae_match_spec_t *spec,
4589 __in uint8_t recirc_id);
4592 extern __checkReturn efx_rc_t
4593 efx_mae_outer_rule_insert(
4594 __in efx_nic_t *enp,
4595 __in const efx_mae_match_spec_t *spec,
4596 __in efx_tunnel_protocol_t encap_type,
4597 __out efx_mae_rule_id_t *or_idp);
4600 extern __checkReturn efx_rc_t
4601 efx_mae_outer_rule_remove(
4602 __in efx_nic_t *enp,
4603 __in const efx_mae_rule_id_t *or_idp);
4606 extern __checkReturn efx_rc_t
4607 efx_mae_match_spec_outer_rule_id_set(
4608 __in efx_mae_match_spec_t *spec,
4609 __in const efx_mae_rule_id_t *or_idp);
4611 /* MAC address entry ID */
4612 typedef struct efx_mae_mac_id_s {
4617 extern __checkReturn efx_rc_t
4618 efx_mae_mac_addr_alloc(
4619 __in efx_nic_t *enp,
4620 __in uint8_t addr_bytes[EFX_MAC_ADDR_LEN],
4621 __out efx_mae_mac_id_t *mac_idp);
4624 extern __checkReturn efx_rc_t
4625 efx_mae_mac_addr_free(
4626 __in efx_nic_t *enp,
4627 __in const efx_mae_mac_id_t *mac_idp);
4629 /* See description before efx_mae_action_set_populate_set_dst_mac(). */
4631 extern __checkReturn efx_rc_t
4632 efx_mae_action_set_fill_in_dst_mac_id(
4633 __in efx_mae_actions_t *spec,
4634 __in const efx_mae_mac_id_t *mac_idp);
4636 /* See description before efx_mae_action_set_populate_set_src_mac(). */
4638 extern __checkReturn efx_rc_t
4639 efx_mae_action_set_fill_in_src_mac_id(
4640 __in efx_mae_actions_t *spec,
4641 __in const efx_mae_mac_id_t *mac_idp);
4643 /* Encap. header ID */
4644 typedef struct efx_mae_eh_id_s {
4649 extern __checkReturn efx_rc_t
4650 efx_mae_encap_header_alloc(
4651 __in efx_nic_t *enp,
4652 __in efx_tunnel_protocol_t encap_type,
4653 __in_bcount(header_size) uint8_t *header_data,
4654 __in size_t header_size,
4655 __out efx_mae_eh_id_t *eh_idp);
4658 extern __checkReturn efx_rc_t
4659 efx_mae_encap_header_free(
4660 __in efx_nic_t *enp,
4661 __in const efx_mae_eh_id_t *eh_idp);
4663 /* See description before efx_mae_action_set_populate_encap(). */
4665 extern __checkReturn efx_rc_t
4666 efx_mae_action_set_fill_in_eh_id(
4667 __in efx_mae_actions_t *spec,
4668 __in const efx_mae_eh_id_t *eh_idp);
4670 typedef struct efx_counter_s {
4675 extern __checkReturn unsigned int
4676 efx_mae_action_set_get_nb_count(
4677 __in const efx_mae_actions_t *spec);
4679 /* See description before efx_mae_action_set_populate_count(). */
4681 extern __checkReturn efx_rc_t
4682 efx_mae_action_set_fill_in_counter_id(
4683 __in efx_mae_actions_t *spec,
4684 __in const efx_counter_t *counter_idp);
4687 typedef struct efx_mae_aset_id_s {
4689 } efx_mae_aset_id_t;
4692 extern __checkReturn efx_rc_t
4693 efx_mae_action_set_alloc(
4694 __in efx_nic_t *enp,
4695 __in const efx_mae_actions_t *spec,
4696 __out efx_mae_aset_id_t *aset_idp);
4699 * Generation count has two purposes:
4701 * 1) Distinguish between counter packets that belong to freed counter
4702 * and the packets that belong to reallocated counter (with the same ID);
4703 * 2) Make sure that all packets are received for a counter that was freed;
4705 * API users should provide generation count out parameter in allocation
4706 * function if counters can be reallocated and consistent counter values are
4709 * API users that need consistent final counter values after counter
4710 * deallocation or counter stream stop should provide the parameter in
4711 * functions that free the counters and stop the counter stream.
4714 extern __checkReturn efx_rc_t
4715 efx_mae_counters_alloc(
4716 __in efx_nic_t *enp,
4717 __in uint32_t n_counters,
4718 __out uint32_t *n_allocatedp,
4719 __out_ecount(n_counters) efx_counter_t *countersp,
4720 __out_opt uint32_t *gen_countp);
4723 extern __checkReturn efx_rc_t
4724 efx_mae_counters_free(
4725 __in efx_nic_t *enp,
4726 __in uint32_t n_counters,
4727 __out uint32_t *n_freedp,
4728 __in_ecount(n_counters) const efx_counter_t *countersp,
4729 __out_opt uint32_t *gen_countp);
4731 /* When set, include counters with a value of zero */
4732 #define EFX_MAE_COUNTERS_STREAM_IN_ZERO_SQUASH_DISABLE (1U << 0)
4735 * Set if credit-based flow control is used. In this case the driver
4736 * must call efx_mae_counters_stream_give_credits() to notify the
4737 * packetiser of descriptors written.
4739 #define EFX_MAE_COUNTERS_STREAM_OUT_USES_CREDITS (1U << 0)
4742 extern __checkReturn efx_rc_t
4743 efx_mae_counters_stream_start(
4744 __in efx_nic_t *enp,
4745 __in uint16_t rxq_id,
4746 __in uint16_t packet_size,
4747 __in uint32_t flags_in,
4748 __out uint32_t *flags_out);
4751 extern __checkReturn efx_rc_t
4752 efx_mae_counters_stream_stop(
4753 __in efx_nic_t *enp,
4754 __in uint16_t rxq_id,
4755 __out_opt uint32_t *gen_countp);
4758 extern __checkReturn efx_rc_t
4759 efx_mae_counters_stream_give_credits(
4760 __in efx_nic_t *enp,
4761 __in uint32_t n_credits);
4764 extern __checkReturn efx_rc_t
4765 efx_mae_action_set_free(
4766 __in efx_nic_t *enp,
4767 __in const efx_mae_aset_id_t *aset_idp);
4769 /* Action set list ID */
4770 typedef struct efx_mae_aset_list_id_s {
4772 } efx_mae_aset_list_id_t;
4775 * Either action set list ID or action set ID must be passed to this API,
4779 extern __checkReturn efx_rc_t
4780 efx_mae_action_rule_insert(
4781 __in efx_nic_t *enp,
4782 __in const efx_mae_match_spec_t *spec,
4783 __in const efx_mae_aset_list_id_t *asl_idp,
4784 __in const efx_mae_aset_id_t *as_idp,
4785 __out efx_mae_rule_id_t *ar_idp);
4788 extern __checkReturn efx_rc_t
4789 efx_mae_action_rule_remove(
4790 __in efx_nic_t *enp,
4791 __in const efx_mae_rule_id_t *ar_idp);
4794 extern __checkReturn efx_rc_t
4795 efx_mcdi_mport_alloc_alias(
4796 __in efx_nic_t *enp,
4797 __out efx_mport_id_t *mportp,
4798 __out_opt uint32_t *labelp);
4801 extern __checkReturn efx_rc_t
4803 __in efx_nic_t *enp,
4804 __in const efx_mport_id_t *mportp);
4806 typedef __checkReturn efx_rc_t
4807 (efx_mae_read_mport_journal_cb)(
4808 __in void *cb_datap,
4809 __in efx_mport_desc_t *mportp,
4810 __in size_t mport_len);
4813 * Read mport descriptions from the MAE journal (which describes added and
4814 * removed mports) and pass them to a user-supplied callback. The user gets
4815 * only one chance to process the data it's given. Once the callback function
4816 * finishes, that particular mport description will be gone.
4817 * The journal will be fully repopulated on PCI reset (efx_nic_reset function).
4820 extern __checkReturn efx_rc_t
4821 efx_mae_read_mport_journal(
4822 __in efx_nic_t *enp,
4823 __in efx_mae_read_mport_journal_cb *cbp,
4824 __in void *cb_datap);
4826 #endif /* EFSYS_OPT_MAE */
4828 #if EFSYS_OPT_VIRTIO
4830 /* A Virtio net device can have one or more pairs of Rx/Tx virtqueues
4831 * while virtio block device has a single virtqueue,
4832 * for further details refer section of 4.2.3 of SF-120734
4834 typedef enum efx_virtio_vq_type_e {
4835 EFX_VIRTIO_VQ_TYPE_NET_RXQ,
4836 EFX_VIRTIO_VQ_TYPE_NET_TXQ,
4837 EFX_VIRTIO_VQ_TYPE_BLOCK,
4838 EFX_VIRTIO_VQ_NTYPES
4839 } efx_virtio_vq_type_t;
4841 typedef struct efx_virtio_vq_dyncfg_s {
4843 * If queue is being created to be migrated then this
4844 * should be the FINAL_PIDX value returned by MC_CMD_VIRTIO_FINI_QUEUE
4845 * of the queue being migrated from. Otherwise, it should be zero.
4847 uint32_t evvd_vq_pidx;
4849 * If this queue is being created to be migrated then this
4850 * should be the FINAL_CIDX value returned by MC_CMD_VIRTIO_FINI_QUEUE
4851 * of the queue being migrated from. Otherwise, it should be zero.
4853 uint32_t evvd_vq_cidx;
4854 } efx_virtio_vq_dyncfg_t;
4857 * Virtqueue size must be a power of 2, maximum size is 32768
4858 * (see VIRTIO v1.1 section 2.6)
4860 #define EFX_VIRTIO_MAX_VQ_SIZE 0x8000
4862 typedef struct efx_virtio_vq_cfg_s {
4863 unsigned int evvc_vq_num;
4864 efx_virtio_vq_type_t evvc_type;
4866 * vDPA as VF : It is target VF number if queue is being created on VF.
4867 * vDPA as PF : If queue to be created on PF then it should be
4868 * EFX_PCI_VF_INVALID.
4870 uint16_t evvc_target_vf;
4872 * Maximum virtqueue size is EFX_VIRTIO_MAX_VQ_SIZE and
4873 * virtqueue size 0 means the queue is unavailable.
4875 uint32_t evvc_vq_size;
4876 efsys_dma_addr_t evvc_desc_tbl_addr;
4877 efsys_dma_addr_t evvc_avail_ring_addr;
4878 efsys_dma_addr_t evvc_used_ring_addr;
4879 /* MSIX vector number for the virtqueue or 0xFFFF if MSIX is not used */
4880 uint16_t evvc_msix_vector;
4882 * evvc_pas_id contains a PCIe address space identifier if the queue
4885 boolean_t evvc_use_pasid;
4886 uint32_t evvc_pas_id;
4887 /* Negotiated virtio features to be applied to this virtqueue */
4888 uint64_t evcc_features;
4889 } efx_virtio_vq_cfg_t;
4891 typedef struct efx_virtio_vq_s efx_virtio_vq_t;
4893 typedef enum efx_virtio_device_type_e {
4894 EFX_VIRTIO_DEVICE_TYPE_RESERVED,
4895 EFX_VIRTIO_DEVICE_TYPE_NET,
4896 EFX_VIRTIO_DEVICE_TYPE_BLOCK,
4897 EFX_VIRTIO_DEVICE_NTYPES
4898 } efx_virtio_device_type_t;
4901 extern __checkReturn efx_rc_t
4903 __in efx_nic_t *enp);
4908 __in efx_nic_t *enp);
4911 * When virtio net driver in the guest sets VIRTIO_CONFIG_STATUS_DRIVER_OK bit,
4912 * hypervisor starts configuring all the virtqueues in the device. When the
4913 * vhost_user has received VHOST_USER_SET_VRING_ENABLE for all the virtqueues,
4914 * then it invokes VDPA driver callback dev_conf. APIs qstart and qcreate would
4915 * be invoked from dev_conf callback to create the virtqueues, For further
4916 * details refer SF-122427.
4919 extern __checkReturn efx_rc_t
4921 __in efx_nic_t *enp,
4922 __deref_out efx_virtio_vq_t **evvpp);
4925 extern __checkReturn efx_rc_t
4927 __in efx_virtio_vq_t *evvp,
4928 __in efx_virtio_vq_cfg_t *evvcp,
4929 __in_opt efx_virtio_vq_dyncfg_t *evvdp);
4932 extern __checkReturn efx_rc_t
4934 __in efx_virtio_vq_t *evvp,
4935 __out_opt efx_virtio_vq_dyncfg_t *evvdp);
4939 efx_virtio_qdestroy(
4940 __in efx_virtio_vq_t *evvp);
4943 * Get the offset in the BAR of the doorbells for a VI.
4944 * net device : doorbell offset of RX & TX queues
4945 * block device : request doorbell offset in the BAR.
4946 * For further details refer section of 4 of SF-119689
4949 extern __checkReturn efx_rc_t
4950 efx_virtio_get_doorbell_offset(
4951 __in efx_virtio_vq_t *evvp,
4952 __out uint32_t *offsetp);
4955 extern __checkReturn efx_rc_t
4956 efx_virtio_get_features(
4957 __in efx_nic_t *enp,
4958 __in efx_virtio_device_type_t type,
4959 __out uint64_t *featuresp);
4962 extern __checkReturn efx_rc_t
4963 efx_virtio_verify_features(
4964 __in efx_nic_t *enp,
4965 __in efx_virtio_device_type_t type,
4966 __in uint64_t features);
4968 #endif /* EFSYS_OPT_VIRTIO */
4971 extern __checkReturn efx_rc_t
4972 efx_nic_dma_config_add(
4973 __in efx_nic_t *enp,
4974 __in efsys_dma_addr_t trgt_addr,
4976 __out_opt efsys_dma_addr_t *nic_basep,
4977 __out_opt efsys_dma_addr_t *trgt_basep,
4978 __out_opt size_t *map_lenp);
4981 extern __checkReturn efx_rc_t
4982 efx_nic_dma_reconfigure(
4983 __in efx_nic_t *enp);
4985 typedef enum efx_nic_dma_addr_type_e {
4986 EFX_NIC_DMA_ADDR_MCDI_BUF,
4987 EFX_NIC_DMA_ADDR_MAC_STATS_BUF,
4988 EFX_NIC_DMA_ADDR_EVENT_RING,
4989 EFX_NIC_DMA_ADDR_RX_RING,
4990 EFX_NIC_DMA_ADDR_TX_RING,
4991 EFX_NIC_DMA_ADDR_RX_BUF,
4992 EFX_NIC_DMA_ADDR_TX_BUF,
4994 EFX_NIC_DMA_ADDR_NTYPES
4995 } efx_nic_dma_addr_type_t;
4998 extern __checkReturn efx_rc_t
5000 __in efx_nic_t *enp,
5001 __in efx_nic_dma_addr_type_t addr_type,
5002 __in efsys_dma_addr_t tgt_addr,
5004 __out efsys_dma_addr_t *nic_addrp);
5010 #endif /* _SYS_EFX_H */