drivers/compress/mlx5/mlx5_compress.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2021 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <rte_malloc.h>
   6 #include <rte_log.h>
   7 #include <rte_errno.h>
   8 #include <rte_bus_pci.h>
   9 #include <rte_spinlock.h>
  10 #include <rte_comp.h>
  11 #include <rte_compressdev.h>
  12 #include <rte_compressdev_pmd.h>
  13
  14 #include <mlx5_glue.h>
  15 #include <mlx5_common.h>
  16 #include <mlx5_devx_cmds.h>
  17 #include <mlx5_common_os.h>
  18 #include <mlx5_common_devx.h>
  19 #include <mlx5_common_mr.h>
  20 #include <mlx5_prm.h>
  21
  22 #include "mlx5_compress_utils.h"
  23
  24 #define MLX5_COMPRESS_DRIVER_NAME mlx5_compress
  25 #define MLX5_COMPRESS_MAX_QPS 1024
  26 #define MLX5_COMP_MAX_WIN_SIZE_CONF 6u
  27
  28 struct mlx5_compress_xform {
  29         LIST_ENTRY(mlx5_compress_xform) next;
  30         enum rte_comp_xform_type type;
  31         enum rte_comp_checksum_type csum_type;
  32         uint32_t opcode;
  33         uint32_t gga_ctrl1; /* BE. */
  34 };
  35
  36 struct mlx5_compress_priv {
  37         TAILQ_ENTRY(mlx5_compress_priv) next;
  38         struct rte_compressdev *compressdev;
  39         struct mlx5_common_device *cdev; /* Backend mlx5 device. */
  40         void *uar;
  41         uint8_t min_block_size;
  42         /* Minimum huffman block size supported by the device. */
  43         struct rte_compressdev_config dev_config;
  44         LIST_HEAD(xform_list, mlx5_compress_xform) xform_list;
  45         rte_spinlock_t xform_sl;
  46         volatile uint64_t *uar_addr;
  47         /* HCA caps*/
  48         uint32_t mmo_decomp_sq:1;
  49         uint32_t mmo_decomp_qp:1;
  50         uint32_t mmo_comp_sq:1;
  51         uint32_t mmo_comp_qp:1;
  52         uint32_t mmo_dma_sq:1;
  53         uint32_t mmo_dma_qp:1;
  54 #ifndef RTE_ARCH_64
  55         rte_spinlock_t uar32_sl;
  56 #endif /* RTE_ARCH_64 */
  57 };
  58
  59 struct mlx5_compress_qp {
  60         uint16_t qp_id;
  61         uint16_t entries_n;
  62         uint16_t pi;
  63         uint16_t ci;
  64         struct mlx5_mr_ctrl mr_ctrl;
  65         int socket_id;
  66         struct mlx5_devx_cq cq;
  67         struct mlx5_devx_qp qp;
  68         struct mlx5_pmd_mr opaque_mr;
  69         struct rte_comp_op **ops;
  70         struct mlx5_compress_priv *priv;
  71         struct rte_compressdev_stats stats;
  72 };
  73
  74 TAILQ_HEAD(mlx5_compress_privs, mlx5_compress_priv) mlx5_compress_priv_list =
  75                                 TAILQ_HEAD_INITIALIZER(mlx5_compress_priv_list);
  76 static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER;
  77
  78 int mlx5_compress_logtype;
  79
  80 static const struct rte_compressdev_capabilities mlx5_caps[] = {
  81         {
  82                 .algo = RTE_COMP_ALGO_NULL,
  83                 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |
  84                                       RTE_COMP_FF_CRC32_CHECKSUM |
  85                                       RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
  86                                       RTE_COMP_FF_SHAREABLE_PRIV_XFORM,
  87         },
  88         {
  89                 .algo = RTE_COMP_ALGO_DEFLATE,
  90                 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |
  91                                       RTE_COMP_FF_CRC32_CHECKSUM |
  92                                       RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
  93                                       RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
  94                                       RTE_COMP_FF_HUFFMAN_FIXED |
  95                                       RTE_COMP_FF_HUFFMAN_DYNAMIC,
  96                 .window_size = {.min = 10, .max = 15, .increment = 1},
  97         },
  98         {
  99                 .algo = RTE_COMP_ALGO_LIST_END,
 100         }
 101 };
 102
 103 static void
 104 mlx5_compress_dev_info_get(struct rte_compressdev *dev,
 105                            struct rte_compressdev_info *info)
 106 {
 107         RTE_SET_USED(dev);
 108         if (info != NULL) {
 109                 info->max_nb_queue_pairs = MLX5_COMPRESS_MAX_QPS;
 110                 info->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
 111                 info->capabilities = mlx5_caps;
 112         }
 113 }
 114
 115 static int
 116 mlx5_compress_dev_configure(struct rte_compressdev *dev,
 117                             struct rte_compressdev_config *config)
 118 {
 119         struct mlx5_compress_priv *priv;
 120
 121         if (dev == NULL || config == NULL)
 122                 return -EINVAL;
 123         priv = dev->data->dev_private;
 124         priv->dev_config = *config;
 125         return 0;
 126 }
 127
 128 static int
 129 mlx5_compress_dev_close(struct rte_compressdev *dev)
 130 {
 131         RTE_SET_USED(dev);
 132         return 0;
 133 }
 134
 135 static int
 136 mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id)
 137 {
 138         struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
 139
 140         if (qp->qp.qp != NULL)
 141                 mlx5_devx_qp_destroy(&qp->qp);
 142         if (qp->cq.cq != NULL)
 143                 mlx5_devx_cq_destroy(&qp->cq);
 144         if (qp->opaque_mr.obj != NULL) {
 145                 void *opaq = qp->opaque_mr.addr;
 146
 147                 mlx5_common_verbs_dereg_mr(&qp->opaque_mr);
 148                 if (opaq != NULL)
 149                         rte_free(opaq);
 150         }
 151         mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);
 152         rte_free(qp);
 153         dev->data->queue_pairs[qp_id] = NULL;
 154         return 0;
 155 }
 156
 157 static void
 158 mlx5_compress_init_qp(struct mlx5_compress_qp *qp)
 159 {
 160         volatile struct mlx5_gga_wqe *restrict wqe =
 161                                     (volatile struct mlx5_gga_wqe *)qp->qp.wqes;
 162         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 163         const uint32_t sq_ds = rte_cpu_to_be_32((qp->qp.qp->id << 8) | 4u);
 164         const uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS <<
 165                                         MLX5_COMP_MODE_OFFSET);
 166         const uint32_t opaq_lkey = rte_cpu_to_be_32(qp->opaque_mr.lkey);
 167         int i;
 168
 169         /* All the next fields state should stay constant. */
 170         for (i = 0; i < qp->entries_n; ++i, ++wqe) {
 171                 wqe->sq_ds = sq_ds;
 172                 wqe->flags = flags;
 173                 wqe->opaque_lkey = opaq_lkey;
 174                 wqe->opaque_vaddr = rte_cpu_to_be_64
 175                                                 ((uint64_t)(uintptr_t)&opaq[i]);
 176         }
 177 }
 178
 179 static int
 180 mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
 181                        uint32_t max_inflight_ops, int socket_id)
 182 {
 183         struct mlx5_compress_priv *priv = dev->data->dev_private;
 184         struct mlx5_compress_qp *qp;
 185         struct mlx5_devx_cq_attr cq_attr = {
 186                 .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar),
 187         };
 188         struct mlx5_devx_qp_attr qp_attr = {
 189                 .pd = priv->cdev->pdn,
 190                 .uar_index = mlx5_os_get_devx_uar_page_id(priv->uar),
 191                 .user_index = qp_id,
 192         };
 193         uint32_t log_ops_n = rte_log2_u32(max_inflight_ops);
 194         uint32_t alloc_size = sizeof(*qp);
 195         void *opaq_buf;
 196         int ret;
 197
 198         alloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE);
 199         alloc_size += sizeof(struct rte_comp_op *) * (1u << log_ops_n);
 200         qp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE,
 201                                 socket_id);
 202         if (qp == NULL) {
 203                 DRV_LOG(ERR, "Failed to allocate qp memory.");
 204                 rte_errno = ENOMEM;
 205                 return -rte_errno;
 206         }
 207         dev->data->queue_pairs[qp_id] = qp;
 208         if (mlx5_mr_ctrl_init(&qp->mr_ctrl, &priv->cdev->mr_scache.dev_gen,
 209                               priv->dev_config.socket_id)) {
 210                 DRV_LOG(ERR, "Cannot allocate MR Btree for qp %u.",
 211                         (uint32_t)qp_id);
 212                 rte_errno = ENOMEM;
 213                 goto err;
 214         }
 215         opaq_buf = rte_calloc(__func__, (size_t)1 << log_ops_n,
 216                               sizeof(struct mlx5_gga_compress_opaque),
 217                               sizeof(struct mlx5_gga_compress_opaque));
 218         if (opaq_buf == NULL) {
 219                 DRV_LOG(ERR, "Failed to allocate opaque memory.");
 220                 rte_errno = ENOMEM;
 221                 goto err;
 222         }
 223         qp->entries_n = 1 << log_ops_n;
 224         qp->socket_id = socket_id;
 225         qp->qp_id = qp_id;
 226         qp->priv = priv;
 227         qp->ops = (struct rte_comp_op **)RTE_ALIGN((uintptr_t)(qp + 1),
 228                                                    RTE_CACHE_LINE_SIZE);
 229         if (mlx5_common_verbs_reg_mr(priv->cdev->pd, opaq_buf, qp->entries_n *
 230                                         sizeof(struct mlx5_gga_compress_opaque),
 231                                                          &qp->opaque_mr) != 0) {
 232                 rte_free(opaq_buf);
 233                 DRV_LOG(ERR, "Failed to register opaque MR.");
 234                 rte_errno = ENOMEM;
 235                 goto err;
 236         }
 237         ret = mlx5_devx_cq_create(priv->cdev->ctx, &qp->cq, log_ops_n, &cq_attr,
 238                                   socket_id);
 239         if (ret != 0) {
 240                 DRV_LOG(ERR, "Failed to create CQ.");
 241                 goto err;
 242         }
 243         qp_attr.cqn = qp->cq.cq->id;
 244         qp_attr.ts_format =
 245                 mlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format);
 246         qp_attr.rq_size = 0;
 247         qp_attr.sq_size = RTE_BIT32(log_ops_n);
 248         qp_attr.mmo = priv->mmo_decomp_qp && priv->mmo_comp_qp
 249                         && priv->mmo_dma_qp;
 250         ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp, log_ops_n, &qp_attr,
 251                                   socket_id);
 252         if (ret != 0) {
 253                 DRV_LOG(ERR, "Failed to create QP.");
 254                 goto err;
 255         }
 256         mlx5_compress_init_qp(qp);
 257         ret = mlx5_devx_qp2rts(&qp->qp, 0);
 258         if (ret)
 259                 goto err;
 260         DRV_LOG(INFO, "QP %u: SQN=0x%X CQN=0x%X entries num = %u",
 261                 (uint32_t)qp_id, qp->qp.qp->id, qp->cq.cq->id, qp->entries_n);
 262         return 0;
 263 err:
 264         mlx5_compress_qp_release(dev, qp_id);
 265         return -1;
 266 }
 267
 268 static int
 269 mlx5_compress_xform_free(struct rte_compressdev *dev, void *xform)
 270 {
 271         struct mlx5_compress_priv *priv = dev->data->dev_private;
 272
 273         rte_spinlock_lock(&priv->xform_sl);
 274         LIST_REMOVE((struct mlx5_compress_xform *)xform, next);
 275         rte_spinlock_unlock(&priv->xform_sl);
 276         rte_free(xform);
 277         return 0;
 278 }
 279
 280 static int
 281 mlx5_compress_xform_create(struct rte_compressdev *dev,
 282                            const struct rte_comp_xform *xform,
 283                            void **private_xform)
 284 {
 285         struct mlx5_compress_priv *priv = dev->data->dev_private;
 286         struct mlx5_compress_xform *xfrm;
 287         uint32_t size;
 288
 289         if (xform->type == RTE_COMP_COMPRESS && xform->compress.level ==
 290                                                           RTE_COMP_LEVEL_NONE) {
 291                 DRV_LOG(ERR, "Non-compressed block is not supported.");
 292                 return -ENOTSUP;
 293         }
 294         if ((xform->type == RTE_COMP_COMPRESS && xform->compress.hash_algo !=
 295              RTE_COMP_HASH_ALGO_NONE) || (xform->type == RTE_COMP_DECOMPRESS &&
 296                       xform->decompress.hash_algo != RTE_COMP_HASH_ALGO_NONE)) {
 297                 DRV_LOG(ERR, "SHA is not supported.");
 298                 return -ENOTSUP;
 299         }
 300         xfrm = rte_zmalloc_socket(__func__, sizeof(*xfrm), 0,
 301                                                     priv->dev_config.socket_id);
 302         if (xfrm == NULL)
 303                 return -ENOMEM;
 304         xfrm->opcode = MLX5_OPCODE_MMO;
 305         xfrm->type = xform->type;
 306         switch (xform->type) {
 307         case RTE_COMP_COMPRESS:
 308                 switch (xform->compress.algo) {
 309                 case RTE_COMP_ALGO_NULL:
 310                         xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
 311                                                         WQE_CSEG_OPC_MOD_OFFSET;
 312                         break;
 313                 case RTE_COMP_ALGO_DEFLATE:
 314                         size = 1 << xform->compress.window_size;
 315                         size /= MLX5_GGA_COMP_WIN_SIZE_UNITS;
 316                         xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size),
 317                                          MLX5_COMP_MAX_WIN_SIZE_CONF) <<
 318                                                 WQE_GGA_COMP_WIN_SIZE_OFFSET;
 319                         switch (xform->compress.level) {
 320                         case RTE_COMP_LEVEL_PMD_DEFAULT:
 321                                 size = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX;
 322                                 break;
 323                         case RTE_COMP_LEVEL_MAX:
 324                                 size = priv->min_block_size;
 325                                 break;
 326                         default:
 327                                 size = RTE_MAX(MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX
 328                                         + 1 - xform->compress.level,
 329                                         priv->min_block_size);
 330                         }
 331                         xfrm->gga_ctrl1 += RTE_MIN(size,
 332                                             MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX) <<
 333                                                  WQE_GGA_COMP_BLOCK_SIZE_OFFSET;
 334                         xfrm->opcode += MLX5_OPC_MOD_MMO_COMP <<
 335                                                         WQE_CSEG_OPC_MOD_OFFSET;
 336                         size = xform->compress.deflate.huffman ==
 337                                                       RTE_COMP_HUFFMAN_DYNAMIC ?
 338                                             MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX :
 339                                              MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN;
 340                         xfrm->gga_ctrl1 += size <<
 341                                                WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET;
 342                         break;
 343                 default:
 344                         goto err;
 345                 }
 346                 xfrm->csum_type = xform->compress.chksum;
 347                 break;
 348         case RTE_COMP_DECOMPRESS:
 349                 switch (xform->decompress.algo) {
 350                 case RTE_COMP_ALGO_NULL:
 351                         xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
 352                                                         WQE_CSEG_OPC_MOD_OFFSET;
 353                         break;
 354                 case RTE_COMP_ALGO_DEFLATE:
 355                         xfrm->opcode += MLX5_OPC_MOD_MMO_DECOMP <<
 356                                                         WQE_CSEG_OPC_MOD_OFFSET;
 357                         break;
 358                 default:
 359                         goto err;
 360                 }
 361                 xfrm->csum_type = xform->decompress.chksum;
 362                 break;
 363         default:
 364                 DRV_LOG(ERR, "Algorithm %u is not supported.", xform->type);
 365                 goto err;
 366         }
 367         DRV_LOG(DEBUG, "New xform: gga ctrl1 = 0x%08X opcode = 0x%08X csum "
 368                 "type = %d.", xfrm->gga_ctrl1, xfrm->opcode, xfrm->csum_type);
 369         xfrm->gga_ctrl1 = rte_cpu_to_be_32(xfrm->gga_ctrl1);
 370         rte_spinlock_lock(&priv->xform_sl);
 371         LIST_INSERT_HEAD(&priv->xform_list, xfrm, next);
 372         rte_spinlock_unlock(&priv->xform_sl);
 373         *private_xform = xfrm;
 374         return 0;
 375 err:
 376         rte_free(xfrm);
 377         return -ENOTSUP;
 378 }
 379
 380 static void
 381 mlx5_compress_dev_stop(struct rte_compressdev *dev)
 382 {
 383         RTE_SET_USED(dev);
 384 }
 385
 386 static int
 387 mlx5_compress_dev_start(struct rte_compressdev *dev)
 388 {
 389         struct mlx5_compress_priv *priv = dev->data->dev_private;
 390
 391         return mlx5_dev_mempool_subscribe(priv->cdev);
 392 }
 393
 394 static void
 395 mlx5_compress_stats_get(struct rte_compressdev *dev,
 396                 struct rte_compressdev_stats *stats)
 397 {
 398         int qp_id;
 399
 400         for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
 401                 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
 402
 403                 stats->enqueued_count += qp->stats.enqueued_count;
 404                 stats->dequeued_count += qp->stats.dequeued_count;
 405                 stats->enqueue_err_count += qp->stats.enqueue_err_count;
 406                 stats->dequeue_err_count += qp->stats.dequeue_err_count;
 407         }
 408 }
 409
 410 static void
 411 mlx5_compress_stats_reset(struct rte_compressdev *dev)
 412 {
 413         int qp_id;
 414
 415         for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
 416                 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
 417
 418                 memset(&qp->stats, 0, sizeof(qp->stats));
 419         }
 420 }
 421
 422 static struct rte_compressdev_ops mlx5_compress_ops = {
 423         .dev_configure          = mlx5_compress_dev_configure,
 424         .dev_start              = mlx5_compress_dev_start,
 425         .dev_stop               = mlx5_compress_dev_stop,
 426         .dev_close              = mlx5_compress_dev_close,
 427         .dev_infos_get          = mlx5_compress_dev_info_get,
 428         .stats_get              = mlx5_compress_stats_get,
 429         .stats_reset            = mlx5_compress_stats_reset,
 430         .queue_pair_setup       = mlx5_compress_qp_setup,
 431         .queue_pair_release     = mlx5_compress_qp_release,
 432         .private_xform_create   = mlx5_compress_xform_create,
 433         .private_xform_free     = mlx5_compress_xform_free,
 434         .stream_create          = NULL,
 435         .stream_free            = NULL,
 436 };
 437
 438 static __rte_always_inline uint32_t
 439 mlx5_compress_dseg_set(struct mlx5_compress_qp *qp,
 440                        volatile struct mlx5_wqe_dseg *restrict dseg,
 441                        struct rte_mbuf *restrict mbuf,
 442                        uint32_t offset, uint32_t len)
 443 {
 444         uintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset);
 445
 446         dseg->bcount = rte_cpu_to_be_32(len);
 447         dseg->lkey = mlx5_mr_mb2mr(qp->priv->cdev, 0, &qp->mr_ctrl, mbuf);
 448         dseg->pbuf = rte_cpu_to_be_64(addr);
 449         return dseg->lkey;
 450 }
 451
 452 /*
 453  * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
 454  * 64bit architectures.
 455  */
 456 static __rte_always_inline void
 457 mlx5_compress_uar_write(uint64_t val, struct mlx5_compress_priv *priv)
 458 {
 459 #ifdef RTE_ARCH_64
 460         *priv->uar_addr = val;
 461 #else /* !RTE_ARCH_64 */
 462         rte_spinlock_lock(&priv->uar32_sl);
 463         *(volatile uint32_t *)priv->uar_addr = val;
 464         rte_io_wmb();
 465         *((volatile uint32_t *)priv->uar_addr + 1) = val >> 32;
 466         rte_spinlock_unlock(&priv->uar32_sl);
 467 #endif
 468 }
 469
 470 static uint16_t
 471 mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops,
 472                             uint16_t nb_ops)
 473 {
 474         struct mlx5_compress_qp *qp = queue_pair;
 475         volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
 476                                                               qp->qp.wqes, *wqe;
 477         struct mlx5_compress_xform *xform;
 478         struct rte_comp_op *op;
 479         uint16_t mask = qp->entries_n - 1;
 480         uint16_t remain = qp->entries_n - (qp->pi - qp->ci);
 481         uint16_t idx;
 482         bool invalid;
 483
 484         if (remain < nb_ops)
 485                 nb_ops = remain;
 486         else
 487                 remain = nb_ops;
 488         if (unlikely(remain == 0))
 489                 return 0;
 490         do {
 491                 idx = qp->pi & mask;
 492                 wqe = &wqes[idx];
 493                 rte_prefetch0(&wqes[(qp->pi + 1) & mask]);
 494                 op = *ops++;
 495                 xform = op->private_xform;
 496                 /*
 497                  * Check operation arguments and error cases:
 498                  *   - Operation type must be state-less.
 499                  *   - Compress operation flush flag must be FULL or FINAL.
 500                  *   - Source and destination buffers must be mapped internally.
 501                  */
 502                 invalid = op->op_type != RTE_COMP_OP_STATELESS ||
 503                                             (xform->type == RTE_COMP_COMPRESS &&
 504                                           op->flush_flag < RTE_COMP_FLUSH_FULL);
 505                 if (unlikely(invalid ||
 506                              (mlx5_compress_dseg_set(qp, &wqe->gather,
 507                                                      op->m_src,
 508                                                      op->src.offset,
 509                                                      op->src.length) ==
 510                                                                   UINT32_MAX) ||
 511                              (mlx5_compress_dseg_set(qp, &wqe->scatter,
 512                                                 op->m_dst,
 513                                                 op->dst.offset,
 514                                                 rte_pktmbuf_pkt_len(op->m_dst) -
 515                                                               op->dst.offset) ==
 516                                                                  UINT32_MAX))) {
 517                         op->status = invalid ? RTE_COMP_OP_STATUS_INVALID_ARGS :
 518                                                        RTE_COMP_OP_STATUS_ERROR;
 519                         nb_ops -= remain;
 520                         if (unlikely(nb_ops == 0))
 521                                 return 0;
 522                         break;
 523                 }
 524                 wqe->gga_ctrl1 = xform->gga_ctrl1;
 525                 wqe->opcode = rte_cpu_to_be_32(xform->opcode + (qp->pi << 8));
 526                 qp->ops[idx] = op;
 527                 qp->pi++;
 528         } while (--remain);
 529         qp->stats.enqueued_count += nb_ops;
 530         rte_io_wmb();
 531         qp->qp.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->pi);
 532         rte_wmb();
 533         mlx5_compress_uar_write(*(volatile uint64_t *)wqe, qp->priv);
 534         rte_wmb();
 535         return nb_ops;
 536 }
 537
 538 static void
 539 mlx5_compress_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe,
 540                              volatile uint32_t *opaq)
 541 {
 542         size_t i;
 543
 544         DRV_LOG(ERR, "Error cqe:");
 545         for (i = 0; i < sizeof(struct mlx5_err_cqe) >> 2; i += 4)
 546                 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1],
 547                         cqe[i + 2], cqe[i + 3]);
 548         DRV_LOG(ERR, "\nError wqe:");
 549         for (i = 0; i < sizeof(struct mlx5_gga_wqe) >> 2; i += 4)
 550                 DRV_LOG(ERR, "%08X %08X %08X %08X", wqe[i], wqe[i + 1],
 551                         wqe[i + 2], wqe[i + 3]);
 552         DRV_LOG(ERR, "\nError opaq:");
 553         for (i = 0; i < sizeof(struct mlx5_gga_compress_opaque) >> 2; i += 4)
 554                 DRV_LOG(ERR, "%08X %08X %08X %08X", opaq[i], opaq[i + 1],
 555                         opaq[i + 2], opaq[i + 3]);
 556 }
 557
 558 static void
 559 mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp,
 560                              struct rte_comp_op *op)
 561 {
 562         const uint32_t idx = qp->ci & (qp->entries_n - 1);
 563         volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *)
 564                                                               &qp->cq.cqes[idx];
 565         volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
 566                                                                     qp->qp.wqes;
 567         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 568
 569         op->status = RTE_COMP_OP_STATUS_ERROR;
 570         op->consumed = 0;
 571         op->produced = 0;
 572         op->output_chksum = 0;
 573         op->debug_status = rte_be_to_cpu_32(opaq[idx].syndrom) |
 574                               ((uint64_t)rte_be_to_cpu_32(cqe->syndrome) << 32);
 575         mlx5_compress_dump_err_objs((volatile uint32_t *)cqe,
 576                                  (volatile uint32_t *)&wqes[idx],
 577                                  (volatile uint32_t *)&opaq[idx]);
 578         qp->stats.dequeue_err_count++;
 579 }
 580
 581 static uint16_t
 582 mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops,
 583                             uint16_t nb_ops)
 584 {
 585         struct mlx5_compress_qp *qp = queue_pair;
 586         volatile struct mlx5_compress_xform *restrict xform;
 587         volatile struct mlx5_cqe *restrict cqe;
 588         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 589         struct rte_comp_op *restrict op;
 590         const unsigned int cq_size = qp->entries_n;
 591         const unsigned int mask = cq_size - 1;
 592         uint32_t idx;
 593         uint32_t next_idx = qp->ci & mask;
 594         const uint16_t max = RTE_MIN((uint16_t)(qp->pi - qp->ci), nb_ops);
 595         uint16_t i = 0;
 596         int ret;
 597
 598         if (unlikely(max == 0))
 599                 return 0;
 600         do {
 601                 idx = next_idx;
 602                 next_idx = (qp->ci + 1) & mask;
 603                 rte_prefetch0(&qp->cq.cqes[next_idx]);
 604                 rte_prefetch0(qp->ops[next_idx]);
 605                 op = qp->ops[idx];
 606                 cqe = &qp->cq.cqes[idx];
 607                 ret = check_cqe(cqe, cq_size, qp->ci);
 608                 /*
 609                  * Be sure owner read is done before any other cookie field or
 610                  * opaque field.
 611                  */
 612                 rte_io_rmb();
 613                 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
 614                         if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
 615                                 break;
 616                         mlx5_compress_cqe_err_handle(qp, op);
 617                 } else {
 618                         xform = op->private_xform;
 619                         op->status = RTE_COMP_OP_STATUS_SUCCESS;
 620                         op->consumed = op->src.length;
 621                         op->produced = rte_be_to_cpu_32(cqe->byte_cnt);
 622                         MLX5_ASSERT(cqe->byte_cnt ==
 623                                     opaq[idx].scattered_length);
 624                         switch (xform->csum_type) {
 625                         case RTE_COMP_CHECKSUM_CRC32:
 626                                 op->output_chksum = (uint64_t)rte_be_to_cpu_32
 627                                                     (opaq[idx].crc32);
 628                                 break;
 629                         case RTE_COMP_CHECKSUM_ADLER32:
 630                                 op->output_chksum = (uint64_t)rte_be_to_cpu_32
 631                                             (opaq[idx].adler32) << 32;
 632                                 break;
 633                         case RTE_COMP_CHECKSUM_CRC32_ADLER32:
 634                                 op->output_chksum = (uint64_t)rte_be_to_cpu_32
 635                                                              (opaq[idx].crc32) |
 636                                                      ((uint64_t)rte_be_to_cpu_32
 637                                                      (opaq[idx].adler32) << 32);
 638                                 break;
 639                         default:
 640                                 break;
 641                         }
 642                 }
 643                 ops[i++] = op;
 644                 qp->ci++;
 645         } while (i < max);
 646         if (likely(i != 0)) {
 647                 rte_io_wmb();
 648                 qp->cq.db_rec[0] = rte_cpu_to_be_32(qp->ci);
 649                 qp->stats.dequeued_count += i;
 650         }
 651         return i;
 652 }
 653
 654 static void
 655 mlx5_compress_uar_release(struct mlx5_compress_priv *priv)
 656 {
 657         if (priv->uar != NULL) {
 658                 mlx5_glue->devx_free_uar(priv->uar);
 659                 priv->uar = NULL;
 660         }
 661 }
 662
 663 static int
 664 mlx5_compress_uar_prepare(struct mlx5_compress_priv *priv)
 665 {
 666         priv->uar = mlx5_devx_alloc_uar(priv->cdev->ctx, -1);
 667         if (priv->uar == NULL || mlx5_os_get_devx_uar_reg_addr(priv->uar) ==
 668             NULL) {
 669                 rte_errno = errno;
 670                 DRV_LOG(ERR, "Failed to allocate UAR.");
 671                 return -1;
 672         }
 673         priv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar);
 674         MLX5_ASSERT(priv->uar_addr);
 675 #ifndef RTE_ARCH_64
 676         rte_spinlock_init(&priv->uar32_sl);
 677 #endif /* RTE_ARCH_64 */
 678         return 0;
 679 }
 680
 681 static int
 682 mlx5_compress_dev_probe(struct mlx5_common_device *cdev)
 683 {
 684         struct rte_compressdev *compressdev;
 685         struct mlx5_compress_priv *priv;
 686         struct mlx5_hca_attr *attr = &cdev->config.hca_attr;
 687         struct rte_compressdev_pmd_init_params init_params = {
 688                 .name = "",
 689                 .socket_id = cdev->dev->numa_node,
 690         };
 691         const char *ibdev_name = mlx5_os_get_ctx_device_name(cdev->ctx);
 692
 693         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 694                 DRV_LOG(ERR, "Non-primary process type is not supported.");
 695                 rte_errno = ENOTSUP;
 696                 return -rte_errno;
 697         }
 698         if ((attr->mmo_compress_sq_en == 0 || attr->mmo_decompress_sq_en == 0 ||
 699             attr->mmo_dma_sq_en == 0) && (attr->mmo_compress_qp_en == 0 ||
 700             attr->mmo_decompress_qp_en == 0 || attr->mmo_dma_qp_en == 0)) {
 701                 DRV_LOG(ERR, "Not enough capabilities to support compress "
 702                         "operations, maybe old FW/OFED version?");
 703                 rte_errno = ENOTSUP;
 704                 return -ENOTSUP;
 705         }
 706         compressdev = rte_compressdev_pmd_create(ibdev_name, cdev->dev,
 707                                                  sizeof(*priv), &init_params);
 708         if (compressdev == NULL) {
 709                 DRV_LOG(ERR, "Failed to create device \"%s\".", ibdev_name);
 710                 return -ENODEV;
 711         }
 712         DRV_LOG(INFO,
 713                 "Compress device %s was created successfully.", ibdev_name);
 714         compressdev->dev_ops = &mlx5_compress_ops;
 715         compressdev->dequeue_burst = mlx5_compress_dequeue_burst;
 716         compressdev->enqueue_burst = mlx5_compress_enqueue_burst;
 717         compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
 718         priv = compressdev->data->dev_private;
 719         priv->mmo_decomp_sq = attr->mmo_decompress_sq_en;
 720         priv->mmo_decomp_qp = attr->mmo_decompress_qp_en;
 721         priv->mmo_comp_sq = attr->mmo_compress_sq_en;
 722         priv->mmo_comp_qp = attr->mmo_compress_qp_en;
 723         priv->mmo_dma_sq = attr->mmo_dma_sq_en;
 724         priv->mmo_dma_qp = attr->mmo_dma_qp_en;
 725         priv->cdev = cdev;
 726         priv->compressdev = compressdev;
 727         priv->min_block_size = attr->compress_min_block_size;
 728         if (mlx5_compress_uar_prepare(priv) != 0) {
 729                 rte_compressdev_pmd_destroy(priv->compressdev);
 730                 return -1;
 731         }
 732         pthread_mutex_lock(&priv_list_lock);
 733         TAILQ_INSERT_TAIL(&mlx5_compress_priv_list, priv, next);
 734         pthread_mutex_unlock(&priv_list_lock);
 735         return 0;
 736 }
 737
 738 static int
 739 mlx5_compress_dev_remove(struct mlx5_common_device *cdev)
 740 {
 741         struct mlx5_compress_priv *priv = NULL;
 742
 743         pthread_mutex_lock(&priv_list_lock);
 744         TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next)
 745                 if (priv->compressdev->device == cdev->dev)
 746                         break;
 747         if (priv)
 748                 TAILQ_REMOVE(&mlx5_compress_priv_list, priv, next);
 749         pthread_mutex_unlock(&priv_list_lock);
 750         if (priv) {
 751                 mlx5_compress_uar_release(priv);
 752                 rte_compressdev_pmd_destroy(priv->compressdev);
 753         }
 754         return 0;
 755 }
 756
 757 static const struct rte_pci_id mlx5_compress_pci_id_map[] = {
 758         {
 759                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
 760                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
 761         },
 762         {
 763                 .vendor_id = 0
 764         }
 765 };
 766
 767 static struct mlx5_class_driver mlx5_compress_driver = {
 768         .drv_class = MLX5_CLASS_COMPRESS,
 769         .name = RTE_STR(MLX5_COMPRESS_DRIVER_NAME),
 770         .id_table = mlx5_compress_pci_id_map,
 771         .probe = mlx5_compress_dev_probe,
 772         .remove = mlx5_compress_dev_remove,
 773 };
 774
 775 RTE_INIT(rte_mlx5_compress_init)
 776 {
 777         mlx5_common_init();
 778         if (mlx5_glue != NULL)
 779                 mlx5_class_driver_register(&mlx5_compress_driver);
 780 }
 781
 782 RTE_LOG_REGISTER_DEFAULT(mlx5_compress_logtype, NOTICE)
 783 RTE_PMD_EXPORT_NAME(MLX5_COMPRESS_DRIVER_NAME, __COUNTER__);
 784 RTE_PMD_REGISTER_PCI_TABLE(MLX5_COMPRESS_DRIVER_NAME, mlx5_compress_pci_id_map);
 785 RTE_PMD_REGISTER_KMOD_DEP(MLX5_COMPRESS_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");