1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Cavium, Inc
5 #ifndef _RTE_OCTEONTX_ZIP_VF_H_
6 #define _RTE_OCTEONTX_ZIP_VF_H_
10 #include <rte_bus_pci.h>
12 #include <rte_compressdev.h>
13 #include <rte_compressdev_pmd.h>
14 #include <rte_malloc.h>
15 #include <rte_memory.h>
16 #include <rte_spinlock.h>
20 int octtx_zip_logtype_driver;
22 /* ZIP VF Control/Status registers (CSRs): */
24 #define ZIP_VQ_ENA (0x10)
25 #define ZIP_VQ_SBUF_ADDR (0x20)
26 #define ZIP_VF_PF_MBOXX(x) (0x400 | (x)<<3)
27 #define ZIP_VQ_DOORBELL (0x1000)
30 #define PCI_VENDOR_ID_CAVIUM 0x177D
31 /**< PCI device id of ZIP VF */
32 #define PCI_DEVICE_ID_OCTEONTX_ZIPVF 0xA037
34 /* maxmum number of zip vf devices */
37 /* max size of one chunk */
38 #define ZIP_MAX_CHUNK_SIZE 8192
40 /* each instruction is fixed 128 bytes */
41 #define ZIP_CMD_SIZE 128
43 #define ZIP_CMD_SIZE_WORDS (ZIP_CMD_SIZE >> 3) /* 16 64_bit words */
45 /* size of next chunk buffer pointer */
46 #define ZIP_MAX_NCBP_SIZE 8
48 /* size of instruction queue in units of instruction size */
49 #define ZIP_MAX_NUM_CMDS ((ZIP_MAX_CHUNK_SIZE - ZIP_MAX_NCBP_SIZE) / \
50 ZIP_CMD_SIZE) /* 63 */
52 /* size of instruct queue in bytes */
53 #define ZIP_MAX_CMDQ_SIZE ((ZIP_MAX_NUM_CMDS * ZIP_CMD_SIZE) + \
54 ZIP_MAX_NCBP_SIZE)/* ~8072ull */
56 #define ZIP_BUF_SIZE 256
58 #define ZIP_SGPTR_ALIGN 16
59 #define ZIP_CMDQ_ALIGN 128
60 #define MAX_SG_LEN ((ZIP_BUF_SIZE - ZIP_SGPTR_ALIGN) / sizeof(void *))
62 /**< ZIP PMD specified queue pairs */
63 #define ZIP_MAX_VF_QUEUE 1
65 #define ZIP_ALIGN_ROUNDUP(x, _align) \
66 ((_align) * (((x) + (_align) - 1) / (_align)))
68 /**< ZIP PMD device name */
69 #define COMPRESSDEV_NAME_ZIP_PMD compress_octeonx
71 #define ZIP_PMD_LOG(level, fmt, args...) \
72 rte_log(RTE_LOG_ ## level, \
73 octtx_zip_logtype_driver, "%s(): "fmt "\n", \
76 #define ZIP_PMD_INFO(fmt, args...) \
77 ZIP_PMD_LOG(INFO, fmt, ## args)
78 #define ZIP_PMD_ERR(fmt, args...) \
79 ZIP_PMD_LOG(ERR, fmt, ## args)
81 /* resources required to process stream */
91 } NUM_BUFS_PER_STREAM;
98 * ZIP instruction Queue
101 rte_spinlock_t qlock;
104 /* pointer to start of 8-byte word length queue-head */
106 /* pointer to instruction queue virtual address */
108 /* iova addr of cmdq head*/
112 * ZIP device queue structure
115 struct zipvf_cmdq cmdq;
116 /* Hardware instruction queue structure */
117 struct rte_ring *processed_pkts;
118 /* Ring for placing processed packets */
119 struct rte_compressdev_stats qp_stats;
120 /* Queue pair statistics */
122 /* Queue Pair Identifier */
124 /* Unique Queue Pair Name */
126 /* pointer to device, queue belongs to */
127 } __rte_cache_aligned;
130 * ZIP VF device structure.
135 struct rte_pci_device *pdev;
138 /* CSR base address for underlying BAR0 VF.*/
140 /* Storing mbox domain and subdomain id for app rerun*/
141 uint32_t max_nb_queue_pairs;
142 /* pointer to device qps */
143 struct rte_mempool *zip_mp;
144 /* pointer to pools */
145 } __rte_cache_aligned;
148 zipvf_create(struct rte_compressdev *compressdev);
151 zipvf_destroy(struct rte_compressdev *compressdev);
154 zipvf_q_init(struct zipvf_qp *qp);
157 zipvf_q_term(struct zipvf_qp *qp);
161 zip_reg_read64(uint8_t *hw_addr, uint64_t offset);
164 zip_reg_write64(uint8_t *hw_addr, uint64_t offset, uint64_t val);
166 #endif /* _RTE_ZIP_VF_H_ */