drivers/crypto/aesni_mb/rte_aesni_mb_pmd_ops.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2015-2017 Intel Corporation. All rights reserved.
   5  *
   6  *   Redistribution and use in source and binary forms, with or without
   7  *   modification, are permitted provided that the following conditions
   8  *   are met:
   9  *
  10  *     * Redistributions of source code must retain the above copyright
  11  *       notice, this list of conditions and the following disclaimer.
  12  *     * Redistributions in binary form must reproduce the above copyright
  13  *       notice, this list of conditions and the following disclaimer in
  14  *       the documentation and/or other materials provided with the
  15  *       distribution.
  16  *     * Neither the name of Intel Corporation nor the names of its
  17  *       contributors may be used to endorse or promote products derived
  18  *       from this software without specific prior written permission.
  19  *
  20  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <string.h>
  34
  35 #include <rte_common.h>
  36 #include <rte_malloc.h>
  37 #include <rte_cryptodev_pmd.h>
  38
  39 #include "rte_aesni_mb_pmd_private.h"
  40
  41
  42 static const struct rte_cryptodev_capabilities aesni_mb_pmd_capabilities[] = {
  43         {       /* MD5 HMAC */
  44                 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
  45                 {.sym = {
  46                         .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
  47                         {.auth = {
  48                                 .algo = RTE_CRYPTO_AUTH_MD5_HMAC,
  49                                 .block_size = 64,
  50                                 .key_size = {
  51                                         .min = 64,
  52                                         .max = 64,
  53                                         .increment = 0
  54                                 },
  55                                 .digest_size = {
  56                                         .min = 12,
  57                                         .max = 12,
  58                                         .increment = 0
  59                                 },
  60                                 .aad_size = { 0 },
  61                                 .iv_size = { 0 }
  62                         }, }
  63                 }, }
  64         },
  65         {       /* SHA1 HMAC */
  66                 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
  67                 {.sym = {
  68                         .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
  69                         {.auth = {
  70                                 .algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
  71                                 .block_size = 64,
  72                                 .key_size = {
  73                                         .min = 64,
  74                                         .max = 64,
  75                                         .increment = 0
  76                                 },
  77                                 .digest_size = {
  78                                         .min = 12,
  79                                         .max = 12,
  80                                         .increment = 0
  81                                 },
  82                                 .aad_size = { 0 },
  83                                 .iv_size = { 0 }
  84                         }, }
  85                 }, }
  86         },
  87         {       /* SHA224 HMAC */
  88                 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
  89                 {.sym = {
  90                         .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
  91                         {.auth = {
  92                                 .algo = RTE_CRYPTO_AUTH_SHA224_HMAC,
  93                                 .block_size = 64,
  94                                 .key_size = {
  95                                         .min = 64,
  96                                         .max = 64,
  97                                         .increment = 0
  98                                 },
  99                                 .digest_size = {
 100                                         .min = 14,
 101                                         .max = 14,
 102                                         .increment = 0
 103                                 },
 104                                 .aad_size = { 0 },
 105                                 .iv_size = { 0 }
 106                         }, }
 107                 }, }
 108         },
 109         {       /* SHA256 HMAC */
 110                 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 111                 {.sym = {
 112                         .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
 113                         {.auth = {
 114                                 .algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
 115                                 .block_size = 64,
 116                                 .key_size = {
 117                                         .min = 64,
 118                                         .max = 64,
 119                                         .increment = 0
 120                                 },
 121                                 .digest_size = {
 122                                         .min = 16,
 123                                         .max = 16,
 124                                         .increment = 0
 125                                 },
 126                                 .aad_size = { 0 },
 127                                 .iv_size = { 0 }
 128                         }, }
 129                 }, }
 130         },
 131         {       /* SHA384 HMAC */
 132                 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 133                 {.sym = {
 134                         .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
 135                         {.auth = {
 136                                 .algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
 137                                 .block_size = 128,
 138                                 .key_size = {
 139                                         .min = 128,
 140                                         .max = 128,
 141                                         .increment = 0
 142                                 },
 143                                 .digest_size = {
 144                                         .min = 24,
 145                                         .max = 24,
 146                                         .increment = 0
 147                                 },
 148                                 .aad_size = { 0 },
 149                                 .iv_size = { 0 }
 150                         }, }
 151                 }, }
 152         },
 153         {       /* SHA512 HMAC */
 154                 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 155                 {.sym = {
 156                         .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
 157                         {.auth = {
 158                                 .algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
 159                                 .block_size = 128,
 160                                 .key_size = {
 161                                         .min = 128,
 162                                         .max = 128,
 163                                         .increment = 0
 164                                 },
 165                                 .digest_size = {
 166                                         .min = 32,
 167                                         .max = 32,
 168                                         .increment = 0
 169                                 },
 170                                 .aad_size = { 0 },
 171                                 .iv_size = { 0 }
 172                         }, }
 173                 }, }
 174         },
 175         {       /* AES XCBC HMAC */
 176                 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 177                 {.sym = {
 178                         .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
 179                         {.auth = {
 180                                 .algo = RTE_CRYPTO_AUTH_AES_XCBC_MAC,
 181                                 .block_size = 16,
 182                                 .key_size = {
 183                                         .min = 16,
 184                                         .max = 16,
 185                                         .increment = 0
 186                                 },
 187                                 .digest_size = {
 188                                         .min = 12,
 189                                         .max = 12,
 190                                         .increment = 0
 191                                 },
 192                                 .aad_size = { 0 },
 193                                 .iv_size = { 0 }
 194                         }, }
 195                 }, }
 196         },
 197         {       /* AES CBC */
 198                 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 199                 {.sym = {
 200                         .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
 201                         {.cipher = {
 202                                 .algo = RTE_CRYPTO_CIPHER_AES_CBC,
 203                                 .block_size = 16,
 204                                 .key_size = {
 205                                         .min = 16,
 206                                         .max = 32,
 207                                         .increment = 8
 208                                 },
 209                                 .iv_size = {
 210                                         .min = 16,
 211                                         .max = 16,
 212                                         .increment = 0
 213                                 }
 214                         }, }
 215                 }, }
 216         },
 217         {       /* AES CTR */
 218                 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 219                 {.sym = {
 220                         .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
 221                         {.cipher = {
 222                                 .algo = RTE_CRYPTO_CIPHER_AES_CTR,
 223                                 .block_size = 16,
 224                                 .key_size = {
 225                                         .min = 16,
 226                                         .max = 32,
 227                                         .increment = 8
 228                                 },
 229                                 .iv_size = {
 230                                         .min = 12,
 231                                         .max = 16,
 232                                         .increment = 4
 233                                 }
 234                         }, }
 235                 }, }
 236         },
 237         {       /* AES DOCSIS BPI */
 238                 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 239                 {.sym = {
 240                         .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
 241                         {.cipher = {
 242                                 .algo = RTE_CRYPTO_CIPHER_AES_DOCSISBPI,
 243                                 .block_size = 16,
 244                                 .key_size = {
 245                                         .min = 16,
 246                                         .max = 16,
 247                                         .increment = 0
 248                                 },
 249                                 .iv_size = {
 250                                         .min = 16,
 251                                         .max = 16,
 252                                         .increment = 0
 253                                 }
 254                         }, }
 255                 }, }
 256         },
 257
 258         RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
 259 };
 260
 261
 262 /** Configure device */
 263 static int
 264 aesni_mb_pmd_config(__rte_unused struct rte_cryptodev *dev,
 265                 __rte_unused struct rte_cryptodev_config *config)
 266 {
 267         return 0;
 268 }
 269
 270 /** Start device */
 271 static int
 272 aesni_mb_pmd_start(__rte_unused struct rte_cryptodev *dev)
 273 {
 274         return 0;
 275 }
 276
 277 /** Stop device */
 278 static void
 279 aesni_mb_pmd_stop(__rte_unused struct rte_cryptodev *dev)
 280 {
 281 }
 282
 283 /** Close device */
 284 static int
 285 aesni_mb_pmd_close(__rte_unused struct rte_cryptodev *dev)
 286 {
 287         return 0;
 288 }
 289
 290
 291 /** Get device statistics */
 292 static void
 293 aesni_mb_pmd_stats_get(struct rte_cryptodev *dev,
 294                 struct rte_cryptodev_stats *stats)
 295 {
 296         int qp_id;
 297
 298         for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
 299                 struct aesni_mb_qp *qp = dev->data->queue_pairs[qp_id];
 300
 301                 stats->enqueued_count += qp->stats.enqueued_count;
 302                 stats->dequeued_count += qp->stats.dequeued_count;
 303
 304                 stats->enqueue_err_count += qp->stats.enqueue_err_count;
 305                 stats->dequeue_err_count += qp->stats.dequeue_err_count;
 306         }
 307 }
 308
 309 /** Reset device statistics */
 310 static void
 311 aesni_mb_pmd_stats_reset(struct rte_cryptodev *dev)
 312 {
 313         int qp_id;
 314
 315         for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
 316                 struct aesni_mb_qp *qp = dev->data->queue_pairs[qp_id];
 317
 318                 memset(&qp->stats, 0, sizeof(qp->stats));
 319         }
 320 }
 321
 322
 323 /** Get device info */
 324 static void
 325 aesni_mb_pmd_info_get(struct rte_cryptodev *dev,
 326                 struct rte_cryptodev_info *dev_info)
 327 {
 328         struct aesni_mb_private *internals = dev->data->dev_private;
 329
 330         if (dev_info != NULL) {
 331                 dev_info->driver_id = dev->driver_id;
 332                 dev_info->feature_flags = dev->feature_flags;
 333                 dev_info->capabilities = aesni_mb_pmd_capabilities;
 334                 dev_info->max_nb_queue_pairs = internals->max_nb_queue_pairs;
 335                 dev_info->sym.max_nb_sessions = internals->max_nb_sessions;
 336         }
 337 }
 338
 339 /** Release queue pair */
 340 static int
 341 aesni_mb_pmd_qp_release(struct rte_cryptodev *dev, uint16_t qp_id)
 342 {
 343         struct aesni_mb_qp *qp = dev->data->queue_pairs[qp_id];
 344         struct rte_ring *r = NULL;
 345
 346         if (qp != NULL) {
 347                 r = rte_ring_lookup(qp->name);
 348                 if (r)
 349                         rte_ring_free(r);
 350                 rte_free(qp);
 351                 dev->data->queue_pairs[qp_id] = NULL;
 352         }
 353         return 0;
 354 }
 355
 356 /** set a unique name for the queue pair based on it's name, dev_id and qp_id */
 357 static int
 358 aesni_mb_pmd_qp_set_unique_name(struct rte_cryptodev *dev,
 359                 struct aesni_mb_qp *qp)
 360 {
 361         unsigned n = snprintf(qp->name, sizeof(qp->name),
 362                         "aesni_mb_pmd_%u_qp_%u",
 363                         dev->data->dev_id, qp->id);
 364
 365         if (n > sizeof(qp->name))
 366                 return -1;
 367
 368         return 0;
 369 }
 370
 371 /** Create a ring to place processed operations on */
 372 static struct rte_ring *
 373 aesni_mb_pmd_qp_create_processed_ops_ring(struct aesni_mb_qp *qp,
 374                 const char *str, unsigned int ring_size, int socket_id)
 375 {
 376         struct rte_ring *r;
 377         char ring_name[RTE_CRYPTODEV_NAME_LEN];
 378
 379         unsigned int n = snprintf(ring_name, sizeof(ring_name),
 380                                 "%s_%s",
 381                                 qp->name, str);
 382
 383         if (n > sizeof(ring_name))
 384                 return NULL;
 385
 386         r = rte_ring_lookup(ring_name);
 387         if (r) {
 388                 if (rte_ring_get_size(r) >= ring_size) {
 389                         MB_LOG_INFO("Reusing existing ring %s for processed ops",
 390                         ring_name);
 391                         return r;
 392                 }
 393
 394                 MB_LOG_ERR("Unable to reuse existing ring %s for processed ops",
 395                         ring_name);
 396                 return NULL;
 397         }
 398
 399         return rte_ring_create(ring_name, ring_size, socket_id,
 400                         RING_F_SP_ENQ | RING_F_SC_DEQ);
 401 }
 402
 403 /** Setup a queue pair */
 404 static int
 405 aesni_mb_pmd_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,
 406                 const struct rte_cryptodev_qp_conf *qp_conf,
 407                 int socket_id, struct rte_mempool *session_pool)
 408 {
 409         struct aesni_mb_qp *qp = NULL;
 410         struct aesni_mb_private *internals = dev->data->dev_private;
 411
 412         /* Free memory prior to re-allocation if needed. */
 413         if (dev->data->queue_pairs[qp_id] != NULL)
 414                 aesni_mb_pmd_qp_release(dev, qp_id);
 415
 416         /* Allocate the queue pair data structure. */
 417         qp = rte_zmalloc_socket("AES-NI PMD Queue Pair", sizeof(*qp),
 418                                         RTE_CACHE_LINE_SIZE, socket_id);
 419         if (qp == NULL)
 420                 return -ENOMEM;
 421
 422         qp->id = qp_id;
 423         dev->data->queue_pairs[qp_id] = qp;
 424
 425         if (aesni_mb_pmd_qp_set_unique_name(dev, qp))
 426                 goto qp_setup_cleanup;
 427
 428
 429         qp->op_fns = &job_ops[internals->vector_mode];
 430
 431         qp->ingress_queue = aesni_mb_pmd_qp_create_processed_ops_ring(qp,
 432                         "ingress", qp_conf->nb_descriptors, socket_id);
 433         if (qp->ingress_queue == NULL)
 434                 goto qp_setup_cleanup;
 435
 436         qp->sess_mp = session_pool;
 437
 438         memset(&qp->stats, 0, sizeof(qp->stats));
 439
 440         /* Initialise multi-buffer manager */
 441         (*qp->op_fns->job.init_mgr)(&qp->mb_mgr);
 442         return 0;
 443
 444 qp_setup_cleanup:
 445         if (qp)
 446                 rte_free(qp);
 447
 448         return -1;
 449 }
 450
 451 /** Start queue pair */
 452 static int
 453 aesni_mb_pmd_qp_start(__rte_unused struct rte_cryptodev *dev,
 454                 __rte_unused uint16_t queue_pair_id)
 455 {
 456         return -ENOTSUP;
 457 }
 458
 459 /** Stop queue pair */
 460 static int
 461 aesni_mb_pmd_qp_stop(__rte_unused struct rte_cryptodev *dev,
 462                 __rte_unused uint16_t queue_pair_id)
 463 {
 464         return -ENOTSUP;
 465 }
 466
 467 /** Return the number of allocated queue pairs */
 468 static uint32_t
 469 aesni_mb_pmd_qp_count(struct rte_cryptodev *dev)
 470 {
 471         return dev->data->nb_queue_pairs;
 472 }
 473
 474 /** Returns the size of the aesni multi-buffer session structure */
 475 static unsigned
 476 aesni_mb_pmd_session_get_size(struct rte_cryptodev *dev __rte_unused)
 477 {
 478         return sizeof(struct aesni_mb_session);
 479 }
 480
 481 /** Configure a aesni multi-buffer session from a crypto xform chain */
 482 static int
 483 aesni_mb_pmd_session_configure(struct rte_cryptodev *dev,
 484                 struct rte_crypto_sym_xform *xform,
 485                 struct rte_cryptodev_sym_session *sess,
 486                 struct rte_mempool *mempool)
 487 {
 488         void *sess_private_data;
 489         struct aesni_mb_private *internals = dev->data->dev_private;
 490
 491         if (unlikely(sess == NULL)) {
 492                 MB_LOG_ERR("invalid session struct");
 493                 return -1;
 494         }
 495
 496         if (rte_mempool_get(mempool, &sess_private_data)) {
 497                 CDEV_LOG_ERR(
 498                         "Couldn't get object from session mempool");
 499                 return -1;
 500         }
 501
 502         if (aesni_mb_set_session_parameters(&job_ops[internals->vector_mode],
 503                         sess_private_data, xform) != 0) {
 504                 MB_LOG_ERR("failed configure session parameters");
 505
 506                 /* Return session to mempool */
 507                 rte_mempool_put(mempool, sess_private_data);
 508                 return -1;
 509         }
 510
 511         set_session_private_data(sess, dev->driver_id,
 512                         sess_private_data);
 513
 514         return 0;
 515 }
 516
 517 /** Clear the memory of session so it doesn't leave key material behind */
 518 static void
 519 aesni_mb_pmd_session_clear(struct rte_cryptodev *dev,
 520                 struct rte_cryptodev_sym_session *sess)
 521 {
 522         uint8_t index = dev->driver_id;
 523         void *sess_priv = get_session_private_data(sess, index);
 524
 525         /* Zero out the whole structure */
 526         if (sess_priv) {
 527                 memset(sess_priv, 0, sizeof(struct aesni_mb_session));
 528                 struct rte_mempool *sess_mp = rte_mempool_from_obj(sess_priv);
 529                 set_session_private_data(sess, index, NULL);
 530                 rte_mempool_put(sess_mp, sess_priv);
 531         }
 532 }
 533
 534 struct rte_cryptodev_ops aesni_mb_pmd_ops = {
 535                 .dev_configure          = aesni_mb_pmd_config,
 536                 .dev_start              = aesni_mb_pmd_start,
 537                 .dev_stop               = aesni_mb_pmd_stop,
 538                 .dev_close              = aesni_mb_pmd_close,
 539
 540                 .stats_get              = aesni_mb_pmd_stats_get,
 541                 .stats_reset            = aesni_mb_pmd_stats_reset,
 542
 543                 .dev_infos_get          = aesni_mb_pmd_info_get,
 544
 545                 .queue_pair_setup       = aesni_mb_pmd_qp_setup,
 546                 .queue_pair_release     = aesni_mb_pmd_qp_release,
 547                 .queue_pair_start       = aesni_mb_pmd_qp_start,
 548                 .queue_pair_stop        = aesni_mb_pmd_qp_stop,
 549                 .queue_pair_count       = aesni_mb_pmd_qp_count,
 550
 551                 .session_get_size       = aesni_mb_pmd_session_get_size,
 552                 .session_configure      = aesni_mb_pmd_session_configure,
 553                 .session_clear          = aesni_mb_pmd_session_clear
 554 };
 555
 556 struct rte_cryptodev_ops *rte_aesni_mb_pmd_ops = &aesni_mb_pmd_ops;