4 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
5 * Copyright (c) 2016 NXP. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Freescale Semiconductor, Inc nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef _RTE_DPAA2_SEC_PMD_PRIVATE_H_
35 #define _RTE_DPAA2_SEC_PMD_PRIVATE_H_
38 #define MAX_DESC_SIZE 64
39 /** private data structure for each DPAA2_SEC device */
40 struct dpaa2_sec_dev_private {
41 void *mc_portal; /**< MC Portal for configuring this device */
42 void *hw; /**< Hardware handle for this device.Used by NADK framework */
43 struct rte_mempool *fle_pool; /* per device memory pool for FLE */
44 int32_t hw_id; /**< An unique ID of this device instance */
45 int32_t vfio_fd; /**< File descriptor received via VFIO */
46 uint16_t token; /**< Token required by DPxxx objects */
47 unsigned int max_nb_queue_pairs;
48 /**< Max number of queue pairs supported by device */
49 unsigned int max_nb_sessions;
50 /**< Max number of sessions supported by device */
54 struct dpaa2_queue rx_vq;
55 struct dpaa2_queue tx_vq;
67 /* SEC Flow Context Descriptor */
68 struct sec_flow_context {
70 uint16_t word0_sdid; /* 11-0 SDID */
71 uint16_t word0_res; /* 31-12 reserved */
74 uint8_t word1_sdl; /* 5-0 SDL */
77 uint8_t word1_bits_15_8; /* 11-8 CRID */
81 uint8_t word1_bits23_16; /* 16 EWS */
86 uint8_t word1_bits31_24; /* 24 RSC */
90 /* word 2 RFLC[31-0] */
91 uint32_t word2_rflc_31_0;
93 /* word 3 RFLC[63-32] */
94 uint32_t word3_rflc_63_32;
97 uint16_t word4_iicid; /* 15-0 IICID */
98 uint16_t word4_oicid; /* 31-16 OICID */
101 uint32_t word5_ofqid:24; /* 23-0 OFQID */
102 uint32_t word5_31_24:8;
109 uint32_t word6_oflc_31_0;
112 uint32_t word7_oflc_63_32;
114 /* Word 8-15 storage profiles */
115 uint16_t dl; /**< DataLength(correction) */
116 uint16_t reserved; /**< reserved */
117 uint16_t dhr; /**< DataHeadRoom(correction) */
118 uint16_t mode_bits; /**< mode bits */
119 uint16_t bpv0; /**< buffer pool0 valid */
120 uint16_t bpid0; /**< Bypass Memory Translation */
121 uint16_t bpv1; /**< buffer pool1 valid */
122 uint16_t bpid1; /**< Bypass Memory Translation */
123 uint64_t word_12_15[2]; /**< word 12-15 are reserved */
126 struct sec_flc_desc {
127 struct sec_flow_context flc;
128 uint32_t desc[MAX_DESC_SIZE];
132 struct rte_mempool *fle_pool; /* per device memory pool for FLE */
133 struct sec_flc_desc flc_desc[0];
136 enum dpaa2_sec_op_type {
137 DPAA2_SEC_NONE, /*!< No Cipher operations*/
138 DPAA2_SEC_CIPHER,/*!< CIPHER operations */
139 DPAA2_SEC_AUTH, /*!< Authentication Operations */
140 DPAA2_SEC_AEAD, /*!< AEAD (AES-GCM/CCM) type operations */
141 DPAA2_SEC_CIPHER_HASH, /*!< Authenticated Encryption with
144 DPAA2_SEC_HASH_CIPHER, /*!< Encryption with Authenticated
147 DPAA2_SEC_IPSEC, /*!< IPSEC protocol operations*/
148 DPAA2_SEC_PDCP, /*!< PDCP protocol operations*/
149 DPAA2_SEC_PKC, /*!< Public Key Cryptographic Operations */
153 struct dpaa2_sec_aead_ctxt {
154 uint16_t auth_only_len; /*!< Length of data for Auth only */
155 uint8_t auth_cipher_text; /**< Authenticate/cipher ordering */
158 typedef struct dpaa2_sec_session_entry {
161 uint8_t dir; /*!< Operation Direction */
162 enum rte_crypto_cipher_algorithm cipher_alg; /*!< Cipher Algorithm*/
163 enum rte_crypto_auth_algorithm auth_alg; /*!< Authentication Algorithm*/
166 uint8_t *data; /**< pointer to key data */
167 size_t length; /**< key length in bytes */
171 uint8_t *data; /**< pointer to key data */
172 size_t length; /**< key length in bytes */
175 uint8_t *data; /**< pointer to key data */
176 size_t length; /**< key length in bytes */
181 uint16_t length; /**< IV length in bytes */
182 uint16_t offset; /**< IV offset in bytes */
184 uint16_t digest_length;
187 struct dpaa2_sec_aead_ctxt aead_ctxt;
191 static const struct rte_cryptodev_capabilities dpaa2_sec_capabilities[] = {
193 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
195 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
197 .algo = RTE_CRYPTO_AUTH_MD5_HMAC,
215 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
217 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
219 .algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
237 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
239 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
241 .algo = RTE_CRYPTO_AUTH_SHA224_HMAC,
259 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
261 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
263 .algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
281 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
283 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
285 .algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
303 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
305 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
307 .algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
325 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
327 .xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,
329 .algo = RTE_CRYPTO_AEAD_AES_GCM,
355 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
357 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
359 .algo = RTE_CRYPTO_CIPHER_AES_CBC,
375 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
377 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
379 .algo = RTE_CRYPTO_CIPHER_AES_CTR,
395 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
397 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
399 .algo = RTE_CRYPTO_CIPHER_3DES_CBC,
415 RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
417 #endif /* _RTE_DPAA2_SEC_PMD_PRIVATE_H_ */