drivers/crypto/octeontx/otx_cryptodev_hw_access.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Cavium, Inc
   3  */
   4 #ifndef _OTX_CRYPTODEV_HW_ACCESS_H_
   5 #define _OTX_CRYPTODEV_HW_ACCESS_H_
   6
   7 #include <stdbool.h>
   8
   9 #include <rte_branch_prediction.h>
  10 #include <rte_cycles.h>
  11 #include <rte_io.h>
  12 #include <rte_memory.h>
  13 #include <rte_prefetch.h>
  14
  15 #include "cpt_common.h"
  16 #include "cpt_hw_types.h"
  17 #include "cpt_mcode_defines.h"
  18 #include "cpt_pmd_logs.h"
  19
  20 #define CPT_INTR_POLL_INTERVAL_MS       (50)
  21
  22 /* Default command queue length */
  23 #define DEFAULT_CMD_QCHUNKS             2
  24 #define DEFAULT_CMD_QCHUNK_SIZE         1023
  25 #define DEFAULT_CMD_QLEN \
  26                 (DEFAULT_CMD_QCHUNK_SIZE * DEFAULT_CMD_QCHUNKS)
  27
  28 #define CPT_CSR_REG_BASE(cpt)           ((cpt)->reg_base)
  29
  30 /* Read hw register */
  31 #define CPT_READ_CSR(__hw_addr, __offset) \
  32         rte_read64_relaxed((uint8_t *)__hw_addr + __offset)
  33
  34 /* Write hw register */
  35 #define CPT_WRITE_CSR(__hw_addr, __offset, __val) \
  36         rte_write64_relaxed((__val), ((uint8_t *)__hw_addr + __offset))
  37
  38 /* cpt instance */
  39 struct cpt_instance {
  40         uint32_t queue_id;
  41         uintptr_t rsvd;
  42         struct rte_mempool *sess_mp;
  43         struct rte_mempool *sess_mp_priv;
  44 };
  45
  46 struct command_chunk {
  47         /** 128-byte aligned real_vaddr */
  48         uint8_t *head;
  49         /** 128-byte aligned real_dma_addr */
  50         phys_addr_t dma_addr;
  51 };
  52
  53 /**
  54  * Command queue structure
  55  */
  56 struct command_queue {
  57         /** Command queue host write idx */
  58         uint32_t idx;
  59         /** Command queue chunk */
  60         uint32_t cchunk;
  61         /** Command queue head; instructions are inserted here */
  62         uint8_t *qhead;
  63         /** Command chunk list head */
  64         struct command_chunk chead[DEFAULT_CMD_QCHUNKS];
  65 };
  66
  67 /**
  68  * CPT VF device structure
  69  */
  70 struct cpt_vf {
  71         /** CPT instance */
  72         struct cpt_instance instance;
  73         /** Register start address */
  74         uint8_t *reg_base;
  75         /** Command queue information */
  76         struct command_queue cqueue;
  77         /** Pending queue information */
  78         struct pending_queue pqueue;
  79         /** Meta information per vf */
  80         struct cptvf_meta_info meta_info;
  81
  82         /** Below fields are accessed only in control path */
  83
  84         /** Env specific pdev representing the pci dev */
  85         void *pdev;
  86         /** Calculated queue size */
  87         uint32_t qsize;
  88         /** Device index (0...CPT_MAX_VQ_NUM)*/
  89         uint8_t  vfid;
  90         /** VF type of cpt_vf_type_t (SE_TYPE(2) or AE_TYPE(1) */
  91         uint8_t  vftype;
  92         /** VF group (0 - 8) */
  93         uint8_t  vfgrp;
  94         /** Operating node: Bits (46:44) in BAR0 address */
  95         uint8_t  node;
  96
  97         /** VF-PF mailbox communication */
  98
  99         /** Flag if acked */
 100         bool pf_acked;
 101         /** Flag if not acked */
 102         bool pf_nacked;
 103
 104         /** Device name */
 105         char dev_name[32];
 106 } __rte_cache_aligned;
 107
 108 /*
 109  * CPT Registers map for 81xx
 110  */
 111
 112 /* VF registers */
 113 #define CPTX_VQX_CTL(a, b)              (0x0000100ll + 0x1000000000ll * \
 114                                          ((a) & 0x0) + 0x100000ll * (b))
 115 #define CPTX_VQX_SADDR(a, b)            (0x0000200ll + 0x1000000000ll * \
 116                                          ((a) & 0x0) + 0x100000ll * (b))
 117 #define CPTX_VQX_DONE_WAIT(a, b)        (0x0000400ll + 0x1000000000ll * \
 118                                          ((a) & 0x0) + 0x100000ll * (b))
 119 #define CPTX_VQX_INPROG(a, b)           (0x0000410ll + 0x1000000000ll * \
 120                                          ((a) & 0x0) + 0x100000ll * (b))
 121 #define CPTX_VQX_DONE(a, b)             (0x0000420ll + 0x1000000000ll * \
 122                                          ((a) & 0x1) + 0x100000ll * (b))
 123 #define CPTX_VQX_DONE_ACK(a, b)         (0x0000440ll + 0x1000000000ll * \
 124                                          ((a) & 0x1) + 0x100000ll * (b))
 125 #define CPTX_VQX_DONE_INT_W1S(a, b)     (0x0000460ll + 0x1000000000ll * \
 126                                          ((a) & 0x1) + 0x100000ll * (b))
 127 #define CPTX_VQX_DONE_INT_W1C(a, b)     (0x0000468ll + 0x1000000000ll * \
 128                                          ((a) & 0x1) + 0x100000ll * (b))
 129 #define CPTX_VQX_DONE_ENA_W1S(a, b)     (0x0000470ll + 0x1000000000ll * \
 130                                          ((a) & 0x1) + 0x100000ll * (b))
 131 #define CPTX_VQX_DONE_ENA_W1C(a, b)     (0x0000478ll + 0x1000000000ll * \
 132                                          ((a) & 0x1) + 0x100000ll * (b))
 133 #define CPTX_VQX_MISC_INT(a, b)         (0x0000500ll + 0x1000000000ll * \
 134                                          ((a) & 0x1) + 0x100000ll * (b))
 135 #define CPTX_VQX_MISC_INT_W1S(a, b)     (0x0000508ll + 0x1000000000ll * \
 136                                          ((a) & 0x1) + 0x100000ll * (b))
 137 #define CPTX_VQX_MISC_ENA_W1S(a, b)     (0x0000510ll + 0x1000000000ll * \
 138                                          ((a) & 0x1) + 0x100000ll * (b))
 139 #define CPTX_VQX_MISC_ENA_W1C(a, b)     (0x0000518ll + 0x1000000000ll * \
 140                                          ((a) & 0x1) + 0x100000ll * (b))
 141 #define CPTX_VQX_DOORBELL(a, b)         (0x0000600ll + 0x1000000000ll * \
 142                                          ((a) & 0x1) + 0x100000ll * (b))
 143 #define CPTX_VFX_PF_MBOXX(a, b, c)      (0x0001000ll + 0x1000000000ll * \
 144                                          ((a) & 0x1) + 0x100000ll * (b) + \
 145                                          8ll * ((c) & 0x1))
 146
 147 /* VF HAL functions */
 148
 149 void
 150 otx_cpt_poll_misc(struct cpt_vf *cptvf);
 151
 152 int
 153 otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name);
 154
 155 int
 156 otx_cpt_deinit_device(void *dev);
 157
 158 int
 159 otx_cpt_get_resource(void *dev, uint8_t group, struct cpt_instance **instance);
 160
 161 int
 162 otx_cpt_put_resource(struct cpt_instance *instance);
 163
 164 int
 165 otx_cpt_start_device(void *cptvf);
 166
 167 void
 168 otx_cpt_stop_device(void *cptvf);
 169
 170 /* Write to VQX_DOORBELL register
 171  */
 172 static __rte_always_inline void
 173 otx_cpt_write_vq_doorbell(struct cpt_vf *cptvf, uint32_t val)
 174 {
 175         cptx_vqx_doorbell_t vqx_dbell;
 176
 177         vqx_dbell.u = 0;
 178         vqx_dbell.s.dbell_cnt = val * 8; /* Num of Instructions * 8 words */
 179         CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
 180                       CPTX_VQX_DOORBELL(0, 0), vqx_dbell.u);
 181 }
 182
 183 static __rte_always_inline uint32_t
 184 otx_cpt_read_vq_doorbell(struct cpt_vf *cptvf)
 185 {
 186         cptx_vqx_doorbell_t vqx_dbell;
 187
 188         vqx_dbell.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
 189                                    CPTX_VQX_DOORBELL(0, 0));
 190         return vqx_dbell.s.dbell_cnt;
 191 }
 192
 193 static __rte_always_inline void
 194 otx_cpt_ring_dbell(struct cpt_instance *instance, uint16_t count)
 195 {
 196         struct cpt_vf *cptvf = (struct cpt_vf *)instance;
 197         /* Memory barrier to flush pending writes */
 198         rte_smp_wmb();
 199         otx_cpt_write_vq_doorbell(cptvf, count);
 200 }
 201
 202 static __rte_always_inline void *
 203 get_cpt_inst(struct command_queue *cqueue)
 204 {
 205         CPT_LOG_DP_DEBUG("CPT queue idx %u\n", cqueue->idx);
 206         return &cqueue->qhead[cqueue->idx * CPT_INST_SIZE];
 207 }
 208
 209 static __rte_always_inline void
 210 fill_cpt_inst(struct cpt_instance *instance, void *req)
 211 {
 212         struct command_queue *cqueue;
 213         cpt_inst_s_t *cpt_ist_p;
 214         struct cpt_vf *cptvf = (struct cpt_vf *)instance;
 215         struct cpt_request_info *user_req = (struct cpt_request_info *)req;
 216         cqueue = &cptvf->cqueue;
 217         cpt_ist_p = get_cpt_inst(cqueue);
 218         rte_prefetch_non_temporal(cpt_ist_p);
 219
 220         /* EI0, EI1, EI2, EI3 are already prepared */
 221         /* HW W0 */
 222         cpt_ist_p->u[0] = 0;
 223         /* HW W1 */
 224         cpt_ist_p->s8x.res_addr = user_req->comp_baddr;
 225         /* HW W2 */
 226         cpt_ist_p->u[2] = 0;
 227         /* HW W3 */
 228         cpt_ist_p->s8x.wq_ptr = 0;
 229
 230         /* MC EI0 */
 231         cpt_ist_p->s8x.ei0 = user_req->ist.ei0;
 232         /* MC EI1 */
 233         cpt_ist_p->s8x.ei1 = user_req->ist.ei1;
 234         /* MC EI2 */
 235         cpt_ist_p->s8x.ei2 = user_req->ist.ei2;
 236         /* MC EI3 */
 237         cpt_ist_p->s8x.ei3 = user_req->ist.ei3;
 238 }
 239
 240 static __rte_always_inline void
 241 mark_cpt_inst(struct cpt_instance *instance)
 242 {
 243         struct cpt_vf *cptvf = (struct cpt_vf *)instance;
 244         struct command_queue *queue = &cptvf->cqueue;
 245         if (unlikely(++queue->idx >= DEFAULT_CMD_QCHUNK_SIZE)) {
 246                 uint32_t cchunk = queue->cchunk;
 247                 MOD_INC(cchunk, DEFAULT_CMD_QCHUNKS);
 248                 queue->qhead = queue->chead[cchunk].head;
 249                 queue->idx = 0;
 250                 queue->cchunk = cchunk;
 251         }
 252 }
 253
 254 static __rte_always_inline uint8_t
 255 check_nb_command_id(struct cpt_request_info *user_req,
 256                 struct cpt_instance *instance)
 257 {
 258         uint8_t ret = ERR_REQ_PENDING;
 259         struct cpt_vf *cptvf = (struct cpt_vf *)instance;
 260         volatile cpt_res_s_t *cptres;
 261
 262         cptres = (volatile cpt_res_s_t *)user_req->completion_addr;
 263
 264         if (unlikely(cptres->s8x.compcode == CPT_8X_COMP_E_NOTDONE)) {
 265                 /*
 266                  * Wait for some time for this command to get completed
 267                  * before timing out
 268                  */
 269                 if (rte_get_timer_cycles() < user_req->time_out)
 270                         return ret;
 271                 /*
 272                  * TODO: See if alternate caddr can be used to not loop
 273                  * longer than needed.
 274                  */
 275                 if ((cptres->s8x.compcode == CPT_8X_COMP_E_NOTDONE) &&
 276                     (user_req->extra_time < TIME_IN_RESET_COUNT)) {
 277                         user_req->extra_time++;
 278                         return ret;
 279                 }
 280
 281                 if (cptres->s8x.compcode != CPT_8X_COMP_E_NOTDONE)
 282                         goto complete;
 283
 284                 ret = ERR_REQ_TIMEOUT;
 285                 CPT_LOG_DP_ERR("Request %p timedout", user_req);
 286                 otx_cpt_poll_misc(cptvf);
 287                 goto exit;
 288         }
 289
 290 complete:
 291         if (likely(cptres->s8x.compcode == CPT_8X_COMP_E_GOOD)) {
 292                 ret = 0; /* success */
 293                 if (unlikely((uint8_t)*user_req->alternate_caddr)) {
 294                         ret = (uint8_t)*user_req->alternate_caddr;
 295                         CPT_LOG_DP_ERR("Request %p : failed with microcode"
 296                                 " error, MC completion code : 0x%x", user_req,
 297                                 ret);
 298                 }
 299                 CPT_LOG_DP_DEBUG("MC status %.8x\n",
 300                            *((volatile uint32_t *)user_req->alternate_caddr));
 301                 CPT_LOG_DP_DEBUG("HW status %.8x\n",
 302                            *((volatile uint32_t *)user_req->completion_addr));
 303         } else if ((cptres->s8x.compcode == CPT_8X_COMP_E_SWERR) ||
 304                    (cptres->s8x.compcode == CPT_8X_COMP_E_FAULT)) {
 305                 ret = (uint8_t)*user_req->alternate_caddr;
 306                 if (!ret)
 307                         ret = ERR_BAD_ALT_CCODE;
 308                 CPT_LOG_DP_DEBUG("Request %p : failed with %s : err code :%x",
 309                            user_req,
 310                            (cptres->s8x.compcode == CPT_8X_COMP_E_FAULT) ?
 311                            "DMA Fault" : "Software error", ret);
 312         } else {
 313                 CPT_LOG_DP_ERR("Request %p : unexpected completion code %d",
 314                            user_req, cptres->s8x.compcode);
 315                 ret = (uint8_t)*user_req->alternate_caddr;
 316         }
 317
 318 exit:
 319         return ret;
 320 }
 321
 322 #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */