drivers/crypto/qat/qat_crypto.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *       * Redistributions of source code must retain the above copyright
  12  *         notice, this list of conditions and the following disclaimer.
  13  *       * Redistributions in binary form must reproduce the above copyright
  14  *         notice, this list of conditions and the following disclaimer in
  15  *         the documentation and/or other materials provided with the
  16  *         distribution.
  17  *       * Neither the name of Intel Corporation nor the names of its
  18  *         contributors may be used to endorse or promote products derived
  19  *         from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <strings.h>
  37 #include <string.h>
  38 #include <inttypes.h>
  39 #include <errno.h>
  40 #include <sys/queue.h>
  41 #include <stdarg.h>
  42
  43 #include <rte_common.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_memory.h>
  47 #include <rte_memzone.h>
  48 #include <rte_tailq.h>
  49 #include <rte_ether.h>
  50 #include <rte_malloc.h>
  51 #include <rte_launch.h>
  52 #include <rte_eal.h>
  53 #include <rte_per_lcore.h>
  54 #include <rte_lcore.h>
  55 #include <rte_atomic.h>
  56 #include <rte_branch_prediction.h>
  57 #include <rte_mempool.h>
  58 #include <rte_mbuf.h>
  59 #include <rte_string_fns.h>
  60 #include <rte_spinlock.h>
  61 #include <rte_hexdump.h>
  62
  63 #include "qat_logs.h"
  64 #include "qat_algs.h"
  65 #include "qat_crypto.h"
  66 #include "adf_transport_access_macros.h"
  67
  68 #define BYTE_LENGTH    8
  69
  70 static const struct rte_cryptodev_capabilities qat_pmd_capabilities[] = {
  71         {       /* SHA1 HMAC */
  72                 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
  73                 {.sym = {
  74                         .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
  75                         {.auth = {
  76                                 .algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
  77                                 .block_size = 64,
  78                                 .key_size = {
  79                                         .min = 64,
  80                                         .max = 64,
  81                                         .increment = 0
  82                                 },
  83                                 .digest_size = {
  84                                         .min = 20,
  85                                         .max = 20,
  86                                         .increment = 0
  87                                 },
  88                                 .aad_size = { 0 }
  89                         }, }
  90                 }, }
  91         },
  92         {       /* SHA224 HMAC */
  93                 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
  94                 {.sym = {
  95                         .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
  96                         {.auth = {
  97                                 .algo = RTE_CRYPTO_AUTH_SHA224_HMAC,
  98                                 .block_size = 64,
  99                                         .key_size = {
 100                                         .min = 64,
 101                                         .max = 64,
 102                                         .increment = 0
 103                                 },
 104                                 .digest_size = {
 105                                         .min = 28,
 106                                         .max = 28,
 107                                         .increment = 0
 108                                 },
 109                                 .aad_size = { 0 }
 110                         }, }
 111                 }, }
 112         },
 113         {       /* SHA256 HMAC */
 114                 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 115                 {.sym = {
 116                         .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
 117                         {.auth = {
 118                                 .algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
 119                                 .block_size = 64,
 120                                 .key_size = {
 121                                         .min = 64,
 122                                         .max = 64,
 123                                         .increment = 0
 124                                 },
 125                                 .digest_size = {
 126                                         .min = 32,
 127                                         .max = 32,
 128                                         .increment = 0
 129                                 },
 130                                 .aad_size = { 0 }
 131                         }, }
 132                 }, }
 133         },
 134         {       /* SHA384 HMAC */
 135                 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 136                 {.sym = {
 137                         .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
 138                         {.auth = {
 139                                 .algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
 140                                 .block_size = 64,
 141                                 .key_size = {
 142                                         .min = 128,
 143                                         .max = 128,
 144                                         .increment = 0
 145                                 },
 146                                 .digest_size = {
 147                                         .min = 48,
 148                                         .max = 48,
 149                                         .increment = 0
 150                                         },
 151                                 .aad_size = { 0 }
 152                         }, }
 153                 }, }
 154         },
 155         {       /* SHA512 HMAC */
 156                 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 157                 {.sym = {
 158                         .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
 159                         {.auth = {
 160                                 .algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
 161                                 .block_size = 128,
 162                                 .key_size = {
 163                                         .min = 128,
 164                                         .max = 128,
 165                                         .increment = 0
 166                                 },
 167                                 .digest_size = {
 168                                         .min = 64,
 169                                         .max = 64,
 170                                         .increment = 0
 171                                 },
 172                                 .aad_size = { 0 }
 173                         }, }
 174                 }, }
 175         },
 176         {       /* MD5 HMAC */
 177                 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 178                 {.sym = {
 179                         .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
 180                         {.auth = {
 181                                 .algo = RTE_CRYPTO_AUTH_MD5_HMAC,
 182                                 .block_size = 64,
 183                                 .key_size = {
 184                                         .min = 8,
 185                                         .max = 64,
 186                                         .increment = 8
 187                                 },
 188                                 .digest_size = {
 189                                         .min = 16,
 190                                         .max = 16,
 191                                         .increment = 0
 192                                 },
 193                                 .aad_size = { 0 }
 194                         }, }
 195                 }, }
 196         },
 197         {       /* AES XCBC MAC */
 198                 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 199                 {.sym = {
 200                         .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
 201                         {.auth = {
 202                                 .algo = RTE_CRYPTO_AUTH_AES_XCBC_MAC,
 203                                 .block_size = 16,
 204                                 .key_size = {
 205                                         .min = 16,
 206                                         .max = 16,
 207                                         .increment = 0
 208                                 },
 209                                 .digest_size = {
 210                                         .min = 16,
 211                                         .max = 16,
 212                                         .increment = 0
 213                                 },
 214                                 .aad_size = { 0 }
 215                         }, }
 216                 }, }
 217         },
 218         {       /* AES GCM (AUTH) */
 219                 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 220                 {.sym = {
 221                         .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
 222                         {.auth = {
 223                                 .algo = RTE_CRYPTO_AUTH_AES_GCM,
 224                                 .block_size = 16,
 225                                 .key_size = {
 226                                         .min = 16,
 227                                         .max = 32,
 228                                         .increment = 8
 229                                 },
 230                                 .digest_size = {
 231                                         .min = 8,
 232                                         .max = 16,
 233                                         .increment = 4
 234                                 },
 235                                 .aad_size = {
 236                                         .min = 8,
 237                                         .max = 12,
 238                                         .increment = 4
 239                                 }
 240                         }, }
 241                 }, }
 242         },
 243         {       /* SNOW3G (UIA2) */
 244                 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 245                 {.sym = {
 246                         .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
 247                         {.auth = {
 248                                 .algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,
 249                                 .block_size = 16,
 250                                 .key_size = {
 251                                         .min = 16,
 252                                         .max = 16,
 253                                         .increment = 0
 254                                 },
 255                                 .digest_size = {
 256                                         .min = 4,
 257                                         .max = 4,
 258                                         .increment = 0
 259                                 },
 260                                 .aad_size = {
 261                                         .min = 16,
 262                                         .max = 16,
 263                                         .increment = 0
 264                                 }
 265                         }, }
 266                 }, }
 267         },
 268         {       /* AES GCM (CIPHER) */
 269                 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 270                 {.sym = {
 271                         .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
 272                         {.cipher = {
 273                                 .algo = RTE_CRYPTO_CIPHER_AES_GCM,
 274                                 .block_size = 16,
 275                                 .key_size = {
 276                                         .min = 16,
 277                                         .max = 32,
 278                                         .increment = 8
 279                                 },
 280                                 .iv_size = {
 281                                         .min = 16,
 282                                         .max = 16,
 283                                         .increment = 0
 284                                 }
 285                         }, }
 286                 }, }
 287         },
 288         {       /* AES CBC */
 289                 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 290                 {.sym = {
 291                         .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
 292                         {.cipher = {
 293                                 .algo = RTE_CRYPTO_CIPHER_AES_CBC,
 294                                 .block_size = 16,
 295                                 .key_size = {
 296                                         .min = 16,
 297                                         .max = 32,
 298                                         .increment = 8
 299                                 },
 300                                 .iv_size = {
 301                                         .min = 16,
 302                                         .max = 16,
 303                                         .increment = 0
 304                                 }
 305                         }, }
 306                 }, }
 307         },
 308         {       /* SNOW3G (UEA2) */
 309                 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 310                 {.sym = {
 311                         .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
 312                         {.cipher = {
 313                                 .algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,
 314                                 .block_size = 16,
 315                                 .key_size = {
 316                                         .min = 16,
 317                                         .max = 16,
 318                                         .increment = 0
 319                                 },
 320                                 .iv_size = {
 321                                         .min = 16,
 322                                         .max = 16,
 323                                         .increment = 0
 324                                 }
 325                         }, }
 326                 }, }
 327         },
 328         {       /* AES CTR */
 329                 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 330                 {.sym = {
 331                         .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
 332                         {.cipher = {
 333                                 .algo = RTE_CRYPTO_CIPHER_AES_CTR,
 334                                 .block_size = 16,
 335                                 .key_size = {
 336                                         .min = 16,
 337                                         .max = 32,
 338                                         .increment = 8
 339                                 },
 340                                 .iv_size = {
 341                                         .min = 16,
 342                                         .max = 16,
 343                                         .increment = 0
 344                                 }
 345                         }, }
 346                 }, }
 347         },
 348         {       /* NULL (AUTH) */
 349                 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 350                 {.sym = {
 351                         .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
 352                         {.auth = {
 353                                 .algo = RTE_CRYPTO_AUTH_NULL,
 354                                 .block_size = 1,
 355                                 .key_size = {
 356                                         .min = 0,
 357                                         .max = 0,
 358                                         .increment = 0
 359                                 },
 360                                 .digest_size = {
 361                                         .min = 0,
 362                                         .max = 0,
 363                                         .increment = 0
 364                                 },
 365                                 .aad_size = { 0 }
 366                         }, },
 367                 }, },
 368         },
 369         {       /* NULL (CIPHER) */
 370                 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 371                 {.sym = {
 372                         .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
 373                         {.cipher = {
 374                                 .algo = RTE_CRYPTO_CIPHER_NULL,
 375                                 .block_size = 1,
 376                                 .key_size = {
 377                                         .min = 0,
 378                                         .max = 0,
 379                                         .increment = 0
 380                                 },
 381                                 .iv_size = {
 382                                         .min = 0,
 383                                         .max = 0,
 384                                         .increment = 0
 385                                 }
 386                         }, },
 387                 }, }
 388         },
 389         RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
 390 };
 391
 392 static inline uint32_t
 393 adf_modulo(uint32_t data, uint32_t shift);
 394
 395 static inline int
 396 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg);
 397
 398 void qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
 399                 void *session)
 400 {
 401         struct qat_session *sess = session;
 402         phys_addr_t cd_paddr;
 403
 404         PMD_INIT_FUNC_TRACE();
 405         if (session) {
 406                 cd_paddr = sess->cd_paddr;
 407                 memset(sess, 0, qat_crypto_sym_get_session_private_size(dev));
 408                 sess->cd_paddr = cd_paddr;
 409         } else
 410                 PMD_DRV_LOG(ERR, "NULL session");
 411 }
 412
 413 static int
 414 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
 415 {
 416         /* Cipher Only */
 417         if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
 418                 return ICP_QAT_FW_LA_CMD_CIPHER;
 419
 420         /* Authentication Only */
 421         if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
 422                 return ICP_QAT_FW_LA_CMD_AUTH;
 423
 424         if (xform->next == NULL)
 425                 return -1;
 426
 427         /* Cipher then Authenticate */
 428         if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
 429                         xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
 430                 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
 431
 432         /* Authenticate then Cipher */
 433         if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
 434                         xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
 435                 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
 436
 437         return -1;
 438 }
 439
 440 static struct rte_crypto_auth_xform *
 441 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
 442 {
 443         do {
 444                 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
 445                         return &xform->auth;
 446
 447                 xform = xform->next;
 448         } while (xform);
 449
 450         return NULL;
 451 }
 452
 453 static struct rte_crypto_cipher_xform *
 454 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
 455 {
 456         do {
 457                 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
 458                         return &xform->cipher;
 459
 460                 xform = xform->next;
 461         } while (xform);
 462
 463         return NULL;
 464 }
 465 void *
 466 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
 467                 struct rte_crypto_sym_xform *xform, void *session_private)
 468 {
 469         struct qat_pmd_private *internals = dev->data->dev_private;
 470
 471         struct qat_session *session = session_private;
 472
 473         struct rte_crypto_cipher_xform *cipher_xform = NULL;
 474
 475         /* Get cipher xform from crypto xform chain */
 476         cipher_xform = qat_get_cipher_xform(xform);
 477
 478         switch (cipher_xform->algo) {
 479         case RTE_CRYPTO_CIPHER_AES_CBC:
 480                 if (qat_alg_validate_aes_key(cipher_xform->key.length,
 481                                 &session->qat_cipher_alg) != 0) {
 482                         PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
 483                         goto error_out;
 484                 }
 485                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 486                 break;
 487         case RTE_CRYPTO_CIPHER_AES_GCM:
 488                 if (qat_alg_validate_aes_key(cipher_xform->key.length,
 489                                 &session->qat_cipher_alg) != 0) {
 490                         PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
 491                         goto error_out;
 492                 }
 493                 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
 494                 break;
 495         case RTE_CRYPTO_CIPHER_AES_CTR:
 496                 if (qat_alg_validate_aes_key(cipher_xform->key.length,
 497                                 &session->qat_cipher_alg) != 0) {
 498                         PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
 499                         goto error_out;
 500                 }
 501                 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
 502                 break;
 503         case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
 504                 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
 505                                         &session->qat_cipher_alg) != 0) {
 506                         PMD_DRV_LOG(ERR, "Invalid SNOW3G cipher key size");
 507                         goto error_out;
 508                 }
 509                 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
 510                 break;
 511         case RTE_CRYPTO_CIPHER_NULL:
 512                 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
 513                 break;
 514         case RTE_CRYPTO_CIPHER_3DES_ECB:
 515         case RTE_CRYPTO_CIPHER_3DES_CBC:
 516         case RTE_CRYPTO_CIPHER_AES_ECB:
 517         case RTE_CRYPTO_CIPHER_AES_CCM:
 518         case RTE_CRYPTO_CIPHER_KASUMI_F8:
 519                 PMD_DRV_LOG(ERR, "Crypto: Unsupported Cipher alg %u",
 520                                 cipher_xform->algo);
 521                 goto error_out;
 522         default:
 523                 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
 524                                 cipher_xform->algo);
 525                 goto error_out;
 526         }
 527
 528         if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
 529                 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
 530         else
 531                 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
 532
 533         if (qat_alg_aead_session_create_content_desc_cipher(session,
 534                                                 cipher_xform->key.data,
 535                                                 cipher_xform->key.length))
 536                 goto error_out;
 537
 538         return session;
 539
 540 error_out:
 541         rte_mempool_put(internals->sess_mp, session);
 542         return NULL;
 543 }
 544
 545
 546 void *
 547 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
 548                 struct rte_crypto_sym_xform *xform, void *session_private)
 549 {
 550         struct qat_pmd_private *internals = dev->data->dev_private;
 551
 552         struct qat_session *session = session_private;
 553
 554         int qat_cmd_id;
 555
 556         PMD_INIT_FUNC_TRACE();
 557
 558         /* Get requested QAT command id */
 559         qat_cmd_id = qat_get_cmd_id(xform);
 560         if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
 561                 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
 562                 goto error_out;
 563         }
 564         session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
 565         switch (session->qat_cmd) {
 566         case ICP_QAT_FW_LA_CMD_CIPHER:
 567         session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
 568                 break;
 569         case ICP_QAT_FW_LA_CMD_AUTH:
 570         session = qat_crypto_sym_configure_session_auth(dev, xform, session);
 571                 break;
 572         case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
 573         session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
 574         session = qat_crypto_sym_configure_session_auth(dev, xform, session);
 575                 break;
 576         case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
 577         session = qat_crypto_sym_configure_session_auth(dev, xform, session);
 578         session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
 579                 break;
 580         case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
 581         case ICP_QAT_FW_LA_CMD_TRNG_TEST:
 582         case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
 583         case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
 584         case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
 585         case ICP_QAT_FW_LA_CMD_MGF1:
 586         case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
 587         case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
 588         case ICP_QAT_FW_LA_CMD_DELIMITER:
 589         PMD_DRV_LOG(ERR, "Unsupported Service %u",
 590                 session->qat_cmd);
 591                 goto error_out;
 592         default:
 593         PMD_DRV_LOG(ERR, "Unsupported Service %u",
 594                 session->qat_cmd);
 595                 goto error_out;
 596         }
 597         return session;
 598
 599 error_out:
 600         rte_mempool_put(internals->sess_mp, session);
 601         return NULL;
 602 }
 603
 604 struct qat_session *
 605 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
 606                                 struct rte_crypto_sym_xform *xform,
 607                                 struct qat_session *session_private)
 608 {
 609
 610         struct qat_pmd_private *internals = dev->data->dev_private;
 611         struct qat_session *session = session_private;
 612         struct rte_crypto_auth_xform *auth_xform = NULL;
 613         struct rte_crypto_cipher_xform *cipher_xform = NULL;
 614         auth_xform = qat_get_auth_xform(xform);
 615
 616         switch (auth_xform->algo) {
 617         case RTE_CRYPTO_AUTH_SHA1_HMAC:
 618                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
 619                 break;
 620         case RTE_CRYPTO_AUTH_SHA224_HMAC:
 621                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
 622                 break;
 623         case RTE_CRYPTO_AUTH_SHA256_HMAC:
 624                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
 625                 break;
 626         case RTE_CRYPTO_AUTH_SHA384_HMAC:
 627                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;
 628                 break;
 629         case RTE_CRYPTO_AUTH_SHA512_HMAC:
 630                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
 631                 break;
 632         case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
 633                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
 634                 break;
 635         case RTE_CRYPTO_AUTH_AES_GCM:
 636                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
 637                 break;
 638         case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
 639                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
 640                 break;
 641         case RTE_CRYPTO_AUTH_MD5_HMAC:
 642                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
 643                 break;
 644         case RTE_CRYPTO_AUTH_NULL:
 645                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;
 646                 break;
 647         case RTE_CRYPTO_AUTH_SHA1:
 648         case RTE_CRYPTO_AUTH_SHA256:
 649         case RTE_CRYPTO_AUTH_SHA512:
 650         case RTE_CRYPTO_AUTH_SHA224:
 651         case RTE_CRYPTO_AUTH_SHA384:
 652         case RTE_CRYPTO_AUTH_MD5:
 653         case RTE_CRYPTO_AUTH_AES_CCM:
 654         case RTE_CRYPTO_AUTH_AES_GMAC:
 655         case RTE_CRYPTO_AUTH_KASUMI_F9:
 656         case RTE_CRYPTO_AUTH_AES_CMAC:
 657         case RTE_CRYPTO_AUTH_AES_CBC_MAC:
 658         case RTE_CRYPTO_AUTH_ZUC_EIA3:
 659                 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
 660                                 auth_xform->algo);
 661                 goto error_out;
 662         default:
 663                 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
 664                                 auth_xform->algo);
 665                 goto error_out;
 666         }
 667         cipher_xform = qat_get_cipher_xform(xform);
 668
 669         if ((session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) ||
 670                         (session->qat_hash_alg ==
 671                                 ICP_QAT_HW_AUTH_ALGO_GALOIS_64))  {
 672                 if (qat_alg_aead_session_create_content_desc_auth(session,
 673                                 cipher_xform->key.data,
 674                                 cipher_xform->key.length,
 675                                 auth_xform->add_auth_data_length,
 676                                 auth_xform->digest_length,
 677                                 auth_xform->op))
 678                         goto error_out;
 679         } else {
 680                 if (qat_alg_aead_session_create_content_desc_auth(session,
 681                                 auth_xform->key.data,
 682                                 auth_xform->key.length,
 683                                 auth_xform->add_auth_data_length,
 684                                 auth_xform->digest_length,
 685                                 auth_xform->op))
 686                         goto error_out;
 687         }
 688         return session;
 689
 690 error_out:
 691         if (internals->sess_mp != NULL)
 692                 rte_mempool_put(internals->sess_mp, session);
 693         return NULL;
 694 }
 695
 696 unsigned qat_crypto_sym_get_session_private_size(
 697                 struct rte_cryptodev *dev __rte_unused)
 698 {
 699         return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
 700 }
 701
 702
 703 uint16_t
 704 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
 705                 uint16_t nb_ops)
 706 {
 707         register struct qat_queue *queue;
 708         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 709         register uint32_t nb_ops_sent = 0;
 710         register struct rte_crypto_op **cur_op = ops;
 711         register int ret;
 712         uint16_t nb_ops_possible = nb_ops;
 713         register uint8_t *base_addr;
 714         register uint32_t tail;
 715         int overflow;
 716
 717         if (unlikely(nb_ops == 0))
 718                 return 0;
 719
 720         /* read params used a lot in main loop into registers */
 721         queue = &(tmp_qp->tx_q);
 722         base_addr = (uint8_t *)queue->base_addr;
 723         tail = queue->tail;
 724
 725         /* Find how many can actually fit on the ring */
 726         overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
 727                                 - queue->max_inflights;
 728         if (overflow > 0) {
 729                 rte_atomic16_sub(&tmp_qp->inflights16, overflow);
 730                 nb_ops_possible = nb_ops - overflow;
 731                 if (nb_ops_possible == 0)
 732                         return 0;
 733         }
 734
 735         while (nb_ops_sent != nb_ops_possible) {
 736                 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail);
 737                 if (ret != 0) {
 738                         tmp_qp->stats.enqueue_err_count++;
 739                         if (nb_ops_sent == 0)
 740                                 return 0;
 741                         goto kick_tail;
 742                 }
 743
 744                 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
 745                 nb_ops_sent++;
 746                 cur_op++;
 747         }
 748 kick_tail:
 749         WRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,
 750                         queue->hw_queue_number, tail);
 751         queue->tail = tail;
 752         tmp_qp->stats.enqueued_count += nb_ops_sent;
 753         return nb_ops_sent;
 754 }
 755
 756 uint16_t
 757 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
 758                 uint16_t nb_ops)
 759 {
 760         struct qat_queue *queue;
 761         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 762         uint32_t msg_counter = 0;
 763         struct rte_crypto_op *rx_op;
 764         struct icp_qat_fw_comn_resp *resp_msg;
 765
 766         queue = &(tmp_qp->rx_q);
 767         resp_msg = (struct icp_qat_fw_comn_resp *)
 768                         ((uint8_t *)queue->base_addr + queue->head);
 769
 770         while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
 771                         msg_counter != nb_ops) {
 772                 rx_op = (struct rte_crypto_op *)(uintptr_t)
 773                                 (resp_msg->opaque_data);
 774
 775 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
 776                 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
 777                                 sizeof(struct icp_qat_fw_comn_resp));
 778 #endif
 779                 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
 780                                 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
 781                                         resp_msg->comn_hdr.comn_status)) {
 782                         rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
 783                 } else {
 784                         rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
 785                 }
 786                 *(uint32_t *)resp_msg = ADF_RING_EMPTY_SIG;
 787                 queue->head = adf_modulo(queue->head +
 788                                 queue->msg_size,
 789                                 ADF_RING_SIZE_MODULO(queue->queue_size));
 790                 resp_msg = (struct icp_qat_fw_comn_resp *)
 791                                         ((uint8_t *)queue->base_addr +
 792                                                         queue->head);
 793                 *ops = rx_op;
 794                 ops++;
 795                 msg_counter++;
 796         }
 797         if (msg_counter > 0) {
 798                 WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
 799                                         queue->hw_bundle_number,
 800                                         queue->hw_queue_number, queue->head);
 801                 rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
 802                 tmp_qp->stats.dequeued_count += msg_counter;
 803         }
 804         return msg_counter;
 805 }
 806
 807 static inline int
 808 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg)
 809 {
 810         struct qat_session *ctx;
 811         struct icp_qat_fw_la_cipher_req_params *cipher_param;
 812         struct icp_qat_fw_la_auth_req_params *auth_param;
 813         register struct icp_qat_fw_la_bulk_req *qat_req;
 814
 815 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 816         if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
 817                 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
 818                                 "operation requests, op (%p) is not a "
 819                                 "symmetric operation.", op);
 820                 return -EINVAL;
 821         }
 822 #endif
 823         if (unlikely(op->sym->sess_type == RTE_CRYPTO_SYM_OP_SESSIONLESS)) {
 824                 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
 825                                 " requests, op (%p) is sessionless.", op);
 826                 return -EINVAL;
 827         }
 828
 829         if (unlikely(op->sym->session->dev_type != RTE_CRYPTODEV_QAT_SYM_PMD)) {
 830                 PMD_DRV_LOG(ERR, "Session was not created for this device");
 831                 return -EINVAL;
 832         }
 833
 834         ctx = (struct qat_session *)op->sym->session->_private;
 835         qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
 836         rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
 837         qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
 838
 839         qat_req->comn_mid.dst_length =
 840                 qat_req->comn_mid.src_length =
 841                                 rte_pktmbuf_data_len(op->sym->m_src);
 842
 843         qat_req->comn_mid.dest_data_addr =
 844                 qat_req->comn_mid.src_data_addr =
 845                             rte_pktmbuf_mtophys(op->sym->m_src);
 846
 847         if (unlikely(op->sym->m_dst != NULL)) {
 848                 qat_req->comn_mid.dest_data_addr =
 849                                 rte_pktmbuf_mtophys(op->sym->m_dst);
 850                 qat_req->comn_mid.dst_length =
 851                                 rte_pktmbuf_data_len(op->sym->m_dst);
 852         }
 853
 854         cipher_param = (void *)&qat_req->serv_specif_rqpars;
 855         auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
 856
 857         cipher_param->cipher_length = op->sym->cipher.data.length;
 858         cipher_param->cipher_offset = op->sym->cipher.data.offset;
 859         if (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) {
 860                 if (unlikely((cipher_param->cipher_length % BYTE_LENGTH != 0) ||
 861                                 (cipher_param->cipher_offset
 862                                         % BYTE_LENGTH != 0))) {
 863                         PMD_DRV_LOG(ERR, " For Snow3g, QAT PMD only "
 864                                 "supports byte aligned values");
 865                         op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
 866                         return -EINVAL;
 867                 }
 868                 cipher_param->cipher_length >>= 3;
 869                 cipher_param->cipher_offset >>= 3;
 870         }
 871
 872         if (op->sym->cipher.iv.length && (op->sym->cipher.iv.length <=
 873                         sizeof(cipher_param->u.cipher_IV_array))) {
 874                 rte_memcpy(cipher_param->u.cipher_IV_array,
 875                                 op->sym->cipher.iv.data,
 876                                 op->sym->cipher.iv.length);
 877         } else {
 878                 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
 879                                 qat_req->comn_hdr.serv_specif_flags,
 880                                 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
 881                 cipher_param->u.s.cipher_IV_ptr = op->sym->cipher.iv.phys_addr;
 882         }
 883         if (op->sym->auth.digest.phys_addr) {
 884                 ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(
 885                                 qat_req->comn_hdr.serv_specif_flags,
 886                                 ICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER);
 887                 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
 888         }
 889         auth_param->auth_off = op->sym->auth.data.offset;
 890         auth_param->auth_len = op->sym->auth.data.length;
 891         if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2) {
 892                 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0) ||
 893                                 (auth_param->auth_len % BYTE_LENGTH != 0))) {
 894                         PMD_DRV_LOG(ERR, " For Snow3g, QAT PMD only "
 895                                 "supports byte aligned values");
 896                         op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
 897                         return -EINVAL;
 898                 }
 899                 auth_param->auth_off >>= 3;
 900                 auth_param->auth_len >>= 3;
 901         }
 902         auth_param->u1.aad_adr = op->sym->auth.aad.phys_addr;
 903
 904         if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
 905                         ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
 906                 if (op->sym->cipher.iv.length == 12) {
 907                         /*
 908                          * For GCM a 12 bit IV is allowed,
 909                          * but we need to inform the f/w
 910                          */
 911                         ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
 912                                 qat_req->comn_hdr.serv_specif_flags,
 913                                 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
 914                 }
 915         }
 916
 917 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 918         rte_hexdump(stdout, "qat_req:", qat_req,
 919                         sizeof(struct icp_qat_fw_la_bulk_req));
 920         rte_hexdump(stdout, "src_data:",
 921                         rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
 922                         rte_pktmbuf_data_len(op->sym->m_src));
 923         rte_hexdump(stdout, "iv:", op->sym->cipher.iv.data,
 924                         op->sym->cipher.iv.length);
 925         rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
 926                         op->sym->auth.digest.length);
 927         rte_hexdump(stdout, "aad:", op->sym->auth.aad.data,
 928                         op->sym->auth.aad.length);
 929 #endif
 930         return 0;
 931 }
 932
 933 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
 934 {
 935         uint32_t div = data >> shift;
 936         uint32_t mult = div << shift;
 937
 938         return data - mult;
 939 }
 940
 941 void qat_crypto_sym_session_init(struct rte_mempool *mp, void *sym_sess)
 942 {
 943         struct rte_cryptodev_sym_session *sess = sym_sess;
 944         struct qat_session *s = (void *)sess->_private;
 945
 946         PMD_INIT_FUNC_TRACE();
 947         s->cd_paddr = rte_mempool_virt2phy(mp, sess) +
 948                 offsetof(struct qat_session, cd) +
 949                 offsetof(struct rte_cryptodev_sym_session, _private);
 950 }
 951
 952 int qat_dev_config(__rte_unused struct rte_cryptodev *dev)
 953 {
 954         PMD_INIT_FUNC_TRACE();
 955         return -ENOTSUP;
 956 }
 957
 958 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
 959 {
 960         PMD_INIT_FUNC_TRACE();
 961         return 0;
 962 }
 963
 964 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
 965 {
 966         PMD_INIT_FUNC_TRACE();
 967 }
 968
 969 int qat_dev_close(struct rte_cryptodev *dev)
 970 {
 971         int i, ret;
 972
 973         PMD_INIT_FUNC_TRACE();
 974
 975         for (i = 0; i < dev->data->nb_queue_pairs; i++) {
 976                 ret = qat_crypto_sym_qp_release(dev, i);
 977                 if (ret < 0)
 978                         return ret;
 979         }
 980
 981         return 0;
 982 }
 983
 984 void qat_dev_info_get(__rte_unused struct rte_cryptodev *dev,
 985                                 struct rte_cryptodev_info *info)
 986 {
 987         struct qat_pmd_private *internals = dev->data->dev_private;
 988
 989         PMD_INIT_FUNC_TRACE();
 990         if (info != NULL) {
 991                 info->max_nb_queue_pairs =
 992                                 ADF_NUM_SYM_QPS_PER_BUNDLE *
 993                                 ADF_NUM_BUNDLES_PER_DEV;
 994                 info->feature_flags = dev->feature_flags;
 995                 info->capabilities = qat_pmd_capabilities;
 996                 info->sym.max_nb_sessions = internals->max_nb_sessions;
 997                 info->dev_type = RTE_CRYPTODEV_QAT_SYM_PMD;
 998         }
 999 }
1000
1001 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
1002                 struct rte_cryptodev_stats *stats)
1003 {
1004         int i;
1005         struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1006
1007         PMD_INIT_FUNC_TRACE();
1008         if (stats == NULL) {
1009                 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
1010                 return;
1011         }
1012         for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1013                 if (qp[i] == NULL) {
1014                         PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
1015                         continue;
1016                 }
1017
1018                 stats->enqueued_count += qp[i]->stats.enqueued_count;
1019                 stats->dequeued_count += qp[i]->stats.enqueued_count;
1020                 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
1021                 stats->dequeue_err_count += qp[i]->stats.enqueue_err_count;
1022         }
1023 }
1024
1025 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
1026 {
1027         int i;
1028         struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1029
1030         PMD_INIT_FUNC_TRACE();
1031         for (i = 0; i < dev->data->nb_queue_pairs; i++)
1032                 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
1033         PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");
1034 }