drivers/crypto/qat/qat_crypto.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2015-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *       * Redistributions of source code must retain the above copyright
  12  *         notice, this list of conditions and the following disclaimer.
  13  *       * Redistributions in binary form must reproduce the above copyright
  14  *         notice, this list of conditions and the following disclaimer in
  15  *         the documentation and/or other materials provided with the
  16  *         distribution.
  17  *       * Neither the name of Intel Corporation nor the names of its
  18  *         contributors may be used to endorse or promote products derived
  19  *         from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <strings.h>
  37 #include <string.h>
  38 #include <inttypes.h>
  39 #include <errno.h>
  40 #include <sys/queue.h>
  41 #include <stdarg.h>
  42
  43 #include <rte_common.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_memory.h>
  47 #include <rte_memzone.h>
  48 #include <rte_tailq.h>
  49 #include <rte_ether.h>
  50 #include <rte_malloc.h>
  51 #include <rte_launch.h>
  52 #include <rte_eal.h>
  53 #include <rte_per_lcore.h>
  54 #include <rte_lcore.h>
  55 #include <rte_atomic.h>
  56 #include <rte_branch_prediction.h>
  57 #include <rte_mempool.h>
  58 #include <rte_mbuf.h>
  59 #include <rte_string_fns.h>
  60 #include <rte_spinlock.h>
  61 #include <rte_hexdump.h>
  62 #include <rte_crypto_sym.h>
  63 #include <rte_cryptodev_pci.h>
  64 #include <openssl/evp.h>
  65
  66 #include "qat_logs.h"
  67 #include "qat_algs.h"
  68 #include "qat_crypto.h"
  69 #include "adf_transport_access_macros.h"
  70
  71 #define BYTE_LENGTH    8
  72
  73 static int
  74 qat_is_cipher_alg_supported(enum rte_crypto_cipher_algorithm algo,
  75                 struct qat_pmd_private *internals) {
  76         int i = 0;
  77         const struct rte_cryptodev_capabilities *capability;
  78
  79         while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
  80                         RTE_CRYPTO_OP_TYPE_UNDEFINED) {
  81                 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
  82                         continue;
  83
  84                 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_CIPHER)
  85                         continue;
  86
  87                 if (capability->sym.cipher.algo == algo)
  88                         return 1;
  89         }
  90         return 0;
  91 }
  92
  93 static int
  94 qat_is_auth_alg_supported(enum rte_crypto_auth_algorithm algo,
  95                 struct qat_pmd_private *internals) {
  96         int i = 0;
  97         const struct rte_cryptodev_capabilities *capability;
  98
  99         while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
 100                         RTE_CRYPTO_OP_TYPE_UNDEFINED) {
 101                 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
 102                         continue;
 103
 104                 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_AUTH)
 105                         continue;
 106
 107                 if (capability->sym.auth.algo == algo)
 108                         return 1;
 109         }
 110         return 0;
 111 }
 112
 113 /** Encrypt a single partial block
 114  *  Depends on openssl libcrypto
 115  *  Uses ECB+XOR to do CFB encryption, same result, more performant
 116  */
 117 static inline int
 118 bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,
 119                 uint8_t *iv, int ivlen, int srclen,
 120                 void *bpi_ctx)
 121 {
 122         EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
 123         int encrypted_ivlen;
 124         uint8_t encrypted_iv[16];
 125         int i;
 126
 127         /* ECB method: encrypt the IV, then XOR this with plaintext */
 128         if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
 129                                                                 <= 0)
 130                 goto cipher_encrypt_err;
 131
 132         for (i = 0; i < srclen; i++)
 133                 *(dst+i) = *(src+i)^(encrypted_iv[i]);
 134
 135         return 0;
 136
 137 cipher_encrypt_err:
 138         PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt failed");
 139         return -EINVAL;
 140 }
 141
 142 /** Decrypt a single partial block
 143  *  Depends on openssl libcrypto
 144  *  Uses ECB+XOR to do CFB encryption, same result, more performant
 145  */
 146 static inline int
 147 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
 148                 uint8_t *iv, int ivlen, int srclen,
 149                 void *bpi_ctx)
 150 {
 151         EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
 152         int encrypted_ivlen;
 153         uint8_t encrypted_iv[16];
 154         int i;
 155
 156         /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
 157         if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
 158                                                                 <= 0)
 159                 goto cipher_decrypt_err;
 160
 161         for (i = 0; i < srclen; i++)
 162                 *(dst+i) = *(src+i)^(encrypted_iv[i]);
 163
 164         return 0;
 165
 166 cipher_decrypt_err:
 167         PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt for BPI IV failed");
 168         return -EINVAL;
 169 }
 170
 171 /** Creates a context in either AES or DES in ECB mode
 172  *  Depends on openssl libcrypto
 173  */
 174 static void *
 175 bpi_cipher_ctx_init(enum rte_crypto_cipher_algorithm cryptodev_algo,
 176                 enum rte_crypto_cipher_operation direction __rte_unused,
 177                                         uint8_t *key)
 178 {
 179         const EVP_CIPHER *algo = NULL;
 180         EVP_CIPHER_CTX *ctx = EVP_CIPHER_CTX_new();
 181
 182         if (ctx == NULL)
 183                 goto ctx_init_err;
 184
 185         if (cryptodev_algo == RTE_CRYPTO_CIPHER_DES_DOCSISBPI)
 186                 algo = EVP_des_ecb();
 187         else
 188                 algo = EVP_aes_128_ecb();
 189
 190         /* IV will be ECB encrypted whether direction is encrypt or decrypt*/
 191         if (EVP_EncryptInit_ex(ctx, algo, NULL, key, 0) != 1)
 192                 goto ctx_init_err;
 193
 194         return ctx;
 195
 196 ctx_init_err:
 197         if (ctx != NULL)
 198                 EVP_CIPHER_CTX_free(ctx);
 199         return NULL;
 200 }
 201
 202 /** Frees a context previously created
 203  *  Depends on openssl libcrypto
 204  */
 205 static void
 206 bpi_cipher_ctx_free(void *bpi_ctx)
 207 {
 208         if (bpi_ctx != NULL)
 209                 EVP_CIPHER_CTX_free((EVP_CIPHER_CTX *)bpi_ctx);
 210 }
 211
 212 static inline uint32_t
 213 adf_modulo(uint32_t data, uint32_t shift);
 214
 215 static inline int
 216 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
 217                 struct qat_crypto_op_cookie *qat_op_cookie);
 218
 219 void qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
 220                 void *session)
 221 {
 222         struct qat_session *sess = session;
 223         phys_addr_t cd_paddr;
 224
 225         PMD_INIT_FUNC_TRACE();
 226         if (sess) {
 227                 if (sess->bpi_ctx) {
 228                         bpi_cipher_ctx_free(sess->bpi_ctx);
 229                         sess->bpi_ctx = NULL;
 230                 }
 231                 cd_paddr = sess->cd_paddr;
 232                 memset(sess, 0, qat_crypto_sym_get_session_private_size(dev));
 233                 sess->cd_paddr = cd_paddr;
 234         } else
 235                 PMD_DRV_LOG(ERR, "NULL session");
 236 }
 237
 238 static int
 239 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
 240 {
 241         /* Cipher Only */
 242         if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
 243                 return ICP_QAT_FW_LA_CMD_CIPHER;
 244
 245         /* Authentication Only */
 246         if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
 247                 return ICP_QAT_FW_LA_CMD_AUTH;
 248
 249         if (xform->next == NULL)
 250                 return -1;
 251
 252         /* Cipher then Authenticate */
 253         if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
 254                         xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
 255                 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
 256
 257         /* Authenticate then Cipher */
 258         if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
 259                         xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
 260                 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
 261
 262         return -1;
 263 }
 264
 265 static struct rte_crypto_auth_xform *
 266 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
 267 {
 268         do {
 269                 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
 270                         return &xform->auth;
 271
 272                 xform = xform->next;
 273         } while (xform);
 274
 275         return NULL;
 276 }
 277
 278 static struct rte_crypto_cipher_xform *
 279 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
 280 {
 281         do {
 282                 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
 283                         return &xform->cipher;
 284
 285                 xform = xform->next;
 286         } while (xform);
 287
 288         return NULL;
 289 }
 290 void *
 291 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
 292                 struct rte_crypto_sym_xform *xform, void *session_private)
 293 {
 294         struct qat_session *session = session_private;
 295         struct qat_pmd_private *internals = dev->data->dev_private;
 296         struct rte_crypto_cipher_xform *cipher_xform = NULL;
 297
 298         /* Get cipher xform from crypto xform chain */
 299         cipher_xform = qat_get_cipher_xform(xform);
 300
 301         session->cipher_iv.offset = cipher_xform->iv.offset;
 302         session->cipher_iv.length = cipher_xform->iv.length;
 303
 304         switch (cipher_xform->algo) {
 305         case RTE_CRYPTO_CIPHER_AES_CBC:
 306                 if (qat_alg_validate_aes_key(cipher_xform->key.length,
 307                                 &session->qat_cipher_alg) != 0) {
 308                         PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
 309                         goto error_out;
 310                 }
 311                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 312                 break;
 313         case RTE_CRYPTO_CIPHER_AES_GCM:
 314                 if (qat_alg_validate_aes_key(cipher_xform->key.length,
 315                                 &session->qat_cipher_alg) != 0) {
 316                         PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
 317                         goto error_out;
 318                 }
 319                 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
 320                 break;
 321         case RTE_CRYPTO_CIPHER_AES_CTR:
 322                 if (qat_alg_validate_aes_key(cipher_xform->key.length,
 323                                 &session->qat_cipher_alg) != 0) {
 324                         PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
 325                         goto error_out;
 326                 }
 327                 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
 328                 break;
 329         case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
 330                 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
 331                                         &session->qat_cipher_alg) != 0) {
 332                         PMD_DRV_LOG(ERR, "Invalid SNOW 3G cipher key size");
 333                         goto error_out;
 334                 }
 335                 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
 336                 break;
 337         case RTE_CRYPTO_CIPHER_NULL:
 338                 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
 339                 break;
 340         case RTE_CRYPTO_CIPHER_KASUMI_F8:
 341                 if (qat_alg_validate_kasumi_key(cipher_xform->key.length,
 342                                         &session->qat_cipher_alg) != 0) {
 343                         PMD_DRV_LOG(ERR, "Invalid KASUMI cipher key size");
 344                         goto error_out;
 345                 }
 346                 session->qat_mode = ICP_QAT_HW_CIPHER_F8_MODE;
 347                 break;
 348         case RTE_CRYPTO_CIPHER_3DES_CBC:
 349                 if (qat_alg_validate_3des_key(cipher_xform->key.length,
 350                                 &session->qat_cipher_alg) != 0) {
 351                         PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
 352                         goto error_out;
 353                 }
 354                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 355                 break;
 356         case RTE_CRYPTO_CIPHER_DES_CBC:
 357                 if (qat_alg_validate_des_key(cipher_xform->key.length,
 358                                 &session->qat_cipher_alg) != 0) {
 359                         PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
 360                         goto error_out;
 361                 }
 362                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 363                 break;
 364         case RTE_CRYPTO_CIPHER_3DES_CTR:
 365                 if (qat_alg_validate_3des_key(cipher_xform->key.length,
 366                                 &session->qat_cipher_alg) != 0) {
 367                         PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
 368                         goto error_out;
 369                 }
 370                 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
 371                 break;
 372         case RTE_CRYPTO_CIPHER_DES_DOCSISBPI:
 373                 session->bpi_ctx = bpi_cipher_ctx_init(
 374                                         cipher_xform->algo,
 375                                         cipher_xform->op,
 376                                         cipher_xform->key.data);
 377                 if (session->bpi_ctx == NULL) {
 378                         PMD_DRV_LOG(ERR, "failed to create DES BPI ctx");
 379                         goto error_out;
 380                 }
 381                 if (qat_alg_validate_des_key(cipher_xform->key.length,
 382                                 &session->qat_cipher_alg) != 0) {
 383                         PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
 384                         goto error_out;
 385                 }
 386                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 387                 break;
 388         case RTE_CRYPTO_CIPHER_AES_DOCSISBPI:
 389                 session->bpi_ctx = bpi_cipher_ctx_init(
 390                                         cipher_xform->algo,
 391                                         cipher_xform->op,
 392                                         cipher_xform->key.data);
 393                 if (session->bpi_ctx == NULL) {
 394                         PMD_DRV_LOG(ERR, "failed to create AES BPI ctx");
 395                         goto error_out;
 396                 }
 397                 if (qat_alg_validate_aes_docsisbpi_key(cipher_xform->key.length,
 398                                 &session->qat_cipher_alg) != 0) {
 399                         PMD_DRV_LOG(ERR, "Invalid AES DOCSISBPI key size");
 400                         goto error_out;
 401                 }
 402                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 403                 break;
 404         case RTE_CRYPTO_CIPHER_ZUC_EEA3:
 405                 if (!qat_is_cipher_alg_supported(
 406                         cipher_xform->algo, internals)) {
 407                         PMD_DRV_LOG(ERR, "%s not supported on this device",
 408                                 rte_crypto_cipher_algorithm_strings
 409                                         [cipher_xform->algo]);
 410                         goto error_out;
 411                 }
 412                 if (qat_alg_validate_zuc_key(cipher_xform->key.length,
 413                                 &session->qat_cipher_alg) != 0) {
 414                         PMD_DRV_LOG(ERR, "Invalid ZUC cipher key size");
 415                         goto error_out;
 416                 }
 417                 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
 418                 break;
 419         case RTE_CRYPTO_CIPHER_3DES_ECB:
 420         case RTE_CRYPTO_CIPHER_AES_ECB:
 421         case RTE_CRYPTO_CIPHER_AES_CCM:
 422         case RTE_CRYPTO_CIPHER_AES_F8:
 423         case RTE_CRYPTO_CIPHER_AES_XTS:
 424         case RTE_CRYPTO_CIPHER_ARC4:
 425                 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported Cipher alg %u",
 426                                 cipher_xform->algo);
 427                 goto error_out;
 428         default:
 429                 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
 430                                 cipher_xform->algo);
 431                 goto error_out;
 432         }
 433
 434         if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
 435                 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
 436         else
 437                 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
 438
 439         if (qat_alg_aead_session_create_content_desc_cipher(session,
 440                                                 cipher_xform->key.data,
 441                                                 cipher_xform->key.length))
 442                 goto error_out;
 443
 444         return session;
 445
 446 error_out:
 447         if (session->bpi_ctx) {
 448                 bpi_cipher_ctx_free(session->bpi_ctx);
 449                 session->bpi_ctx = NULL;
 450         }
 451         return NULL;
 452 }
 453
 454
 455 void *
 456 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
 457                 struct rte_crypto_sym_xform *xform, void *session_private)
 458 {
 459         struct qat_session *session = session_private;
 460
 461         int qat_cmd_id;
 462         PMD_INIT_FUNC_TRACE();
 463
 464         /* Get requested QAT command id */
 465         qat_cmd_id = qat_get_cmd_id(xform);
 466         if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
 467                 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
 468                 goto error_out;
 469         }
 470         session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
 471         switch (session->qat_cmd) {
 472         case ICP_QAT_FW_LA_CMD_CIPHER:
 473         session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
 474                 break;
 475         case ICP_QAT_FW_LA_CMD_AUTH:
 476         session = qat_crypto_sym_configure_session_auth(dev, xform, session);
 477                 break;
 478         case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
 479         session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
 480         session = qat_crypto_sym_configure_session_auth(dev, xform, session);
 481                 break;
 482         case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
 483         session = qat_crypto_sym_configure_session_auth(dev, xform, session);
 484         session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
 485                 break;
 486         case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
 487         case ICP_QAT_FW_LA_CMD_TRNG_TEST:
 488         case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
 489         case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
 490         case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
 491         case ICP_QAT_FW_LA_CMD_MGF1:
 492         case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
 493         case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
 494         case ICP_QAT_FW_LA_CMD_DELIMITER:
 495         PMD_DRV_LOG(ERR, "Unsupported Service %u",
 496                 session->qat_cmd);
 497                 goto error_out;
 498         default:
 499         PMD_DRV_LOG(ERR, "Unsupported Service %u",
 500                 session->qat_cmd);
 501                 goto error_out;
 502         }
 503
 504         return session;
 505
 506 error_out:
 507         return NULL;
 508 }
 509
 510 struct qat_session *
 511 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
 512                                 struct rte_crypto_sym_xform *xform,
 513                                 struct qat_session *session_private)
 514 {
 515
 516         struct qat_session *session = session_private;
 517         struct rte_crypto_auth_xform *auth_xform = NULL;
 518         struct rte_crypto_cipher_xform *cipher_xform = NULL;
 519         struct qat_pmd_private *internals = dev->data->dev_private;
 520         auth_xform = qat_get_auth_xform(xform);
 521         uint8_t *key_data = auth_xform->key.data;
 522         uint8_t key_length = auth_xform->key.length;
 523
 524         switch (auth_xform->algo) {
 525         case RTE_CRYPTO_AUTH_SHA1_HMAC:
 526                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
 527                 break;
 528         case RTE_CRYPTO_AUTH_SHA224_HMAC:
 529                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
 530                 break;
 531         case RTE_CRYPTO_AUTH_SHA256_HMAC:
 532                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
 533                 break;
 534         case RTE_CRYPTO_AUTH_SHA384_HMAC:
 535                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;
 536                 break;
 537         case RTE_CRYPTO_AUTH_SHA512_HMAC:
 538                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
 539                 break;
 540         case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
 541                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
 542                 break;
 543         case RTE_CRYPTO_AUTH_AES_GCM:
 544                 cipher_xform = qat_get_cipher_xform(xform);
 545
 546                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
 547
 548                 key_data = cipher_xform->key.data;
 549                 key_length = cipher_xform->key.length;
 550                 break;
 551         case RTE_CRYPTO_AUTH_AES_GMAC:
 552                 if (qat_alg_validate_aes_key(auth_xform->key.length,
 553                                 &session->qat_cipher_alg) != 0) {
 554                         PMD_DRV_LOG(ERR, "Invalid AES key size");
 555                         goto error_out;
 556                 }
 557                 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
 558                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
 559
 560                 break;
 561         case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
 562                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
 563                 break;
 564         case RTE_CRYPTO_AUTH_MD5_HMAC:
 565                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
 566                 break;
 567         case RTE_CRYPTO_AUTH_NULL:
 568                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;
 569                 break;
 570         case RTE_CRYPTO_AUTH_KASUMI_F9:
 571                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_KASUMI_F9;
 572                 break;
 573         case RTE_CRYPTO_AUTH_ZUC_EIA3:
 574                 if (!qat_is_auth_alg_supported(auth_xform->algo, internals)) {
 575                         PMD_DRV_LOG(ERR, "%s not supported on this device",
 576                                 rte_crypto_auth_algorithm_strings
 577                                 [auth_xform->algo]);
 578                         goto error_out;
 579                 }
 580                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3;
 581                 break;
 582         case RTE_CRYPTO_AUTH_SHA1:
 583         case RTE_CRYPTO_AUTH_SHA256:
 584         case RTE_CRYPTO_AUTH_SHA512:
 585         case RTE_CRYPTO_AUTH_SHA224:
 586         case RTE_CRYPTO_AUTH_SHA384:
 587         case RTE_CRYPTO_AUTH_MD5:
 588         case RTE_CRYPTO_AUTH_AES_CCM:
 589         case RTE_CRYPTO_AUTH_AES_CMAC:
 590         case RTE_CRYPTO_AUTH_AES_CBC_MAC:
 591                 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
 592                                 auth_xform->algo);
 593                 goto error_out;
 594         default:
 595                 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
 596                                 auth_xform->algo);
 597                 goto error_out;
 598         }
 599
 600         session->auth_iv.offset = auth_xform->iv.offset;
 601         session->auth_iv.length = auth_xform->iv.length;
 602
 603         if (auth_xform->algo == RTE_CRYPTO_AUTH_AES_GMAC) {
 604                 if (auth_xform->op == RTE_CRYPTO_AUTH_OP_GENERATE) {
 605                         session->qat_cmd = ICP_QAT_FW_LA_CMD_CIPHER_HASH;
 606                         session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
 607                         /*
 608                          * It needs to create cipher desc content first,
 609                          * then authentication
 610                          */
 611                         if (qat_alg_aead_session_create_content_desc_cipher(session,
 612                                                 auth_xform->key.data,
 613                                                 auth_xform->key.length))
 614                                 goto error_out;
 615
 616                         if (qat_alg_aead_session_create_content_desc_auth(session,
 617                                                 key_data,
 618                                                 key_length,
 619                                                 0,
 620                                                 auth_xform->digest_length,
 621                                                 auth_xform->op))
 622                                 goto error_out;
 623                 } else {
 624                         session->qat_cmd = ICP_QAT_FW_LA_CMD_HASH_CIPHER;
 625                         session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
 626                         /*
 627                          * It needs to create authentication desc content first,
 628                          * then cipher
 629                          */
 630                         if (qat_alg_aead_session_create_content_desc_auth(session,
 631                                         key_data,
 632                                         key_length,
 633                                         0,
 634                                         auth_xform->digest_length,
 635                                         auth_xform->op))
 636                                 goto error_out;
 637
 638                         if (qat_alg_aead_session_create_content_desc_cipher(session,
 639                                                 auth_xform->key.data,
 640                                                 auth_xform->key.length))
 641                                 goto error_out;
 642                 }
 643                 /* Restore to authentication only only */
 644                 session->qat_cmd = ICP_QAT_FW_LA_CMD_AUTH;
 645         } else {
 646                 if (qat_alg_aead_session_create_content_desc_auth(session,
 647                                 key_data,
 648                                 key_length,
 649                                 auth_xform->add_auth_data_length,
 650                                 auth_xform->digest_length,
 651                                 auth_xform->op))
 652                         goto error_out;
 653         }
 654
 655         session->digest_length = auth_xform->digest_length;
 656         return session;
 657
 658 error_out:
 659         return NULL;
 660 }
 661
 662 unsigned qat_crypto_sym_get_session_private_size(
 663                 struct rte_cryptodev *dev __rte_unused)
 664 {
 665         return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
 666 }
 667
 668 static inline uint32_t
 669 qat_bpicipher_preprocess(struct qat_session *ctx,
 670                                 struct rte_crypto_op *op)
 671 {
 672         uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
 673         struct rte_crypto_sym_op *sym_op = op->sym;
 674         uint8_t last_block_len = sym_op->cipher.data.length % block_len;
 675
 676         if (last_block_len &&
 677                         ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
 678
 679                 /* Decrypt last block */
 680                 uint8_t *last_block, *dst, *iv;
 681                 uint32_t last_block_offset = sym_op->cipher.data.offset +
 682                                 sym_op->cipher.data.length - last_block_len;
 683                 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
 684                                 uint8_t *, last_block_offset);
 685
 686                 if (unlikely(sym_op->m_dst != NULL))
 687                         /* out-of-place operation (OOP) */
 688                         dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
 689                                                 uint8_t *, last_block_offset);
 690                 else
 691                         dst = last_block;
 692
 693                 if (last_block_len < sym_op->cipher.data.length)
 694                         /* use previous block ciphertext as IV */
 695                         iv = last_block - block_len;
 696                 else
 697                         /* runt block, i.e. less than one full block */
 698                         iv = rte_crypto_op_ctod_offset(op, uint8_t *,
 699                                         ctx->cipher_iv.offset);
 700
 701 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 702                 rte_hexdump(stdout, "BPI: src before pre-process:", last_block,
 703                         last_block_len);
 704                 if (sym_op->m_dst != NULL)
 705                         rte_hexdump(stdout, "BPI: dst before pre-process:", dst,
 706                                 last_block_len);
 707 #endif
 708                 bpi_cipher_decrypt(last_block, dst, iv, block_len,
 709                                 last_block_len, ctx->bpi_ctx);
 710 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 711                 rte_hexdump(stdout, "BPI: src after pre-process:", last_block,
 712                         last_block_len);
 713                 if (sym_op->m_dst != NULL)
 714                         rte_hexdump(stdout, "BPI: dst after pre-process:", dst,
 715                                 last_block_len);
 716 #endif
 717         }
 718
 719         return sym_op->cipher.data.length - last_block_len;
 720 }
 721
 722 static inline uint32_t
 723 qat_bpicipher_postprocess(struct qat_session *ctx,
 724                                 struct rte_crypto_op *op)
 725 {
 726         uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
 727         struct rte_crypto_sym_op *sym_op = op->sym;
 728         uint8_t last_block_len = sym_op->cipher.data.length % block_len;
 729
 730         if (last_block_len > 0 &&
 731                         ctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
 732
 733                 /* Encrypt last block */
 734                 uint8_t *last_block, *dst, *iv;
 735                 uint32_t last_block_offset;
 736
 737                 last_block_offset = sym_op->cipher.data.offset +
 738                                 sym_op->cipher.data.length - last_block_len;
 739                 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
 740                                 uint8_t *, last_block_offset);
 741
 742                 if (unlikely(sym_op->m_dst != NULL))
 743                         /* out-of-place operation (OOP) */
 744                         dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
 745                                                 uint8_t *, last_block_offset);
 746                 else
 747                         dst = last_block;
 748
 749                 if (last_block_len < sym_op->cipher.data.length)
 750                         /* use previous block ciphertext as IV */
 751                         iv = dst - block_len;
 752                 else
 753                         /* runt block, i.e. less than one full block */
 754                         iv = rte_crypto_op_ctod_offset(op, uint8_t *,
 755                                         ctx->cipher_iv.offset);
 756
 757 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
 758                 rte_hexdump(stdout, "BPI: src before post-process:", last_block,
 759                         last_block_len);
 760                 if (sym_op->m_dst != NULL)
 761                         rte_hexdump(stdout, "BPI: dst before post-process:",
 762                                         dst, last_block_len);
 763 #endif
 764                 bpi_cipher_encrypt(last_block, dst, iv, block_len,
 765                                 last_block_len, ctx->bpi_ctx);
 766 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
 767                 rte_hexdump(stdout, "BPI: src after post-process:", last_block,
 768                         last_block_len);
 769                 if (sym_op->m_dst != NULL)
 770                         rte_hexdump(stdout, "BPI: dst after post-process:", dst,
 771                                 last_block_len);
 772 #endif
 773         }
 774         return sym_op->cipher.data.length - last_block_len;
 775 }
 776
 777 uint16_t
 778 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
 779                 uint16_t nb_ops)
 780 {
 781         register struct qat_queue *queue;
 782         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 783         register uint32_t nb_ops_sent = 0;
 784         register struct rte_crypto_op **cur_op = ops;
 785         register int ret;
 786         uint16_t nb_ops_possible = nb_ops;
 787         register uint8_t *base_addr;
 788         register uint32_t tail;
 789         int overflow;
 790
 791         if (unlikely(nb_ops == 0))
 792                 return 0;
 793
 794         /* read params used a lot in main loop into registers */
 795         queue = &(tmp_qp->tx_q);
 796         base_addr = (uint8_t *)queue->base_addr;
 797         tail = queue->tail;
 798
 799         /* Find how many can actually fit on the ring */
 800         overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
 801                                 - queue->max_inflights;
 802         if (overflow > 0) {
 803                 rte_atomic16_sub(&tmp_qp->inflights16, overflow);
 804                 nb_ops_possible = nb_ops - overflow;
 805                 if (nb_ops_possible == 0)
 806                         return 0;
 807         }
 808
 809         while (nb_ops_sent != nb_ops_possible) {
 810                 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail,
 811                                 tmp_qp->op_cookies[tail / queue->msg_size]);
 812                 if (ret != 0) {
 813                         tmp_qp->stats.enqueue_err_count++;
 814                         /*
 815                          * This message cannot be enqueued,
 816                          * decrease number of ops that wasn't sent
 817                          */
 818                         rte_atomic16_sub(&tmp_qp->inflights16,
 819                                         nb_ops_possible - nb_ops_sent);
 820                         if (nb_ops_sent == 0)
 821                                 return 0;
 822                         goto kick_tail;
 823                 }
 824
 825                 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
 826                 nb_ops_sent++;
 827                 cur_op++;
 828         }
 829 kick_tail:
 830         WRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,
 831                         queue->hw_queue_number, tail);
 832         queue->tail = tail;
 833         tmp_qp->stats.enqueued_count += nb_ops_sent;
 834         return nb_ops_sent;
 835 }
 836
 837 uint16_t
 838 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
 839                 uint16_t nb_ops)
 840 {
 841         struct qat_queue *queue;
 842         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 843         uint32_t msg_counter = 0;
 844         struct rte_crypto_op *rx_op;
 845         struct icp_qat_fw_comn_resp *resp_msg;
 846
 847         queue = &(tmp_qp->rx_q);
 848         resp_msg = (struct icp_qat_fw_comn_resp *)
 849                         ((uint8_t *)queue->base_addr + queue->head);
 850
 851         while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
 852                         msg_counter != nb_ops) {
 853                 rx_op = (struct rte_crypto_op *)(uintptr_t)
 854                                 (resp_msg->opaque_data);
 855
 856 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
 857                 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
 858                         sizeof(struct icp_qat_fw_comn_resp));
 859
 860 #endif
 861                 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
 862                                 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
 863                                         resp_msg->comn_hdr.comn_status)) {
 864                         rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
 865                 } else {
 866                         struct qat_session *sess = (struct qat_session *)
 867                                                 (rx_op->sym->session->_private);
 868                         if (sess->bpi_ctx)
 869                                 qat_bpicipher_postprocess(sess, rx_op);
 870                         rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
 871                 }
 872
 873                 *(uint32_t *)resp_msg = ADF_RING_EMPTY_SIG;
 874                 queue->head = adf_modulo(queue->head +
 875                                 queue->msg_size,
 876                                 ADF_RING_SIZE_MODULO(queue->queue_size));
 877                 resp_msg = (struct icp_qat_fw_comn_resp *)
 878                                         ((uint8_t *)queue->base_addr +
 879                                                         queue->head);
 880                 *ops = rx_op;
 881                 ops++;
 882                 msg_counter++;
 883         }
 884         if (msg_counter > 0) {
 885                 WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
 886                                         queue->hw_bundle_number,
 887                                         queue->hw_queue_number, queue->head);
 888                 rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
 889                 tmp_qp->stats.dequeued_count += msg_counter;
 890         }
 891         return msg_counter;
 892 }
 893
 894 static inline int
 895 qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buff_start,
 896                 struct qat_alg_buf_list *list, uint32_t data_len)
 897 {
 898         int nr = 1;
 899
 900         uint32_t buf_len = rte_pktmbuf_mtophys(buf) -
 901                         buff_start + rte_pktmbuf_data_len(buf);
 902
 903         list->bufers[0].addr = buff_start;
 904         list->bufers[0].resrvd = 0;
 905         list->bufers[0].len = buf_len;
 906
 907         if (data_len <= buf_len) {
 908                 list->num_bufs = nr;
 909                 list->bufers[0].len = data_len;
 910                 return 0;
 911         }
 912
 913         buf = buf->next;
 914         while (buf) {
 915                 if (unlikely(nr == QAT_SGL_MAX_NUMBER)) {
 916                         PMD_DRV_LOG(ERR, "QAT PMD exceeded size of QAT SGL"
 917                                         " entry(%u)",
 918                                         QAT_SGL_MAX_NUMBER);
 919                         return -EINVAL;
 920                 }
 921
 922                 list->bufers[nr].len = rte_pktmbuf_data_len(buf);
 923                 list->bufers[nr].resrvd = 0;
 924                 list->bufers[nr].addr = rte_pktmbuf_mtophys(buf);
 925
 926                 buf_len += list->bufers[nr].len;
 927                 buf = buf->next;
 928
 929                 if (buf_len > data_len) {
 930                         list->bufers[nr].len -=
 931                                 buf_len - data_len;
 932                         buf = NULL;
 933                 }
 934                 ++nr;
 935         }
 936         list->num_bufs = nr;
 937
 938         return 0;
 939 }
 940
 941 static inline void
 942 set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,
 943                 struct icp_qat_fw_la_cipher_req_params *cipher_param,
 944                 struct rte_crypto_op *op,
 945                 struct icp_qat_fw_la_bulk_req *qat_req)
 946 {
 947         /* copy IV into request if it fits */
 948         if (iv_length <= sizeof(cipher_param->u.cipher_IV_array)) {
 949                 rte_memcpy(cipher_param->u.cipher_IV_array,
 950                                 rte_crypto_op_ctod_offset(op, uint8_t *,
 951                                         iv_offset),
 952                                 iv_length);
 953         } else {
 954                 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
 955                                 qat_req->comn_hdr.serv_specif_flags,
 956                                 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
 957                 cipher_param->u.s.cipher_IV_ptr =
 958                                 rte_crypto_op_ctophys_offset(op,
 959                                         iv_offset);
 960         }
 961 }
 962
 963 static inline int
 964 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
 965                 struct qat_crypto_op_cookie *qat_op_cookie)
 966 {
 967         int ret = 0;
 968         struct qat_session *ctx;
 969         struct icp_qat_fw_la_cipher_req_params *cipher_param;
 970         struct icp_qat_fw_la_auth_req_params *auth_param;
 971         register struct icp_qat_fw_la_bulk_req *qat_req;
 972         uint8_t do_auth = 0, do_cipher = 0;
 973         uint32_t cipher_len = 0, cipher_ofs = 0;
 974         uint32_t auth_len = 0, auth_ofs = 0;
 975         uint32_t min_ofs = 0;
 976         uint64_t src_buf_start = 0, dst_buf_start = 0;
 977         uint8_t do_sgl = 0;
 978
 979 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 980         if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
 981                 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
 982                                 "operation requests, op (%p) is not a "
 983                                 "symmetric operation.", op);
 984                 return -EINVAL;
 985         }
 986 #endif
 987         if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
 988                 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
 989                                 " requests, op (%p) is sessionless.", op);
 990                 return -EINVAL;
 991         }
 992
 993         if (unlikely(op->sym->session->dev_type != RTE_CRYPTODEV_QAT_SYM_PMD)) {
 994                 PMD_DRV_LOG(ERR, "Session was not created for this device");
 995                 return -EINVAL;
 996         }
 997
 998         ctx = (struct qat_session *)op->sym->session->_private;
 999         qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
1000         rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
1001         qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
1002         cipher_param = (void *)&qat_req->serv_specif_rqpars;
1003         auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
1004
1005         if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
1006                 ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
1007                 do_auth = 1;
1008                 do_cipher = 1;
1009         } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
1010                 do_auth = 1;
1011                 do_cipher = 0;
1012         } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
1013                 do_auth = 0;
1014                 do_cipher = 1;
1015         }
1016
1017         if (do_cipher) {
1018
1019                 if (ctx->qat_cipher_alg ==
1020                                          ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
1021                         ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
1022                         ctx->qat_cipher_alg ==
1023                                 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
1024
1025                         if (unlikely(
1026                                 (cipher_param->cipher_length % BYTE_LENGTH != 0)
1027                                  || (cipher_param->cipher_offset
1028                                                         % BYTE_LENGTH != 0))) {
1029                                 PMD_DRV_LOG(ERR,
1030                   "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
1031                                 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1032                                 return -EINVAL;
1033                         }
1034                         cipher_len = op->sym->cipher.data.length >> 3;
1035                         cipher_ofs = op->sym->cipher.data.offset >> 3;
1036
1037                 } else if (ctx->bpi_ctx) {
1038                         /* DOCSIS - only send complete blocks to device
1039                          * Process any partial block using CFB mode.
1040                          * Even if 0 complete blocks, still send this to device
1041                          * to get into rx queue for post-process and dequeuing
1042                          */
1043                         cipher_len = qat_bpicipher_preprocess(ctx, op);
1044                         cipher_ofs = op->sym->cipher.data.offset;
1045                 } else {
1046                         cipher_len = op->sym->cipher.data.length;
1047                         cipher_ofs = op->sym->cipher.data.offset;
1048                 }
1049
1050                 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
1051                                 cipher_param, op, qat_req);
1052                 min_ofs = cipher_ofs;
1053         }
1054
1055         if (do_auth) {
1056
1057                 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
1058                         ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
1059                         ctx->qat_hash_alg ==
1060                                 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
1061                         if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0)
1062                                 || (auth_param->auth_len % BYTE_LENGTH != 0))) {
1063                                 PMD_DRV_LOG(ERR,
1064                 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
1065                                 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1066                                 return -EINVAL;
1067                         }
1068                         auth_ofs = op->sym->auth.data.offset >> 3;
1069                         auth_len = op->sym->auth.data.length >> 3;
1070
1071                         if (ctx->qat_hash_alg ==
1072                                         ICP_QAT_HW_AUTH_ALGO_KASUMI_F9) {
1073                                 if (do_cipher) {
1074                                         auth_len = auth_len + auth_ofs + 1 -
1075                                                 ICP_QAT_HW_KASUMI_BLK_SZ;
1076                                         auth_ofs = ICP_QAT_HW_KASUMI_BLK_SZ;
1077                                 } else {
1078                                         auth_len = auth_len + auth_ofs + 1;
1079                                         auth_ofs = 0;
1080                                 }
1081                         } else
1082                                 auth_param->u1.aad_adr =
1083                                         rte_crypto_op_ctophys_offset(op,
1084                                                         ctx->auth_iv.offset);
1085
1086                 } else if (ctx->qat_hash_alg ==
1087                                         ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1088                                 ctx->qat_hash_alg ==
1089                                         ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1090                         /* AES-GCM */
1091                         if (do_cipher) {
1092                                 auth_ofs = op->sym->cipher.data.offset;
1093                                 auth_len = op->sym->cipher.data.length;
1094
1095                                 auth_param->u1.aad_adr = op->sym->auth.aad.phys_addr;
1096                         /* AES-GMAC */
1097                         } else {
1098                                 set_cipher_iv(ctx->auth_iv.length,
1099                                         ctx->auth_iv.offset,
1100                                         cipher_param, op, qat_req);
1101                         }
1102                 } else {
1103                         auth_ofs = op->sym->auth.data.offset;
1104                         auth_len = op->sym->auth.data.length;
1105
1106                 }
1107                 min_ofs = auth_ofs;
1108
1109                 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
1110
1111         }
1112
1113         if (op->sym->m_src->next || (op->sym->m_dst && op->sym->m_dst->next))
1114                 do_sgl = 1;
1115
1116         /* adjust for chain case */
1117         if (do_cipher && do_auth)
1118                 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
1119
1120         if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
1121                 min_ofs = 0;
1122
1123         if (unlikely(op->sym->m_dst != NULL)) {
1124                 /* Out-of-place operation (OOP)
1125                  * Don't align DMA start. DMA the minimum data-set
1126                  * so as not to overwrite data in dest buffer
1127                  */
1128                 src_buf_start =
1129                         rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs);
1130                 dst_buf_start =
1131                         rte_pktmbuf_mtophys_offset(op->sym->m_dst, min_ofs);
1132
1133         } else {
1134                 /* In-place operation
1135                  * Start DMA at nearest aligned address below min_ofs
1136                  */
1137                 src_buf_start =
1138                         rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs)
1139                                                 & QAT_64_BTYE_ALIGN_MASK;
1140
1141                 if (unlikely((rte_pktmbuf_mtophys(op->sym->m_src) -
1142                                         rte_pktmbuf_headroom(op->sym->m_src))
1143                                                         > src_buf_start)) {
1144                         /* alignment has pushed addr ahead of start of mbuf
1145                          * so revert and take the performance hit
1146                          */
1147                         src_buf_start =
1148                                 rte_pktmbuf_mtophys_offset(op->sym->m_src,
1149                                                                 min_ofs);
1150                 }
1151                 dst_buf_start = src_buf_start;
1152         }
1153
1154         if (do_cipher) {
1155                 cipher_param->cipher_offset =
1156                                 (uint32_t)rte_pktmbuf_mtophys_offset(
1157                                 op->sym->m_src, cipher_ofs) - src_buf_start;
1158                 cipher_param->cipher_length = cipher_len;
1159         } else {
1160                 cipher_param->cipher_offset = 0;
1161                 cipher_param->cipher_length = 0;
1162         }
1163         if (do_auth) {
1164                 auth_param->auth_off = (uint32_t)rte_pktmbuf_mtophys_offset(
1165                                 op->sym->m_src, auth_ofs) - src_buf_start;
1166                 auth_param->auth_len = auth_len;
1167         } else {
1168                 auth_param->auth_off = 0;
1169                 auth_param->auth_len = 0;
1170         }
1171         qat_req->comn_mid.dst_length =
1172                 qat_req->comn_mid.src_length =
1173                 (cipher_param->cipher_offset + cipher_param->cipher_length)
1174                 > (auth_param->auth_off + auth_param->auth_len) ?
1175                 (cipher_param->cipher_offset + cipher_param->cipher_length)
1176                 : (auth_param->auth_off + auth_param->auth_len);
1177
1178         if (do_sgl) {
1179
1180                 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
1181                                 QAT_COMN_PTR_TYPE_SGL);
1182                 ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
1183                                 &qat_op_cookie->qat_sgl_list_src,
1184                                 qat_req->comn_mid.src_length);
1185                 if (ret) {
1186                         PMD_DRV_LOG(ERR, "QAT PMD Cannot fill sgl array");
1187                         return ret;
1188                 }
1189
1190                 if (likely(op->sym->m_dst == NULL))
1191                         qat_req->comn_mid.dest_data_addr =
1192                                 qat_req->comn_mid.src_data_addr =
1193                                 qat_op_cookie->qat_sgl_src_phys_addr;
1194                 else {
1195                         ret = qat_sgl_fill_array(op->sym->m_dst,
1196                                         dst_buf_start,
1197                                         &qat_op_cookie->qat_sgl_list_dst,
1198                                                 qat_req->comn_mid.dst_length);
1199
1200                         if (ret) {
1201                                 PMD_DRV_LOG(ERR, "QAT PMD Cannot "
1202                                                 "fill sgl array");
1203                                 return ret;
1204                         }
1205
1206                         qat_req->comn_mid.src_data_addr =
1207                                 qat_op_cookie->qat_sgl_src_phys_addr;
1208                         qat_req->comn_mid.dest_data_addr =
1209                                         qat_op_cookie->qat_sgl_dst_phys_addr;
1210                 }
1211         } else {
1212                 qat_req->comn_mid.src_data_addr = src_buf_start;
1213                 qat_req->comn_mid.dest_data_addr = dst_buf_start;
1214         }
1215
1216         if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1217                         ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1218                 if (ctx->cipher_iv.length == 12 ||
1219                                 ctx->auth_iv.length == 12) {
1220                         /*
1221                          * For GCM a 12 byte IV is allowed,
1222                          * but we need to inform the f/w
1223                          */
1224                         ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1225                                 qat_req->comn_hdr.serv_specif_flags,
1226                                 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1227                 }
1228                 /* GMAC */
1229                 if (!do_cipher) {
1230                         qat_req->comn_mid.dst_length =
1231                                 qat_req->comn_mid.src_length =
1232                                         rte_pktmbuf_data_len(op->sym->m_src);
1233                         auth_param->u1.aad_adr = 0;
1234                         auth_param->auth_len = op->sym->auth.data.length;
1235                         auth_param->auth_off = op->sym->auth.data.offset;
1236                         auth_param->u2.aad_sz = 0;
1237                 }
1238         }
1239
1240 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1241         rte_hexdump(stdout, "qat_req:", qat_req,
1242                         sizeof(struct icp_qat_fw_la_bulk_req));
1243         rte_hexdump(stdout, "src_data:",
1244                         rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
1245                         rte_pktmbuf_data_len(op->sym->m_src));
1246         if (do_cipher) {
1247                 uint8_t *cipher_iv_ptr = rte_crypto_op_ctod_offset(op,
1248                                                 uint8_t *,
1249                                                 ctx->cipher_iv.offset);
1250                 rte_hexdump(stdout, "cipher iv:", cipher_iv_ptr,
1251                                 ctx->cipher_iv.length);
1252         }
1253
1254         if (do_auth) {
1255                 if (ctx->auth_iv.length) {
1256                         uint8_t *auth_iv_ptr = rte_crypto_op_ctod_offset(op,
1257                                                         uint8_t *,
1258                                                         ctx->auth_iv.offset);
1259                         rte_hexdump(stdout, "auth iv:", auth_iv_ptr,
1260                                                 ctx->auth_iv.length);
1261                 }
1262                 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
1263                                 ctx->digest_length);
1264                 rte_hexdump(stdout, "aad:", op->sym->auth.aad.data,
1265                                 ctx->aad_len);
1266         }
1267 #endif
1268         return 0;
1269 }
1270
1271 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
1272 {
1273         uint32_t div = data >> shift;
1274         uint32_t mult = div << shift;
1275
1276         return data - mult;
1277 }
1278
1279 void qat_crypto_sym_session_init(struct rte_mempool *mp, void *sym_sess)
1280 {
1281         struct rte_cryptodev_sym_session *sess = sym_sess;
1282         struct qat_session *s = (void *)sess->_private;
1283
1284         PMD_INIT_FUNC_TRACE();
1285         s->cd_paddr = rte_mempool_virt2phy(mp, sess) +
1286                 offsetof(struct qat_session, cd) +
1287                 offsetof(struct rte_cryptodev_sym_session, _private);
1288 }
1289
1290 int qat_dev_config(__rte_unused struct rte_cryptodev *dev,
1291                 __rte_unused struct rte_cryptodev_config *config)
1292 {
1293         PMD_INIT_FUNC_TRACE();
1294         return 0;
1295 }
1296
1297 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
1298 {
1299         PMD_INIT_FUNC_TRACE();
1300         return 0;
1301 }
1302
1303 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
1304 {
1305         PMD_INIT_FUNC_TRACE();
1306 }
1307
1308 int qat_dev_close(struct rte_cryptodev *dev)
1309 {
1310         int i, ret;
1311
1312         PMD_INIT_FUNC_TRACE();
1313
1314         for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1315                 ret = qat_crypto_sym_qp_release(dev, i);
1316                 if (ret < 0)
1317                         return ret;
1318         }
1319
1320         return 0;
1321 }
1322
1323 void qat_dev_info_get(struct rte_cryptodev *dev,
1324                         struct rte_cryptodev_info *info)
1325 {
1326         struct qat_pmd_private *internals = dev->data->dev_private;
1327
1328         PMD_INIT_FUNC_TRACE();
1329         if (info != NULL) {
1330                 info->max_nb_queue_pairs =
1331                                 ADF_NUM_SYM_QPS_PER_BUNDLE *
1332                                 ADF_NUM_BUNDLES_PER_DEV;
1333                 info->feature_flags = dev->feature_flags;
1334                 info->capabilities = internals->qat_dev_capabilities;
1335                 info->sym.max_nb_sessions = internals->max_nb_sessions;
1336                 info->dev_type = RTE_CRYPTODEV_QAT_SYM_PMD;
1337                 info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1338         }
1339 }
1340
1341 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
1342                 struct rte_cryptodev_stats *stats)
1343 {
1344         int i;
1345         struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1346
1347         PMD_INIT_FUNC_TRACE();
1348         if (stats == NULL) {
1349                 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
1350                 return;
1351         }
1352         for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1353                 if (qp[i] == NULL) {
1354                         PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
1355                         continue;
1356                 }
1357
1358                 stats->enqueued_count += qp[i]->stats.enqueued_count;
1359                 stats->dequeued_count += qp[i]->stats.dequeued_count;
1360                 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
1361                 stats->dequeue_err_count += qp[i]->stats.dequeue_err_count;
1362         }
1363 }
1364
1365 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
1366 {
1367         int i;
1368         struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1369
1370         PMD_INIT_FUNC_TRACE();
1371         for (i = 0; i < dev->data->nb_queue_pairs; i++)
1372                 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
1373         PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");
1374 }