drivers/crypto/qat/qat_crypto.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2015-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *       * Redistributions of source code must retain the above copyright
  12  *         notice, this list of conditions and the following disclaimer.
  13  *       * Redistributions in binary form must reproduce the above copyright
  14  *         notice, this list of conditions and the following disclaimer in
  15  *         the documentation and/or other materials provided with the
  16  *         distribution.
  17  *       * Neither the name of Intel Corporation nor the names of its
  18  *         contributors may be used to endorse or promote products derived
  19  *         from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <strings.h>
  37 #include <string.h>
  38 #include <inttypes.h>
  39 #include <errno.h>
  40 #include <sys/queue.h>
  41 #include <stdarg.h>
  42
  43 #include <rte_common.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_memory.h>
  47 #include <rte_memzone.h>
  48 #include <rte_tailq.h>
  49 #include <rte_ether.h>
  50 #include <rte_malloc.h>
  51 #include <rte_launch.h>
  52 #include <rte_eal.h>
  53 #include <rte_per_lcore.h>
  54 #include <rte_lcore.h>
  55 #include <rte_atomic.h>
  56 #include <rte_branch_prediction.h>
  57 #include <rte_mempool.h>
  58 #include <rte_mbuf.h>
  59 #include <rte_string_fns.h>
  60 #include <rte_spinlock.h>
  61 #include <rte_hexdump.h>
  62 #include <rte_crypto_sym.h>
  63 #include <rte_cryptodev_pci.h>
  64 #include <openssl/evp.h>
  65
  66 #include "qat_logs.h"
  67 #include "qat_algs.h"
  68 #include "qat_crypto.h"
  69 #include "adf_transport_access_macros.h"
  70
  71 #define BYTE_LENGTH    8
  72
  73 static int
  74 qat_is_cipher_alg_supported(enum rte_crypto_cipher_algorithm algo,
  75                 struct qat_pmd_private *internals) {
  76         int i = 0;
  77         const struct rte_cryptodev_capabilities *capability;
  78
  79         while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
  80                         RTE_CRYPTO_OP_TYPE_UNDEFINED) {
  81                 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
  82                         continue;
  83
  84                 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_CIPHER)
  85                         continue;
  86
  87                 if (capability->sym.cipher.algo == algo)
  88                         return 1;
  89         }
  90         return 0;
  91 }
  92
  93 static int
  94 qat_is_auth_alg_supported(enum rte_crypto_auth_algorithm algo,
  95                 struct qat_pmd_private *internals) {
  96         int i = 0;
  97         const struct rte_cryptodev_capabilities *capability;
  98
  99         while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
 100                         RTE_CRYPTO_OP_TYPE_UNDEFINED) {
 101                 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
 102                         continue;
 103
 104                 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_AUTH)
 105                         continue;
 106
 107                 if (capability->sym.auth.algo == algo)
 108                         return 1;
 109         }
 110         return 0;
 111 }
 112
 113 /** Encrypt a single partial block
 114  *  Depends on openssl libcrypto
 115  *  Uses ECB+XOR to do CFB encryption, same result, more performant
 116  */
 117 static inline int
 118 bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,
 119                 uint8_t *iv, int ivlen, int srclen,
 120                 void *bpi_ctx)
 121 {
 122         EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
 123         int encrypted_ivlen;
 124         uint8_t encrypted_iv[16];
 125         int i;
 126
 127         /* ECB method: encrypt the IV, then XOR this with plaintext */
 128         if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
 129                                                                 <= 0)
 130                 goto cipher_encrypt_err;
 131
 132         for (i = 0; i < srclen; i++)
 133                 *(dst+i) = *(src+i)^(encrypted_iv[i]);
 134
 135         return 0;
 136
 137 cipher_encrypt_err:
 138         PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt failed");
 139         return -EINVAL;
 140 }
 141
 142 /** Decrypt a single partial block
 143  *  Depends on openssl libcrypto
 144  *  Uses ECB+XOR to do CFB encryption, same result, more performant
 145  */
 146 static inline int
 147 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
 148                 uint8_t *iv, int ivlen, int srclen,
 149                 void *bpi_ctx)
 150 {
 151         EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
 152         int encrypted_ivlen;
 153         uint8_t encrypted_iv[16];
 154         int i;
 155
 156         /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
 157         if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
 158                                                                 <= 0)
 159                 goto cipher_decrypt_err;
 160
 161         for (i = 0; i < srclen; i++)
 162                 *(dst+i) = *(src+i)^(encrypted_iv[i]);
 163
 164         return 0;
 165
 166 cipher_decrypt_err:
 167         PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt for BPI IV failed");
 168         return -EINVAL;
 169 }
 170
 171 /** Creates a context in either AES or DES in ECB mode
 172  *  Depends on openssl libcrypto
 173  */
 174 static void *
 175 bpi_cipher_ctx_init(enum rte_crypto_cipher_algorithm cryptodev_algo,
 176                 enum rte_crypto_cipher_operation direction __rte_unused,
 177                                         uint8_t *key)
 178 {
 179         const EVP_CIPHER *algo = NULL;
 180         EVP_CIPHER_CTX *ctx = EVP_CIPHER_CTX_new();
 181
 182         if (ctx == NULL)
 183                 goto ctx_init_err;
 184
 185         if (cryptodev_algo == RTE_CRYPTO_CIPHER_DES_DOCSISBPI)
 186                 algo = EVP_des_ecb();
 187         else
 188                 algo = EVP_aes_128_ecb();
 189
 190         /* IV will be ECB encrypted whether direction is encrypt or decrypt*/
 191         if (EVP_EncryptInit_ex(ctx, algo, NULL, key, 0) != 1)
 192                 goto ctx_init_err;
 193
 194         return ctx;
 195
 196 ctx_init_err:
 197         if (ctx != NULL)
 198                 EVP_CIPHER_CTX_free(ctx);
 199         return NULL;
 200 }
 201
 202 /** Frees a context previously created
 203  *  Depends on openssl libcrypto
 204  */
 205 static void
 206 bpi_cipher_ctx_free(void *bpi_ctx)
 207 {
 208         if (bpi_ctx != NULL)
 209                 EVP_CIPHER_CTX_free((EVP_CIPHER_CTX *)bpi_ctx);
 210 }
 211
 212 static inline uint32_t
 213 adf_modulo(uint32_t data, uint32_t shift);
 214
 215 static inline int
 216 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
 217                 struct qat_crypto_op_cookie *qat_op_cookie);
 218
 219 void qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
 220                 void *session)
 221 {
 222         struct qat_session *sess = session;
 223         phys_addr_t cd_paddr;
 224
 225         PMD_INIT_FUNC_TRACE();
 226         if (sess) {
 227                 if (sess->bpi_ctx) {
 228                         bpi_cipher_ctx_free(sess->bpi_ctx);
 229                         sess->bpi_ctx = NULL;
 230                 }
 231                 cd_paddr = sess->cd_paddr;
 232                 memset(sess, 0, qat_crypto_sym_get_session_private_size(dev));
 233                 sess->cd_paddr = cd_paddr;
 234         } else
 235                 PMD_DRV_LOG(ERR, "NULL session");
 236 }
 237
 238 static int
 239 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
 240 {
 241         /* Cipher Only */
 242         if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
 243                 return ICP_QAT_FW_LA_CMD_CIPHER;
 244
 245         /* Authentication Only */
 246         if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
 247                 return ICP_QAT_FW_LA_CMD_AUTH;
 248
 249         /* AEAD */
 250         if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
 251                 if (xform->aead.op == RTE_CRYPTO_AEAD_OP_ENCRYPT)
 252                         return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
 253                 else
 254                         return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
 255         }
 256
 257         if (xform->next == NULL)
 258                 return -1;
 259
 260         /* Cipher then Authenticate */
 261         if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
 262                         xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
 263                 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
 264
 265         /* Authenticate then Cipher */
 266         if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
 267                         xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
 268                 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
 269
 270         return -1;
 271 }
 272
 273 static struct rte_crypto_auth_xform *
 274 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
 275 {
 276         do {
 277                 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
 278                         return &xform->auth;
 279
 280                 xform = xform->next;
 281         } while (xform);
 282
 283         return NULL;
 284 }
 285
 286 static struct rte_crypto_cipher_xform *
 287 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
 288 {
 289         do {
 290                 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
 291                         return &xform->cipher;
 292
 293                 xform = xform->next;
 294         } while (xform);
 295
 296         return NULL;
 297 }
 298 void *
 299 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
 300                 struct rte_crypto_sym_xform *xform, void *session_private)
 301 {
 302         struct qat_session *session = session_private;
 303         struct qat_pmd_private *internals = dev->data->dev_private;
 304         struct rte_crypto_cipher_xform *cipher_xform = NULL;
 305
 306         /* Get cipher xform from crypto xform chain */
 307         cipher_xform = qat_get_cipher_xform(xform);
 308
 309         session->cipher_iv.offset = cipher_xform->iv.offset;
 310         session->cipher_iv.length = cipher_xform->iv.length;
 311
 312         switch (cipher_xform->algo) {
 313         case RTE_CRYPTO_CIPHER_AES_CBC:
 314                 if (qat_alg_validate_aes_key(cipher_xform->key.length,
 315                                 &session->qat_cipher_alg) != 0) {
 316                         PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
 317                         goto error_out;
 318                 }
 319                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 320                 break;
 321         case RTE_CRYPTO_CIPHER_AES_CTR:
 322                 if (qat_alg_validate_aes_key(cipher_xform->key.length,
 323                                 &session->qat_cipher_alg) != 0) {
 324                         PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
 325                         goto error_out;
 326                 }
 327                 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
 328                 break;
 329         case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
 330                 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
 331                                         &session->qat_cipher_alg) != 0) {
 332                         PMD_DRV_LOG(ERR, "Invalid SNOW 3G cipher key size");
 333                         goto error_out;
 334                 }
 335                 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
 336                 break;
 337         case RTE_CRYPTO_CIPHER_NULL:
 338                 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
 339                 break;
 340         case RTE_CRYPTO_CIPHER_KASUMI_F8:
 341                 if (qat_alg_validate_kasumi_key(cipher_xform->key.length,
 342                                         &session->qat_cipher_alg) != 0) {
 343                         PMD_DRV_LOG(ERR, "Invalid KASUMI cipher key size");
 344                         goto error_out;
 345                 }
 346                 session->qat_mode = ICP_QAT_HW_CIPHER_F8_MODE;
 347                 break;
 348         case RTE_CRYPTO_CIPHER_3DES_CBC:
 349                 if (qat_alg_validate_3des_key(cipher_xform->key.length,
 350                                 &session->qat_cipher_alg) != 0) {
 351                         PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
 352                         goto error_out;
 353                 }
 354                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 355                 break;
 356         case RTE_CRYPTO_CIPHER_DES_CBC:
 357                 if (qat_alg_validate_des_key(cipher_xform->key.length,
 358                                 &session->qat_cipher_alg) != 0) {
 359                         PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
 360                         goto error_out;
 361                 }
 362                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 363                 break;
 364         case RTE_CRYPTO_CIPHER_3DES_CTR:
 365                 if (qat_alg_validate_3des_key(cipher_xform->key.length,
 366                                 &session->qat_cipher_alg) != 0) {
 367                         PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
 368                         goto error_out;
 369                 }
 370                 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
 371                 break;
 372         case RTE_CRYPTO_CIPHER_DES_DOCSISBPI:
 373                 session->bpi_ctx = bpi_cipher_ctx_init(
 374                                         cipher_xform->algo,
 375                                         cipher_xform->op,
 376                                         cipher_xform->key.data);
 377                 if (session->bpi_ctx == NULL) {
 378                         PMD_DRV_LOG(ERR, "failed to create DES BPI ctx");
 379                         goto error_out;
 380                 }
 381                 if (qat_alg_validate_des_key(cipher_xform->key.length,
 382                                 &session->qat_cipher_alg) != 0) {
 383                         PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
 384                         goto error_out;
 385                 }
 386                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 387                 break;
 388         case RTE_CRYPTO_CIPHER_AES_DOCSISBPI:
 389                 session->bpi_ctx = bpi_cipher_ctx_init(
 390                                         cipher_xform->algo,
 391                                         cipher_xform->op,
 392                                         cipher_xform->key.data);
 393                 if (session->bpi_ctx == NULL) {
 394                         PMD_DRV_LOG(ERR, "failed to create AES BPI ctx");
 395                         goto error_out;
 396                 }
 397                 if (qat_alg_validate_aes_docsisbpi_key(cipher_xform->key.length,
 398                                 &session->qat_cipher_alg) != 0) {
 399                         PMD_DRV_LOG(ERR, "Invalid AES DOCSISBPI key size");
 400                         goto error_out;
 401                 }
 402                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 403                 break;
 404         case RTE_CRYPTO_CIPHER_ZUC_EEA3:
 405                 if (!qat_is_cipher_alg_supported(
 406                         cipher_xform->algo, internals)) {
 407                         PMD_DRV_LOG(ERR, "%s not supported on this device",
 408                                 rte_crypto_cipher_algorithm_strings
 409                                         [cipher_xform->algo]);
 410                         goto error_out;
 411                 }
 412                 if (qat_alg_validate_zuc_key(cipher_xform->key.length,
 413                                 &session->qat_cipher_alg) != 0) {
 414                         PMD_DRV_LOG(ERR, "Invalid ZUC cipher key size");
 415                         goto error_out;
 416                 }
 417                 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
 418                 break;
 419         case RTE_CRYPTO_CIPHER_3DES_ECB:
 420         case RTE_CRYPTO_CIPHER_AES_ECB:
 421         case RTE_CRYPTO_CIPHER_AES_F8:
 422         case RTE_CRYPTO_CIPHER_AES_XTS:
 423         case RTE_CRYPTO_CIPHER_ARC4:
 424                 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported Cipher alg %u",
 425                                 cipher_xform->algo);
 426                 goto error_out;
 427         default:
 428                 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
 429                                 cipher_xform->algo);
 430                 goto error_out;
 431         }
 432
 433         if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
 434                 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
 435         else
 436                 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
 437
 438         if (qat_alg_aead_session_create_content_desc_cipher(session,
 439                                                 cipher_xform->key.data,
 440                                                 cipher_xform->key.length))
 441                 goto error_out;
 442
 443         return session;
 444
 445 error_out:
 446         if (session->bpi_ctx) {
 447                 bpi_cipher_ctx_free(session->bpi_ctx);
 448                 session->bpi_ctx = NULL;
 449         }
 450         return NULL;
 451 }
 452
 453
 454 void *
 455 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
 456                 struct rte_crypto_sym_xform *xform, void *session_private)
 457 {
 458         struct qat_session *session = session_private;
 459
 460         int qat_cmd_id;
 461         PMD_INIT_FUNC_TRACE();
 462
 463         /* Get requested QAT command id */
 464         qat_cmd_id = qat_get_cmd_id(xform);
 465         if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
 466                 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
 467                 goto error_out;
 468         }
 469         session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
 470         switch (session->qat_cmd) {
 471         case ICP_QAT_FW_LA_CMD_CIPHER:
 472         session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
 473                 break;
 474         case ICP_QAT_FW_LA_CMD_AUTH:
 475         session = qat_crypto_sym_configure_session_auth(dev, xform, session);
 476                 break;
 477         case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
 478                 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD)
 479                         session = qat_crypto_sym_configure_session_aead(xform,
 480                                         session);
 481                 else {
 482                         session = qat_crypto_sym_configure_session_cipher(dev,
 483                                         xform, session);
 484                         session = qat_crypto_sym_configure_session_auth(dev,
 485                                         xform, session);
 486                 }
 487                 break;
 488         case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
 489                 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD)
 490                         session = qat_crypto_sym_configure_session_aead(xform,
 491                                         session);
 492                 else {
 493                         session = qat_crypto_sym_configure_session_auth(dev,
 494                                         xform, session);
 495                         session = qat_crypto_sym_configure_session_cipher(dev,
 496                                         xform, session);
 497                 }
 498                 break;
 499         case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
 500         case ICP_QAT_FW_LA_CMD_TRNG_TEST:
 501         case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
 502         case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
 503         case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
 504         case ICP_QAT_FW_LA_CMD_MGF1:
 505         case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
 506         case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
 507         case ICP_QAT_FW_LA_CMD_DELIMITER:
 508         PMD_DRV_LOG(ERR, "Unsupported Service %u",
 509                 session->qat_cmd);
 510                 goto error_out;
 511         default:
 512         PMD_DRV_LOG(ERR, "Unsupported Service %u",
 513                 session->qat_cmd);
 514                 goto error_out;
 515         }
 516
 517         return session;
 518
 519 error_out:
 520         return NULL;
 521 }
 522
 523 struct qat_session *
 524 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
 525                                 struct rte_crypto_sym_xform *xform,
 526                                 struct qat_session *session_private)
 527 {
 528
 529         struct qat_session *session = session_private;
 530         struct rte_crypto_auth_xform *auth_xform = NULL;
 531         struct qat_pmd_private *internals = dev->data->dev_private;
 532         auth_xform = qat_get_auth_xform(xform);
 533         uint8_t *key_data = auth_xform->key.data;
 534         uint8_t key_length = auth_xform->key.length;
 535
 536         switch (auth_xform->algo) {
 537         case RTE_CRYPTO_AUTH_SHA1_HMAC:
 538                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
 539                 break;
 540         case RTE_CRYPTO_AUTH_SHA224_HMAC:
 541                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
 542                 break;
 543         case RTE_CRYPTO_AUTH_SHA256_HMAC:
 544                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
 545                 break;
 546         case RTE_CRYPTO_AUTH_SHA384_HMAC:
 547                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;
 548                 break;
 549         case RTE_CRYPTO_AUTH_SHA512_HMAC:
 550                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
 551                 break;
 552         case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
 553                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
 554                 break;
 555         case RTE_CRYPTO_AUTH_AES_GMAC:
 556                 if (qat_alg_validate_aes_key(auth_xform->key.length,
 557                                 &session->qat_cipher_alg) != 0) {
 558                         PMD_DRV_LOG(ERR, "Invalid AES key size");
 559                         goto error_out;
 560                 }
 561                 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
 562                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
 563
 564                 break;
 565         case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
 566                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
 567                 break;
 568         case RTE_CRYPTO_AUTH_MD5_HMAC:
 569                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
 570                 break;
 571         case RTE_CRYPTO_AUTH_NULL:
 572                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;
 573                 break;
 574         case RTE_CRYPTO_AUTH_KASUMI_F9:
 575                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_KASUMI_F9;
 576                 break;
 577         case RTE_CRYPTO_AUTH_ZUC_EIA3:
 578                 if (!qat_is_auth_alg_supported(auth_xform->algo, internals)) {
 579                         PMD_DRV_LOG(ERR, "%s not supported on this device",
 580                                 rte_crypto_auth_algorithm_strings
 581                                 [auth_xform->algo]);
 582                         goto error_out;
 583                 }
 584                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3;
 585                 break;
 586         case RTE_CRYPTO_AUTH_SHA1:
 587         case RTE_CRYPTO_AUTH_SHA256:
 588         case RTE_CRYPTO_AUTH_SHA512:
 589         case RTE_CRYPTO_AUTH_SHA224:
 590         case RTE_CRYPTO_AUTH_SHA384:
 591         case RTE_CRYPTO_AUTH_MD5:
 592         case RTE_CRYPTO_AUTH_AES_CMAC:
 593         case RTE_CRYPTO_AUTH_AES_CBC_MAC:
 594                 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
 595                                 auth_xform->algo);
 596                 goto error_out;
 597         default:
 598                 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
 599                                 auth_xform->algo);
 600                 goto error_out;
 601         }
 602
 603         session->auth_iv.offset = auth_xform->iv.offset;
 604         session->auth_iv.length = auth_xform->iv.length;
 605
 606         if (auth_xform->algo == RTE_CRYPTO_AUTH_AES_GMAC) {
 607                 if (auth_xform->op == RTE_CRYPTO_AUTH_OP_GENERATE) {
 608                         session->qat_cmd = ICP_QAT_FW_LA_CMD_CIPHER_HASH;
 609                         session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
 610                         /*
 611                          * It needs to create cipher desc content first,
 612                          * then authentication
 613                          */
 614                         if (qat_alg_aead_session_create_content_desc_cipher(session,
 615                                                 auth_xform->key.data,
 616                                                 auth_xform->key.length))
 617                                 goto error_out;
 618
 619                         if (qat_alg_aead_session_create_content_desc_auth(session,
 620                                                 key_data,
 621                                                 key_length,
 622                                                 0,
 623                                                 auth_xform->digest_length,
 624                                                 auth_xform->op))
 625                                 goto error_out;
 626                 } else {
 627                         session->qat_cmd = ICP_QAT_FW_LA_CMD_HASH_CIPHER;
 628                         session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
 629                         /*
 630                          * It needs to create authentication desc content first,
 631                          * then cipher
 632                          */
 633                         if (qat_alg_aead_session_create_content_desc_auth(session,
 634                                         key_data,
 635                                         key_length,
 636                                         0,
 637                                         auth_xform->digest_length,
 638                                         auth_xform->op))
 639                                 goto error_out;
 640
 641                         if (qat_alg_aead_session_create_content_desc_cipher(session,
 642                                                 auth_xform->key.data,
 643                                                 auth_xform->key.length))
 644                                 goto error_out;
 645                 }
 646                 /* Restore to authentication only only */
 647                 session->qat_cmd = ICP_QAT_FW_LA_CMD_AUTH;
 648         } else {
 649                 if (qat_alg_aead_session_create_content_desc_auth(session,
 650                                 key_data,
 651                                 key_length,
 652                                 0,
 653                                 auth_xform->digest_length,
 654                                 auth_xform->op))
 655                         goto error_out;
 656         }
 657
 658         session->digest_length = auth_xform->digest_length;
 659         return session;
 660
 661 error_out:
 662         return NULL;
 663 }
 664
 665 struct qat_session *
 666 qat_crypto_sym_configure_session_aead(struct rte_crypto_sym_xform *xform,
 667                                 struct qat_session *session_private)
 668 {
 669         struct qat_session *session = session_private;
 670         struct rte_crypto_aead_xform *aead_xform = &xform->aead;
 671
 672         /*
 673          * Store AEAD IV parameters as cipher IV,
 674          * to avoid unnecessary memory usage
 675          */
 676         session->cipher_iv.offset = xform->aead.iv.offset;
 677         session->cipher_iv.length = xform->aead.iv.length;
 678
 679         switch (aead_xform->algo) {
 680         case RTE_CRYPTO_AEAD_AES_GCM:
 681                 if (qat_alg_validate_aes_key(aead_xform->key.length,
 682                                 &session->qat_cipher_alg) != 0) {
 683                         PMD_DRV_LOG(ERR, "Invalid AES key size");
 684                         goto error_out;
 685                 }
 686                 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
 687                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
 688                 break;
 689         case RTE_CRYPTO_AEAD_AES_CCM:
 690                 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported AEAD alg %u",
 691                                 aead_xform->algo);
 692                 goto error_out;
 693         default:
 694                 PMD_DRV_LOG(ERR, "Crypto: Undefined AEAD specified %u\n",
 695                                 aead_xform->algo);
 696                 goto error_out;
 697         }
 698
 699         if (aead_xform->op == RTE_CRYPTO_AEAD_OP_ENCRYPT) {
 700                 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
 701                 /*
 702                  * It needs to create cipher desc content first,
 703                  * then authentication
 704                  */
 705                 if (qat_alg_aead_session_create_content_desc_cipher(session,
 706                                         aead_xform->key.data,
 707                                         aead_xform->key.length))
 708                         goto error_out;
 709
 710                 if (qat_alg_aead_session_create_content_desc_auth(session,
 711                                         aead_xform->key.data,
 712                                         aead_xform->key.length,
 713                                         aead_xform->add_auth_data_length,
 714                                         aead_xform->digest_length,
 715                                         RTE_CRYPTO_AUTH_OP_GENERATE))
 716                         goto error_out;
 717         } else {
 718                 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
 719                 /*
 720                  * It needs to create authentication desc content first,
 721                  * then cipher
 722                  */
 723                 if (qat_alg_aead_session_create_content_desc_auth(session,
 724                                         aead_xform->key.data,
 725                                         aead_xform->key.length,
 726                                         aead_xform->add_auth_data_length,
 727                                         aead_xform->digest_length,
 728                                         RTE_CRYPTO_AUTH_OP_VERIFY))
 729                         goto error_out;
 730
 731                 if (qat_alg_aead_session_create_content_desc_cipher(session,
 732                                         aead_xform->key.data,
 733                                         aead_xform->key.length))
 734                         goto error_out;
 735         }
 736
 737         session->digest_length = aead_xform->digest_length;
 738         return session;
 739
 740 error_out:
 741         return NULL;
 742 }
 743
 744 unsigned qat_crypto_sym_get_session_private_size(
 745                 struct rte_cryptodev *dev __rte_unused)
 746 {
 747         return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
 748 }
 749
 750 static inline uint32_t
 751 qat_bpicipher_preprocess(struct qat_session *ctx,
 752                                 struct rte_crypto_op *op)
 753 {
 754         uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
 755         struct rte_crypto_sym_op *sym_op = op->sym;
 756         uint8_t last_block_len = sym_op->cipher.data.length % block_len;
 757
 758         if (last_block_len &&
 759                         ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
 760
 761                 /* Decrypt last block */
 762                 uint8_t *last_block, *dst, *iv;
 763                 uint32_t last_block_offset = sym_op->cipher.data.offset +
 764                                 sym_op->cipher.data.length - last_block_len;
 765                 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
 766                                 uint8_t *, last_block_offset);
 767
 768                 if (unlikely(sym_op->m_dst != NULL))
 769                         /* out-of-place operation (OOP) */
 770                         dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
 771                                                 uint8_t *, last_block_offset);
 772                 else
 773                         dst = last_block;
 774
 775                 if (last_block_len < sym_op->cipher.data.length)
 776                         /* use previous block ciphertext as IV */
 777                         iv = last_block - block_len;
 778                 else
 779                         /* runt block, i.e. less than one full block */
 780                         iv = rte_crypto_op_ctod_offset(op, uint8_t *,
 781                                         ctx->cipher_iv.offset);
 782
 783 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 784                 rte_hexdump(stdout, "BPI: src before pre-process:", last_block,
 785                         last_block_len);
 786                 if (sym_op->m_dst != NULL)
 787                         rte_hexdump(stdout, "BPI: dst before pre-process:", dst,
 788                                 last_block_len);
 789 #endif
 790                 bpi_cipher_decrypt(last_block, dst, iv, block_len,
 791                                 last_block_len, ctx->bpi_ctx);
 792 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 793                 rte_hexdump(stdout, "BPI: src after pre-process:", last_block,
 794                         last_block_len);
 795                 if (sym_op->m_dst != NULL)
 796                         rte_hexdump(stdout, "BPI: dst after pre-process:", dst,
 797                                 last_block_len);
 798 #endif
 799         }
 800
 801         return sym_op->cipher.data.length - last_block_len;
 802 }
 803
 804 static inline uint32_t
 805 qat_bpicipher_postprocess(struct qat_session *ctx,
 806                                 struct rte_crypto_op *op)
 807 {
 808         uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
 809         struct rte_crypto_sym_op *sym_op = op->sym;
 810         uint8_t last_block_len = sym_op->cipher.data.length % block_len;
 811
 812         if (last_block_len > 0 &&
 813                         ctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
 814
 815                 /* Encrypt last block */
 816                 uint8_t *last_block, *dst, *iv;
 817                 uint32_t last_block_offset;
 818
 819                 last_block_offset = sym_op->cipher.data.offset +
 820                                 sym_op->cipher.data.length - last_block_len;
 821                 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
 822                                 uint8_t *, last_block_offset);
 823
 824                 if (unlikely(sym_op->m_dst != NULL))
 825                         /* out-of-place operation (OOP) */
 826                         dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
 827                                                 uint8_t *, last_block_offset);
 828                 else
 829                         dst = last_block;
 830
 831                 if (last_block_len < sym_op->cipher.data.length)
 832                         /* use previous block ciphertext as IV */
 833                         iv = dst - block_len;
 834                 else
 835                         /* runt block, i.e. less than one full block */
 836                         iv = rte_crypto_op_ctod_offset(op, uint8_t *,
 837                                         ctx->cipher_iv.offset);
 838
 839 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
 840                 rte_hexdump(stdout, "BPI: src before post-process:", last_block,
 841                         last_block_len);
 842                 if (sym_op->m_dst != NULL)
 843                         rte_hexdump(stdout, "BPI: dst before post-process:",
 844                                         dst, last_block_len);
 845 #endif
 846                 bpi_cipher_encrypt(last_block, dst, iv, block_len,
 847                                 last_block_len, ctx->bpi_ctx);
 848 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
 849                 rte_hexdump(stdout, "BPI: src after post-process:", last_block,
 850                         last_block_len);
 851                 if (sym_op->m_dst != NULL)
 852                         rte_hexdump(stdout, "BPI: dst after post-process:", dst,
 853                                 last_block_len);
 854 #endif
 855         }
 856         return sym_op->cipher.data.length - last_block_len;
 857 }
 858
 859 uint16_t
 860 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
 861                 uint16_t nb_ops)
 862 {
 863         register struct qat_queue *queue;
 864         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 865         register uint32_t nb_ops_sent = 0;
 866         register struct rte_crypto_op **cur_op = ops;
 867         register int ret;
 868         uint16_t nb_ops_possible = nb_ops;
 869         register uint8_t *base_addr;
 870         register uint32_t tail;
 871         int overflow;
 872
 873         if (unlikely(nb_ops == 0))
 874                 return 0;
 875
 876         /* read params used a lot in main loop into registers */
 877         queue = &(tmp_qp->tx_q);
 878         base_addr = (uint8_t *)queue->base_addr;
 879         tail = queue->tail;
 880
 881         /* Find how many can actually fit on the ring */
 882         overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
 883                                 - queue->max_inflights;
 884         if (overflow > 0) {
 885                 rte_atomic16_sub(&tmp_qp->inflights16, overflow);
 886                 nb_ops_possible = nb_ops - overflow;
 887                 if (nb_ops_possible == 0)
 888                         return 0;
 889         }
 890
 891         while (nb_ops_sent != nb_ops_possible) {
 892                 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail,
 893                                 tmp_qp->op_cookies[tail / queue->msg_size]);
 894                 if (ret != 0) {
 895                         tmp_qp->stats.enqueue_err_count++;
 896                         /*
 897                          * This message cannot be enqueued,
 898                          * decrease number of ops that wasn't sent
 899                          */
 900                         rte_atomic16_sub(&tmp_qp->inflights16,
 901                                         nb_ops_possible - nb_ops_sent);
 902                         if (nb_ops_sent == 0)
 903                                 return 0;
 904                         goto kick_tail;
 905                 }
 906
 907                 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
 908                 nb_ops_sent++;
 909                 cur_op++;
 910         }
 911 kick_tail:
 912         WRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,
 913                         queue->hw_queue_number, tail);
 914         queue->tail = tail;
 915         tmp_qp->stats.enqueued_count += nb_ops_sent;
 916         return nb_ops_sent;
 917 }
 918
 919 uint16_t
 920 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
 921                 uint16_t nb_ops)
 922 {
 923         struct qat_queue *queue;
 924         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 925         uint32_t msg_counter = 0;
 926         struct rte_crypto_op *rx_op;
 927         struct icp_qat_fw_comn_resp *resp_msg;
 928
 929         queue = &(tmp_qp->rx_q);
 930         resp_msg = (struct icp_qat_fw_comn_resp *)
 931                         ((uint8_t *)queue->base_addr + queue->head);
 932
 933         while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
 934                         msg_counter != nb_ops) {
 935                 rx_op = (struct rte_crypto_op *)(uintptr_t)
 936                                 (resp_msg->opaque_data);
 937
 938 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
 939                 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
 940                         sizeof(struct icp_qat_fw_comn_resp));
 941
 942 #endif
 943                 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
 944                                 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
 945                                         resp_msg->comn_hdr.comn_status)) {
 946                         rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
 947                 } else {
 948                         struct qat_session *sess = (struct qat_session *)
 949                                                 (rx_op->sym->session->_private);
 950                         if (sess->bpi_ctx)
 951                                 qat_bpicipher_postprocess(sess, rx_op);
 952                         rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
 953                 }
 954
 955                 *(uint32_t *)resp_msg = ADF_RING_EMPTY_SIG;
 956                 queue->head = adf_modulo(queue->head +
 957                                 queue->msg_size,
 958                                 ADF_RING_SIZE_MODULO(queue->queue_size));
 959                 resp_msg = (struct icp_qat_fw_comn_resp *)
 960                                         ((uint8_t *)queue->base_addr +
 961                                                         queue->head);
 962                 *ops = rx_op;
 963                 ops++;
 964                 msg_counter++;
 965         }
 966         if (msg_counter > 0) {
 967                 WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
 968                                         queue->hw_bundle_number,
 969                                         queue->hw_queue_number, queue->head);
 970                 rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
 971                 tmp_qp->stats.dequeued_count += msg_counter;
 972         }
 973         return msg_counter;
 974 }
 975
 976 static inline int
 977 qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buff_start,
 978                 struct qat_alg_buf_list *list, uint32_t data_len)
 979 {
 980         int nr = 1;
 981
 982         uint32_t buf_len = rte_pktmbuf_mtophys(buf) -
 983                         buff_start + rte_pktmbuf_data_len(buf);
 984
 985         list->bufers[0].addr = buff_start;
 986         list->bufers[0].resrvd = 0;
 987         list->bufers[0].len = buf_len;
 988
 989         if (data_len <= buf_len) {
 990                 list->num_bufs = nr;
 991                 list->bufers[0].len = data_len;
 992                 return 0;
 993         }
 994
 995         buf = buf->next;
 996         while (buf) {
 997                 if (unlikely(nr == QAT_SGL_MAX_NUMBER)) {
 998                         PMD_DRV_LOG(ERR, "QAT PMD exceeded size of QAT SGL"
 999                                         " entry(%u)",
1000                                         QAT_SGL_MAX_NUMBER);
1001                         return -EINVAL;
1002                 }
1003
1004                 list->bufers[nr].len = rte_pktmbuf_data_len(buf);
1005                 list->bufers[nr].resrvd = 0;
1006                 list->bufers[nr].addr = rte_pktmbuf_mtophys(buf);
1007
1008                 buf_len += list->bufers[nr].len;
1009                 buf = buf->next;
1010
1011                 if (buf_len > data_len) {
1012                         list->bufers[nr].len -=
1013                                 buf_len - data_len;
1014                         buf = NULL;
1015                 }
1016                 ++nr;
1017         }
1018         list->num_bufs = nr;
1019
1020         return 0;
1021 }
1022
1023 static inline void
1024 set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,
1025                 struct icp_qat_fw_la_cipher_req_params *cipher_param,
1026                 struct rte_crypto_op *op,
1027                 struct icp_qat_fw_la_bulk_req *qat_req)
1028 {
1029         /* copy IV into request if it fits */
1030         if (iv_length <= sizeof(cipher_param->u.cipher_IV_array)) {
1031                 rte_memcpy(cipher_param->u.cipher_IV_array,
1032                                 rte_crypto_op_ctod_offset(op, uint8_t *,
1033                                         iv_offset),
1034                                 iv_length);
1035         } else {
1036                 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
1037                                 qat_req->comn_hdr.serv_specif_flags,
1038                                 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
1039                 cipher_param->u.s.cipher_IV_ptr =
1040                                 rte_crypto_op_ctophys_offset(op,
1041                                         iv_offset);
1042         }
1043 }
1044
1045 static inline int
1046 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
1047                 struct qat_crypto_op_cookie *qat_op_cookie)
1048 {
1049         int ret = 0;
1050         struct qat_session *ctx;
1051         struct icp_qat_fw_la_cipher_req_params *cipher_param;
1052         struct icp_qat_fw_la_auth_req_params *auth_param;
1053         register struct icp_qat_fw_la_bulk_req *qat_req;
1054         uint8_t do_auth = 0, do_cipher = 0, do_aead = 0;
1055         uint32_t cipher_len = 0, cipher_ofs = 0;
1056         uint32_t auth_len = 0, auth_ofs = 0;
1057         uint32_t min_ofs = 0;
1058         uint64_t src_buf_start = 0, dst_buf_start = 0;
1059         uint8_t do_sgl = 0;
1060
1061 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1062         if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
1063                 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
1064                                 "operation requests, op (%p) is not a "
1065                                 "symmetric operation.", op);
1066                 return -EINVAL;
1067         }
1068 #endif
1069         if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
1070                 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
1071                                 " requests, op (%p) is sessionless.", op);
1072                 return -EINVAL;
1073         }
1074
1075         if (unlikely(op->sym->session->dev_type != RTE_CRYPTODEV_QAT_SYM_PMD)) {
1076                 PMD_DRV_LOG(ERR, "Session was not created for this device");
1077                 return -EINVAL;
1078         }
1079
1080         ctx = (struct qat_session *)op->sym->session->_private;
1081         qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
1082         rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
1083         qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
1084         cipher_param = (void *)&qat_req->serv_specif_rqpars;
1085         auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
1086
1087         if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
1088                         ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
1089                 /* AES-GCM */
1090                 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1091                                 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1092                         do_aead = 1;
1093                 } else {
1094                         do_auth = 1;
1095                         do_cipher = 1;
1096                 }
1097         } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
1098                 do_auth = 1;
1099                 do_cipher = 0;
1100         } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
1101                 do_auth = 0;
1102                 do_cipher = 1;
1103         }
1104
1105         if (do_cipher) {
1106
1107                 if (ctx->qat_cipher_alg ==
1108                                          ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
1109                         ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
1110                         ctx->qat_cipher_alg ==
1111                                 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
1112
1113                         if (unlikely(
1114                                 (cipher_param->cipher_length % BYTE_LENGTH != 0)
1115                                  || (cipher_param->cipher_offset
1116                                                         % BYTE_LENGTH != 0))) {
1117                                 PMD_DRV_LOG(ERR,
1118                   "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
1119                                 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1120                                 return -EINVAL;
1121                         }
1122                         cipher_len = op->sym->cipher.data.length >> 3;
1123                         cipher_ofs = op->sym->cipher.data.offset >> 3;
1124
1125                 } else if (ctx->bpi_ctx) {
1126                         /* DOCSIS - only send complete blocks to device
1127                          * Process any partial block using CFB mode.
1128                          * Even if 0 complete blocks, still send this to device
1129                          * to get into rx queue for post-process and dequeuing
1130                          */
1131                         cipher_len = qat_bpicipher_preprocess(ctx, op);
1132                         cipher_ofs = op->sym->cipher.data.offset;
1133                 } else {
1134                         cipher_len = op->sym->cipher.data.length;
1135                         cipher_ofs = op->sym->cipher.data.offset;
1136                 }
1137
1138                 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
1139                                 cipher_param, op, qat_req);
1140                 min_ofs = cipher_ofs;
1141         }
1142
1143         if (do_auth) {
1144
1145                 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
1146                         ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
1147                         ctx->qat_hash_alg ==
1148                                 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
1149                         if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0)
1150                                 || (auth_param->auth_len % BYTE_LENGTH != 0))) {
1151                                 PMD_DRV_LOG(ERR,
1152                 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
1153                                 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1154                                 return -EINVAL;
1155                         }
1156                         auth_ofs = op->sym->auth.data.offset >> 3;
1157                         auth_len = op->sym->auth.data.length >> 3;
1158
1159                         if (ctx->qat_hash_alg ==
1160                                         ICP_QAT_HW_AUTH_ALGO_KASUMI_F9) {
1161                                 if (do_cipher) {
1162                                         auth_len = auth_len + auth_ofs + 1 -
1163                                                 ICP_QAT_HW_KASUMI_BLK_SZ;
1164                                         auth_ofs = ICP_QAT_HW_KASUMI_BLK_SZ;
1165                                 } else {
1166                                         auth_len = auth_len + auth_ofs + 1;
1167                                         auth_ofs = 0;
1168                                 }
1169                         } else
1170                                 auth_param->u1.aad_adr =
1171                                         rte_crypto_op_ctophys_offset(op,
1172                                                         ctx->auth_iv.offset);
1173
1174                 } else if (ctx->qat_hash_alg ==
1175                                         ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1176                                 ctx->qat_hash_alg ==
1177                                         ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1178                         /* AES-GMAC */
1179                         set_cipher_iv(ctx->auth_iv.length,
1180                                 ctx->auth_iv.offset,
1181                                 cipher_param, op, qat_req);
1182                 } else {
1183                         auth_ofs = op->sym->auth.data.offset;
1184                         auth_len = op->sym->auth.data.length;
1185
1186                 }
1187                 min_ofs = auth_ofs;
1188
1189                 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
1190
1191         }
1192
1193         if (do_aead) {
1194                 cipher_len = op->sym->aead.data.length;
1195                 cipher_ofs = op->sym->aead.data.offset;
1196                 auth_len = op->sym->aead.data.length;
1197                 auth_ofs = op->sym->aead.data.offset;
1198
1199                 auth_param->u1.aad_adr = op->sym->aead.aad.phys_addr;
1200                 auth_param->auth_res_addr = op->sym->aead.digest.phys_addr;
1201                 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
1202                                 cipher_param, op, qat_req);
1203                 min_ofs = op->sym->aead.data.offset;
1204         }
1205
1206         if (op->sym->m_src->next || (op->sym->m_dst && op->sym->m_dst->next))
1207                 do_sgl = 1;
1208
1209         /* adjust for chain case */
1210         if (do_cipher && do_auth)
1211                 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
1212
1213         if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
1214                 min_ofs = 0;
1215
1216         if (unlikely(op->sym->m_dst != NULL)) {
1217                 /* Out-of-place operation (OOP)
1218                  * Don't align DMA start. DMA the minimum data-set
1219                  * so as not to overwrite data in dest buffer
1220                  */
1221                 src_buf_start =
1222                         rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs);
1223                 dst_buf_start =
1224                         rte_pktmbuf_mtophys_offset(op->sym->m_dst, min_ofs);
1225
1226         } else {
1227                 /* In-place operation
1228                  * Start DMA at nearest aligned address below min_ofs
1229                  */
1230                 src_buf_start =
1231                         rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs)
1232                                                 & QAT_64_BTYE_ALIGN_MASK;
1233
1234                 if (unlikely((rte_pktmbuf_mtophys(op->sym->m_src) -
1235                                         rte_pktmbuf_headroom(op->sym->m_src))
1236                                                         > src_buf_start)) {
1237                         /* alignment has pushed addr ahead of start of mbuf
1238                          * so revert and take the performance hit
1239                          */
1240                         src_buf_start =
1241                                 rte_pktmbuf_mtophys_offset(op->sym->m_src,
1242                                                                 min_ofs);
1243                 }
1244                 dst_buf_start = src_buf_start;
1245         }
1246
1247         if (do_cipher || do_aead) {
1248                 cipher_param->cipher_offset =
1249                                 (uint32_t)rte_pktmbuf_mtophys_offset(
1250                                 op->sym->m_src, cipher_ofs) - src_buf_start;
1251                 cipher_param->cipher_length = cipher_len;
1252         } else {
1253                 cipher_param->cipher_offset = 0;
1254                 cipher_param->cipher_length = 0;
1255         }
1256
1257         if (do_auth || do_aead) {
1258                 auth_param->auth_off = (uint32_t)rte_pktmbuf_mtophys_offset(
1259                                 op->sym->m_src, auth_ofs) - src_buf_start;
1260                 auth_param->auth_len = auth_len;
1261         } else {
1262                 auth_param->auth_off = 0;
1263                 auth_param->auth_len = 0;
1264         }
1265
1266         qat_req->comn_mid.dst_length =
1267                 qat_req->comn_mid.src_length =
1268                 (cipher_param->cipher_offset + cipher_param->cipher_length)
1269                 > (auth_param->auth_off + auth_param->auth_len) ?
1270                 (cipher_param->cipher_offset + cipher_param->cipher_length)
1271                 : (auth_param->auth_off + auth_param->auth_len);
1272
1273         if (do_sgl) {
1274
1275                 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
1276                                 QAT_COMN_PTR_TYPE_SGL);
1277                 ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
1278                                 &qat_op_cookie->qat_sgl_list_src,
1279                                 qat_req->comn_mid.src_length);
1280                 if (ret) {
1281                         PMD_DRV_LOG(ERR, "QAT PMD Cannot fill sgl array");
1282                         return ret;
1283                 }
1284
1285                 if (likely(op->sym->m_dst == NULL))
1286                         qat_req->comn_mid.dest_data_addr =
1287                                 qat_req->comn_mid.src_data_addr =
1288                                 qat_op_cookie->qat_sgl_src_phys_addr;
1289                 else {
1290                         ret = qat_sgl_fill_array(op->sym->m_dst,
1291                                         dst_buf_start,
1292                                         &qat_op_cookie->qat_sgl_list_dst,
1293                                                 qat_req->comn_mid.dst_length);
1294
1295                         if (ret) {
1296                                 PMD_DRV_LOG(ERR, "QAT PMD Cannot "
1297                                                 "fill sgl array");
1298                                 return ret;
1299                         }
1300
1301                         qat_req->comn_mid.src_data_addr =
1302                                 qat_op_cookie->qat_sgl_src_phys_addr;
1303                         qat_req->comn_mid.dest_data_addr =
1304                                         qat_op_cookie->qat_sgl_dst_phys_addr;
1305                 }
1306         } else {
1307                 qat_req->comn_mid.src_data_addr = src_buf_start;
1308                 qat_req->comn_mid.dest_data_addr = dst_buf_start;
1309         }
1310
1311         if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1312                         ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1313                 if (ctx->cipher_iv.length == 12 ||
1314                                 ctx->auth_iv.length == 12) {
1315                         /*
1316                          * For GCM a 12 byte IV is allowed,
1317                          * but we need to inform the f/w
1318                          */
1319                         ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1320                                 qat_req->comn_hdr.serv_specif_flags,
1321                                 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1322                 }
1323                 /* GMAC */
1324                 if (!do_aead) {
1325                         qat_req->comn_mid.dst_length =
1326                                 qat_req->comn_mid.src_length =
1327                                         rte_pktmbuf_data_len(op->sym->m_src);
1328                         auth_param->u1.aad_adr = 0;
1329                         auth_param->auth_len = op->sym->auth.data.length;
1330                         auth_param->auth_off = op->sym->auth.data.offset;
1331                         auth_param->u2.aad_sz = 0;
1332                 }
1333         }
1334
1335 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1336         rte_hexdump(stdout, "qat_req:", qat_req,
1337                         sizeof(struct icp_qat_fw_la_bulk_req));
1338         rte_hexdump(stdout, "src_data:",
1339                         rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
1340                         rte_pktmbuf_data_len(op->sym->m_src));
1341         if (do_cipher) {
1342                 uint8_t *cipher_iv_ptr = rte_crypto_op_ctod_offset(op,
1343                                                 uint8_t *,
1344                                                 ctx->cipher_iv.offset);
1345                 rte_hexdump(stdout, "cipher iv:", cipher_iv_ptr,
1346                                 ctx->cipher_iv.length);
1347         }
1348
1349         if (do_auth) {
1350                 if (ctx->auth_iv.length) {
1351                         uint8_t *auth_iv_ptr = rte_crypto_op_ctod_offset(op,
1352                                                         uint8_t *,
1353                                                         ctx->auth_iv.offset);
1354                         rte_hexdump(stdout, "auth iv:", auth_iv_ptr,
1355                                                 ctx->auth_iv.length);
1356                 }
1357                 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
1358                                 ctx->digest_length);
1359         }
1360
1361         if (do_aead) {
1362                 rte_hexdump(stdout, "digest:", op->sym->aead.digest.data,
1363                                 ctx->digest_length);
1364                 rte_hexdump(stdout, "aad:", op->sym->aead.aad.data,
1365                                 ctx->aad_len);
1366         }
1367 #endif
1368         return 0;
1369 }
1370
1371 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
1372 {
1373         uint32_t div = data >> shift;
1374         uint32_t mult = div << shift;
1375
1376         return data - mult;
1377 }
1378
1379 void qat_crypto_sym_session_init(struct rte_mempool *mp, void *sym_sess)
1380 {
1381         struct rte_cryptodev_sym_session *sess = sym_sess;
1382         struct qat_session *s = (void *)sess->_private;
1383
1384         PMD_INIT_FUNC_TRACE();
1385         s->cd_paddr = rte_mempool_virt2phy(mp, sess) +
1386                 offsetof(struct qat_session, cd) +
1387                 offsetof(struct rte_cryptodev_sym_session, _private);
1388 }
1389
1390 int qat_dev_config(__rte_unused struct rte_cryptodev *dev,
1391                 __rte_unused struct rte_cryptodev_config *config)
1392 {
1393         PMD_INIT_FUNC_TRACE();
1394         return 0;
1395 }
1396
1397 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
1398 {
1399         PMD_INIT_FUNC_TRACE();
1400         return 0;
1401 }
1402
1403 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
1404 {
1405         PMD_INIT_FUNC_TRACE();
1406 }
1407
1408 int qat_dev_close(struct rte_cryptodev *dev)
1409 {
1410         int i, ret;
1411
1412         PMD_INIT_FUNC_TRACE();
1413
1414         for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1415                 ret = qat_crypto_sym_qp_release(dev, i);
1416                 if (ret < 0)
1417                         return ret;
1418         }
1419
1420         return 0;
1421 }
1422
1423 void qat_dev_info_get(struct rte_cryptodev *dev,
1424                         struct rte_cryptodev_info *info)
1425 {
1426         struct qat_pmd_private *internals = dev->data->dev_private;
1427
1428         PMD_INIT_FUNC_TRACE();
1429         if (info != NULL) {
1430                 info->max_nb_queue_pairs =
1431                                 ADF_NUM_SYM_QPS_PER_BUNDLE *
1432                                 ADF_NUM_BUNDLES_PER_DEV;
1433                 info->feature_flags = dev->feature_flags;
1434                 info->capabilities = internals->qat_dev_capabilities;
1435                 info->sym.max_nb_sessions = internals->max_nb_sessions;
1436                 info->dev_type = RTE_CRYPTODEV_QAT_SYM_PMD;
1437                 info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1438         }
1439 }
1440
1441 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
1442                 struct rte_cryptodev_stats *stats)
1443 {
1444         int i;
1445         struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1446
1447         PMD_INIT_FUNC_TRACE();
1448         if (stats == NULL) {
1449                 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
1450                 return;
1451         }
1452         for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1453                 if (qp[i] == NULL) {
1454                         PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
1455                         continue;
1456                 }
1457
1458                 stats->enqueued_count += qp[i]->stats.enqueued_count;
1459                 stats->dequeued_count += qp[i]->stats.dequeued_count;
1460                 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
1461                 stats->dequeue_err_count += qp[i]->stats.dequeue_err_count;
1462         }
1463 }
1464
1465 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
1466 {
1467         int i;
1468         struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1469
1470         PMD_INIT_FUNC_TRACE();
1471         for (i = 0; i < dev->data->nb_queue_pairs; i++)
1472                 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
1473         PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");
1474 }