drivers/crypto/qat/qat_crypto.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2015-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *       * Redistributions of source code must retain the above copyright
  12  *         notice, this list of conditions and the following disclaimer.
  13  *       * Redistributions in binary form must reproduce the above copyright
  14  *         notice, this list of conditions and the following disclaimer in
  15  *         the documentation and/or other materials provided with the
  16  *         distribution.
  17  *       * Neither the name of Intel Corporation nor the names of its
  18  *         contributors may be used to endorse or promote products derived
  19  *         from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <strings.h>
  37 #include <string.h>
  38 #include <inttypes.h>
  39 #include <errno.h>
  40 #include <sys/queue.h>
  41 #include <stdarg.h>
  42
  43 #include <rte_common.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_memory.h>
  47 #include <rte_memzone.h>
  48 #include <rte_tailq.h>
  49 #include <rte_ether.h>
  50 #include <rte_malloc.h>
  51 #include <rte_launch.h>
  52 #include <rte_eal.h>
  53 #include <rte_per_lcore.h>
  54 #include <rte_lcore.h>
  55 #include <rte_atomic.h>
  56 #include <rte_branch_prediction.h>
  57 #include <rte_mempool.h>
  58 #include <rte_mbuf.h>
  59 #include <rte_string_fns.h>
  60 #include <rte_spinlock.h>
  61 #include <rte_hexdump.h>
  62 #include <rte_crypto_sym.h>
  63 #include <rte_cryptodev_pci.h>
  64 #include <openssl/evp.h>
  65
  66 #include "qat_logs.h"
  67 #include "qat_algs.h"
  68 #include "qat_crypto.h"
  69 #include "adf_transport_access_macros.h"
  70
  71 #define BYTE_LENGTH    8
  72
  73 static int
  74 qat_is_cipher_alg_supported(enum rte_crypto_cipher_algorithm algo,
  75                 struct qat_pmd_private *internals) {
  76         int i = 0;
  77         const struct rte_cryptodev_capabilities *capability;
  78
  79         while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
  80                         RTE_CRYPTO_OP_TYPE_UNDEFINED) {
  81                 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
  82                         continue;
  83
  84                 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_CIPHER)
  85                         continue;
  86
  87                 if (capability->sym.cipher.algo == algo)
  88                         return 1;
  89         }
  90         return 0;
  91 }
  92
  93 static int
  94 qat_is_auth_alg_supported(enum rte_crypto_auth_algorithm algo,
  95                 struct qat_pmd_private *internals) {
  96         int i = 0;
  97         const struct rte_cryptodev_capabilities *capability;
  98
  99         while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
 100                         RTE_CRYPTO_OP_TYPE_UNDEFINED) {
 101                 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
 102                         continue;
 103
 104                 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_AUTH)
 105                         continue;
 106
 107                 if (capability->sym.auth.algo == algo)
 108                         return 1;
 109         }
 110         return 0;
 111 }
 112
 113 /** Encrypt a single partial block
 114  *  Depends on openssl libcrypto
 115  *  Uses ECB+XOR to do CFB encryption, same result, more performant
 116  */
 117 static inline int
 118 bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,
 119                 uint8_t *iv, int ivlen, int srclen,
 120                 void *bpi_ctx)
 121 {
 122         EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
 123         int encrypted_ivlen;
 124         uint8_t encrypted_iv[16];
 125         int i;
 126
 127         /* ECB method: encrypt the IV, then XOR this with plaintext */
 128         if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
 129                                                                 <= 0)
 130                 goto cipher_encrypt_err;
 131
 132         for (i = 0; i < srclen; i++)
 133                 *(dst+i) = *(src+i)^(encrypted_iv[i]);
 134
 135         return 0;
 136
 137 cipher_encrypt_err:
 138         PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt failed");
 139         return -EINVAL;
 140 }
 141
 142 /** Decrypt a single partial block
 143  *  Depends on openssl libcrypto
 144  *  Uses ECB+XOR to do CFB encryption, same result, more performant
 145  */
 146 static inline int
 147 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
 148                 uint8_t *iv, int ivlen, int srclen,
 149                 void *bpi_ctx)
 150 {
 151         EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
 152         int encrypted_ivlen;
 153         uint8_t encrypted_iv[16];
 154         int i;
 155
 156         /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
 157         if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
 158                                                                 <= 0)
 159                 goto cipher_decrypt_err;
 160
 161         for (i = 0; i < srclen; i++)
 162                 *(dst+i) = *(src+i)^(encrypted_iv[i]);
 163
 164         return 0;
 165
 166 cipher_decrypt_err:
 167         PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt for BPI IV failed");
 168         return -EINVAL;
 169 }
 170
 171 /** Creates a context in either AES or DES in ECB mode
 172  *  Depends on openssl libcrypto
 173  */
 174 static void *
 175 bpi_cipher_ctx_init(enum rte_crypto_cipher_algorithm cryptodev_algo,
 176                 enum rte_crypto_cipher_operation direction __rte_unused,
 177                                         uint8_t *key)
 178 {
 179         const EVP_CIPHER *algo = NULL;
 180         EVP_CIPHER_CTX *ctx = EVP_CIPHER_CTX_new();
 181
 182         if (ctx == NULL)
 183                 goto ctx_init_err;
 184
 185         if (cryptodev_algo == RTE_CRYPTO_CIPHER_DES_DOCSISBPI)
 186                 algo = EVP_des_ecb();
 187         else
 188                 algo = EVP_aes_128_ecb();
 189
 190         /* IV will be ECB encrypted whether direction is encrypt or decrypt*/
 191         if (EVP_EncryptInit_ex(ctx, algo, NULL, key, 0) != 1)
 192                 goto ctx_init_err;
 193
 194         return ctx;
 195
 196 ctx_init_err:
 197         if (ctx != NULL)
 198                 EVP_CIPHER_CTX_free(ctx);
 199         return NULL;
 200 }
 201
 202 /** Frees a context previously created
 203  *  Depends on openssl libcrypto
 204  */
 205 static void
 206 bpi_cipher_ctx_free(void *bpi_ctx)
 207 {
 208         if (bpi_ctx != NULL)
 209                 EVP_CIPHER_CTX_free((EVP_CIPHER_CTX *)bpi_ctx);
 210 }
 211
 212 static inline uint32_t
 213 adf_modulo(uint32_t data, uint32_t shift);
 214
 215 static inline int
 216 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
 217                 struct qat_crypto_op_cookie *qat_op_cookie, struct qat_qp *qp);
 218
 219 void
 220 qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
 221                 struct rte_cryptodev_sym_session *sess)
 222 {
 223         PMD_INIT_FUNC_TRACE();
 224         uint8_t index = dev->driver_id;
 225         void *sess_priv = get_session_private_data(sess, index);
 226         struct qat_session *s = (struct qat_session *)sess_priv;
 227
 228         if (sess_priv) {
 229                 if (s->bpi_ctx)
 230                         bpi_cipher_ctx_free(s->bpi_ctx);
 231                 memset(s, 0, qat_crypto_sym_get_session_private_size(dev));
 232                 struct rte_mempool *sess_mp = rte_mempool_from_obj(sess_priv);
 233                 set_session_private_data(sess, index, NULL);
 234                 rte_mempool_put(sess_mp, sess_priv);
 235         }
 236 }
 237
 238 static int
 239 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
 240 {
 241         /* Cipher Only */
 242         if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
 243                 return ICP_QAT_FW_LA_CMD_CIPHER;
 244
 245         /* Authentication Only */
 246         if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
 247                 return ICP_QAT_FW_LA_CMD_AUTH;
 248
 249         /* AEAD */
 250         if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
 251                 if (xform->aead.op == RTE_CRYPTO_AEAD_OP_ENCRYPT)
 252                         return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
 253                 else
 254                         return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
 255         }
 256
 257         if (xform->next == NULL)
 258                 return -1;
 259
 260         /* Cipher then Authenticate */
 261         if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
 262                         xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
 263                 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
 264
 265         /* Authenticate then Cipher */
 266         if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
 267                         xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
 268                 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
 269
 270         return -1;
 271 }
 272
 273 static struct rte_crypto_auth_xform *
 274 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
 275 {
 276         do {
 277                 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
 278                         return &xform->auth;
 279
 280                 xform = xform->next;
 281         } while (xform);
 282
 283         return NULL;
 284 }
 285
 286 static struct rte_crypto_cipher_xform *
 287 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
 288 {
 289         do {
 290                 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
 291                         return &xform->cipher;
 292
 293                 xform = xform->next;
 294         } while (xform);
 295
 296         return NULL;
 297 }
 298 void *
 299 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
 300                 struct rte_crypto_sym_xform *xform, void *session_private)
 301 {
 302         struct qat_session *session = session_private;
 303         struct qat_pmd_private *internals = dev->data->dev_private;
 304         struct rte_crypto_cipher_xform *cipher_xform = NULL;
 305
 306         /* Get cipher xform from crypto xform chain */
 307         cipher_xform = qat_get_cipher_xform(xform);
 308
 309         session->cipher_iv.offset = cipher_xform->iv.offset;
 310         session->cipher_iv.length = cipher_xform->iv.length;
 311
 312         switch (cipher_xform->algo) {
 313         case RTE_CRYPTO_CIPHER_AES_CBC:
 314                 if (qat_alg_validate_aes_key(cipher_xform->key.length,
 315                                 &session->qat_cipher_alg) != 0) {
 316                         PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
 317                         goto error_out;
 318                 }
 319                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 320                 break;
 321         case RTE_CRYPTO_CIPHER_AES_CTR:
 322                 if (qat_alg_validate_aes_key(cipher_xform->key.length,
 323                                 &session->qat_cipher_alg) != 0) {
 324                         PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
 325                         goto error_out;
 326                 }
 327                 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
 328                 break;
 329         case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
 330                 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
 331                                         &session->qat_cipher_alg) != 0) {
 332                         PMD_DRV_LOG(ERR, "Invalid SNOW 3G cipher key size");
 333                         goto error_out;
 334                 }
 335                 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
 336                 break;
 337         case RTE_CRYPTO_CIPHER_NULL:
 338                 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
 339                 break;
 340         case RTE_CRYPTO_CIPHER_KASUMI_F8:
 341                 if (qat_alg_validate_kasumi_key(cipher_xform->key.length,
 342                                         &session->qat_cipher_alg) != 0) {
 343                         PMD_DRV_LOG(ERR, "Invalid KASUMI cipher key size");
 344                         goto error_out;
 345                 }
 346                 session->qat_mode = ICP_QAT_HW_CIPHER_F8_MODE;
 347                 break;
 348         case RTE_CRYPTO_CIPHER_3DES_CBC:
 349                 if (qat_alg_validate_3des_key(cipher_xform->key.length,
 350                                 &session->qat_cipher_alg) != 0) {
 351                         PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
 352                         goto error_out;
 353                 }
 354                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 355                 break;
 356         case RTE_CRYPTO_CIPHER_DES_CBC:
 357                 if (qat_alg_validate_des_key(cipher_xform->key.length,
 358                                 &session->qat_cipher_alg) != 0) {
 359                         PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
 360                         goto error_out;
 361                 }
 362                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 363                 break;
 364         case RTE_CRYPTO_CIPHER_3DES_CTR:
 365                 if (qat_alg_validate_3des_key(cipher_xform->key.length,
 366                                 &session->qat_cipher_alg) != 0) {
 367                         PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
 368                         goto error_out;
 369                 }
 370                 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
 371                 break;
 372         case RTE_CRYPTO_CIPHER_DES_DOCSISBPI:
 373                 session->bpi_ctx = bpi_cipher_ctx_init(
 374                                         cipher_xform->algo,
 375                                         cipher_xform->op,
 376                                         cipher_xform->key.data);
 377                 if (session->bpi_ctx == NULL) {
 378                         PMD_DRV_LOG(ERR, "failed to create DES BPI ctx");
 379                         goto error_out;
 380                 }
 381                 if (qat_alg_validate_des_key(cipher_xform->key.length,
 382                                 &session->qat_cipher_alg) != 0) {
 383                         PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
 384                         goto error_out;
 385                 }
 386                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 387                 break;
 388         case RTE_CRYPTO_CIPHER_AES_DOCSISBPI:
 389                 session->bpi_ctx = bpi_cipher_ctx_init(
 390                                         cipher_xform->algo,
 391                                         cipher_xform->op,
 392                                         cipher_xform->key.data);
 393                 if (session->bpi_ctx == NULL) {
 394                         PMD_DRV_LOG(ERR, "failed to create AES BPI ctx");
 395                         goto error_out;
 396                 }
 397                 if (qat_alg_validate_aes_docsisbpi_key(cipher_xform->key.length,
 398                                 &session->qat_cipher_alg) != 0) {
 399                         PMD_DRV_LOG(ERR, "Invalid AES DOCSISBPI key size");
 400                         goto error_out;
 401                 }
 402                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 403                 break;
 404         case RTE_CRYPTO_CIPHER_ZUC_EEA3:
 405                 if (!qat_is_cipher_alg_supported(
 406                         cipher_xform->algo, internals)) {
 407                         PMD_DRV_LOG(ERR, "%s not supported on this device",
 408                                 rte_crypto_cipher_algorithm_strings
 409                                         [cipher_xform->algo]);
 410                         goto error_out;
 411                 }
 412                 if (qat_alg_validate_zuc_key(cipher_xform->key.length,
 413                                 &session->qat_cipher_alg) != 0) {
 414                         PMD_DRV_LOG(ERR, "Invalid ZUC cipher key size");
 415                         goto error_out;
 416                 }
 417                 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
 418                 break;
 419         case RTE_CRYPTO_CIPHER_3DES_ECB:
 420         case RTE_CRYPTO_CIPHER_AES_ECB:
 421         case RTE_CRYPTO_CIPHER_AES_F8:
 422         case RTE_CRYPTO_CIPHER_AES_XTS:
 423         case RTE_CRYPTO_CIPHER_ARC4:
 424                 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported Cipher alg %u",
 425                                 cipher_xform->algo);
 426                 goto error_out;
 427         default:
 428                 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
 429                                 cipher_xform->algo);
 430                 goto error_out;
 431         }
 432
 433         if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
 434                 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
 435         else
 436                 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
 437
 438         if (qat_alg_aead_session_create_content_desc_cipher(session,
 439                                                 cipher_xform->key.data,
 440                                                 cipher_xform->key.length))
 441                 goto error_out;
 442
 443         return session;
 444
 445 error_out:
 446         if (session->bpi_ctx) {
 447                 bpi_cipher_ctx_free(session->bpi_ctx);
 448                 session->bpi_ctx = NULL;
 449         }
 450         return NULL;
 451 }
 452
 453 int
 454 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
 455                 struct rte_crypto_sym_xform *xform,
 456                 struct rte_cryptodev_sym_session *sess,
 457                 struct rte_mempool *mempool)
 458 {
 459         void *sess_private_data;
 460
 461         if (rte_mempool_get(mempool, &sess_private_data)) {
 462                 CDEV_LOG_ERR(
 463                         "Couldn't get object from session mempool");
 464                 return -1;
 465         }
 466
 467         if (qat_crypto_set_session_parameters(dev, xform, sess_private_data) != 0) {
 468                 PMD_DRV_LOG(ERR, "Crypto QAT PMD: failed to configure "
 469                                 "session parameters");
 470
 471                 /* Return session to mempool */
 472                 rte_mempool_put(mempool, sess_private_data);
 473                 return -1;
 474         }
 475
 476         set_session_private_data(sess, dev->driver_id,
 477                 sess_private_data);
 478
 479         return 0;
 480 }
 481
 482 int
 483 qat_crypto_set_session_parameters(struct rte_cryptodev *dev,
 484                 struct rte_crypto_sym_xform *xform, void *session_private)
 485 {
 486         struct qat_session *session = session_private;
 487
 488         int qat_cmd_id;
 489         PMD_INIT_FUNC_TRACE();
 490
 491         /* Set context descriptor physical address */
 492         session->cd_paddr = rte_mempool_virt2phy(NULL, session) +
 493                         offsetof(struct qat_session, cd);
 494
 495         session->min_qat_dev_gen = QAT_GEN1;
 496
 497         /* Get requested QAT command id */
 498         qat_cmd_id = qat_get_cmd_id(xform);
 499         if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
 500                 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
 501                 goto error_out;
 502         }
 503         session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
 504         switch (session->qat_cmd) {
 505         case ICP_QAT_FW_LA_CMD_CIPHER:
 506         session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
 507                 break;
 508         case ICP_QAT_FW_LA_CMD_AUTH:
 509         session = qat_crypto_sym_configure_session_auth(dev, xform, session);
 510                 break;
 511         case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
 512                 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD)
 513                         session = qat_crypto_sym_configure_session_aead(xform,
 514                                         session);
 515                 else {
 516                         session = qat_crypto_sym_configure_session_cipher(dev,
 517                                         xform, session);
 518                         session = qat_crypto_sym_configure_session_auth(dev,
 519                                         xform, session);
 520                 }
 521                 break;
 522         case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
 523                 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD)
 524                         session = qat_crypto_sym_configure_session_aead(xform,
 525                                         session);
 526                 else {
 527                         session = qat_crypto_sym_configure_session_auth(dev,
 528                                         xform, session);
 529                         session = qat_crypto_sym_configure_session_cipher(dev,
 530                                         xform, session);
 531                 }
 532                 break;
 533         case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
 534         case ICP_QAT_FW_LA_CMD_TRNG_TEST:
 535         case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
 536         case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
 537         case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
 538         case ICP_QAT_FW_LA_CMD_MGF1:
 539         case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
 540         case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
 541         case ICP_QAT_FW_LA_CMD_DELIMITER:
 542         PMD_DRV_LOG(ERR, "Unsupported Service %u",
 543                 session->qat_cmd);
 544                 goto error_out;
 545         default:
 546         PMD_DRV_LOG(ERR, "Unsupported Service %u",
 547                 session->qat_cmd);
 548                 goto error_out;
 549         }
 550
 551         return 0;
 552
 553 error_out:
 554         return -1;
 555 }
 556
 557 struct qat_session *
 558 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
 559                                 struct rte_crypto_sym_xform *xform,
 560                                 struct qat_session *session_private)
 561 {
 562
 563         struct qat_session *session = session_private;
 564         struct rte_crypto_auth_xform *auth_xform = NULL;
 565         struct qat_pmd_private *internals = dev->data->dev_private;
 566         auth_xform = qat_get_auth_xform(xform);
 567         uint8_t *key_data = auth_xform->key.data;
 568         uint8_t key_length = auth_xform->key.length;
 569
 570         switch (auth_xform->algo) {
 571         case RTE_CRYPTO_AUTH_SHA1_HMAC:
 572                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
 573                 break;
 574         case RTE_CRYPTO_AUTH_SHA224_HMAC:
 575                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
 576                 break;
 577         case RTE_CRYPTO_AUTH_SHA256_HMAC:
 578                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
 579                 break;
 580         case RTE_CRYPTO_AUTH_SHA384_HMAC:
 581                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;
 582                 break;
 583         case RTE_CRYPTO_AUTH_SHA512_HMAC:
 584                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
 585                 break;
 586         case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
 587                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
 588                 break;
 589         case RTE_CRYPTO_AUTH_AES_GMAC:
 590                 if (qat_alg_validate_aes_key(auth_xform->key.length,
 591                                 &session->qat_cipher_alg) != 0) {
 592                         PMD_DRV_LOG(ERR, "Invalid AES key size");
 593                         goto error_out;
 594                 }
 595                 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
 596                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
 597
 598                 break;
 599         case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
 600                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
 601                 break;
 602         case RTE_CRYPTO_AUTH_MD5_HMAC:
 603                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
 604                 break;
 605         case RTE_CRYPTO_AUTH_NULL:
 606                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;
 607                 break;
 608         case RTE_CRYPTO_AUTH_KASUMI_F9:
 609                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_KASUMI_F9;
 610                 break;
 611         case RTE_CRYPTO_AUTH_ZUC_EIA3:
 612                 if (!qat_is_auth_alg_supported(auth_xform->algo, internals)) {
 613                         PMD_DRV_LOG(ERR, "%s not supported on this device",
 614                                 rte_crypto_auth_algorithm_strings
 615                                 [auth_xform->algo]);
 616                         goto error_out;
 617                 }
 618                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3;
 619                 break;
 620         case RTE_CRYPTO_AUTH_SHA1:
 621         case RTE_CRYPTO_AUTH_SHA256:
 622         case RTE_CRYPTO_AUTH_SHA512:
 623         case RTE_CRYPTO_AUTH_SHA224:
 624         case RTE_CRYPTO_AUTH_SHA384:
 625         case RTE_CRYPTO_AUTH_MD5:
 626         case RTE_CRYPTO_AUTH_AES_CMAC:
 627         case RTE_CRYPTO_AUTH_AES_CBC_MAC:
 628                 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
 629                                 auth_xform->algo);
 630                 goto error_out;
 631         default:
 632                 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
 633                                 auth_xform->algo);
 634                 goto error_out;
 635         }
 636
 637         session->auth_iv.offset = auth_xform->iv.offset;
 638         session->auth_iv.length = auth_xform->iv.length;
 639
 640         if (auth_xform->algo == RTE_CRYPTO_AUTH_AES_GMAC) {
 641                 if (auth_xform->op == RTE_CRYPTO_AUTH_OP_GENERATE) {
 642                         session->qat_cmd = ICP_QAT_FW_LA_CMD_CIPHER_HASH;
 643                         session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
 644                         /*
 645                          * It needs to create cipher desc content first,
 646                          * then authentication
 647                          */
 648                         if (qat_alg_aead_session_create_content_desc_cipher(session,
 649                                                 auth_xform->key.data,
 650                                                 auth_xform->key.length))
 651                                 goto error_out;
 652
 653                         if (qat_alg_aead_session_create_content_desc_auth(session,
 654                                                 key_data,
 655                                                 key_length,
 656                                                 0,
 657                                                 auth_xform->digest_length,
 658                                                 auth_xform->op))
 659                                 goto error_out;
 660                 } else {
 661                         session->qat_cmd = ICP_QAT_FW_LA_CMD_HASH_CIPHER;
 662                         session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
 663                         /*
 664                          * It needs to create authentication desc content first,
 665                          * then cipher
 666                          */
 667                         if (qat_alg_aead_session_create_content_desc_auth(session,
 668                                         key_data,
 669                                         key_length,
 670                                         0,
 671                                         auth_xform->digest_length,
 672                                         auth_xform->op))
 673                                 goto error_out;
 674
 675                         if (qat_alg_aead_session_create_content_desc_cipher(session,
 676                                                 auth_xform->key.data,
 677                                                 auth_xform->key.length))
 678                                 goto error_out;
 679                 }
 680                 /* Restore to authentication only only */
 681                 session->qat_cmd = ICP_QAT_FW_LA_CMD_AUTH;
 682         } else {
 683                 if (qat_alg_aead_session_create_content_desc_auth(session,
 684                                 key_data,
 685                                 key_length,
 686                                 0,
 687                                 auth_xform->digest_length,
 688                                 auth_xform->op))
 689                         goto error_out;
 690         }
 691
 692         session->digest_length = auth_xform->digest_length;
 693         return session;
 694
 695 error_out:
 696         return NULL;
 697 }
 698
 699 struct qat_session *
 700 qat_crypto_sym_configure_session_aead(struct rte_crypto_sym_xform *xform,
 701                                 struct qat_session *session_private)
 702 {
 703         struct qat_session *session = session_private;
 704         struct rte_crypto_aead_xform *aead_xform = &xform->aead;
 705
 706         /*
 707          * Store AEAD IV parameters as cipher IV,
 708          * to avoid unnecessary memory usage
 709          */
 710         session->cipher_iv.offset = xform->aead.iv.offset;
 711         session->cipher_iv.length = xform->aead.iv.length;
 712
 713         switch (aead_xform->algo) {
 714         case RTE_CRYPTO_AEAD_AES_GCM:
 715                 if (qat_alg_validate_aes_key(aead_xform->key.length,
 716                                 &session->qat_cipher_alg) != 0) {
 717                         PMD_DRV_LOG(ERR, "Invalid AES key size");
 718                         goto error_out;
 719                 }
 720                 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
 721                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
 722                 break;
 723         case RTE_CRYPTO_AEAD_AES_CCM:
 724                 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported AEAD alg %u",
 725                                 aead_xform->algo);
 726                 goto error_out;
 727         default:
 728                 PMD_DRV_LOG(ERR, "Crypto: Undefined AEAD specified %u\n",
 729                                 aead_xform->algo);
 730                 goto error_out;
 731         }
 732
 733         if (aead_xform->op == RTE_CRYPTO_AEAD_OP_ENCRYPT) {
 734                 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
 735                 /*
 736                  * It needs to create cipher desc content first,
 737                  * then authentication
 738                  */
 739                 if (qat_alg_aead_session_create_content_desc_cipher(session,
 740                                         aead_xform->key.data,
 741                                         aead_xform->key.length))
 742                         goto error_out;
 743
 744                 if (qat_alg_aead_session_create_content_desc_auth(session,
 745                                         aead_xform->key.data,
 746                                         aead_xform->key.length,
 747                                         aead_xform->aad_length,
 748                                         aead_xform->digest_length,
 749                                         RTE_CRYPTO_AUTH_OP_GENERATE))
 750                         goto error_out;
 751         } else {
 752                 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
 753                 /*
 754                  * It needs to create authentication desc content first,
 755                  * then cipher
 756                  */
 757                 if (qat_alg_aead_session_create_content_desc_auth(session,
 758                                         aead_xform->key.data,
 759                                         aead_xform->key.length,
 760                                         aead_xform->aad_length,
 761                                         aead_xform->digest_length,
 762                                         RTE_CRYPTO_AUTH_OP_VERIFY))
 763                         goto error_out;
 764
 765                 if (qat_alg_aead_session_create_content_desc_cipher(session,
 766                                         aead_xform->key.data,
 767                                         aead_xform->key.length))
 768                         goto error_out;
 769         }
 770
 771         session->digest_length = aead_xform->digest_length;
 772         return session;
 773
 774 error_out:
 775         return NULL;
 776 }
 777
 778 unsigned qat_crypto_sym_get_session_private_size(
 779                 struct rte_cryptodev *dev __rte_unused)
 780 {
 781         return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
 782 }
 783
 784 static inline uint32_t
 785 qat_bpicipher_preprocess(struct qat_session *ctx,
 786                                 struct rte_crypto_op *op)
 787 {
 788         uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
 789         struct rte_crypto_sym_op *sym_op = op->sym;
 790         uint8_t last_block_len = block_len > 0 ?
 791                         sym_op->cipher.data.length % block_len : 0;
 792
 793         if (last_block_len &&
 794                         ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
 795
 796                 /* Decrypt last block */
 797                 uint8_t *last_block, *dst, *iv;
 798                 uint32_t last_block_offset = sym_op->cipher.data.offset +
 799                                 sym_op->cipher.data.length - last_block_len;
 800                 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
 801                                 uint8_t *, last_block_offset);
 802
 803                 if (unlikely(sym_op->m_dst != NULL))
 804                         /* out-of-place operation (OOP) */
 805                         dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
 806                                                 uint8_t *, last_block_offset);
 807                 else
 808                         dst = last_block;
 809
 810                 if (last_block_len < sym_op->cipher.data.length)
 811                         /* use previous block ciphertext as IV */
 812                         iv = last_block - block_len;
 813                 else
 814                         /* runt block, i.e. less than one full block */
 815                         iv = rte_crypto_op_ctod_offset(op, uint8_t *,
 816                                         ctx->cipher_iv.offset);
 817
 818 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 819                 rte_hexdump(stdout, "BPI: src before pre-process:", last_block,
 820                         last_block_len);
 821                 if (sym_op->m_dst != NULL)
 822                         rte_hexdump(stdout, "BPI: dst before pre-process:", dst,
 823                                 last_block_len);
 824 #endif
 825                 bpi_cipher_decrypt(last_block, dst, iv, block_len,
 826                                 last_block_len, ctx->bpi_ctx);
 827 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 828                 rte_hexdump(stdout, "BPI: src after pre-process:", last_block,
 829                         last_block_len);
 830                 if (sym_op->m_dst != NULL)
 831                         rte_hexdump(stdout, "BPI: dst after pre-process:", dst,
 832                                 last_block_len);
 833 #endif
 834         }
 835
 836         return sym_op->cipher.data.length - last_block_len;
 837 }
 838
 839 static inline uint32_t
 840 qat_bpicipher_postprocess(struct qat_session *ctx,
 841                                 struct rte_crypto_op *op)
 842 {
 843         uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
 844         struct rte_crypto_sym_op *sym_op = op->sym;
 845         uint8_t last_block_len = block_len > 0 ?
 846                         sym_op->cipher.data.length % block_len : 0;
 847
 848         if (last_block_len > 0 &&
 849                         ctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
 850
 851                 /* Encrypt last block */
 852                 uint8_t *last_block, *dst, *iv;
 853                 uint32_t last_block_offset;
 854
 855                 last_block_offset = sym_op->cipher.data.offset +
 856                                 sym_op->cipher.data.length - last_block_len;
 857                 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
 858                                 uint8_t *, last_block_offset);
 859
 860                 if (unlikely(sym_op->m_dst != NULL))
 861                         /* out-of-place operation (OOP) */
 862                         dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
 863                                                 uint8_t *, last_block_offset);
 864                 else
 865                         dst = last_block;
 866
 867                 if (last_block_len < sym_op->cipher.data.length)
 868                         /* use previous block ciphertext as IV */
 869                         iv = dst - block_len;
 870                 else
 871                         /* runt block, i.e. less than one full block */
 872                         iv = rte_crypto_op_ctod_offset(op, uint8_t *,
 873                                         ctx->cipher_iv.offset);
 874
 875 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
 876                 rte_hexdump(stdout, "BPI: src before post-process:", last_block,
 877                         last_block_len);
 878                 if (sym_op->m_dst != NULL)
 879                         rte_hexdump(stdout, "BPI: dst before post-process:",
 880                                         dst, last_block_len);
 881 #endif
 882                 bpi_cipher_encrypt(last_block, dst, iv, block_len,
 883                                 last_block_len, ctx->bpi_ctx);
 884 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
 885                 rte_hexdump(stdout, "BPI: src after post-process:", last_block,
 886                         last_block_len);
 887                 if (sym_op->m_dst != NULL)
 888                         rte_hexdump(stdout, "BPI: dst after post-process:", dst,
 889                                 last_block_len);
 890 #endif
 891         }
 892         return sym_op->cipher.data.length - last_block_len;
 893 }
 894
 895 uint16_t
 896 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
 897                 uint16_t nb_ops)
 898 {
 899         register struct qat_queue *queue;
 900         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 901         register uint32_t nb_ops_sent = 0;
 902         register struct rte_crypto_op **cur_op = ops;
 903         register int ret;
 904         uint16_t nb_ops_possible = nb_ops;
 905         register uint8_t *base_addr;
 906         register uint32_t tail;
 907         int overflow;
 908
 909         if (unlikely(nb_ops == 0))
 910                 return 0;
 911
 912         /* read params used a lot in main loop into registers */
 913         queue = &(tmp_qp->tx_q);
 914         base_addr = (uint8_t *)queue->base_addr;
 915         tail = queue->tail;
 916
 917         /* Find how many can actually fit on the ring */
 918         overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
 919                                 - queue->max_inflights;
 920         if (overflow > 0) {
 921                 rte_atomic16_sub(&tmp_qp->inflights16, overflow);
 922                 nb_ops_possible = nb_ops - overflow;
 923                 if (nb_ops_possible == 0)
 924                         return 0;
 925         }
 926
 927         while (nb_ops_sent != nb_ops_possible) {
 928                 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail,
 929                         tmp_qp->op_cookies[tail / queue->msg_size], tmp_qp);
 930                 if (ret != 0) {
 931                         tmp_qp->stats.enqueue_err_count++;
 932                         /*
 933                          * This message cannot be enqueued,
 934                          * decrease number of ops that wasn't sent
 935                          */
 936                         rte_atomic16_sub(&tmp_qp->inflights16,
 937                                         nb_ops_possible - nb_ops_sent);
 938                         if (nb_ops_sent == 0)
 939                                 return 0;
 940                         goto kick_tail;
 941                 }
 942
 943                 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
 944                 nb_ops_sent++;
 945                 cur_op++;
 946         }
 947 kick_tail:
 948         WRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,
 949                         queue->hw_queue_number, tail);
 950         queue->tail = tail;
 951         tmp_qp->stats.enqueued_count += nb_ops_sent;
 952         return nb_ops_sent;
 953 }
 954
 955 uint16_t
 956 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
 957                 uint16_t nb_ops)
 958 {
 959         struct qat_queue *queue;
 960         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 961         uint32_t msg_counter = 0;
 962         struct rte_crypto_op *rx_op;
 963         struct icp_qat_fw_comn_resp *resp_msg;
 964
 965         queue = &(tmp_qp->rx_q);
 966         resp_msg = (struct icp_qat_fw_comn_resp *)
 967                         ((uint8_t *)queue->base_addr + queue->head);
 968
 969         while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
 970                         msg_counter != nb_ops) {
 971                 rx_op = (struct rte_crypto_op *)(uintptr_t)
 972                                 (resp_msg->opaque_data);
 973
 974 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
 975                 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
 976                         sizeof(struct icp_qat_fw_comn_resp));
 977
 978 #endif
 979                 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
 980                                 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
 981                                         resp_msg->comn_hdr.comn_status)) {
 982                         rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
 983                 } else {
 984                         struct qat_session *sess = (struct qat_session *)
 985                                         get_session_private_data(
 986                                         rx_op->sym->session,
 987                                         cryptodev_qat_driver_id);
 988
 989                         if (sess->bpi_ctx)
 990                                 qat_bpicipher_postprocess(sess, rx_op);
 991                         rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
 992                 }
 993
 994                 *(uint32_t *)resp_msg = ADF_RING_EMPTY_SIG;
 995                 queue->head = adf_modulo(queue->head +
 996                                 queue->msg_size,
 997                                 ADF_RING_SIZE_MODULO(queue->queue_size));
 998                 resp_msg = (struct icp_qat_fw_comn_resp *)
 999                                         ((uint8_t *)queue->base_addr +
1000                                                         queue->head);
1001                 *ops = rx_op;
1002                 ops++;
1003                 msg_counter++;
1004         }
1005         if (msg_counter > 0) {
1006                 WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
1007                                         queue->hw_bundle_number,
1008                                         queue->hw_queue_number, queue->head);
1009                 rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
1010                 tmp_qp->stats.dequeued_count += msg_counter;
1011         }
1012         return msg_counter;
1013 }
1014
1015 static inline int
1016 qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buff_start,
1017                 struct qat_alg_buf_list *list, uint32_t data_len)
1018 {
1019         int nr = 1;
1020
1021         uint32_t buf_len = rte_pktmbuf_mtophys(buf) -
1022                         buff_start + rte_pktmbuf_data_len(buf);
1023
1024         list->bufers[0].addr = buff_start;
1025         list->bufers[0].resrvd = 0;
1026         list->bufers[0].len = buf_len;
1027
1028         if (data_len <= buf_len) {
1029                 list->num_bufs = nr;
1030                 list->bufers[0].len = data_len;
1031                 return 0;
1032         }
1033
1034         buf = buf->next;
1035         while (buf) {
1036                 if (unlikely(nr == QAT_SGL_MAX_NUMBER)) {
1037                         PMD_DRV_LOG(ERR, "QAT PMD exceeded size of QAT SGL"
1038                                         " entry(%u)",
1039                                         QAT_SGL_MAX_NUMBER);
1040                         return -EINVAL;
1041                 }
1042
1043                 list->bufers[nr].len = rte_pktmbuf_data_len(buf);
1044                 list->bufers[nr].resrvd = 0;
1045                 list->bufers[nr].addr = rte_pktmbuf_mtophys(buf);
1046
1047                 buf_len += list->bufers[nr].len;
1048                 buf = buf->next;
1049
1050                 if (buf_len > data_len) {
1051                         list->bufers[nr].len -=
1052                                 buf_len - data_len;
1053                         buf = NULL;
1054                 }
1055                 ++nr;
1056         }
1057         list->num_bufs = nr;
1058
1059         return 0;
1060 }
1061
1062 static inline void
1063 set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,
1064                 struct icp_qat_fw_la_cipher_req_params *cipher_param,
1065                 struct rte_crypto_op *op,
1066                 struct icp_qat_fw_la_bulk_req *qat_req)
1067 {
1068         /* copy IV into request if it fits */
1069         if (iv_length <= sizeof(cipher_param->u.cipher_IV_array)) {
1070                 rte_memcpy(cipher_param->u.cipher_IV_array,
1071                                 rte_crypto_op_ctod_offset(op, uint8_t *,
1072                                         iv_offset),
1073                                 iv_length);
1074         } else {
1075                 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
1076                                 qat_req->comn_hdr.serv_specif_flags,
1077                                 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
1078                 cipher_param->u.s.cipher_IV_ptr =
1079                                 rte_crypto_op_ctophys_offset(op,
1080                                         iv_offset);
1081         }
1082 }
1083
1084 static inline int
1085 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
1086                 struct qat_crypto_op_cookie *qat_op_cookie, struct qat_qp *qp)
1087 {
1088         int ret = 0;
1089         struct qat_session *ctx;
1090         struct icp_qat_fw_la_cipher_req_params *cipher_param;
1091         struct icp_qat_fw_la_auth_req_params *auth_param;
1092         register struct icp_qat_fw_la_bulk_req *qat_req;
1093         uint8_t do_auth = 0, do_cipher = 0, do_aead = 0;
1094         uint32_t cipher_len = 0, cipher_ofs = 0;
1095         uint32_t auth_len = 0, auth_ofs = 0;
1096         uint32_t min_ofs = 0;
1097         uint64_t src_buf_start = 0, dst_buf_start = 0;
1098         uint8_t do_sgl = 0;
1099
1100 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1101         if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
1102                 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
1103                                 "operation requests, op (%p) is not a "
1104                                 "symmetric operation.", op);
1105                 return -EINVAL;
1106         }
1107 #endif
1108         if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
1109                 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
1110                                 " requests, op (%p) is sessionless.", op);
1111                 return -EINVAL;
1112         }
1113
1114         ctx = (struct qat_session *)get_session_private_data(
1115                         op->sym->session, cryptodev_qat_driver_id);
1116
1117         if (unlikely(ctx == NULL)) {
1118                 PMD_DRV_LOG(ERR, "Session was not created for this device");
1119                 return -EINVAL;
1120         }
1121
1122         if (unlikely(ctx->min_qat_dev_gen > qp->qat_dev_gen)) {
1123                 PMD_DRV_LOG(ERR, "Session alg not supported on this device gen");
1124                 op->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;
1125                 return -EINVAL;
1126         }
1127
1128         qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
1129         rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
1130         qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
1131         cipher_param = (void *)&qat_req->serv_specif_rqpars;
1132         auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
1133
1134         if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
1135                         ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
1136                 /* AES-GCM */
1137                 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1138                                 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1139                         do_aead = 1;
1140                 } else {
1141                         do_auth = 1;
1142                         do_cipher = 1;
1143                 }
1144         } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
1145                 do_auth = 1;
1146                 do_cipher = 0;
1147         } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
1148                 do_auth = 0;
1149                 do_cipher = 1;
1150         }
1151
1152         if (do_cipher) {
1153
1154                 if (ctx->qat_cipher_alg ==
1155                                          ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
1156                         ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
1157                         ctx->qat_cipher_alg ==
1158                                 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
1159
1160                         if (unlikely(
1161                                 (cipher_param->cipher_length % BYTE_LENGTH != 0)
1162                                  || (cipher_param->cipher_offset
1163                                                         % BYTE_LENGTH != 0))) {
1164                                 PMD_DRV_LOG(ERR,
1165                   "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
1166                                 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1167                                 return -EINVAL;
1168                         }
1169                         cipher_len = op->sym->cipher.data.length >> 3;
1170                         cipher_ofs = op->sym->cipher.data.offset >> 3;
1171
1172                 } else if (ctx->bpi_ctx) {
1173                         /* DOCSIS - only send complete blocks to device
1174                          * Process any partial block using CFB mode.
1175                          * Even if 0 complete blocks, still send this to device
1176                          * to get into rx queue for post-process and dequeuing
1177                          */
1178                         cipher_len = qat_bpicipher_preprocess(ctx, op);
1179                         cipher_ofs = op->sym->cipher.data.offset;
1180                 } else {
1181                         cipher_len = op->sym->cipher.data.length;
1182                         cipher_ofs = op->sym->cipher.data.offset;
1183                 }
1184
1185                 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
1186                                 cipher_param, op, qat_req);
1187                 min_ofs = cipher_ofs;
1188         }
1189
1190         if (do_auth) {
1191
1192                 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
1193                         ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
1194                         ctx->qat_hash_alg ==
1195                                 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
1196                         if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0)
1197                                 || (auth_param->auth_len % BYTE_LENGTH != 0))) {
1198                                 PMD_DRV_LOG(ERR,
1199                 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
1200                                 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1201                                 return -EINVAL;
1202                         }
1203                         auth_ofs = op->sym->auth.data.offset >> 3;
1204                         auth_len = op->sym->auth.data.length >> 3;
1205
1206                         auth_param->u1.aad_adr =
1207                                         rte_crypto_op_ctophys_offset(op,
1208                                                         ctx->auth_iv.offset);
1209
1210                 } else if (ctx->qat_hash_alg ==
1211                                         ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1212                                 ctx->qat_hash_alg ==
1213                                         ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1214                         /* AES-GMAC */
1215                         set_cipher_iv(ctx->auth_iv.length,
1216                                 ctx->auth_iv.offset,
1217                                 cipher_param, op, qat_req);
1218                         auth_ofs = op->sym->auth.data.offset;
1219                         auth_len = op->sym->auth.data.length;
1220
1221                         auth_param->u1.aad_adr = 0;
1222                         auth_param->u2.aad_sz = 0;
1223
1224                         /*
1225                          * If len(iv)==12B fw computes J0
1226                          */
1227                         if (ctx->auth_iv.length == 12) {
1228                                 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1229                                         qat_req->comn_hdr.serv_specif_flags,
1230                                         ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1231
1232                         }
1233                 } else {
1234                         auth_ofs = op->sym->auth.data.offset;
1235                         auth_len = op->sym->auth.data.length;
1236
1237                 }
1238                 min_ofs = auth_ofs;
1239
1240                 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
1241
1242         }
1243
1244         if (do_aead) {
1245                 if (ctx->qat_hash_alg ==
1246                                 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1247                                 ctx->qat_hash_alg ==
1248                                         ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1249                         /*
1250                          * If len(iv)==12B fw computes J0
1251                          */
1252                         if (ctx->cipher_iv.length == 12) {
1253                                 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1254                                         qat_req->comn_hdr.serv_specif_flags,
1255                                         ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1256                         }
1257
1258                 }
1259
1260                 cipher_len = op->sym->aead.data.length;
1261                 cipher_ofs = op->sym->aead.data.offset;
1262                 auth_len = op->sym->aead.data.length;
1263                 auth_ofs = op->sym->aead.data.offset;
1264
1265                 auth_param->u1.aad_adr = op->sym->aead.aad.phys_addr;
1266                 auth_param->auth_res_addr = op->sym->aead.digest.phys_addr;
1267                 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
1268                                 cipher_param, op, qat_req);
1269                 min_ofs = op->sym->aead.data.offset;
1270         }
1271
1272         if (op->sym->m_src->next || (op->sym->m_dst && op->sym->m_dst->next))
1273                 do_sgl = 1;
1274
1275         /* adjust for chain case */
1276         if (do_cipher && do_auth)
1277                 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
1278
1279         if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
1280                 min_ofs = 0;
1281
1282         if (unlikely(op->sym->m_dst != NULL)) {
1283                 /* Out-of-place operation (OOP)
1284                  * Don't align DMA start. DMA the minimum data-set
1285                  * so as not to overwrite data in dest buffer
1286                  */
1287                 src_buf_start =
1288                         rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs);
1289                 dst_buf_start =
1290                         rte_pktmbuf_mtophys_offset(op->sym->m_dst, min_ofs);
1291
1292         } else {
1293                 /* In-place operation
1294                  * Start DMA at nearest aligned address below min_ofs
1295                  */
1296                 src_buf_start =
1297                         rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs)
1298                                                 & QAT_64_BTYE_ALIGN_MASK;
1299
1300                 if (unlikely((rte_pktmbuf_mtophys(op->sym->m_src) -
1301                                         rte_pktmbuf_headroom(op->sym->m_src))
1302                                                         > src_buf_start)) {
1303                         /* alignment has pushed addr ahead of start of mbuf
1304                          * so revert and take the performance hit
1305                          */
1306                         src_buf_start =
1307                                 rte_pktmbuf_mtophys_offset(op->sym->m_src,
1308                                                                 min_ofs);
1309                 }
1310                 dst_buf_start = src_buf_start;
1311         }
1312
1313         if (do_cipher || do_aead) {
1314                 cipher_param->cipher_offset =
1315                                 (uint32_t)rte_pktmbuf_mtophys_offset(
1316                                 op->sym->m_src, cipher_ofs) - src_buf_start;
1317                 cipher_param->cipher_length = cipher_len;
1318         } else {
1319                 cipher_param->cipher_offset = 0;
1320                 cipher_param->cipher_length = 0;
1321         }
1322
1323         if (do_auth || do_aead) {
1324                 auth_param->auth_off = (uint32_t)rte_pktmbuf_mtophys_offset(
1325                                 op->sym->m_src, auth_ofs) - src_buf_start;
1326                 auth_param->auth_len = auth_len;
1327         } else {
1328                 auth_param->auth_off = 0;
1329                 auth_param->auth_len = 0;
1330         }
1331
1332         qat_req->comn_mid.dst_length =
1333                 qat_req->comn_mid.src_length =
1334                 (cipher_param->cipher_offset + cipher_param->cipher_length)
1335                 > (auth_param->auth_off + auth_param->auth_len) ?
1336                 (cipher_param->cipher_offset + cipher_param->cipher_length)
1337                 : (auth_param->auth_off + auth_param->auth_len);
1338
1339         if (do_sgl) {
1340
1341                 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
1342                                 QAT_COMN_PTR_TYPE_SGL);
1343                 ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
1344                                 &qat_op_cookie->qat_sgl_list_src,
1345                                 qat_req->comn_mid.src_length);
1346                 if (ret) {
1347                         PMD_DRV_LOG(ERR, "QAT PMD Cannot fill sgl array");
1348                         return ret;
1349                 }
1350
1351                 if (likely(op->sym->m_dst == NULL))
1352                         qat_req->comn_mid.dest_data_addr =
1353                                 qat_req->comn_mid.src_data_addr =
1354                                 qat_op_cookie->qat_sgl_src_phys_addr;
1355                 else {
1356                         ret = qat_sgl_fill_array(op->sym->m_dst,
1357                                         dst_buf_start,
1358                                         &qat_op_cookie->qat_sgl_list_dst,
1359                                                 qat_req->comn_mid.dst_length);
1360
1361                         if (ret) {
1362                                 PMD_DRV_LOG(ERR, "QAT PMD Cannot "
1363                                                 "fill sgl array");
1364                                 return ret;
1365                         }
1366
1367                         qat_req->comn_mid.src_data_addr =
1368                                 qat_op_cookie->qat_sgl_src_phys_addr;
1369                         qat_req->comn_mid.dest_data_addr =
1370                                         qat_op_cookie->qat_sgl_dst_phys_addr;
1371                 }
1372         } else {
1373                 qat_req->comn_mid.src_data_addr = src_buf_start;
1374                 qat_req->comn_mid.dest_data_addr = dst_buf_start;
1375         }
1376
1377 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1378         rte_hexdump(stdout, "qat_req:", qat_req,
1379                         sizeof(struct icp_qat_fw_la_bulk_req));
1380         rte_hexdump(stdout, "src_data:",
1381                         rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
1382                         rte_pktmbuf_data_len(op->sym->m_src));
1383         if (do_cipher) {
1384                 uint8_t *cipher_iv_ptr = rte_crypto_op_ctod_offset(op,
1385                                                 uint8_t *,
1386                                                 ctx->cipher_iv.offset);
1387                 rte_hexdump(stdout, "cipher iv:", cipher_iv_ptr,
1388                                 ctx->cipher_iv.length);
1389         }
1390
1391         if (do_auth) {
1392                 if (ctx->auth_iv.length) {
1393                         uint8_t *auth_iv_ptr = rte_crypto_op_ctod_offset(op,
1394                                                         uint8_t *,
1395                                                         ctx->auth_iv.offset);
1396                         rte_hexdump(stdout, "auth iv:", auth_iv_ptr,
1397                                                 ctx->auth_iv.length);
1398                 }
1399                 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
1400                                 ctx->digest_length);
1401         }
1402
1403         if (do_aead) {
1404                 rte_hexdump(stdout, "digest:", op->sym->aead.digest.data,
1405                                 ctx->digest_length);
1406                 rte_hexdump(stdout, "aad:", op->sym->aead.aad.data,
1407                                 ctx->aad_len);
1408         }
1409 #endif
1410         return 0;
1411 }
1412
1413 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
1414 {
1415         uint32_t div = data >> shift;
1416         uint32_t mult = div << shift;
1417
1418         return data - mult;
1419 }
1420
1421 int qat_dev_config(__rte_unused struct rte_cryptodev *dev,
1422                 __rte_unused struct rte_cryptodev_config *config)
1423 {
1424         PMD_INIT_FUNC_TRACE();
1425         return 0;
1426 }
1427
1428 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
1429 {
1430         PMD_INIT_FUNC_TRACE();
1431         return 0;
1432 }
1433
1434 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
1435 {
1436         PMD_INIT_FUNC_TRACE();
1437 }
1438
1439 int qat_dev_close(struct rte_cryptodev *dev)
1440 {
1441         int i, ret;
1442
1443         PMD_INIT_FUNC_TRACE();
1444
1445         for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1446                 ret = qat_crypto_sym_qp_release(dev, i);
1447                 if (ret < 0)
1448                         return ret;
1449         }
1450
1451         return 0;
1452 }
1453
1454 void qat_dev_info_get(struct rte_cryptodev *dev,
1455                         struct rte_cryptodev_info *info)
1456 {
1457         struct qat_pmd_private *internals = dev->data->dev_private;
1458
1459         PMD_INIT_FUNC_TRACE();
1460         if (info != NULL) {
1461                 info->max_nb_queue_pairs =
1462                                 ADF_NUM_SYM_QPS_PER_BUNDLE *
1463                                 ADF_NUM_BUNDLES_PER_DEV;
1464                 info->feature_flags = dev->feature_flags;
1465                 info->capabilities = internals->qat_dev_capabilities;
1466                 info->sym.max_nb_sessions = internals->max_nb_sessions;
1467                 info->driver_id = cryptodev_qat_driver_id;
1468                 info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1469         }
1470 }
1471
1472 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
1473                 struct rte_cryptodev_stats *stats)
1474 {
1475         int i;
1476         struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1477
1478         PMD_INIT_FUNC_TRACE();
1479         if (stats == NULL) {
1480                 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
1481                 return;
1482         }
1483         for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1484                 if (qp[i] == NULL) {
1485                         PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
1486                         continue;
1487                 }
1488
1489                 stats->enqueued_count += qp[i]->stats.enqueued_count;
1490                 stats->dequeued_count += qp[i]->stats.dequeued_count;
1491                 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
1492                 stats->dequeue_err_count += qp[i]->stats.dequeue_err_count;
1493         }
1494 }
1495
1496 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
1497 {
1498         int i;
1499         struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1500
1501         PMD_INIT_FUNC_TRACE();
1502         for (i = 0; i < dev->data->nb_queue_pairs; i++)
1503                 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
1504         PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");
1505 }