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40 #include <sys/epoll.h>
42 #include <rte_atomic.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_debug.h>
48 #include <rte_fslmc.h>
49 #include <rte_lcore.h>
51 #include <rte_malloc.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
57 #include <fslmc_vfio.h>
58 #include <dpaa2_hw_pvt.h>
59 #include <dpaa2_hw_mempool.h>
60 #include <dpaa2_hw_dpio.h>
61 #include "dpaa2_eventdev.h"
62 #include <portal/dpaa2_hw_pvt.h>
63 #include <mc/fsl_dpci.h>
66 * Evendev = SoC Instance
67 * Eventport = DPIO Instance
68 * Eventqueue = DPCON Instance
69 * 1 Eventdev can have N Eventqueue
70 * Soft Event Flow is DPCI Instance
74 dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[],
79 RTE_SET_USED(nb_events);
85 dpaa2_eventdev_enqueue(void *port, const struct rte_event *ev)
87 return dpaa2_eventdev_enqueue_burst(port, ev, 1);
91 dpaa2_eventdev_dequeue_burst(void *port, struct rte_event ev[],
92 uint16_t nb_events, uint64_t timeout_ticks)
96 RTE_SET_USED(nb_events);
97 RTE_SET_USED(timeout_ticks);
103 dpaa2_eventdev_dequeue(void *port, struct rte_event *ev,
104 uint64_t timeout_ticks)
106 return dpaa2_eventdev_dequeue_burst(port, ev, 1, timeout_ticks);
109 static const struct rte_eventdev_ops dpaa2_eventdev_ops;
112 dpaa2_eventdev_setup_dpci(struct dpaa2_dpci_dev *dpci_dev,
113 struct dpaa2_dpcon_dev *dpcon_dev)
115 struct dpci_rx_queue_cfg rx_queue_cfg;
118 /*Do settings to get the frame on a DPCON object*/
119 rx_queue_cfg.options = DPCI_QUEUE_OPT_DEST;
120 rx_queue_cfg.dest_cfg.dest_type = DPCI_DEST_DPCON;
121 rx_queue_cfg.dest_cfg.dest_id = dpcon_dev->dpcon_id;
122 rx_queue_cfg.dest_cfg.priority = DPAA2_EVENT_DEFAULT_DPCI_PRIO;
124 for (i = 0 ; i < DPAA2_EVENT_DPCI_MAX_QUEUES; i++) {
125 rx_queue_cfg.user_ctx = (uint64_t)(&dpci_dev->queue[i]);
126 ret = dpci_set_rx_queue(&dpci_dev->dpci,
131 PMD_DRV_LOG(ERR, PMD,
132 "set_rx_q failed with err code: %d", ret);
140 dpaa2_eventdev_create(const char *name)
142 struct rte_eventdev *eventdev;
143 struct dpaa2_eventdev *priv;
144 struct dpaa2_dpcon_dev *dpcon_dev = NULL;
145 struct dpaa2_dpci_dev *dpci_dev = NULL;
148 eventdev = rte_event_pmd_vdev_init(name,
149 sizeof(struct dpaa2_eventdev),
151 if (eventdev == NULL) {
152 PMD_DRV_ERR("Failed to create eventdev vdev %s", name);
156 eventdev->dev_ops = &dpaa2_eventdev_ops;
157 eventdev->schedule = NULL;
158 eventdev->enqueue = dpaa2_eventdev_enqueue;
159 eventdev->enqueue_burst = dpaa2_eventdev_enqueue_burst;
160 eventdev->dequeue = dpaa2_eventdev_dequeue;
161 eventdev->dequeue_burst = dpaa2_eventdev_dequeue_burst;
163 /* For secondary processes, the primary has done all the work */
164 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
167 priv = eventdev->data->dev_private;
168 priv->max_event_queues = 0;
171 dpcon_dev = rte_dpaa2_alloc_dpcon_dev();
174 priv->evq_info[priv->max_event_queues].dpcon = dpcon_dev;
176 dpci_dev = rte_dpaa2_alloc_dpci_dev();
178 rte_dpaa2_free_dpcon_dev(dpcon_dev);
181 priv->evq_info[priv->max_event_queues].dpci = dpci_dev;
183 ret = dpaa2_eventdev_setup_dpci(dpci_dev, dpcon_dev);
185 PMD_DRV_LOG(ERR, PMD,
186 "dpci setup failed with err code: %d", ret);
189 priv->max_event_queues++;
190 } while (dpcon_dev && dpci_dev);
198 dpaa2_eventdev_probe(struct rte_vdev_device *vdev)
202 name = rte_vdev_device_name(vdev);
203 PMD_DRV_LOG(INFO, PMD, "Initializing %s\n", name);
204 return dpaa2_eventdev_create(name);
208 dpaa2_eventdev_remove(struct rte_vdev_device *vdev)
212 name = rte_vdev_device_name(vdev);
213 PMD_DRV_LOG(INFO, "Closing %s", name);
215 return rte_event_pmd_vdev_uninit(name);
218 static struct rte_vdev_driver vdev_eventdev_dpaa2_pmd = {
219 .probe = dpaa2_eventdev_probe,
220 .remove = dpaa2_eventdev_remove
223 RTE_PMD_REGISTER_VDEV(EVENTDEV_NAME_DPAA2_PMD, vdev_eventdev_dpaa2_pmd);