drivers/event/dpaa2/dpaa2_eventdev.h

   1 /*
   2  * SPDX-License-Identifier: BSD-3-Clause
   3  *
   4  *   Copyright 2017 NXP
   5  *
   6  */
   7
   8 #ifndef __DPAA2_EVENTDEV_H__
   9 #define __DPAA2_EVENTDEV_H__
  10
  11 #include <rte_eventdev_pmd.h>
  12 #include <rte_eventdev_pmd_vdev.h>
  13 #include <rte_atomic.h>
  14 #include <mc/fsl_dpcon.h>
  15 #include <mc/fsl_mc_sys.h>
  16
  17 #define EVENTDEV_NAME_DPAA2_PMD         event_dpaa2
  18
  19 #ifdef RTE_LIBRTE_PMD_DPAA2_EVENTDEV_DEBUG
  20 #define PMD_DRV_LOG(level, fmt, args...) \
  21         RTE_LOG(level, PMD, "%s(): " fmt "\n", __func__, ## args)
  22 #define PMD_DRV_FUNC_TRACE() PMD_DRV_LOG(DEBUG, ">>")
  23 #else
  24 #define PMD_DRV_LOG(level, fmt, args...) do { } while (0)
  25 #define PMD_DRV_FUNC_TRACE() do { } while (0)
  26 #endif
  27
  28 #define PMD_DRV_ERR(fmt, args...) \
  29         RTE_LOG(ERR, PMD, "%s(): " fmt "\n", __func__, ## args)
  30
  31 #define DPAA2_EVENT_DEFAULT_DPCI_PRIO 0
  32
  33 #define DPAA2_EVENT_MAX_QUEUES                  16
  34 #define DPAA2_EVENT_MIN_DEQUEUE_TIMEOUT         1
  35 #define DPAA2_EVENT_MAX_DEQUEUE_TIMEOUT         (UINT32_MAX - 1)
  36 #define DPAA2_EVENT_MAX_QUEUE_FLOWS             2048
  37 #define DPAA2_EVENT_MAX_QUEUE_PRIORITY_LEVELS   8
  38 #define DPAA2_EVENT_MAX_EVENT_PRIORITY_LEVELS   0
  39 #define DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH      8
  40 #define DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH      8
  41 #define DPAA2_EVENT_MAX_NUM_EVENTS              (INT32_MAX - 1)
  42
  43 #define DPAA2_EVENT_QUEUE_ATOMIC_FLOWS          2048
  44 #define DPAA2_EVENT_QUEUE_ORDER_SEQUENCES       2048
  45
  46 enum {
  47         DPAA2_EVENT_DPCI_PARALLEL_QUEUE,
  48         DPAA2_EVENT_DPCI_ATOMIC_QUEUE,
  49         DPAA2_EVENT_DPCI_MAX_QUEUES
  50 };
  51
  52 #define RTE_EVENT_ETH_RX_ADAPTER_DPAA2_CAP \
  53                 (RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT | \
  54                 RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ | \
  55                 RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID)
  56 /**< Ethernet Rx adapter cap to return If the packet transfers from
  57  * the ethdev to eventdev with DPAA2 devices.
  58  */
  59
  60 struct dpaa2_dpcon_dev {
  61         TAILQ_ENTRY(dpaa2_dpcon_dev) next;
  62         struct fsl_mc_io dpcon;
  63         uint16_t token;
  64         rte_atomic16_t in_use;
  65         uint32_t dpcon_id;
  66         uint16_t qbman_ch_id;
  67         uint8_t num_priorities;
  68         uint8_t channel_index;
  69 };
  70
  71 struct evq_info_t {
  72         /* DPcon device */
  73         struct dpaa2_dpcon_dev *dpcon;
  74         /* Attached DPCI device */
  75         struct dpaa2_dpci_dev *dpci;
  76         /* Configuration provided by the user */
  77         uint32_t event_queue_cfg;
  78         uint8_t link;
  79 };
  80
  81 struct dpaa2_eventdev {
  82         struct evq_info_t evq_info[DPAA2_EVENT_MAX_QUEUES];
  83         uint32_t dequeue_timeout_ns;
  84         uint8_t max_event_queues;
  85         uint8_t nb_event_queues;
  86         uint8_t nb_event_ports;
  87         uint8_t resvd_1;
  88         uint32_t nb_event_queue_flows;
  89         uint32_t nb_event_port_dequeue_depth;
  90         uint32_t nb_event_port_enqueue_depth;
  91         uint32_t event_dev_cfg;
  92 };
  93
  94 struct dpaa2_dpcon_dev *rte_dpaa2_alloc_dpcon_dev(void);
  95 void rte_dpaa2_free_dpcon_dev(struct dpaa2_dpcon_dev *dpcon);
  96
  97 #endif /* __DPAA2_EVENTDEV_H__ */