drivers/event/octeontx/ssovf_evdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Cavium, Inc
   3  */
   4
   5 #ifndef __SSOVF_EVDEV_H__
   6 #define __SSOVF_EVDEV_H__
   7
   8 #include <rte_eventdev_pmd_vdev.h>
   9 #include <rte_io.h>
  10
  11 #include <octeontx_mbox.h>
  12 #include <octeontx_ethdev.h>
  13
  14 #define EVENTDEV_NAME_OCTEONTX_PMD event_octeontx
  15
  16 #define SSOVF_LOG(level, fmt, args...) \
  17         rte_log(RTE_LOG_ ## level, otx_logtype_ssovf, \
  18                         "[%s] %s() " fmt "\n", \
  19                         RTE_STR(EVENTDEV_NAME_OCTEONTX_PMD), __func__, ## args)
  20
  21 #define ssovf_log_info(fmt, ...) SSOVF_LOG(INFO, fmt, ##__VA_ARGS__)
  22 #define ssovf_log_dbg(fmt, ...) SSOVF_LOG(DEBUG, fmt, ##__VA_ARGS__)
  23 #define ssovf_log_err(fmt, ...) SSOVF_LOG(ERR, fmt, ##__VA_ARGS__)
  24 #define ssovf_func_trace ssovf_log_dbg
  25
  26 #define SSO_MAX_VHGRP                     (64)
  27 #define SSO_MAX_VHWS                      (32)
  28
  29 /* SSO VF register offsets */
  30 #define SSO_VHGRP_QCTL                    (0x010ULL)
  31 #define SSO_VHGRP_INT                     (0x100ULL)
  32 #define SSO_VHGRP_INT_W1S                 (0x108ULL)
  33 #define SSO_VHGRP_INT_ENA_W1S             (0x110ULL)
  34 #define SSO_VHGRP_INT_ENA_W1C             (0x118ULL)
  35 #define SSO_VHGRP_INT_THR                 (0x140ULL)
  36 #define SSO_VHGRP_INT_CNT                 (0x180ULL)
  37 #define SSO_VHGRP_XAQ_CNT                 (0x1B0ULL)
  38 #define SSO_VHGRP_AQ_CNT                  (0x1C0ULL)
  39 #define SSO_VHGRP_AQ_THR                  (0x1E0ULL)
  40
  41 /* BAR2 */
  42 #define SSO_VHGRP_OP_ADD_WORK0            (0x00ULL)
  43 #define SSO_VHGRP_OP_ADD_WORK1            (0x08ULL)
  44
  45 /* SSOW VF register offsets (BAR0) */
  46 #define SSOW_VHWS_GRPMSK_CHGX(x)          (0x080ULL | ((x) << 3))
  47 #define SSOW_VHWS_TAG                     (0x300ULL)
  48 #define SSOW_VHWS_WQP                     (0x308ULL)
  49 #define SSOW_VHWS_LINKS                   (0x310ULL)
  50 #define SSOW_VHWS_PENDTAG                 (0x340ULL)
  51 #define SSOW_VHWS_PENDWQP                 (0x348ULL)
  52 #define SSOW_VHWS_SWTP                    (0x400ULL)
  53 #define SSOW_VHWS_OP_ALLOC_WE             (0x410ULL)
  54 #define SSOW_VHWS_OP_UPD_WQP_GRP0         (0x440ULL)
  55 #define SSOW_VHWS_OP_UPD_WQP_GRP1         (0x448ULL)
  56 #define SSOW_VHWS_OP_SWTAG_UNTAG          (0x490ULL)
  57 #define SSOW_VHWS_OP_SWTAG_CLR            (0x820ULL)
  58 #define SSOW_VHWS_OP_DESCHED              (0x860ULL)
  59 #define SSOW_VHWS_OP_DESCHED_NOSCH        (0x870ULL)
  60 #define SSOW_VHWS_OP_SWTAG_DESCHED        (0x8C0ULL)
  61 #define SSOW_VHWS_OP_SWTAG_NOSCHED        (0x8D0ULL)
  62 #define SSOW_VHWS_OP_SWTP_SET             (0xC20ULL)
  63 #define SSOW_VHWS_OP_SWTAG_NORM           (0xC80ULL)
  64 #define SSOW_VHWS_OP_SWTAG_FULL0          (0xCA0UL)
  65 #define SSOW_VHWS_OP_SWTAG_FULL1          (0xCA8ULL)
  66 #define SSOW_VHWS_OP_CLR_NSCHED           (0x10000ULL)
  67 #define SSOW_VHWS_OP_GET_WORK0            (0x80000ULL)
  68 #define SSOW_VHWS_OP_GET_WORK1            (0x80008ULL)
  69
  70 /* Mailbox message constants */
  71 #define SSO_COPROC                        0x2
  72
  73 #define SSO_GETDOMAINCFG                  0x1
  74 #define SSO_IDENTIFY                      0x2
  75 #define SSO_GET_DEV_INFO                  0x3
  76 #define SSO_GET_GETWORK_WAIT              0x4
  77 #define SSO_SET_GETWORK_WAIT              0x5
  78 #define SSO_CONVERT_NS_GETWORK_ITER       0x6
  79 #define SSO_GRP_GET_PRIORITY              0x7
  80 #define SSO_GRP_SET_PRIORITY              0x8
  81
  82 /*
  83  * In Cavium OcteonTX SoC, all accesses to the device registers are
  84  * implictly strongly ordered. So, The relaxed version of IO operation is
  85  * safe to use with out any IO memory barriers.
  86  */
  87 #define ssovf_read64 rte_read64_relaxed
  88 #define ssovf_write64 rte_write64_relaxed
  89
  90 /* ARM64 specific functions */
  91 #if defined(RTE_ARCH_ARM64)
  92 #define ssovf_load_pair(val0, val1, addr) ({            \
  93                         asm volatile(                   \
  94                         "ldp %x[x0], %x[x1], [%x[p1]]"  \
  95                         :[x0]"=r"(val0), [x1]"=r"(val1) \
  96                         :[p1]"r"(addr)                  \
  97                         ); })
  98
  99 #define ssovf_store_pair(val0, val1, addr) ({           \
 100                         asm volatile(                   \
 101                         "stp %x[x0], %x[x1], [%x[p1]]"  \
 102                         ::[x0]"r"(val0), [x1]"r"(val1), [p1]"r"(addr) \
 103                         ); })
 104 #else /* Un optimized functions for building on non arm64 arch */
 105
 106 #define ssovf_load_pair(val0, val1, addr)               \
 107 do {                                                    \
 108         val0 = rte_read64(addr);                        \
 109         val1 = rte_read64(((uint8_t *)addr) + 8);       \
 110 } while (0)
 111
 112 #define ssovf_store_pair(val0, val1, addr)              \
 113 do {                                                    \
 114         rte_write64(val0, addr);                        \
 115         rte_write64(val1, (((uint8_t *)addr) + 8));     \
 116 } while (0)
 117 #endif
 118
 119
 120 struct ssovf_evdev {
 121         uint8_t max_event_queues;
 122         uint8_t max_event_ports;
 123         uint8_t is_timeout_deq;
 124         uint8_t nb_event_queues;
 125         uint8_t nb_event_ports;
 126         uint32_t min_deq_timeout_ns;
 127         uint32_t max_deq_timeout_ns;
 128         int32_t max_num_events;
 129 } __rte_cache_aligned;
 130
 131 /* Event port aka HWS */
 132 struct ssows {
 133         uint8_t cur_tt;
 134         uint8_t cur_grp;
 135         uint8_t swtag_req;
 136         uint8_t *base;
 137         uint8_t *getwork;
 138         uint8_t *grps[SSO_MAX_VHGRP];
 139         uint8_t port;
 140 } __rte_cache_aligned;
 141
 142 static inline struct ssovf_evdev *
 143 ssovf_pmd_priv(const struct rte_eventdev *eventdev)
 144 {
 145         return eventdev->data->dev_private;
 146 }
 147
 148 extern int otx_logtype_ssovf;
 149
 150 uint16_t ssows_enq(void *port, const struct rte_event *ev);
 151 uint16_t ssows_enq_burst(void *port,
 152                 const struct rte_event ev[], uint16_t nb_events);
 153 uint16_t ssows_enq_new_burst(void *port,
 154                 const struct rte_event ev[], uint16_t nb_events);
 155 uint16_t ssows_enq_fwd_burst(void *port,
 156                 const struct rte_event ev[], uint16_t nb_events);
 157 uint16_t ssows_deq(void *port, struct rte_event *ev, uint64_t timeout_ticks);
 158 uint16_t ssows_deq_burst(void *port, struct rte_event ev[],
 159                 uint16_t nb_events, uint64_t timeout_ticks);
 160 uint16_t ssows_deq_timeout(void *port, struct rte_event *ev,
 161                 uint64_t timeout_ticks);
 162 uint16_t ssows_deq_timeout_burst(void *port, struct rte_event ev[],
 163                 uint16_t nb_events, uint64_t timeout_ticks);
 164 void ssows_flush_events(struct ssows *ws, uint8_t queue_id);
 165 void ssows_reset(struct ssows *ws);
 166
 167 #endif /* __SSOVF_EVDEV_H__ */