drivers/event/octeontx2/otx2_evdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2019 Marvell International Ltd.
   3  */
   4
   5 #include <inttypes.h>
   6
   7 #include <rte_bus_pci.h>
   8 #include <rte_common.h>
   9 #include <rte_eal.h>
  10 #include <rte_eventdev_pmd_pci.h>
  11 #include <rte_kvargs.h>
  12 #include <rte_mbuf_pool_ops.h>
  13 #include <rte_pci.h>
  14
  15 #include "otx2_evdev_stats.h"
  16 #include "otx2_evdev.h"
  17 #include "otx2_irq.h"
  18 #include "otx2_tim_evdev.h"
  19
  20 static inline int
  21 sso_get_msix_offsets(const struct rte_eventdev *event_dev)
  22 {
  23         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
  24         uint8_t nb_ports = dev->nb_event_ports * (dev->dual_ws ? 2 : 1);
  25         struct otx2_mbox *mbox = dev->mbox;
  26         struct msix_offset_rsp *msix_rsp;
  27         int i, rc;
  28
  29         /* Get SSO and SSOW MSIX vector offsets */
  30         otx2_mbox_alloc_msg_msix_offset(mbox);
  31         rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
  32
  33         for (i = 0; i < nb_ports; i++)
  34                 dev->ssow_msixoff[i] = msix_rsp->ssow_msixoff[i];
  35
  36         for (i = 0; i < dev->nb_event_queues; i++)
  37                 dev->sso_msixoff[i] = msix_rsp->sso_msixoff[i];
  38
  39         return rc;
  40 }
  41
  42 void
  43 sso_fastpath_fns_set(struct rte_eventdev *event_dev)
  44 {
  45         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
  46         /* Single WS modes */
  47         const event_dequeue_t ssogws_deq[2][2][2][2][2][2][2] = {
  48 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  49                 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_ ##name,
  50 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  51 #undef R
  52         };
  53
  54         const event_dequeue_burst_t ssogws_deq_burst[2][2][2][2][2][2][2] = {
  55 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  56                 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_burst_ ##name,
  57 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  58 #undef R
  59         };
  60
  61         const event_dequeue_t ssogws_deq_timeout[2][2][2][2][2][2][2] = {
  62 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  63                 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_timeout_ ##name,
  64 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  65 #undef R
  66         };
  67
  68         const event_dequeue_burst_t
  69                 ssogws_deq_timeout_burst[2][2][2][2][2][2][2] = {
  70 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  71                 [f6][f5][f4][f3][f2][f1][f0] =                          \
  72                         otx2_ssogws_deq_timeout_burst_ ##name,
  73 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  74 #undef R
  75         };
  76
  77         const event_dequeue_t ssogws_deq_seg[2][2][2][2][2][2][2] = {
  78 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  79                 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_seg_ ##name,
  80 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  81 #undef R
  82         };
  83
  84         const event_dequeue_burst_t
  85                 ssogws_deq_seg_burst[2][2][2][2][2][2][2] = {
  86 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  87                 [f6][f5][f4][f3][f2][f1][f0] =                          \
  88                         otx2_ssogws_deq_seg_burst_ ##name,
  89 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  90 #undef R
  91         };
  92
  93         const event_dequeue_t ssogws_deq_seg_timeout[2][2][2][2][2][2][2] = {
  94 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  95                 [f6][f5][f4][f3][f2][f1][f0] =                          \
  96                         otx2_ssogws_deq_seg_timeout_ ##name,
  97 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  98 #undef R
  99         };
 100
 101         const event_dequeue_burst_t
 102                 ssogws_deq_seg_timeout_burst[2][2][2][2][2][2][2] = {
 103 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 104                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 105                                 otx2_ssogws_deq_seg_timeout_burst_ ##name,
 106 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 107 #undef R
 108         };
 109
 110
 111         /* Dual WS modes */
 112         const event_dequeue_t ssogws_dual_deq[2][2][2][2][2][2][2] = {
 113 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 114                 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_dual_deq_ ##name,
 115 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 116 #undef R
 117         };
 118
 119         const event_dequeue_burst_t
 120                 ssogws_dual_deq_burst[2][2][2][2][2][2][2] = {
 121 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 122                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 123                         otx2_ssogws_dual_deq_burst_ ##name,
 124 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 125 #undef R
 126         };
 127
 128         const event_dequeue_t ssogws_dual_deq_timeout[2][2][2][2][2][2][2] = {
 129 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 130                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 131                         otx2_ssogws_dual_deq_timeout_ ##name,
 132 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 133 #undef R
 134         };
 135
 136         const event_dequeue_burst_t
 137                 ssogws_dual_deq_timeout_burst[2][2][2][2][2][2][2] = {
 138 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 139         [f6][f5][f4][f3][f2][f1][f0] =                                  \
 140                         otx2_ssogws_dual_deq_timeout_burst_ ##name,
 141 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 142 #undef R
 143         };
 144
 145         const event_dequeue_t ssogws_dual_deq_seg[2][2][2][2][2][2][2] = {
 146 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 147                 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_dual_deq_seg_ ##name,
 148 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 149 #undef R
 150         };
 151
 152         const event_dequeue_burst_t
 153                 ssogws_dual_deq_seg_burst[2][2][2][2][2][2][2] = {
 154 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 155                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 156                         otx2_ssogws_dual_deq_seg_burst_ ##name,
 157 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 158 #undef R
 159         };
 160
 161         const event_dequeue_t
 162                 ssogws_dual_deq_seg_timeout[2][2][2][2][2][2][2] = {
 163 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 164                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 165                         otx2_ssogws_dual_deq_seg_timeout_ ##name,
 166 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 167 #undef R
 168         };
 169
 170         const event_dequeue_burst_t
 171                 ssogws_dual_deq_seg_timeout_burst[2][2][2][2][2][2][2] = {
 172 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 173                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 174                         otx2_ssogws_dual_deq_seg_timeout_burst_ ##name,
 175 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 176 #undef R
 177         };
 178
 179         /* Tx modes */
 180         const event_tx_adapter_enqueue
 181                 ssogws_tx_adptr_enq[2][2][2][2][2][2][2] = {
 182 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)                  \
 183                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 184                         otx2_ssogws_tx_adptr_enq_ ## name,
 185 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
 186 #undef T
 187         };
 188
 189         const event_tx_adapter_enqueue
 190                 ssogws_tx_adptr_enq_seg[2][2][2][2][2][2][2] = {
 191 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)                  \
 192                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 193                         otx2_ssogws_tx_adptr_enq_seg_ ## name,
 194 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
 195 #undef T
 196         };
 197
 198         const event_tx_adapter_enqueue
 199                 ssogws_dual_tx_adptr_enq[2][2][2][2][2][2][2] = {
 200 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)                  \
 201                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 202                         otx2_ssogws_dual_tx_adptr_enq_ ## name,
 203 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
 204 #undef T
 205         };
 206
 207         const event_tx_adapter_enqueue
 208                 ssogws_dual_tx_adptr_enq_seg[2][2][2][2][2][2][2] = {
 209 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)                  \
 210                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 211                         otx2_ssogws_dual_tx_adptr_enq_seg_ ## name,
 212 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
 213 #undef T
 214         };
 215
 216         event_dev->enqueue                      = otx2_ssogws_enq;
 217         event_dev->enqueue_burst                = otx2_ssogws_enq_burst;
 218         event_dev->enqueue_new_burst            = otx2_ssogws_enq_new_burst;
 219         event_dev->enqueue_forward_burst        = otx2_ssogws_enq_fwd_burst;
 220         if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
 221                 event_dev->dequeue              = ssogws_deq_seg
 222                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 223                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 224                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 225                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 226                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 227                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 228                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 229                 event_dev->dequeue_burst        = ssogws_deq_seg_burst
 230                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 231                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 232                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 233                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 234                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 235                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 236                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 237                 if (dev->is_timeout_deq) {
 238                         event_dev->dequeue      = ssogws_deq_seg_timeout
 239                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 240                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 241                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 242                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 243                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 244                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 245                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 246                         event_dev->dequeue_burst        =
 247                                 ssogws_deq_seg_timeout_burst
 248                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 249                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 250                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 251                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 252                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 253                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 254                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 255                 }
 256         } else {
 257                 event_dev->dequeue                      = ssogws_deq
 258                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 259                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 260                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 261                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 262                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 263                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 264                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 265                 event_dev->dequeue_burst                = ssogws_deq_burst
 266                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 267                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 268                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 269                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 270                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 271                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 272                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 273                 if (dev->is_timeout_deq) {
 274                         event_dev->dequeue              = ssogws_deq_timeout
 275                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 276                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 277                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 278                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 279                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 280                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 281                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 282                         event_dev->dequeue_burst        =
 283                                 ssogws_deq_timeout_burst
 284                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 285                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 286                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 287                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 288                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 289                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 290                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 291                 }
 292         }
 293
 294         if (dev->tx_offloads & NIX_TX_MULTI_SEG_F) {
 295                 /* [SEC] [TSMP] [MBUF_NOFF] [VLAN] [OL3_L4_CSUM] [L3_L4_CSUM] */
 296                 event_dev->txa_enqueue = ssogws_tx_adptr_enq_seg
 297                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_SECURITY_F)]
 298                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
 299                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
 300                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)]
 301                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)]
 302                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
 303                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
 304         } else {
 305                 event_dev->txa_enqueue = ssogws_tx_adptr_enq
 306                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_SECURITY_F)]
 307                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
 308                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
 309                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)]
 310                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)]
 311                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
 312                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
 313         }
 314
 315         if (dev->dual_ws) {
 316                 event_dev->enqueue              = otx2_ssogws_dual_enq;
 317                 event_dev->enqueue_burst        = otx2_ssogws_dual_enq_burst;
 318                 event_dev->enqueue_new_burst    =
 319                                         otx2_ssogws_dual_enq_new_burst;
 320                 event_dev->enqueue_forward_burst =
 321                                         otx2_ssogws_dual_enq_fwd_burst;
 322
 323                 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
 324                         event_dev->dequeue      = ssogws_dual_deq_seg
 325                                 [!!(dev->rx_offloads &
 326                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 327                                 [!!(dev->rx_offloads &
 328                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 329                                 [!!(dev->rx_offloads &
 330                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 331                                 [!!(dev->rx_offloads &
 332                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 333                                 [!!(dev->rx_offloads &
 334                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 335                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 336                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 337                         event_dev->dequeue_burst = ssogws_dual_deq_seg_burst
 338                                 [!!(dev->rx_offloads &
 339                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 340                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 341                                 [!!(dev->rx_offloads &
 342                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 343                                 [!!(dev->rx_offloads &
 344                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 345                                 [!!(dev->rx_offloads &
 346                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 347                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 348                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 349                         if (dev->is_timeout_deq) {
 350                                 event_dev->dequeue      =
 351                                         ssogws_dual_deq_seg_timeout
 352                                         [!!(dev->rx_offloads &
 353                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 354                                         [!!(dev->rx_offloads &
 355                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 356                                         [!!(dev->rx_offloads &
 357                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 358                                         [!!(dev->rx_offloads &
 359                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 360                                         [!!(dev->rx_offloads &
 361                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 362                                         [!!(dev->rx_offloads &
 363                                                         NIX_RX_OFFLOAD_PTYPE_F)]
 364                                         [!!(dev->rx_offloads &
 365                                                         NIX_RX_OFFLOAD_RSS_F)];
 366                                 event_dev->dequeue_burst =
 367                                         ssogws_dual_deq_seg_timeout_burst
 368                                         [!!(dev->rx_offloads &
 369                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 370                                         [!!(dev->rx_offloads &
 371                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 372                                         [!!(dev->rx_offloads &
 373                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 374                                         [!!(dev->rx_offloads &
 375                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 376                                         [!!(dev->rx_offloads &
 377                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 378                                         [!!(dev->rx_offloads &
 379                                                         NIX_RX_OFFLOAD_PTYPE_F)]
 380                                         [!!(dev->rx_offloads &
 381                                                         NIX_RX_OFFLOAD_RSS_F)];
 382                         }
 383                 } else {
 384                         event_dev->dequeue              = ssogws_dual_deq
 385                                 [!!(dev->rx_offloads &
 386                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 387                                 [!!(dev->rx_offloads &
 388                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 389                                 [!!(dev->rx_offloads &
 390                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 391                                 [!!(dev->rx_offloads &
 392                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 393                                 [!!(dev->rx_offloads &
 394                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 395                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 396                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 397                         event_dev->dequeue_burst        = ssogws_dual_deq_burst
 398                                 [!!(dev->rx_offloads &
 399                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 400                                 [!!(dev->rx_offloads &
 401                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 402                                 [!!(dev->rx_offloads &
 403                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 404                                 [!!(dev->rx_offloads &
 405                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 406                                 [!!(dev->rx_offloads &
 407                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 408                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 409                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 410                         if (dev->is_timeout_deq) {
 411                                 event_dev->dequeue      =
 412                                         ssogws_dual_deq_timeout
 413                                         [!!(dev->rx_offloads &
 414                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 415                                         [!!(dev->rx_offloads &
 416                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 417                                         [!!(dev->rx_offloads &
 418                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 419                                         [!!(dev->rx_offloads &
 420                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 421                                         [!!(dev->rx_offloads &
 422                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 423                                         [!!(dev->rx_offloads &
 424                                                         NIX_RX_OFFLOAD_PTYPE_F)]
 425                                         [!!(dev->rx_offloads &
 426                                                         NIX_RX_OFFLOAD_RSS_F)];
 427                                 event_dev->dequeue_burst =
 428                                         ssogws_dual_deq_timeout_burst
 429                                         [!!(dev->rx_offloads &
 430                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 431                                         [!!(dev->rx_offloads &
 432                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 433                                         [!!(dev->rx_offloads &
 434                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 435                                         [!!(dev->rx_offloads &
 436                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 437                                         [!!(dev->rx_offloads &
 438                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 439                                         [!!(dev->rx_offloads &
 440                                                         NIX_RX_OFFLOAD_PTYPE_F)]
 441                                         [!!(dev->rx_offloads &
 442                                                         NIX_RX_OFFLOAD_RSS_F)];
 443                         }
 444                 }
 445
 446                 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F) {
 447                 /* [SEC] [TSMP] [MBUF_NOFF] [VLAN] [OL3_L4_CSUM] [L3_L4_CSUM] */
 448                         event_dev->txa_enqueue = ssogws_dual_tx_adptr_enq_seg
 449                                 [!!(dev->tx_offloads &
 450                                                 NIX_TX_OFFLOAD_SECURITY_F)]
 451                                 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
 452                                 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
 453                                 [!!(dev->tx_offloads &
 454                                                 NIX_TX_OFFLOAD_MBUF_NOFF_F)]
 455                                 [!!(dev->tx_offloads &
 456                                                 NIX_TX_OFFLOAD_VLAN_QINQ_F)]
 457                                 [!!(dev->tx_offloads &
 458                                                 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
 459                                 [!!(dev->tx_offloads &
 460                                                 NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
 461                 } else {
 462                         event_dev->txa_enqueue = ssogws_dual_tx_adptr_enq
 463                                 [!!(dev->tx_offloads &
 464                                                 NIX_TX_OFFLOAD_SECURITY_F)]
 465                                 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
 466                                 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
 467                                 [!!(dev->tx_offloads &
 468                                                 NIX_TX_OFFLOAD_MBUF_NOFF_F)]
 469                                 [!!(dev->tx_offloads &
 470                                                 NIX_TX_OFFLOAD_VLAN_QINQ_F)]
 471                                 [!!(dev->tx_offloads &
 472                                                 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
 473                                 [!!(dev->tx_offloads &
 474                                                 NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
 475                 }
 476         }
 477
 478         event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
 479         rte_mb();
 480 }
 481
 482 static void
 483 otx2_sso_info_get(struct rte_eventdev *event_dev,
 484                   struct rte_event_dev_info *dev_info)
 485 {
 486         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 487
 488         dev_info->driver_name = RTE_STR(EVENTDEV_NAME_OCTEONTX2_PMD);
 489         dev_info->min_dequeue_timeout_ns = dev->min_dequeue_timeout_ns;
 490         dev_info->max_dequeue_timeout_ns = dev->max_dequeue_timeout_ns;
 491         dev_info->max_event_queues = dev->max_event_queues;
 492         dev_info->max_event_queue_flows = (1ULL << 20);
 493         dev_info->max_event_queue_priority_levels = 8;
 494         dev_info->max_event_priority_levels = 1;
 495         dev_info->max_event_ports = dev->max_event_ports;
 496         dev_info->max_event_port_dequeue_depth = 1;
 497         dev_info->max_event_port_enqueue_depth = 1;
 498         dev_info->max_num_events =  dev->max_num_events;
 499         dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_QUEUE_QOS |
 500                                         RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
 501                                         RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES |
 502                                         RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK |
 503                                         RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT |
 504                                         RTE_EVENT_DEV_CAP_NONSEQ_MODE |
 505                                         RTE_EVENT_DEV_CAP_CARRY_FLOW_ID;
 506 }
 507
 508 static void
 509 sso_port_link_modify(struct otx2_ssogws *ws, uint8_t queue, uint8_t enable)
 510 {
 511         uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
 512         uint64_t val;
 513
 514         val = queue;
 515         val |= 0ULL << 12; /* SET 0 */
 516         val |= 0x8000800080000000; /* Dont modify rest of the masks */
 517         val |= (uint64_t)enable << 14;   /* Enable/Disable Membership. */
 518
 519         otx2_write64(val, base + SSOW_LF_GWS_GRPMSK_CHG);
 520 }
 521
 522 static int
 523 otx2_sso_port_link(struct rte_eventdev *event_dev, void *port,
 524                    const uint8_t queues[], const uint8_t priorities[],
 525                    uint16_t nb_links)
 526 {
 527         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 528         uint8_t port_id = 0;
 529         uint16_t link;
 530
 531         RTE_SET_USED(priorities);
 532         for (link = 0; link < nb_links; link++) {
 533                 if (dev->dual_ws) {
 534                         struct otx2_ssogws_dual *ws = port;
 535
 536                         port_id = ws->port;
 537                         sso_port_link_modify((struct otx2_ssogws *)
 538                                         &ws->ws_state[0], queues[link], true);
 539                         sso_port_link_modify((struct otx2_ssogws *)
 540                                         &ws->ws_state[1], queues[link], true);
 541                 } else {
 542                         struct otx2_ssogws *ws = port;
 543
 544                         port_id = ws->port;
 545                         sso_port_link_modify(ws, queues[link], true);
 546                 }
 547         }
 548         sso_func_trace("Port=%d nb_links=%d", port_id, nb_links);
 549
 550         return (int)nb_links;
 551 }
 552
 553 static int
 554 otx2_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
 555                      uint8_t queues[], uint16_t nb_unlinks)
 556 {
 557         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 558         uint8_t port_id = 0;
 559         uint16_t unlink;
 560
 561         for (unlink = 0; unlink < nb_unlinks; unlink++) {
 562                 if (dev->dual_ws) {
 563                         struct otx2_ssogws_dual *ws = port;
 564
 565                         port_id = ws->port;
 566                         sso_port_link_modify((struct otx2_ssogws *)
 567                                         &ws->ws_state[0], queues[unlink],
 568                                         false);
 569                         sso_port_link_modify((struct otx2_ssogws *)
 570                                         &ws->ws_state[1], queues[unlink],
 571                                         false);
 572                 } else {
 573                         struct otx2_ssogws *ws = port;
 574
 575                         port_id = ws->port;
 576                         sso_port_link_modify(ws, queues[unlink], false);
 577                 }
 578         }
 579         sso_func_trace("Port=%d nb_unlinks=%d", port_id, nb_unlinks);
 580
 581         return (int)nb_unlinks;
 582 }
 583
 584 static int
 585 sso_hw_lf_cfg(struct otx2_mbox *mbox, enum otx2_sso_lf_type type,
 586               uint16_t nb_lf, uint8_t attach)
 587 {
 588         if (attach) {
 589                 struct rsrc_attach_req *req;
 590
 591                 req = otx2_mbox_alloc_msg_attach_resources(mbox);
 592                 switch (type) {
 593                 case SSO_LF_GGRP:
 594                         req->sso = nb_lf;
 595                         break;
 596                 case SSO_LF_GWS:
 597                         req->ssow = nb_lf;
 598                         break;
 599                 default:
 600                         return -EINVAL;
 601                 }
 602                 req->modify = true;
 603                 if (otx2_mbox_process(mbox) < 0)
 604                         return -EIO;
 605         } else {
 606                 struct rsrc_detach_req *req;
 607
 608                 req = otx2_mbox_alloc_msg_detach_resources(mbox);
 609                 switch (type) {
 610                 case SSO_LF_GGRP:
 611                         req->sso = true;
 612                         break;
 613                 case SSO_LF_GWS:
 614                         req->ssow = true;
 615                         break;
 616                 default:
 617                         return -EINVAL;
 618                 }
 619                 req->partial = true;
 620                 if (otx2_mbox_process(mbox) < 0)
 621                         return -EIO;
 622         }
 623
 624         return 0;
 625 }
 626
 627 static int
 628 sso_lf_cfg(struct otx2_sso_evdev *dev, struct otx2_mbox *mbox,
 629            enum otx2_sso_lf_type type, uint16_t nb_lf, uint8_t alloc)
 630 {
 631         void *rsp;
 632         int rc;
 633
 634         if (alloc) {
 635                 switch (type) {
 636                 case SSO_LF_GGRP:
 637                         {
 638                         struct sso_lf_alloc_req *req_ggrp;
 639                         req_ggrp = otx2_mbox_alloc_msg_sso_lf_alloc(mbox);
 640                         req_ggrp->hwgrps = nb_lf;
 641                         }
 642                         break;
 643                 case SSO_LF_GWS:
 644                         {
 645                         struct ssow_lf_alloc_req *req_hws;
 646                         req_hws = otx2_mbox_alloc_msg_ssow_lf_alloc(mbox);
 647                         req_hws->hws = nb_lf;
 648                         }
 649                         break;
 650                 default:
 651                         return -EINVAL;
 652                 }
 653         } else {
 654                 switch (type) {
 655                 case SSO_LF_GGRP:
 656                         {
 657                         struct sso_lf_free_req *req_ggrp;
 658                         req_ggrp = otx2_mbox_alloc_msg_sso_lf_free(mbox);
 659                         req_ggrp->hwgrps = nb_lf;
 660                         }
 661                         break;
 662                 case SSO_LF_GWS:
 663                         {
 664                         struct ssow_lf_free_req *req_hws;
 665                         req_hws = otx2_mbox_alloc_msg_ssow_lf_free(mbox);
 666                         req_hws->hws = nb_lf;
 667                         }
 668                         break;
 669                 default:
 670                         return -EINVAL;
 671                 }
 672         }
 673
 674         rc = otx2_mbox_process_msg_tmo(mbox, (void **)&rsp, ~0);
 675         if (rc < 0)
 676                 return rc;
 677
 678         if (alloc && type == SSO_LF_GGRP) {
 679                 struct sso_lf_alloc_rsp *rsp_ggrp = rsp;
 680
 681                 dev->xaq_buf_size = rsp_ggrp->xaq_buf_size;
 682                 dev->xae_waes = rsp_ggrp->xaq_wq_entries;
 683                 dev->iue = rsp_ggrp->in_unit_entries;
 684         }
 685
 686         return 0;
 687 }
 688
 689 static void
 690 otx2_sso_port_release(void *port)
 691 {
 692         rte_free(port);
 693 }
 694
 695 static void
 696 otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)
 697 {
 698         RTE_SET_USED(event_dev);
 699         RTE_SET_USED(queue_id);
 700 }
 701
 702 static void
 703 sso_clr_links(const struct rte_eventdev *event_dev)
 704 {
 705         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 706         int i, j;
 707
 708         for (i = 0; i < dev->nb_event_ports; i++) {
 709                 if (dev->dual_ws) {
 710                         struct otx2_ssogws_dual *ws;
 711
 712                         ws = event_dev->data->ports[i];
 713                         for (j = 0; j < dev->nb_event_queues; j++) {
 714                                 sso_port_link_modify((struct otx2_ssogws *)
 715                                                 &ws->ws_state[0], j, false);
 716                                 sso_port_link_modify((struct otx2_ssogws *)
 717                                                 &ws->ws_state[1], j, false);
 718                         }
 719                 } else {
 720                         struct otx2_ssogws *ws;
 721
 722                         ws = event_dev->data->ports[i];
 723                         for (j = 0; j < dev->nb_event_queues; j++)
 724                                 sso_port_link_modify(ws, j, false);
 725                 }
 726         }
 727 }
 728
 729 static void
 730 sso_restore_links(const struct rte_eventdev *event_dev)
 731 {
 732         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 733         uint16_t *links_map;
 734         int i, j;
 735
 736         for (i = 0; i < dev->nb_event_ports; i++) {
 737                 links_map = event_dev->data->links_map;
 738                 /* Point links_map to this port specific area */
 739                 links_map += (i * RTE_EVENT_MAX_QUEUES_PER_DEV);
 740                 if (dev->dual_ws) {
 741                         struct otx2_ssogws_dual *ws;
 742
 743                         ws = event_dev->data->ports[i];
 744                         for (j = 0; j < dev->nb_event_queues; j++) {
 745                                 if (links_map[j] == 0xdead)
 746                                         continue;
 747                                 sso_port_link_modify((struct otx2_ssogws *)
 748                                                 &ws->ws_state[0], j, true);
 749                                 sso_port_link_modify((struct otx2_ssogws *)
 750                                                 &ws->ws_state[1], j, true);
 751                                 sso_func_trace("Restoring port %d queue %d "
 752                                                 "link", i, j);
 753                         }
 754                 } else {
 755                         struct otx2_ssogws *ws;
 756
 757                         ws = event_dev->data->ports[i];
 758                         for (j = 0; j < dev->nb_event_queues; j++) {
 759                                 if (links_map[j] == 0xdead)
 760                                         continue;
 761                                 sso_port_link_modify(ws, j, true);
 762                                 sso_func_trace("Restoring port %d queue %d "
 763                                                 "link", i, j);
 764                         }
 765                 }
 766         }
 767 }
 768
 769 static void
 770 sso_set_port_ops(struct otx2_ssogws *ws, uintptr_t base)
 771 {
 772         ws->tag_op              = base + SSOW_LF_GWS_TAG;
 773         ws->wqp_op              = base + SSOW_LF_GWS_WQP;
 774         ws->getwrk_op           = base + SSOW_LF_GWS_OP_GET_WORK;
 775         ws->swtag_flush_op      = base + SSOW_LF_GWS_OP_SWTAG_FLUSH;
 776         ws->swtag_norm_op       = base + SSOW_LF_GWS_OP_SWTAG_NORM;
 777         ws->swtag_desched_op    = base + SSOW_LF_GWS_OP_SWTAG_DESCHED;
 778 }
 779
 780 static int
 781 sso_configure_dual_ports(const struct rte_eventdev *event_dev)
 782 {
 783         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 784         struct otx2_mbox *mbox = dev->mbox;
 785         uint8_t vws = 0;
 786         uint8_t nb_lf;
 787         int i, rc;
 788
 789         otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
 790
 791         nb_lf = dev->nb_event_ports * 2;
 792         /* Ask AF to attach required LFs. */
 793         rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
 794         if (rc < 0) {
 795                 otx2_err("Failed to attach SSO GWS LF");
 796                 return -ENODEV;
 797         }
 798
 799         if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
 800                 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
 801                 otx2_err("Failed to init SSO GWS LF");
 802                 return -ENODEV;
 803         }
 804
 805         for (i = 0; i < dev->nb_event_ports; i++) {
 806                 struct otx2_ssogws_dual *ws;
 807                 uintptr_t base;
 808
 809                 if (event_dev->data->ports[i] != NULL) {
 810                         ws = event_dev->data->ports[i];
 811                 } else {
 812                         /* Allocate event port memory */
 813                         ws = rte_zmalloc_socket("otx2_sso_ws",
 814                                         sizeof(struct otx2_ssogws_dual),
 815                                         RTE_CACHE_LINE_SIZE,
 816                                         event_dev->data->socket_id);
 817                 }
 818                 if (ws == NULL) {
 819                         otx2_err("Failed to alloc memory for port=%d", i);
 820                         rc = -ENOMEM;
 821                         break;
 822                 }
 823
 824                 ws->port = i;
 825                 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
 826                 sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[0], base);
 827                 vws++;
 828
 829                 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
 830                 sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[1], base);
 831                 vws++;
 832
 833                 event_dev->data->ports[i] = ws;
 834         }
 835
 836         if (rc < 0) {
 837                 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
 838                 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
 839         }
 840
 841         return rc;
 842 }
 843
 844 static int
 845 sso_configure_ports(const struct rte_eventdev *event_dev)
 846 {
 847         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 848         struct otx2_mbox *mbox = dev->mbox;
 849         uint8_t nb_lf;
 850         int i, rc;
 851
 852         otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
 853
 854         nb_lf = dev->nb_event_ports;
 855         /* Ask AF to attach required LFs. */
 856         rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
 857         if (rc < 0) {
 858                 otx2_err("Failed to attach SSO GWS LF");
 859                 return -ENODEV;
 860         }
 861
 862         if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
 863                 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
 864                 otx2_err("Failed to init SSO GWS LF");
 865                 return -ENODEV;
 866         }
 867
 868         for (i = 0; i < nb_lf; i++) {
 869                 struct otx2_ssogws *ws;
 870                 uintptr_t base;
 871
 872                 /* Free memory prior to re-allocation if needed */
 873                 if (event_dev->data->ports[i] != NULL) {
 874                         ws = event_dev->data->ports[i];
 875                         rte_free(ws);
 876                         ws = NULL;
 877                 }
 878
 879                 /* Allocate event port memory */
 880                 ws = rte_zmalloc_socket("otx2_sso_ws",
 881                                         sizeof(struct otx2_ssogws),
 882                                         RTE_CACHE_LINE_SIZE,
 883                                         event_dev->data->socket_id);
 884                 if (ws == NULL) {
 885                         otx2_err("Failed to alloc memory for port=%d", i);
 886                         rc = -ENOMEM;
 887                         break;
 888                 }
 889
 890                 ws->port = i;
 891                 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | i << 12);
 892                 sso_set_port_ops(ws, base);
 893
 894                 event_dev->data->ports[i] = ws;
 895         }
 896
 897         if (rc < 0) {
 898                 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
 899                 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
 900         }
 901
 902         return rc;
 903 }
 904
 905 static int
 906 sso_configure_queues(const struct rte_eventdev *event_dev)
 907 {
 908         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 909         struct otx2_mbox *mbox = dev->mbox;
 910         uint8_t nb_lf;
 911         int rc;
 912
 913         otx2_sso_dbg("Configuring event queues %d", dev->nb_event_queues);
 914
 915         nb_lf = dev->nb_event_queues;
 916         /* Ask AF to attach required LFs. */
 917         rc = sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, true);
 918         if (rc < 0) {
 919                 otx2_err("Failed to attach SSO GGRP LF");
 920                 return -ENODEV;
 921         }
 922
 923         if (sso_lf_cfg(dev, mbox, SSO_LF_GGRP, nb_lf, true) < 0) {
 924                 sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, false);
 925                 otx2_err("Failed to init SSO GGRP LF");
 926                 return -ENODEV;
 927         }
 928
 929         return rc;
 930 }
 931
 932 static int
 933 sso_xaq_allocate(struct otx2_sso_evdev *dev)
 934 {
 935         const struct rte_memzone *mz;
 936         struct npa_aura_s *aura;
 937         static int reconfig_cnt;
 938         char pool_name[RTE_MEMZONE_NAMESIZE];
 939         uint32_t xaq_cnt;
 940         int rc;
 941
 942         if (dev->xaq_pool)
 943                 rte_mempool_free(dev->xaq_pool);
 944
 945         /*
 946          * Allocate memory for Add work backpressure.
 947          */
 948         mz = rte_memzone_lookup(OTX2_SSO_FC_NAME);
 949         if (mz == NULL)
 950                 mz = rte_memzone_reserve_aligned(OTX2_SSO_FC_NAME,
 951                                                  OTX2_ALIGN +
 952                                                  sizeof(struct npa_aura_s),
 953                                                  rte_socket_id(),
 954                                                  RTE_MEMZONE_IOVA_CONTIG,
 955                                                  OTX2_ALIGN);
 956         if (mz == NULL) {
 957                 otx2_err("Failed to allocate mem for fcmem");
 958                 return -ENOMEM;
 959         }
 960
 961         dev->fc_iova = mz->iova;
 962         dev->fc_mem = mz->addr;
 963
 964         aura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem + OTX2_ALIGN);
 965         memset(aura, 0, sizeof(struct npa_aura_s));
 966
 967         aura->fc_ena = 1;
 968         aura->fc_addr = dev->fc_iova;
 969         aura->fc_hyst_bits = 0; /* Store count on all updates */
 970
 971         /* Taken from HRM 14.3.3(4) */
 972         xaq_cnt = dev->nb_event_queues * OTX2_SSO_XAQ_CACHE_CNT;
 973         if (dev->xae_cnt)
 974                 xaq_cnt += dev->xae_cnt / dev->xae_waes;
 975         else if (dev->adptr_xae_cnt)
 976                 xaq_cnt += (dev->adptr_xae_cnt / dev->xae_waes) +
 977                         (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);
 978         else
 979                 xaq_cnt += (dev->iue / dev->xae_waes) +
 980                         (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);
 981
 982         otx2_sso_dbg("Configuring %d xaq buffers", xaq_cnt);
 983         /* Setup XAQ based on number of nb queues. */
 984         snprintf(pool_name, 30, "otx2_xaq_buf_pool_%d", reconfig_cnt);
 985         dev->xaq_pool = (void *)rte_mempool_create_empty(pool_name,
 986                         xaq_cnt, dev->xaq_buf_size, 0, 0,
 987                         rte_socket_id(), 0);
 988
 989         if (dev->xaq_pool == NULL) {
 990                 otx2_err("Unable to create empty mempool.");
 991                 rte_memzone_free(mz);
 992                 return -ENOMEM;
 993         }
 994
 995         rc = rte_mempool_set_ops_byname(dev->xaq_pool,
 996                                         rte_mbuf_platform_mempool_ops(), aura);
 997         if (rc != 0) {
 998                 otx2_err("Unable to set xaqpool ops.");
 999                 goto alloc_fail;
1000         }
1001
1002         rc = rte_mempool_populate_default(dev->xaq_pool);
1003         if (rc < 0) {
1004                 otx2_err("Unable to set populate xaqpool.");
1005                 goto alloc_fail;
1006         }
1007         reconfig_cnt++;
1008         /* When SW does addwork (enqueue) check if there is space in XAQ by
1009          * comparing fc_addr above against the xaq_lmt calculated below.
1010          * There should be a minimum headroom (OTX2_SSO_XAQ_SLACK / 2) for SSO
1011          * to request XAQ to cache them even before enqueue is called.
1012          */
1013         dev->xaq_lmt = xaq_cnt - (OTX2_SSO_XAQ_SLACK / 2 *
1014                                   dev->nb_event_queues);
1015         dev->nb_xaq_cfg = xaq_cnt;
1016
1017         return 0;
1018 alloc_fail:
1019         rte_mempool_free(dev->xaq_pool);
1020         rte_memzone_free(mz);
1021         return rc;
1022 }
1023
1024 static int
1025 sso_ggrp_alloc_xaq(struct otx2_sso_evdev *dev)
1026 {
1027         struct otx2_mbox *mbox = dev->mbox;
1028         struct sso_hw_setconfig *req;
1029
1030         otx2_sso_dbg("Configuring XAQ for GGRPs");
1031         req = otx2_mbox_alloc_msg_sso_hw_setconfig(mbox);
1032         req->npa_pf_func = otx2_npa_pf_func_get();
1033         req->npa_aura_id = npa_lf_aura_handle_to_aura(dev->xaq_pool->pool_id);
1034         req->hwgrps = dev->nb_event_queues;
1035
1036         return otx2_mbox_process(mbox);
1037 }
1038
1039 static void
1040 sso_lf_teardown(struct otx2_sso_evdev *dev,
1041                 enum otx2_sso_lf_type lf_type)
1042 {
1043         uint8_t nb_lf;
1044
1045         switch (lf_type) {
1046         case SSO_LF_GGRP:
1047                 nb_lf = dev->nb_event_queues;
1048                 break;
1049         case SSO_LF_GWS:
1050                 nb_lf = dev->nb_event_ports;
1051                 nb_lf *= dev->dual_ws ? 2 : 1;
1052                 break;
1053         default:
1054                 return;
1055         }
1056
1057         sso_lf_cfg(dev, dev->mbox, lf_type, nb_lf, false);
1058         sso_hw_lf_cfg(dev->mbox, lf_type, nb_lf, false);
1059 }
1060
1061 static int
1062 otx2_sso_configure(const struct rte_eventdev *event_dev)
1063 {
1064         struct rte_event_dev_config *conf = &event_dev->data->dev_conf;
1065         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1066         uint32_t deq_tmo_ns;
1067         int rc;
1068
1069         sso_func_trace();
1070         deq_tmo_ns = conf->dequeue_timeout_ns;
1071
1072         if (deq_tmo_ns == 0)
1073                 deq_tmo_ns = dev->min_dequeue_timeout_ns;
1074
1075         if (deq_tmo_ns < dev->min_dequeue_timeout_ns ||
1076             deq_tmo_ns > dev->max_dequeue_timeout_ns) {
1077                 otx2_err("Unsupported dequeue timeout requested");
1078                 return -EINVAL;
1079         }
1080
1081         if (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)
1082                 dev->is_timeout_deq = 1;
1083
1084         dev->deq_tmo_ns = deq_tmo_ns;
1085
1086         if (conf->nb_event_ports > dev->max_event_ports ||
1087             conf->nb_event_queues > dev->max_event_queues) {
1088                 otx2_err("Unsupported event queues/ports requested");
1089                 return -EINVAL;
1090         }
1091
1092         if (conf->nb_event_port_dequeue_depth > 1) {
1093                 otx2_err("Unsupported event port deq depth requested");
1094                 return -EINVAL;
1095         }
1096
1097         if (conf->nb_event_port_enqueue_depth > 1) {
1098                 otx2_err("Unsupported event port enq depth requested");
1099                 return -EINVAL;
1100         }
1101
1102         if (dev->configured) {
1103                 sso_unregister_irqs(event_dev);
1104                 /* Clear any prior port-queue mapping. */
1105                 sso_clr_links(event_dev);
1106         }
1107
1108         if (dev->nb_event_queues) {
1109                 /* Finit any previous queues. */
1110                 sso_lf_teardown(dev, SSO_LF_GGRP);
1111         }
1112         if (dev->nb_event_ports) {
1113                 /* Finit any previous ports. */
1114                 sso_lf_teardown(dev, SSO_LF_GWS);
1115         }
1116
1117         dev->nb_event_queues = conf->nb_event_queues;
1118         dev->nb_event_ports = conf->nb_event_ports;
1119
1120         if (dev->dual_ws)
1121                 rc = sso_configure_dual_ports(event_dev);
1122         else
1123                 rc = sso_configure_ports(event_dev);
1124
1125         if (rc < 0) {
1126                 otx2_err("Failed to configure event ports");
1127                 return -ENODEV;
1128         }
1129
1130         if (sso_configure_queues(event_dev) < 0) {
1131                 otx2_err("Failed to configure event queues");
1132                 rc = -ENODEV;
1133                 goto teardown_hws;
1134         }
1135
1136         if (sso_xaq_allocate(dev) < 0) {
1137                 rc = -ENOMEM;
1138                 goto teardown_hwggrp;
1139         }
1140
1141         /* Restore any prior port-queue mapping. */
1142         sso_restore_links(event_dev);
1143         rc = sso_ggrp_alloc_xaq(dev);
1144         if (rc < 0) {
1145                 otx2_err("Failed to alloc xaq to ggrp %d", rc);
1146                 goto teardown_hwggrp;
1147         }
1148
1149         rc = sso_get_msix_offsets(event_dev);
1150         if (rc < 0) {
1151                 otx2_err("Failed to get msix offsets %d", rc);
1152                 goto teardown_hwggrp;
1153         }
1154
1155         rc = sso_register_irqs(event_dev);
1156         if (rc < 0) {
1157                 otx2_err("Failed to register irq %d", rc);
1158                 goto teardown_hwggrp;
1159         }
1160
1161         dev->configured = 1;
1162         rte_mb();
1163
1164         return 0;
1165 teardown_hwggrp:
1166         sso_lf_teardown(dev, SSO_LF_GGRP);
1167 teardown_hws:
1168         sso_lf_teardown(dev, SSO_LF_GWS);
1169         dev->nb_event_queues = 0;
1170         dev->nb_event_ports = 0;
1171         dev->configured = 0;
1172         return rc;
1173 }
1174
1175 static void
1176 otx2_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,
1177                         struct rte_event_queue_conf *queue_conf)
1178 {
1179         RTE_SET_USED(event_dev);
1180         RTE_SET_USED(queue_id);
1181
1182         queue_conf->nb_atomic_flows = (1ULL << 20);
1183         queue_conf->nb_atomic_order_sequences = (1ULL << 20);
1184         queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;
1185         queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
1186 }
1187
1188 static int
1189 otx2_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
1190                      const struct rte_event_queue_conf *queue_conf)
1191 {
1192         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1193         struct otx2_mbox *mbox = dev->mbox;
1194         struct sso_grp_priority *req;
1195         int rc;
1196
1197         sso_func_trace("Queue=%d prio=%d", queue_id, queue_conf->priority);
1198
1199         req = otx2_mbox_alloc_msg_sso_grp_set_priority(dev->mbox);
1200         req->grp = queue_id;
1201         req->weight = 0xFF;
1202         req->affinity = 0xFF;
1203         /* Normalize <0-255> to <0-7> */
1204         req->priority = queue_conf->priority / 32;
1205
1206         rc = otx2_mbox_process(mbox);
1207         if (rc < 0) {
1208                 otx2_err("Failed to set priority queue=%d", queue_id);
1209                 return rc;
1210         }
1211
1212         return 0;
1213 }
1214
1215 static void
1216 otx2_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
1217                        struct rte_event_port_conf *port_conf)
1218 {
1219         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1220
1221         RTE_SET_USED(port_id);
1222         port_conf->new_event_threshold = dev->max_num_events;
1223         port_conf->dequeue_depth = 1;
1224         port_conf->enqueue_depth = 1;
1225 }
1226
1227 static int
1228 otx2_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
1229                     const struct rte_event_port_conf *port_conf)
1230 {
1231         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1232         uintptr_t grps_base[OTX2_SSO_MAX_VHGRP] = {0};
1233         uint64_t val;
1234         uint16_t q;
1235
1236         sso_func_trace("Port=%d", port_id);
1237         RTE_SET_USED(port_conf);
1238
1239         if (event_dev->data->ports[port_id] == NULL) {
1240                 otx2_err("Invalid port Id %d", port_id);
1241                 return -EINVAL;
1242         }
1243
1244         for (q = 0; q < dev->nb_event_queues; q++) {
1245                 grps_base[q] = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | q << 12);
1246                 if (grps_base[q] == 0) {
1247                         otx2_err("Failed to get grp[%d] base addr", q);
1248                         return -EINVAL;
1249                 }
1250         }
1251
1252         /* Set get_work timeout for HWS */
1253         val = NSEC2USEC(dev->deq_tmo_ns) - 1;
1254
1255         if (dev->dual_ws) {
1256                 struct otx2_ssogws_dual *ws = event_dev->data->ports[port_id];
1257
1258                 rte_memcpy(ws->grps_base, grps_base,
1259                            sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
1260                 ws->fc_mem = dev->fc_mem;
1261                 ws->xaq_lmt = dev->xaq_lmt;
1262                 ws->tstamp = dev->tstamp;
1263                 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(
1264                              ws->ws_state[0].getwrk_op) + SSOW_LF_GWS_NW_TIM);
1265                 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(
1266                              ws->ws_state[1].getwrk_op) + SSOW_LF_GWS_NW_TIM);
1267         } else {
1268                 struct otx2_ssogws *ws = event_dev->data->ports[port_id];
1269                 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
1270
1271                 rte_memcpy(ws->grps_base, grps_base,
1272                            sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
1273                 ws->fc_mem = dev->fc_mem;
1274                 ws->xaq_lmt = dev->xaq_lmt;
1275                 ws->tstamp = dev->tstamp;
1276                 otx2_write64(val, base + SSOW_LF_GWS_NW_TIM);
1277         }
1278
1279         otx2_sso_dbg("Port=%d ws=%p", port_id, event_dev->data->ports[port_id]);
1280
1281         return 0;
1282 }
1283
1284 static int
1285 otx2_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns,
1286                        uint64_t *tmo_ticks)
1287 {
1288         RTE_SET_USED(event_dev);
1289         *tmo_ticks = NSEC2TICK(ns, rte_get_timer_hz());
1290
1291         return 0;
1292 }
1293
1294 static void
1295 ssogws_dump(struct otx2_ssogws *ws, FILE *f)
1296 {
1297         uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
1298
1299         fprintf(f, "SSOW_LF_GWS Base addr   0x%" PRIx64 "\n", (uint64_t)base);
1300         fprintf(f, "SSOW_LF_GWS_LINKS       0x%" PRIx64 "\n",
1301                 otx2_read64(base + SSOW_LF_GWS_LINKS));
1302         fprintf(f, "SSOW_LF_GWS_PENDWQP     0x%" PRIx64 "\n",
1303                 otx2_read64(base + SSOW_LF_GWS_PENDWQP));
1304         fprintf(f, "SSOW_LF_GWS_PENDSTATE   0x%" PRIx64 "\n",
1305                 otx2_read64(base + SSOW_LF_GWS_PENDSTATE));
1306         fprintf(f, "SSOW_LF_GWS_NW_TIM      0x%" PRIx64 "\n",
1307                 otx2_read64(base + SSOW_LF_GWS_NW_TIM));
1308         fprintf(f, "SSOW_LF_GWS_TAG         0x%" PRIx64 "\n",
1309                 otx2_read64(base + SSOW_LF_GWS_TAG));
1310         fprintf(f, "SSOW_LF_GWS_WQP         0x%" PRIx64 "\n",
1311                 otx2_read64(base + SSOW_LF_GWS_TAG));
1312         fprintf(f, "SSOW_LF_GWS_SWTP        0x%" PRIx64 "\n",
1313                 otx2_read64(base + SSOW_LF_GWS_SWTP));
1314         fprintf(f, "SSOW_LF_GWS_PENDTAG     0x%" PRIx64 "\n",
1315                 otx2_read64(base + SSOW_LF_GWS_PENDTAG));
1316 }
1317
1318 static void
1319 ssoggrp_dump(uintptr_t base, FILE *f)
1320 {
1321         fprintf(f, "SSO_LF_GGRP Base addr   0x%" PRIx64 "\n", (uint64_t)base);
1322         fprintf(f, "SSO_LF_GGRP_QCTL        0x%" PRIx64 "\n",
1323                 otx2_read64(base + SSO_LF_GGRP_QCTL));
1324         fprintf(f, "SSO_LF_GGRP_XAQ_CNT     0x%" PRIx64 "\n",
1325                 otx2_read64(base + SSO_LF_GGRP_XAQ_CNT));
1326         fprintf(f, "SSO_LF_GGRP_INT_THR     0x%" PRIx64 "\n",
1327                 otx2_read64(base + SSO_LF_GGRP_INT_THR));
1328         fprintf(f, "SSO_LF_GGRP_INT_CNT     0x%" PRIX64 "\n",
1329                 otx2_read64(base + SSO_LF_GGRP_INT_CNT));
1330         fprintf(f, "SSO_LF_GGRP_AQ_CNT      0x%" PRIX64 "\n",
1331                 otx2_read64(base + SSO_LF_GGRP_AQ_CNT));
1332         fprintf(f, "SSO_LF_GGRP_AQ_THR      0x%" PRIX64 "\n",
1333                 otx2_read64(base + SSO_LF_GGRP_AQ_THR));
1334         fprintf(f, "SSO_LF_GGRP_MISC_CNT    0x%" PRIx64 "\n",
1335                 otx2_read64(base + SSO_LF_GGRP_MISC_CNT));
1336 }
1337
1338 static void
1339 otx2_sso_dump(struct rte_eventdev *event_dev, FILE *f)
1340 {
1341         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1342         uint8_t queue;
1343         uint8_t port;
1344
1345         fprintf(f, "[%s] SSO running in [%s] mode\n", __func__, dev->dual_ws ?
1346                 "dual_ws" : "single_ws");
1347         /* Dump SSOW registers */
1348         for (port = 0; port < dev->nb_event_ports; port++) {
1349                 if (dev->dual_ws) {
1350                         struct otx2_ssogws_dual *ws =
1351                                 event_dev->data->ports[port];
1352
1353                         fprintf(f, "[%s] SSO dual workslot[%d] vws[%d] dump\n",
1354                                 __func__, port, 0);
1355                         ssogws_dump((struct otx2_ssogws *)&ws->ws_state[0], f);
1356                         fprintf(f, "[%s]SSO dual workslot[%d] vws[%d] dump\n",
1357                                 __func__, port, 1);
1358                         ssogws_dump((struct otx2_ssogws *)&ws->ws_state[1], f);
1359                 } else {
1360                         fprintf(f, "[%s]SSO single workslot[%d] dump\n",
1361                                 __func__, port);
1362                         ssogws_dump(event_dev->data->ports[port], f);
1363                 }
1364         }
1365
1366         /* Dump SSO registers */
1367         for (queue = 0; queue < dev->nb_event_queues; queue++) {
1368                 fprintf(f, "[%s]SSO group[%d] dump\n", __func__, queue);
1369                 if (dev->dual_ws) {
1370                         struct otx2_ssogws_dual *ws = event_dev->data->ports[0];
1371                         ssoggrp_dump(ws->grps_base[queue], f);
1372                 } else {
1373                         struct otx2_ssogws *ws = event_dev->data->ports[0];
1374                         ssoggrp_dump(ws->grps_base[queue], f);
1375                 }
1376         }
1377 }
1378
1379 static void
1380 otx2_handle_event(void *arg, struct rte_event event)
1381 {
1382         struct rte_eventdev *event_dev = arg;
1383
1384         if (event_dev->dev_ops->dev_stop_flush != NULL)
1385                 event_dev->dev_ops->dev_stop_flush(event_dev->data->dev_id,
1386                                 event, event_dev->data->dev_stop_flush_arg);
1387 }
1388
1389 static void
1390 sso_qos_cfg(struct rte_eventdev *event_dev)
1391 {
1392         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1393         struct sso_grp_qos_cfg *req;
1394         uint16_t i;
1395
1396         for (i = 0; i < dev->qos_queue_cnt; i++) {
1397                 uint8_t xaq_prcnt = dev->qos_parse_data[i].xaq_prcnt;
1398                 uint8_t iaq_prcnt = dev->qos_parse_data[i].iaq_prcnt;
1399                 uint8_t taq_prcnt = dev->qos_parse_data[i].taq_prcnt;
1400
1401                 if (dev->qos_parse_data[i].queue >= dev->nb_event_queues)
1402                         continue;
1403
1404                 req = otx2_mbox_alloc_msg_sso_grp_qos_config(dev->mbox);
1405                 req->xaq_limit = (dev->nb_xaq_cfg *
1406                                   (xaq_prcnt ? xaq_prcnt : 100)) / 100;
1407                 req->taq_thr = (SSO_HWGRP_IAQ_MAX_THR_MASK *
1408                                 (iaq_prcnt ? iaq_prcnt : 100)) / 100;
1409                 req->iaq_thr = (SSO_HWGRP_TAQ_MAX_THR_MASK *
1410                                 (taq_prcnt ? taq_prcnt : 100)) / 100;
1411         }
1412
1413         if (dev->qos_queue_cnt)
1414                 otx2_mbox_process(dev->mbox);
1415 }
1416
1417 static void
1418 sso_cleanup(struct rte_eventdev *event_dev, uint8_t enable)
1419 {
1420         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1421         uint16_t i;
1422
1423         for (i = 0; i < dev->nb_event_ports; i++) {
1424                 if (dev->dual_ws) {
1425                         struct otx2_ssogws_dual *ws;
1426
1427                         ws = event_dev->data->ports[i];
1428                         ssogws_reset((struct otx2_ssogws *)&ws->ws_state[0]);
1429                         ssogws_reset((struct otx2_ssogws *)&ws->ws_state[1]);
1430                         ws->swtag_req = 0;
1431                         ws->vws = 0;
1432                         ws->ws_state[0].cur_grp = 0;
1433                         ws->ws_state[0].cur_tt = SSO_SYNC_EMPTY;
1434                         ws->ws_state[1].cur_grp = 0;
1435                         ws->ws_state[1].cur_tt = SSO_SYNC_EMPTY;
1436                 } else {
1437                         struct otx2_ssogws *ws;
1438
1439                         ws = event_dev->data->ports[i];
1440                         ssogws_reset(ws);
1441                         ws->swtag_req = 0;
1442                         ws->cur_grp = 0;
1443                         ws->cur_tt = SSO_SYNC_EMPTY;
1444                 }
1445         }
1446
1447         rte_mb();
1448         if (dev->dual_ws) {
1449                 struct otx2_ssogws_dual *ws = event_dev->data->ports[0];
1450                 struct otx2_ssogws temp_ws;
1451
1452                 memcpy(&temp_ws, &ws->ws_state[0],
1453                        sizeof(struct otx2_ssogws_state));
1454                 for (i = 0; i < dev->nb_event_queues; i++) {
1455                         /* Consume all the events through HWS0 */
1456                         ssogws_flush_events(&temp_ws, i, ws->grps_base[i],
1457                                             otx2_handle_event, event_dev);
1458                         /* Enable/Disable SSO GGRP */
1459                         otx2_write64(enable, ws->grps_base[i] +
1460                                      SSO_LF_GGRP_QCTL);
1461                 }
1462                 ws->ws_state[0].cur_grp = 0;
1463                 ws->ws_state[0].cur_tt = SSO_SYNC_EMPTY;
1464         } else {
1465                 struct otx2_ssogws *ws = event_dev->data->ports[0];
1466
1467                 for (i = 0; i < dev->nb_event_queues; i++) {
1468                         /* Consume all the events through HWS0 */
1469                         ssogws_flush_events(ws, i, ws->grps_base[i],
1470                                             otx2_handle_event, event_dev);
1471                         /* Enable/Disable SSO GGRP */
1472                         otx2_write64(enable, ws->grps_base[i] +
1473                                      SSO_LF_GGRP_QCTL);
1474                 }
1475                 ws->cur_grp = 0;
1476                 ws->cur_tt = SSO_SYNC_EMPTY;
1477         }
1478
1479         /* reset SSO GWS cache */
1480         otx2_mbox_alloc_msg_sso_ws_cache_inv(dev->mbox);
1481         otx2_mbox_process(dev->mbox);
1482 }
1483
1484 int
1485 sso_xae_reconfigure(struct rte_eventdev *event_dev)
1486 {
1487         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1488         struct rte_mempool *prev_xaq_pool;
1489         int rc = 0;
1490
1491         if (event_dev->data->dev_started)
1492                 sso_cleanup(event_dev, 0);
1493
1494         prev_xaq_pool = dev->xaq_pool;
1495         dev->xaq_pool = NULL;
1496         rc = sso_xaq_allocate(dev);
1497         if (rc < 0) {
1498                 otx2_err("Failed to alloc xaq pool %d", rc);
1499                 rte_mempool_free(prev_xaq_pool);
1500                 return rc;
1501         }
1502         rc = sso_ggrp_alloc_xaq(dev);
1503         if (rc < 0) {
1504                 otx2_err("Failed to alloc xaq to ggrp %d", rc);
1505                 rte_mempool_free(prev_xaq_pool);
1506                 return rc;
1507         }
1508
1509         rte_mempool_free(prev_xaq_pool);
1510         rte_mb();
1511         if (event_dev->data->dev_started)
1512                 sso_cleanup(event_dev, 1);
1513
1514         return 0;
1515 }
1516
1517 static int
1518 otx2_sso_start(struct rte_eventdev *event_dev)
1519 {
1520         sso_func_trace();
1521         sso_qos_cfg(event_dev);
1522         sso_cleanup(event_dev, 1);
1523         sso_fastpath_fns_set(event_dev);
1524
1525         return 0;
1526 }
1527
1528 static void
1529 otx2_sso_stop(struct rte_eventdev *event_dev)
1530 {
1531         sso_func_trace();
1532         sso_cleanup(event_dev, 0);
1533         rte_mb();
1534 }
1535
1536 static int
1537 otx2_sso_close(struct rte_eventdev *event_dev)
1538 {
1539         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1540         uint8_t all_queues[RTE_EVENT_MAX_QUEUES_PER_DEV];
1541         uint16_t i;
1542
1543         if (!dev->configured)
1544                 return 0;
1545
1546         sso_unregister_irqs(event_dev);
1547
1548         for (i = 0; i < dev->nb_event_queues; i++)
1549                 all_queues[i] = i;
1550
1551         for (i = 0; i < dev->nb_event_ports; i++)
1552                 otx2_sso_port_unlink(event_dev, event_dev->data->ports[i],
1553                                      all_queues, dev->nb_event_queues);
1554
1555         sso_lf_teardown(dev, SSO_LF_GGRP);
1556         sso_lf_teardown(dev, SSO_LF_GWS);
1557         dev->nb_event_ports = 0;
1558         dev->nb_event_queues = 0;
1559         rte_mempool_free(dev->xaq_pool);
1560         rte_memzone_free(rte_memzone_lookup(OTX2_SSO_FC_NAME));
1561
1562         return 0;
1563 }
1564
1565 /* Initialize and register event driver with DPDK Application */
1566 static struct rte_eventdev_ops otx2_sso_ops = {
1567         .dev_infos_get    = otx2_sso_info_get,
1568         .dev_configure    = otx2_sso_configure,
1569         .queue_def_conf   = otx2_sso_queue_def_conf,
1570         .queue_setup      = otx2_sso_queue_setup,
1571         .queue_release    = otx2_sso_queue_release,
1572         .port_def_conf    = otx2_sso_port_def_conf,
1573         .port_setup       = otx2_sso_port_setup,
1574         .port_release     = otx2_sso_port_release,
1575         .port_link        = otx2_sso_port_link,
1576         .port_unlink      = otx2_sso_port_unlink,
1577         .timeout_ticks    = otx2_sso_timeout_ticks,
1578
1579         .eth_rx_adapter_caps_get  = otx2_sso_rx_adapter_caps_get,
1580         .eth_rx_adapter_queue_add = otx2_sso_rx_adapter_queue_add,
1581         .eth_rx_adapter_queue_del = otx2_sso_rx_adapter_queue_del,
1582         .eth_rx_adapter_start = otx2_sso_rx_adapter_start,
1583         .eth_rx_adapter_stop = otx2_sso_rx_adapter_stop,
1584
1585         .eth_tx_adapter_caps_get = otx2_sso_tx_adapter_caps_get,
1586         .eth_tx_adapter_queue_add = otx2_sso_tx_adapter_queue_add,
1587         .eth_tx_adapter_queue_del = otx2_sso_tx_adapter_queue_del,
1588
1589         .timer_adapter_caps_get = otx2_tim_caps_get,
1590
1591         .crypto_adapter_caps_get = otx2_ca_caps_get,
1592         .crypto_adapter_queue_pair_add = otx2_ca_qp_add,
1593         .crypto_adapter_queue_pair_del = otx2_ca_qp_del,
1594
1595         .xstats_get       = otx2_sso_xstats_get,
1596         .xstats_reset     = otx2_sso_xstats_reset,
1597         .xstats_get_names = otx2_sso_xstats_get_names,
1598
1599         .dump             = otx2_sso_dump,
1600         .dev_start        = otx2_sso_start,
1601         .dev_stop         = otx2_sso_stop,
1602         .dev_close        = otx2_sso_close,
1603         .dev_selftest     = otx2_sso_selftest,
1604 };
1605
1606 #define OTX2_SSO_XAE_CNT        "xae_cnt"
1607 #define OTX2_SSO_SINGLE_WS      "single_ws"
1608 #define OTX2_SSO_GGRP_QOS       "qos"
1609 #define OTX2_SSO_SELFTEST       "selftest"
1610
1611 static void
1612 parse_queue_param(char *value, void *opaque)
1613 {
1614         struct otx2_sso_qos queue_qos = {0};
1615         uint8_t *val = (uint8_t *)&queue_qos;
1616         struct otx2_sso_evdev *dev = opaque;
1617         char *tok = strtok(value, "-");
1618         struct otx2_sso_qos *old_ptr;
1619
1620         if (!strlen(value))
1621                 return;
1622
1623         while (tok != NULL) {
1624                 *val = atoi(tok);
1625                 tok = strtok(NULL, "-");
1626                 val++;
1627         }
1628
1629         if (val != (&queue_qos.iaq_prcnt + 1)) {
1630                 otx2_err("Invalid QoS parameter expected [Qx-XAQ-TAQ-IAQ]");
1631                 return;
1632         }
1633
1634         dev->qos_queue_cnt++;
1635         old_ptr = dev->qos_parse_data;
1636         dev->qos_parse_data = rte_realloc(dev->qos_parse_data,
1637                                           sizeof(struct otx2_sso_qos) *
1638                                           dev->qos_queue_cnt, 0);
1639         if (dev->qos_parse_data == NULL) {
1640                 dev->qos_parse_data = old_ptr;
1641                 dev->qos_queue_cnt--;
1642                 return;
1643         }
1644         dev->qos_parse_data[dev->qos_queue_cnt - 1] = queue_qos;
1645 }
1646
1647 static void
1648 parse_qos_list(const char *value, void *opaque)
1649 {
1650         char *s = strdup(value);
1651         char *start = NULL;
1652         char *end = NULL;
1653         char *f = s;
1654
1655         while (*s) {
1656                 if (*s == '[')
1657                         start = s;
1658                 else if (*s == ']')
1659                         end = s;
1660
1661                 if (start && start < end) {
1662                         *end = 0;
1663                         parse_queue_param(start + 1, opaque);
1664                         s = end;
1665                         start = end;
1666                 }
1667                 s++;
1668         }
1669
1670         free(f);
1671 }
1672
1673 static int
1674 parse_sso_kvargs_dict(const char *key, const char *value, void *opaque)
1675 {
1676         RTE_SET_USED(key);
1677
1678         /* Dict format [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] use '-' cause ','
1679          * isn't allowed. Everything is expressed in percentages, 0 represents
1680          * default.
1681          */
1682         parse_qos_list(value, opaque);
1683
1684         return 0;
1685 }
1686
1687 static void
1688 sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs)
1689 {
1690         struct rte_kvargs *kvlist;
1691         uint8_t single_ws = 0;
1692
1693         if (devargs == NULL)
1694                 return;
1695         kvlist = rte_kvargs_parse(devargs->args, NULL);
1696         if (kvlist == NULL)
1697                 return;
1698
1699         rte_kvargs_process(kvlist, OTX2_SSO_SELFTEST, &parse_kvargs_flag,
1700                            &dev->selftest);
1701         rte_kvargs_process(kvlist, OTX2_SSO_XAE_CNT, &parse_kvargs_value,
1702                            &dev->xae_cnt);
1703         rte_kvargs_process(kvlist, OTX2_SSO_SINGLE_WS, &parse_kvargs_flag,
1704                            &single_ws);
1705         rte_kvargs_process(kvlist, OTX2_SSO_GGRP_QOS, &parse_sso_kvargs_dict,
1706                            dev);
1707         otx2_parse_common_devargs(kvlist);
1708         dev->dual_ws = !single_ws;
1709         rte_kvargs_free(kvlist);
1710 }
1711
1712 static int
1713 otx2_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1714 {
1715         return rte_event_pmd_pci_probe(pci_drv, pci_dev,
1716                                        sizeof(struct otx2_sso_evdev),
1717                                        otx2_sso_init);
1718 }
1719
1720 static int
1721 otx2_sso_remove(struct rte_pci_device *pci_dev)
1722 {
1723         return rte_event_pmd_pci_remove(pci_dev, otx2_sso_fini);
1724 }
1725
1726 static const struct rte_pci_id pci_sso_map[] = {
1727         {
1728                 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
1729                                PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF)
1730         },
1731         {
1732                 .vendor_id = 0,
1733         },
1734 };
1735
1736 static struct rte_pci_driver pci_sso = {
1737         .id_table = pci_sso_map,
1738         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
1739         .probe = otx2_sso_probe,
1740         .remove = otx2_sso_remove,
1741 };
1742
1743 int
1744 otx2_sso_init(struct rte_eventdev *event_dev)
1745 {
1746         struct free_rsrcs_rsp *rsrc_cnt;
1747         struct rte_pci_device *pci_dev;
1748         struct otx2_sso_evdev *dev;
1749         int rc;
1750
1751         event_dev->dev_ops = &otx2_sso_ops;
1752         /* For secondary processes, the primary has done all the work */
1753         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1754                 sso_fastpath_fns_set(event_dev);
1755                 return 0;
1756         }
1757
1758         dev = sso_pmd_priv(event_dev);
1759
1760         pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
1761
1762         /* Initialize the base otx2_dev object */
1763         rc = otx2_dev_init(pci_dev, dev);
1764         if (rc < 0) {
1765                 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
1766                 goto error;
1767         }
1768
1769         /* Get SSO and SSOW MSIX rsrc cnt */
1770         otx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
1771         rc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);
1772         if (rc < 0) {
1773                 otx2_err("Unable to get free rsrc count");
1774                 goto otx2_dev_uninit;
1775         }
1776         otx2_sso_dbg("SSO %d SSOW %d NPA %d provisioned", rsrc_cnt->sso,
1777                      rsrc_cnt->ssow, rsrc_cnt->npa);
1778
1779         dev->max_event_ports = RTE_MIN(rsrc_cnt->ssow, OTX2_SSO_MAX_VHWS);
1780         dev->max_event_queues = RTE_MIN(rsrc_cnt->sso, OTX2_SSO_MAX_VHGRP);
1781         /* Grab the NPA LF if required */
1782         rc = otx2_npa_lf_init(pci_dev, dev);
1783         if (rc < 0) {
1784                 otx2_err("Unable to init NPA lf. It might not be provisioned");
1785                 goto otx2_dev_uninit;
1786         }
1787
1788         dev->drv_inited = true;
1789         dev->is_timeout_deq = 0;
1790         dev->min_dequeue_timeout_ns = USEC2NSEC(1);
1791         dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF);
1792         dev->max_num_events = -1;
1793         dev->nb_event_queues = 0;
1794         dev->nb_event_ports = 0;
1795
1796         if (!dev->max_event_ports || !dev->max_event_queues) {
1797                 otx2_err("Not enough eventdev resource queues=%d ports=%d",
1798                          dev->max_event_queues, dev->max_event_ports);
1799                 rc = -ENODEV;
1800                 goto otx2_npa_lf_uninit;
1801         }
1802
1803         dev->dual_ws = 1;
1804         sso_parse_devargs(dev, pci_dev->device.devargs);
1805         if (dev->dual_ws) {
1806                 otx2_sso_dbg("Using dual workslot mode");
1807                 dev->max_event_ports = dev->max_event_ports / 2;
1808         } else {
1809                 otx2_sso_dbg("Using single workslot mode");
1810         }
1811
1812         otx2_sso_pf_func_set(dev->pf_func);
1813         otx2_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
1814                      event_dev->data->name, dev->max_event_queues,
1815                      dev->max_event_ports);
1816         if (dev->selftest) {
1817                 event_dev->dev->driver = &pci_sso.driver;
1818                 event_dev->dev_ops->dev_selftest();
1819         }
1820
1821         otx2_tim_init(pci_dev, (struct otx2_dev *)dev);
1822
1823         return 0;
1824
1825 otx2_npa_lf_uninit:
1826         otx2_npa_lf_fini();
1827 otx2_dev_uninit:
1828         otx2_dev_fini(pci_dev, dev);
1829 error:
1830         return rc;
1831 }
1832
1833 int
1834 otx2_sso_fini(struct rte_eventdev *event_dev)
1835 {
1836         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1837         struct rte_pci_device *pci_dev;
1838
1839         /* For secondary processes, nothing to be done */
1840         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1841                 return 0;
1842
1843         pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
1844
1845         if (!dev->drv_inited)
1846                 goto dev_fini;
1847
1848         dev->drv_inited = false;
1849         otx2_npa_lf_fini();
1850
1851 dev_fini:
1852         if (otx2_npa_lf_active(dev)) {
1853                 otx2_info("Common resource in use by other devices");
1854                 return -EAGAIN;
1855         }
1856
1857         otx2_tim_fini();
1858         otx2_dev_fini(pci_dev, dev);
1859
1860         return 0;
1861 }
1862
1863 RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso);
1864 RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map);
1865 RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, "vfio-pci");
1866 RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT "=<int>"
1867                               OTX2_SSO_SINGLE_WS "=1"
1868                               OTX2_SSO_GGRP_QOS "=<string>"
1869                               OTX2_SSO_SELFTEST "=1"
1870                               OTX2_NPA_LOCK_MASK "=<1-65535>");